1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * drivers/irq/irq-nvic.c
  4 *
  5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
  6 * Copyright (C) 2013 Pengutronix
  7 *
  8 * Support for the Nested Vectored Interrupt Controller found on the
  9 * ARMv7-M CPUs (Cortex-M3/M4)
 10 */
 11#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt
 12
 13#include <linux/init.h>
 14#include <linux/kernel.h>
 15#include <linux/slab.h>
 16#include <linux/err.h>
 17#include <linux/io.h>
 18#include <linux/of.h>
 19#include <linux/of_address.h>
 20#include <linux/irq.h>
 21#include <linux/irqchip.h>
 22#include <linux/irqdomain.h>
 23
 24#include <asm/v7m.h>
 25#include <asm/exception.h>
 26
 27#define NVIC_ISER		0x000
 28#define NVIC_ICER		0x080
 29#define NVIC_IPR		0x300
 30
 31#define NVIC_MAX_BANKS		16
 32/*
 33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
 34 * 16 irqs.
 35 */
 36#define NVIC_MAX_IRQ		((NVIC_MAX_BANKS - 1) * 32 + 16)
 37
 38static struct irq_domain *nvic_irq_domain;
 39
 40asmlinkage void __exception_irq_entry
 41nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs)
 42{
 43	handle_domain_irq(nvic_irq_domain, hwirq, regs);
 44}
 45
 46static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 47				unsigned int nr_irqs, void *arg)
 48{
 49	int i, ret;
 50	irq_hw_number_t hwirq;
 51	unsigned int type = IRQ_TYPE_NONE;
 52	struct irq_fwspec *fwspec = arg;
 53
 54	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
 55	if (ret)
 56		return ret;
 57
 58	for (i = 0; i < nr_irqs; i++)
 59		irq_map_generic_chip(domain, virq + i, hwirq + i);
 60
 61	return 0;
 62}
 63
 64static const struct irq_domain_ops nvic_irq_domain_ops = {
 65	.translate = irq_domain_translate_onecell,
 66	.alloc = nvic_irq_domain_alloc,
 67	.free = irq_domain_free_irqs_top,
 68};
 69
 70static int __init nvic_of_init(struct device_node *node,
 71			       struct device_node *parent)
 72{
 73	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 74	unsigned int irqs, i, ret, numbanks;
 75	void __iomem *nvic_base;
 76
 77	numbanks = (readl_relaxed(V7M_SCS_ICTR) &
 78		    V7M_SCS_ICTR_INTLINESNUM_MASK) + 1;
 79
 80	nvic_base = of_iomap(node, 0);
 81	if (!nvic_base) {
 82		pr_warn("unable to map nvic registers\n");
 83		return -ENOMEM;
 84	}
 85
 86	irqs = numbanks * 32;
 87	if (irqs > NVIC_MAX_IRQ)
 88		irqs = NVIC_MAX_IRQ;
 89
 90	nvic_irq_domain =
 91		irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL);
 92
 93	if (!nvic_irq_domain) {
 94		pr_warn("Failed to allocate irq domain\n");
 95		return -ENOMEM;
 96	}
 97
 98	ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1,
 99					     "nvic_irq", handle_fasteoi_irq,
100					     clr, 0, IRQ_GC_INIT_MASK_CACHE);
101	if (ret) {
102		pr_warn("Failed to allocate irq chips\n");
103		irq_domain_remove(nvic_irq_domain);
104		return ret;
105	}
106
107	for (i = 0; i < numbanks; ++i) {
108		struct irq_chip_generic *gc;
109
110		gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i);
111		gc->reg_base = nvic_base + 4 * i;
112		gc->chip_types[0].regs.enable = NVIC_ISER;
113		gc->chip_types[0].regs.disable = NVIC_ICER;
114		gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
115		gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
116		/* This is a no-op as end of interrupt is signaled by the
117		 * exception return sequence.
118		 */
119		gc->chip_types[0].chip.irq_eoi = irq_gc_noop;
120
121		/* disable interrupts */
122		writel_relaxed(~0, gc->reg_base + NVIC_ICER);
123	}
124
125	/* Set priority on all interrupts */
126	for (i = 0; i < irqs; i += 4)
127		writel_relaxed(0, nvic_base + NVIC_IPR + i);
128
129	return 0;
130}
131IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);