Loading...
Note: File does not exist in v3.1.
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2015 Free Electrons
4 * Copyright (C) 2015 NextThing Co
5 *
6 * Boris Brezillon <boris.brezillon@free-electrons.com>
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10#ifndef __SUN4I_TCON_H__
11#define __SUN4I_TCON_H__
12
13#include <drm/drm_crtc.h>
14
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/reset.h>
18
19#define SUN4I_TCON_GCTL_REG 0x0
20#define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31)
21#define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
22#define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
23#define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
24
25#define SUN4I_TCON_GINT0_REG 0x4
26#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe))
27#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE BIT(27)
28#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE BIT(26)
29#define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe))
30#define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT BIT(11)
31#define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT BIT(10)
32
33#define SUN4I_TCON_GINT1_REG 0x8
34
35#define SUN4I_TCON_FRM_CTL_REG 0x10
36#define SUN4I_TCON0_FRM_CTL_EN BIT(31)
37#define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6)
38#define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5)
39#define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4)
40
41#define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
42#define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
43#define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
44#define SUN4I_TCON0_FRM_SEED_LR_REG 0x20
45#define SUN4I_TCON0_FRM_SEED_LG_REG 0x24
46#define SUN4I_TCON0_FRM_SEED_LB_REG 0x28
47#define SUN4I_TCON0_FRM_TBL0_REG 0x2c
48#define SUN4I_TCON0_FRM_TBL1_REG 0x30
49#define SUN4I_TCON0_FRM_TBL2_REG 0x34
50#define SUN4I_TCON0_FRM_TBL3_REG 0x38
51
52#define SUN4I_TCON0_CTL_REG 0x40
53#define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31)
54#define SUN4I_TCON0_CTL_IF_MASK GENMASK(25, 24)
55#define SUN4I_TCON0_CTL_IF_8080 (1 << 24)
56#define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4)
57#define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
58#define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0)
59
60#define SUN4I_TCON0_DCLK_REG 0x44
61#define SUN4I_TCON0_DCLK_GATE_BIT (31)
62#define SUN4I_TCON0_DCLK_DIV_SHIFT (0)
63#define SUN4I_TCON0_DCLK_DIV_WIDTH (7)
64
65#define SUN4I_TCON0_BASIC0_REG 0x48
66#define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
67#define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff)
68
69#define SUN4I_TCON0_BASIC1_REG 0x4c
70#define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
71#define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
72
73#define SUN4I_TCON0_BASIC2_REG 0x50
74#define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16)
75#define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
76
77#define SUN4I_TCON0_BASIC3_REG 0x54
78#define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16)
79#define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff)
80
81#define SUN4I_TCON0_HV_IF_REG 0x58
82
83#define SUN4I_TCON0_CPU_IF_REG 0x60
84#define SUN4I_TCON0_CPU_IF_MODE_MASK GENMASK(31, 28)
85#define SUN4I_TCON0_CPU_IF_MODE_DSI (1 << 28)
86#define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH BIT(16)
87#define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN BIT(2)
88#define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0)
89
90#define SUN4I_TCON0_CPU_WR_REG 0x64
91#define SUN4I_TCON0_CPU_RD0_REG 0x68
92#define SUN4I_TCON0_CPU_RDA_REG 0x6c
93#define SUN4I_TCON0_TTL0_REG 0x70
94#define SUN4I_TCON0_TTL1_REG 0x74
95#define SUN4I_TCON0_TTL2_REG 0x78
96#define SUN4I_TCON0_TTL3_REG 0x7c
97#define SUN4I_TCON0_TTL4_REG 0x80
98
99#define SUN4I_TCON0_LVDS_IF_REG 0x84
100#define SUN4I_TCON0_LVDS_IF_EN BIT(31)
101#define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26)
102#define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26)
103#define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26)
104#define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20)
105#define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20)
106#define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4)
107#define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4)
108#define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4)
109#define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0)
110#define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf)
111#define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0)
112
113#define SUN4I_TCON0_IO_POL_REG 0x88
114#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
115#define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
116#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
117#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
118#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
119
120#define SUN4I_TCON0_IO_TRI_REG 0x8c
121#define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25)
122#define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24)
123#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0)
124
125#define SUN4I_TCON1_CTL_REG 0x90
126#define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31)
127#define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20)
128#define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4)
129#define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK)
130#define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0)
131
132#define SUN4I_TCON1_BASIC0_REG 0x94
133#define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16)
134#define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff)
135
136#define SUN4I_TCON1_BASIC1_REG 0x98
137#define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16)
138#define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff)
139
140#define SUN4I_TCON1_BASIC2_REG 0x9c
141#define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16)
142#define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff)
143
144#define SUN4I_TCON1_BASIC3_REG 0xa0
145#define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16)
146#define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff)
147
148#define SUN4I_TCON1_BASIC4_REG 0xa4
149#define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16)
150#define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff)
151
152#define SUN4I_TCON1_BASIC5_REG 0xa8
153#define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16)
154#define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff)
155
156#define SUN4I_TCON1_IO_POL_REG 0xf0
157/* there is no documentation about this bit */
158#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26)
159#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25)
160#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24)
161
162#define SUN4I_TCON1_IO_TRI_REG 0xf4
163
164#define SUN4I_TCON_ECC_FIFO_REG 0xf8
165#define SUN4I_TCON_ECC_FIFO_EN BIT(3)
166
167#define SUN4I_TCON_CEU_CTL_REG 0x100
168#define SUN4I_TCON_CEU_MUL_RR_REG 0x110
169#define SUN4I_TCON_CEU_MUL_RG_REG 0x114
170#define SUN4I_TCON_CEU_MUL_RB_REG 0x118
171#define SUN4I_TCON_CEU_ADD_RC_REG 0x11c
172#define SUN4I_TCON_CEU_MUL_GR_REG 0x120
173#define SUN4I_TCON_CEU_MUL_GG_REG 0x124
174#define SUN4I_TCON_CEU_MUL_GB_REG 0x128
175#define SUN4I_TCON_CEU_ADD_GC_REG 0x12c
176#define SUN4I_TCON_CEU_MUL_BR_REG 0x130
177#define SUN4I_TCON_CEU_MUL_BG_REG 0x134
178#define SUN4I_TCON_CEU_MUL_BB_REG 0x138
179#define SUN4I_TCON_CEU_ADD_BC_REG 0x13c
180#define SUN4I_TCON_CEU_RANGE_R_REG 0x140
181#define SUN4I_TCON_CEU_RANGE_G_REG 0x144
182#define SUN4I_TCON_CEU_RANGE_B_REG 0x148
183
184#define SUN4I_TCON0_CPU_TRI0_REG 0x160
185#define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space) ((((space) - 1) & 0xfff) << 16)
186#define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size) (((size) - 1) & 0xfff)
187
188#define SUN4I_TCON0_CPU_TRI1_REG 0x164
189#define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num) (((num) - 1) & 0xffff)
190
191#define SUN4I_TCON0_CPU_TRI2_REG 0x168
192#define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay) (((delay) & 0xffff) << 16)
193#define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set) ((set) & 0xfff)
194
195#define SUN4I_TCON_SAFE_PERIOD_REG 0x1f0
196#define SUN4I_TCON_SAFE_PERIOD_NUM(num) (((num) & 0xfff) << 16)
197#define SUN4I_TCON_SAFE_PERIOD_MODE(mode) ((mode) & 0x3)
198
199#define SUN4I_TCON_MUX_CTRL_REG 0x200
200
201#define SUN4I_TCON0_LVDS_ANA0_REG 0x220
202#define SUN4I_TCON0_LVDS_ANA0_DCHS BIT(16)
203#define SUN4I_TCON0_LVDS_ANA0_PD (BIT(20) | BIT(21))
204#define SUN4I_TCON0_LVDS_ANA0_EN_MB BIT(22)
205#define SUN4I_TCON0_LVDS_ANA0_REG_C (BIT(24) | BIT(25))
206#define SUN4I_TCON0_LVDS_ANA0_REG_V (BIT(26) | BIT(27))
207#define SUN4I_TCON0_LVDS_ANA0_CK_EN (BIT(29) | BIT(28))
208
209#define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31)
210#define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30)
211#define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24)
212#define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20)
213#define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17)
214#define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8)
215#define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4)
216
217#define SUN4I_TCON0_LVDS_ANA1_REG 0x224
218#define SUN4I_TCON0_LVDS_ANA1_INIT (0x1f << 26 | 0x1f << 10)
219#define SUN4I_TCON0_LVDS_ANA1_UPDATE (0x1f << 16 | 0x1f << 00)
220
221#define SUN4I_TCON1_FILL_CTL_REG 0x300
222#define SUN4I_TCON1_FILL_BEG0_REG 0x304
223#define SUN4I_TCON1_FILL_END0_REG 0x308
224#define SUN4I_TCON1_FILL_DATA0_REG 0x30c
225#define SUN4I_TCON1_FILL_BEG1_REG 0x310
226#define SUN4I_TCON1_FILL_END1_REG 0x314
227#define SUN4I_TCON1_FILL_DATA1_REG 0x318
228#define SUN4I_TCON1_FILL_BEG2_REG 0x31c
229#define SUN4I_TCON1_FILL_END2_REG 0x320
230#define SUN4I_TCON1_FILL_DATA2_REG 0x324
231#define SUN4I_TCON1_GAMMA_TABLE_REG 0x400
232
233#define SUN4I_TCON_MAX_CHANNELS 2
234
235struct sun4i_tcon;
236
237struct sun4i_tcon_quirks {
238 bool has_channel_0; /* a83t does not have channel 0 on second TCON */
239 bool has_channel_1; /* a33 does not have channel 1 */
240 bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */
241 bool needs_de_be_mux; /* sun6i needs mux to select backend */
242 bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
243 bool supports_lvds; /* Does the TCON support an LVDS output? */
244 bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
245 u8 dclk_min_div; /* minimum divider for TCON0 DCLK */
246
247 /* callback to handle tcon muxing options */
248 int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
249 /* handler for LVDS setup routine */
250 void (*setup_lvds_phy)(struct sun4i_tcon *tcon,
251 const struct drm_encoder *encoder);
252};
253
254struct sun4i_tcon {
255 struct device *dev;
256 struct drm_device *drm;
257 struct regmap *regs;
258
259 /* Main bus clock */
260 struct clk *clk;
261
262 /* Clocks for the TCON channels */
263 struct clk *sclk0;
264 struct clk *sclk1;
265
266 /* Possible mux for the LVDS clock */
267 struct clk *lvds_pll;
268
269 /* Pixel clock */
270 struct clk *dclk;
271 u8 dclk_max_div;
272 u8 dclk_min_div;
273
274 /* Reset control */
275 struct reset_control *lcd_rst;
276 struct reset_control *lvds_rst;
277
278 /* Platform adjustments */
279 const struct sun4i_tcon_quirks *quirks;
280
281 /* Associated crtc */
282 struct sun4i_crtc *crtc;
283
284 int id;
285
286 /* TCON list management */
287 struct list_head list;
288};
289
290struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
291struct drm_panel *sun4i_tcon_find_panel(struct device_node *node);
292
293void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable);
294void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
295 const struct drm_encoder *encoder,
296 const struct drm_display_mode *mode);
297void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
298 const struct drm_encoder *encoder, bool enable);
299
300extern const struct of_device_id sun4i_tcon_of_table[];
301
302#endif /* __SUN4I_TCON_H__ */