1/*
   2 * Copyright 2007-11 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26
  27#include <linux/backlight.h>
  28#include <linux/dmi.h>
  29#include <linux/pci.h>
  30
  31#include <drm/drm_crtc_helper.h>
  32#include <drm/drm_file.h>
  33#include <drm/radeon_drm.h>
  34
  35#include "atom.h"
  36#include "radeon_atombios.h"
  37#include "radeon.h"
  38#include "radeon_asic.h"
  39#include "radeon_audio.h"
  40
  41extern int atom_debug;
  42
  43static u8
  44radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  45{
  46	u8 backlight_level;
  47	u32 bios_2_scratch;
  48
  49	if (rdev->family >= CHIP_R600)
  50		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  51	else
  52		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  53
  54	backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  55			   ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  56
  57	return backlight_level;
  58}
  59
  60static void
  61radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  62				       u8 backlight_level)
  63{
  64	u32 bios_2_scratch;
  65
  66	if (rdev->family >= CHIP_R600)
  67		bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  68	else
  69		bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  70
  71	bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  72	bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  73			   ATOM_S2_CURRENT_BL_LEVEL_MASK);
  74
  75	if (rdev->family >= CHIP_R600)
  76		WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  77	else
  78		WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  79}
  80
  81u8
  82atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  83{
  84	struct drm_device *dev = radeon_encoder->base.dev;
  85	struct radeon_device *rdev = dev->dev_private;
  86
  87	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  88		return 0;
  89
  90	return radeon_atom_get_backlight_level_from_reg(rdev);
  91}
  92
  93void
  94atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  95{
  96	struct drm_encoder *encoder = &radeon_encoder->base;
  97	struct drm_device *dev = radeon_encoder->base.dev;
  98	struct radeon_device *rdev = dev->dev_private;
  99	struct radeon_encoder_atom_dig *dig;
 100	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 101	int index;
 102
 103	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 104		return;
 105
 106	if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 107	    radeon_encoder->enc_priv) {
 108		dig = radeon_encoder->enc_priv;
 109		dig->backlight_level = level;
 110		radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 111
 112		switch (radeon_encoder->encoder_id) {
 113		case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 114		case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 115			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 116			if (dig->backlight_level == 0) {
 117				args.ucAction = ATOM_LCD_BLOFF;
 118				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 119			} else {
 120				args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 121				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 122				args.ucAction = ATOM_LCD_BLON;
 123				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 124			}
 125			break;
 126		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 127		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 128		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 129		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 130		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 131			if (dig->backlight_level == 0)
 132				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 133			else {
 134				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 135				atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 136			}
 137			break;
 138		default:
 139			break;
 140		}
 141	}
 142}
 143
 144#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 145
 146static u8 radeon_atom_bl_level(struct backlight_device *bd)
 147{
 148	u8 level;
 149
 150	/* Convert brightness to hardware level */
 151	if (bd->props.brightness < 0)
 152		level = 0;
 153	else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 154		level = RADEON_MAX_BL_LEVEL;
 155	else
 156		level = bd->props.brightness;
 157
 158	return level;
 159}
 160
 161static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 162{
 163	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 164	struct radeon_encoder *radeon_encoder = pdata->encoder;
 165
 166	atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 167
 168	return 0;
 169}
 170
 171static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 172{
 173	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 174	struct radeon_encoder *radeon_encoder = pdata->encoder;
 175	struct drm_device *dev = radeon_encoder->base.dev;
 176	struct radeon_device *rdev = dev->dev_private;
 177
 178	return radeon_atom_get_backlight_level_from_reg(rdev);
 179}
 180
 181static const struct backlight_ops radeon_atom_backlight_ops = {
 182	.get_brightness = radeon_atom_backlight_get_brightness,
 183	.update_status	= radeon_atom_backlight_update_status,
 184};
 185
 186void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 187				struct drm_connector *drm_connector)
 188{
 189	struct drm_device *dev = radeon_encoder->base.dev;
 190	struct radeon_device *rdev = dev->dev_private;
 191	struct backlight_device *bd;
 192	struct backlight_properties props;
 193	struct radeon_backlight_privdata *pdata;
 194	struct radeon_encoder_atom_dig *dig;
 195	char bl_name[16];
 196
 197	/* Mac laptops with multiple GPUs use the gmux driver for backlight
 198	 * so don't register a backlight device
 199	 */
 200	if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 201	    (rdev->pdev->device == 0x6741))
 202		return;
 203
 204	if (!radeon_encoder->enc_priv)
 205		return;
 206
 207	if (!rdev->is_atom_bios)
 208		return;
 209
 210	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 211		return;
 212
 213	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 214	if (!pdata) {
 215		DRM_ERROR("Memory allocation failed\n");
 216		goto error;
 217	}
 218
 219	memset(&props, 0, sizeof(props));
 220	props.max_brightness = RADEON_MAX_BL_LEVEL;
 221	props.type = BACKLIGHT_RAW;
 222	snprintf(bl_name, sizeof(bl_name),
 223		 "radeon_bl%d", dev->primary->index);
 224	bd = backlight_device_register(bl_name, drm_connector->kdev,
 225				       pdata, &radeon_atom_backlight_ops, &props);
 226	if (IS_ERR(bd)) {
 227		DRM_ERROR("Backlight registration failed\n");
 228		goto error;
 229	}
 230
 231	pdata->encoder = radeon_encoder;
 232
 233	dig = radeon_encoder->enc_priv;
 234	dig->bl_dev = bd;
 235
 236	bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 237	/* Set a reasonable default here if the level is 0 otherwise
 238	 * fbdev will attempt to turn the backlight on after console
 239	 * unblanking and it will try and restore 0 which turns the backlight
 240	 * off again.
 241	 */
 242	if (bd->props.brightness == 0)
 243		bd->props.brightness = RADEON_MAX_BL_LEVEL;
 244	bd->props.power = FB_BLANK_UNBLANK;
 245	backlight_update_status(bd);
 246
 247	DRM_INFO("radeon atom DIG backlight initialized\n");
 248	rdev->mode_info.bl_encoder = radeon_encoder;
 249
 250	return;
 251
 252error:
 253	kfree(pdata);
 254	return;
 255}
 256
 257static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 258{
 259	struct drm_device *dev = radeon_encoder->base.dev;
 260	struct radeon_device *rdev = dev->dev_private;
 261	struct backlight_device *bd = NULL;
 262	struct radeon_encoder_atom_dig *dig;
 263
 264	if (!radeon_encoder->enc_priv)
 265		return;
 266
 267	if (!rdev->is_atom_bios)
 268		return;
 269
 270	if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 271		return;
 272
 273	dig = radeon_encoder->enc_priv;
 274	bd = dig->bl_dev;
 275	dig->bl_dev = NULL;
 276
 277	if (bd) {
 278		struct radeon_legacy_backlight_privdata *pdata;
 279
 280		pdata = bl_get_data(bd);
 281		backlight_device_unregister(bd);
 282		kfree(pdata);
 283
 284		DRM_INFO("radeon atom LVDS backlight unloaded\n");
 285	}
 286}
 287
 288#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 289
 290void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 291{
 292}
 293
 294static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 295{
 296}
 297
 298#endif
 299
 300static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 301				   const struct drm_display_mode *mode,
 302				   struct drm_display_mode *adjusted_mode)
 303{
 304	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 305	struct drm_device *dev = encoder->dev;
 306	struct radeon_device *rdev = dev->dev_private;
 307
 308	/* set the active encoder to connector routing */
 309	radeon_encoder_set_active_device(encoder);
 310	drm_mode_set_crtcinfo(adjusted_mode, 0);
 311
 312	/* hw bug */
 313	if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 314	    && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 315		adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 316
 317	/* vertical FP must be at least 1 */
 318	if (mode->crtc_vsync_start == mode->crtc_vdisplay)
 319		adjusted_mode->crtc_vsync_start++;
 320
 321	/* get the native mode for scaling */
 322	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 323		radeon_panel_mode_fixup(encoder, adjusted_mode);
 324	} else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 325		struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 326		if (tv_dac) {
 327			if (tv_dac->tv_std == TV_STD_NTSC ||
 328			    tv_dac->tv_std == TV_STD_NTSC_J ||
 329			    tv_dac->tv_std == TV_STD_PAL_M)
 330				radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 331			else
 332				radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 333		}
 334	} else if (radeon_encoder->rmx_type != RMX_OFF) {
 335		radeon_panel_mode_fixup(encoder, adjusted_mode);
 336	}
 337
 338	if (ASIC_IS_DCE3(rdev) &&
 339	    ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 340	     (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 341		struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 342		radeon_dp_set_link_config(connector, adjusted_mode);
 343	}
 344
 345	return true;
 346}
 347
 348static void
 349atombios_dac_setup(struct drm_encoder *encoder, int action)
 350{
 351	struct drm_device *dev = encoder->dev;
 352	struct radeon_device *rdev = dev->dev_private;
 353	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 354	DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 355	int index = 0;
 356	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 357
 358	memset(&args, 0, sizeof(args));
 359
 360	switch (radeon_encoder->encoder_id) {
 361	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 362	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 363		index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 364		break;
 365	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 366	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 367		index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 368		break;
 369	}
 370
 371	args.ucAction = action;
 372
 373	if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 374		args.ucDacStandard = ATOM_DAC1_PS2;
 375	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 376		args.ucDacStandard = ATOM_DAC1_CV;
 377	else {
 378		switch (dac_info->tv_std) {
 379		case TV_STD_PAL:
 380		case TV_STD_PAL_M:
 381		case TV_STD_SCART_PAL:
 382		case TV_STD_SECAM:
 383		case TV_STD_PAL_CN:
 384			args.ucDacStandard = ATOM_DAC1_PAL;
 385			break;
 386		case TV_STD_NTSC:
 387		case TV_STD_NTSC_J:
 388		case TV_STD_PAL_60:
 389		default:
 390			args.ucDacStandard = ATOM_DAC1_NTSC;
 391			break;
 392		}
 393	}
 394	args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 395
 396	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 397
 398}
 399
 400static void
 401atombios_tv_setup(struct drm_encoder *encoder, int action)
 402{
 403	struct drm_device *dev = encoder->dev;
 404	struct radeon_device *rdev = dev->dev_private;
 405	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 406	TV_ENCODER_CONTROL_PS_ALLOCATION args;
 407	int index = 0;
 408	struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 409
 410	memset(&args, 0, sizeof(args));
 411
 412	index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 413
 414	args.sTVEncoder.ucAction = action;
 415
 416	if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 417		args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 418	else {
 419		switch (dac_info->tv_std) {
 420		case TV_STD_NTSC:
 421			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 422			break;
 423		case TV_STD_PAL:
 424			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 425			break;
 426		case TV_STD_PAL_M:
 427			args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 428			break;
 429		case TV_STD_PAL_60:
 430			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 431			break;
 432		case TV_STD_NTSC_J:
 433			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 434			break;
 435		case TV_STD_SCART_PAL:
 436			args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 437			break;
 438		case TV_STD_SECAM:
 439			args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 440			break;
 441		case TV_STD_PAL_CN:
 442			args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 443			break;
 444		default:
 445			args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 446			break;
 447		}
 448	}
 449
 450	args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 451
 452	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 453
 454}
 455
 456static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 457{
 458	int bpc = 8;
 459
 460	if (encoder->crtc) {
 461		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 462		bpc = radeon_crtc->bpc;
 463	}
 464
 465	switch (bpc) {
 466	case 0:
 467		return PANEL_BPC_UNDEFINE;
 468	case 6:
 469		return PANEL_6BIT_PER_COLOR;
 470	case 8:
 471	default:
 472		return PANEL_8BIT_PER_COLOR;
 473	case 10:
 474		return PANEL_10BIT_PER_COLOR;
 475	case 12:
 476		return PANEL_12BIT_PER_COLOR;
 477	case 16:
 478		return PANEL_16BIT_PER_COLOR;
 479	}
 480}
 481
 482union dvo_encoder_control {
 483	ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 484	DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 485	DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 486	DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 487};
 488
 489void
 490atombios_dvo_setup(struct drm_encoder *encoder, int action)
 491{
 492	struct drm_device *dev = encoder->dev;
 493	struct radeon_device *rdev = dev->dev_private;
 494	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 495	union dvo_encoder_control args;
 496	int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 497	uint8_t frev, crev;
 498
 499	memset(&args, 0, sizeof(args));
 500
 501	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 502		return;
 503
 504	/* some R4xx chips have the wrong frev */
 505	if (rdev->family <= CHIP_RV410)
 506		frev = 1;
 507
 508	switch (frev) {
 509	case 1:
 510		switch (crev) {
 511		case 1:
 512			/* R4xx, R5xx */
 513			args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 514
 515			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 516				args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 517
 518			args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 519			break;
 520		case 2:
 521			/* RS600/690/740 */
 522			args.dvo.sDVOEncoder.ucAction = action;
 523			args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 524			/* DFP1, CRT1, TV1 depending on the type of port */
 525			args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 526
 527			if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 528				args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 529			break;
 530		case 3:
 531			/* R6xx */
 532			args.dvo_v3.ucAction = action;
 533			args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 534			args.dvo_v3.ucDVOConfig = 0; /* XXX */
 535			break;
 536		case 4:
 537			/* DCE8 */
 538			args.dvo_v4.ucAction = action;
 539			args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 540			args.dvo_v4.ucDVOConfig = 0; /* XXX */
 541			args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 542			break;
 543		default:
 544			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 545			break;
 546		}
 547		break;
 548	default:
 549		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 550		break;
 551	}
 552
 553	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 554}
 555
 556union lvds_encoder_control {
 557	LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 558	LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 559};
 560
 561void
 562atombios_digital_setup(struct drm_encoder *encoder, int action)
 563{
 564	struct drm_device *dev = encoder->dev;
 565	struct radeon_device *rdev = dev->dev_private;
 566	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 567	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 568	union lvds_encoder_control args;
 569	int index = 0;
 570	int hdmi_detected = 0;
 571	uint8_t frev, crev;
 572
 573	if (!dig)
 574		return;
 575
 576	if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 577		hdmi_detected = 1;
 578
 579	memset(&args, 0, sizeof(args));
 580
 581	switch (radeon_encoder->encoder_id) {
 582	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 583		index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 584		break;
 585	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 586	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 587		index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 588		break;
 589	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 590		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 591			index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 592		else
 593			index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 594		break;
 595	}
 596
 597	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 598		return;
 599
 600	switch (frev) {
 601	case 1:
 602	case 2:
 603		switch (crev) {
 604		case 1:
 605			args.v1.ucMisc = 0;
 606			args.v1.ucAction = action;
 607			if (hdmi_detected)
 608				args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 609			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 610			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 611				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 612					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 613				if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 614					args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 615			} else {
 616				if (dig->linkb)
 617					args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 618				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 619					args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 620				/*if (pScrn->rgbBits == 8) */
 621				args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 622			}
 623			break;
 624		case 2:
 625		case 3:
 626			args.v2.ucMisc = 0;
 627			args.v2.ucAction = action;
 628			if (crev == 3) {
 629				if (dig->coherent_mode)
 630					args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 631			}
 632			if (hdmi_detected)
 633				args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 634			args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 635			args.v2.ucTruncate = 0;
 636			args.v2.ucSpatial = 0;
 637			args.v2.ucTemporal = 0;
 638			args.v2.ucFRC = 0;
 639			if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 640				if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 641					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 642				if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 643					args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 644					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 645						args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 646				}
 647				if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 648					args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 649					if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 650						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 651					if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 652						args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 653				}
 654			} else {
 655				if (dig->linkb)
 656					args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 657				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 658					args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 659			}
 660			break;
 661		default:
 662			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 663			break;
 664		}
 665		break;
 666	default:
 667		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 668		break;
 669	}
 670
 671	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 672}
 673
 674int
 675atombios_get_encoder_mode(struct drm_encoder *encoder)
 676{
 677	struct drm_device *dev = encoder->dev;
 678	struct radeon_device *rdev = dev->dev_private;
 679	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 680	struct drm_connector *connector;
 681	struct radeon_connector *radeon_connector;
 682	struct radeon_connector_atom_dig *dig_connector;
 683	struct radeon_encoder_atom_dig *dig_enc;
 684
 685	if (radeon_encoder_is_digital(encoder)) {
 686		dig_enc = radeon_encoder->enc_priv;
 687		if (dig_enc->active_mst_links)
 688			return ATOM_ENCODER_MODE_DP_MST;
 689	}
 690	if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 691		return ATOM_ENCODER_MODE_DP_MST;
 692	/* dp bridges are always DP */
 693	if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 694		return ATOM_ENCODER_MODE_DP;
 695
 696	/* DVO is always DVO */
 697	if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 698	    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 699		return ATOM_ENCODER_MODE_DVO;
 700
 701	connector = radeon_get_connector_for_encoder(encoder);
 702	/* if we don't have an active device yet, just use one of
 703	 * the connectors tied to the encoder.
 704	 */
 705	if (!connector)
 706		connector = radeon_get_connector_for_encoder_init(encoder);
 707	radeon_connector = to_radeon_connector(connector);
 708
 709	switch (connector->connector_type) {
 710	case DRM_MODE_CONNECTOR_DVII:
 711	case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 712		if (radeon_audio != 0) {
 713			if (radeon_connector->use_digital &&
 714			    (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 715				return ATOM_ENCODER_MODE_HDMI;
 716			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 717				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 718				return ATOM_ENCODER_MODE_HDMI;
 719			else if (radeon_connector->use_digital)
 720				return ATOM_ENCODER_MODE_DVI;
 721			else
 722				return ATOM_ENCODER_MODE_CRT;
 723		} else if (radeon_connector->use_digital) {
 724			return ATOM_ENCODER_MODE_DVI;
 725		} else {
 726			return ATOM_ENCODER_MODE_CRT;
 727		}
 728		break;
 729	case DRM_MODE_CONNECTOR_DVID:
 730	case DRM_MODE_CONNECTOR_HDMIA:
 731	default:
 732		if (radeon_audio != 0) {
 733			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 734				return ATOM_ENCODER_MODE_HDMI;
 735			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 736				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 737				return ATOM_ENCODER_MODE_HDMI;
 738			else
 739				return ATOM_ENCODER_MODE_DVI;
 740		} else {
 741			return ATOM_ENCODER_MODE_DVI;
 742		}
 743		break;
 744	case DRM_MODE_CONNECTOR_LVDS:
 745		return ATOM_ENCODER_MODE_LVDS;
 746		break;
 747	case DRM_MODE_CONNECTOR_DisplayPort:
 748		dig_connector = radeon_connector->con_priv;
 749		if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 750		    (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 751			if (radeon_audio != 0 &&
 752			    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 753			    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 754				return ATOM_ENCODER_MODE_DP_AUDIO;
 755			return ATOM_ENCODER_MODE_DP;
 756		} else if (radeon_audio != 0) {
 757			if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 758				return ATOM_ENCODER_MODE_HDMI;
 759			else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 760				 (radeon_connector->audio == RADEON_AUDIO_AUTO))
 761				return ATOM_ENCODER_MODE_HDMI;
 762			else
 763				return ATOM_ENCODER_MODE_DVI;
 764		} else {
 765			return ATOM_ENCODER_MODE_DVI;
 766		}
 767		break;
 768	case DRM_MODE_CONNECTOR_eDP:
 769		if (radeon_audio != 0 &&
 770		    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 771		    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 772			return ATOM_ENCODER_MODE_DP_AUDIO;
 773		return ATOM_ENCODER_MODE_DP;
 774	case DRM_MODE_CONNECTOR_DVIA:
 775	case DRM_MODE_CONNECTOR_VGA:
 776		return ATOM_ENCODER_MODE_CRT;
 777		break;
 778	case DRM_MODE_CONNECTOR_Composite:
 779	case DRM_MODE_CONNECTOR_SVIDEO:
 780	case DRM_MODE_CONNECTOR_9PinDIN:
 781		/* fix me */
 782		return ATOM_ENCODER_MODE_TV;
 783		/*return ATOM_ENCODER_MODE_CV;*/
 784		break;
 785	}
 786}
 787
 788/*
 789 * DIG Encoder/Transmitter Setup
 790 *
 791 * DCE 3.0/3.1
 792 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 793 * Supports up to 3 digital outputs
 794 * - 2 DIG encoder blocks.
 795 * DIG1 can drive UNIPHY link A or link B
 796 * DIG2 can drive UNIPHY link B or LVTMA
 797 *
 798 * DCE 3.2
 799 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 800 * Supports up to 5 digital outputs
 801 * - 2 DIG encoder blocks.
 802 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 803 *
 804 * DCE 4.0/5.0/6.0
 805 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 806 * Supports up to 6 digital outputs
 807 * - 6 DIG encoder blocks.
 808 * - DIG to PHY mapping is hardcoded
 809 * DIG1 drives UNIPHY0 link A, A+B
 810 * DIG2 drives UNIPHY0 link B
 811 * DIG3 drives UNIPHY1 link A, A+B
 812 * DIG4 drives UNIPHY1 link B
 813 * DIG5 drives UNIPHY2 link A, A+B
 814 * DIG6 drives UNIPHY2 link B
 815 *
 816 * DCE 4.1
 817 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 818 * Supports up to 6 digital outputs
 819 * - 2 DIG encoder blocks.
 820 * llano
 821 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 822 * ontario
 823 * DIG1 drives UNIPHY0/1/2 link A
 824 * DIG2 drives UNIPHY0/1/2 link B
 825 *
 826 * Routing
 827 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 828 * Examples:
 829 * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 830 * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 831 * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 832 * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 833 */
 834
 835union dig_encoder_control {
 836	DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 837	DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 838	DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 839	DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 840};
 841
 842void
 843atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 844{
 845	struct drm_device *dev = encoder->dev;
 846	struct radeon_device *rdev = dev->dev_private;
 847	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 848	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 849	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 850	union dig_encoder_control args;
 851	int index = 0;
 852	uint8_t frev, crev;
 853	int dp_clock = 0;
 854	int dp_lane_count = 0;
 855	int hpd_id = RADEON_HPD_NONE;
 856
 857	if (connector) {
 858		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 859		struct radeon_connector_atom_dig *dig_connector =
 860			radeon_connector->con_priv;
 861
 862		dp_clock = dig_connector->dp_clock;
 863		dp_lane_count = dig_connector->dp_lane_count;
 864		hpd_id = radeon_connector->hpd.hpd;
 865	}
 866
 867	/* no dig encoder assigned */
 868	if (dig->dig_encoder == -1)
 869		return;
 870
 871	memset(&args, 0, sizeof(args));
 872
 873	if (ASIC_IS_DCE4(rdev))
 874		index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 875	else {
 876		if (dig->dig_encoder)
 877			index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 878		else
 879			index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 880	}
 881
 882	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 883		return;
 884
 885	switch (frev) {
 886	case 1:
 887		switch (crev) {
 888		case 1:
 889			args.v1.ucAction = action;
 890			args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 891			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 892				args.v3.ucPanelMode = panel_mode;
 893			else
 894				args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 895
 896			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 897				args.v1.ucLaneNum = dp_lane_count;
 898			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 899				args.v1.ucLaneNum = 8;
 900			else
 901				args.v1.ucLaneNum = 4;
 902
 903			switch (radeon_encoder->encoder_id) {
 904			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 905				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 906				break;
 907			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 908			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 909				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 910				break;
 911			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 912				args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 913				break;
 914			}
 915			if (dig->linkb)
 916				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 917			else
 918				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 919
 920			if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 921				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 922
 923			break;
 924		case 2:
 925		case 3:
 926			args.v3.ucAction = action;
 927			args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 928			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 929				args.v3.ucPanelMode = panel_mode;
 930			else
 931				args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 932
 933			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 934				args.v3.ucLaneNum = dp_lane_count;
 935			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 936				args.v3.ucLaneNum = 8;
 937			else
 938				args.v3.ucLaneNum = 4;
 939
 940			if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 941				args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 942			if (enc_override != -1)
 943				args.v3.acConfig.ucDigSel = enc_override;
 944			else
 945				args.v3.acConfig.ucDigSel = dig->dig_encoder;
 946			args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 947			break;
 948		case 4:
 949			args.v4.ucAction = action;
 950			args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 951			if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 952				args.v4.ucPanelMode = panel_mode;
 953			else
 954				args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 955
 956			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 957				args.v4.ucLaneNum = dp_lane_count;
 958			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 959				args.v4.ucLaneNum = 8;
 960			else
 961				args.v4.ucLaneNum = 4;
 962
 963			if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 964				if (dp_clock == 540000)
 965					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 966				else if (dp_clock == 324000)
 967					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 968				else if (dp_clock == 270000)
 969					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 970				else
 971					args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 972			}
 973
 974			if (enc_override != -1)
 975				args.v4.acConfig.ucDigSel = enc_override;
 976			else
 977				args.v4.acConfig.ucDigSel = dig->dig_encoder;
 978			args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 979			if (hpd_id == RADEON_HPD_NONE)
 980				args.v4.ucHPD_ID = 0;
 981			else
 982				args.v4.ucHPD_ID = hpd_id + 1;
 983			break;
 984		default:
 985			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 986			break;
 987		}
 988		break;
 989	default:
 990		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 991		break;
 992	}
 993
 994	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 995
 996}
 997
 998void
 999atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
1000{
1001	atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
1002}
1003
1004union dig_transmitter_control {
1005	DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
1006	DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
1007	DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
1008	DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
1009	DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
1010};
1011
1012void
1013atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1014{
1015	struct drm_device *dev = encoder->dev;
1016	struct radeon_device *rdev = dev->dev_private;
1017	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1018	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1019	struct drm_connector *connector;
1020	union dig_transmitter_control args;
1021	int index = 0;
1022	uint8_t frev, crev;
1023	bool is_dp = false;
1024	int pll_id = 0;
1025	int dp_clock = 0;
1026	int dp_lane_count = 0;
1027	int connector_object_id = 0;
1028	int igp_lane_info = 0;
1029	int dig_encoder = dig->dig_encoder;
1030	int hpd_id = RADEON_HPD_NONE;
1031
1032	if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1033		connector = radeon_get_connector_for_encoder_init(encoder);
1034		/* just needed to avoid bailing in the encoder check.  the encoder
1035		 * isn't used for init
1036		 */
1037		dig_encoder = 0;
1038	} else
1039		connector = radeon_get_connector_for_encoder(encoder);
1040
1041	if (connector) {
1042		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1043		struct radeon_connector_atom_dig *dig_connector =
1044			radeon_connector->con_priv;
1045
1046		hpd_id = radeon_connector->hpd.hpd;
1047		dp_clock = dig_connector->dp_clock;
1048		dp_lane_count = dig_connector->dp_lane_count;
1049		connector_object_id =
1050			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1051		igp_lane_info = dig_connector->igp_lane_info;
1052	}
1053
1054	if (encoder->crtc) {
1055		struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1056		pll_id = radeon_crtc->pll_id;
1057	}
1058
1059	/* no dig encoder assigned */
1060	if (dig_encoder == -1)
1061		return;
1062
1063	if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1064		is_dp = true;
1065
1066	memset(&args, 0, sizeof(args));
1067
1068	switch (radeon_encoder->encoder_id) {
1069	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1070		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1071		break;
1072	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1073	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1074	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1075	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1076		index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1077		break;
1078	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1079		index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1080		break;
1081	}
1082
1083	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1084		return;
1085
1086	switch (frev) {
1087	case 1:
1088		switch (crev) {
1089		case 1:
1090			args.v1.ucAction = action;
1091			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1092				args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1093			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1094				args.v1.asMode.ucLaneSel = lane_num;
1095				args.v1.asMode.ucLaneSet = lane_set;
1096			} else {
1097				if (is_dp)
1098					args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1099				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1100					args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1101				else
1102					args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1103			}
1104
1105			args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1106
1107			if (dig_encoder)
1108				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1109			else
1110				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1111
1112			if ((rdev->flags & RADEON_IS_IGP) &&
1113			    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1114				if (is_dp ||
1115				    !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1116					if (igp_lane_info & 0x1)
1117						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1118					else if (igp_lane_info & 0x2)
1119						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1120					else if (igp_lane_info & 0x4)
1121						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1122					else if (igp_lane_info & 0x8)
1123						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1124				} else {
1125					if (igp_lane_info & 0x3)
1126						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1127					else if (igp_lane_info & 0xc)
1128						args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1129				}
1130			}
1131
1132			if (dig->linkb)
1133				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1134			else
1135				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1136
1137			if (is_dp)
1138				args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1139			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1140				if (dig->coherent_mode)
1141					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1142				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1143					args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1144			}
1145			break;
1146		case 2:
1147			args.v2.ucAction = action;
1148			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1149				args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1150			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1151				args.v2.asMode.ucLaneSel = lane_num;
1152				args.v2.asMode.ucLaneSet = lane_set;
1153			} else {
1154				if (is_dp)
1155					args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1156				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1157					args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1158				else
1159					args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1160			}
1161
1162			args.v2.acConfig.ucEncoderSel = dig_encoder;
1163			if (dig->linkb)
1164				args.v2.acConfig.ucLinkSel = 1;
1165
1166			switch (radeon_encoder->encoder_id) {
1167			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1168				args.v2.acConfig.ucTransmitterSel = 0;
1169				break;
1170			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1171				args.v2.acConfig.ucTransmitterSel = 1;
1172				break;
1173			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1174				args.v2.acConfig.ucTransmitterSel = 2;
1175				break;
1176			}
1177
1178			if (is_dp) {
1179				args.v2.acConfig.fCoherentMode = 1;
1180				args.v2.acConfig.fDPConnector = 1;
1181			} else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1182				if (dig->coherent_mode)
1183					args.v2.acConfig.fCoherentMode = 1;
1184				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1185					args.v2.acConfig.fDualLinkConnector = 1;
1186			}
1187			break;
1188		case 3:
1189			args.v3.ucAction = action;
1190			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1191				args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1192			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1193				args.v3.asMode.ucLaneSel = lane_num;
1194				args.v3.asMode.ucLaneSet = lane_set;
1195			} else {
1196				if (is_dp)
1197					args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1198				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1199					args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1200				else
1201					args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1202			}
1203
1204			if (is_dp)
1205				args.v3.ucLaneNum = dp_lane_count;
1206			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1207				args.v3.ucLaneNum = 8;
1208			else
1209				args.v3.ucLaneNum = 4;
1210
1211			if (dig->linkb)
1212				args.v3.acConfig.ucLinkSel = 1;
1213			if (dig_encoder & 1)
1214				args.v3.acConfig.ucEncoderSel = 1;
1215
1216			/* Select the PLL for the PHY
1217			 * DP PHY should be clocked from external src if there is
1218			 * one.
1219			 */
1220			/* On DCE4, if there is an external clock, it generates the DP ref clock */
1221			if (is_dp && rdev->clock.dp_extclk)
1222				args.v3.acConfig.ucRefClkSource = 2; /* external src */
1223			else
1224				args.v3.acConfig.ucRefClkSource = pll_id;
1225
1226			switch (radeon_encoder->encoder_id) {
1227			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1228				args.v3.acConfig.ucTransmitterSel = 0;
1229				break;
1230			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1231				args.v3.acConfig.ucTransmitterSel = 1;
1232				break;
1233			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1234				args.v3.acConfig.ucTransmitterSel = 2;
1235				break;
1236			}
1237
1238			if (is_dp)
1239				args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1240			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1241				if (dig->coherent_mode)
1242					args.v3.acConfig.fCoherentMode = 1;
1243				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1244					args.v3.acConfig.fDualLinkConnector = 1;
1245			}
1246			break;
1247		case 4:
1248			args.v4.ucAction = action;
1249			if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1250				args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1251			} else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1252				args.v4.asMode.ucLaneSel = lane_num;
1253				args.v4.asMode.ucLaneSet = lane_set;
1254			} else {
1255				if (is_dp)
1256					args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1257				else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1258					args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1259				else
1260					args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1261			}
1262
1263			if (is_dp)
1264				args.v4.ucLaneNum = dp_lane_count;
1265			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1266				args.v4.ucLaneNum = 8;
1267			else
1268				args.v4.ucLaneNum = 4;
1269
1270			if (dig->linkb)
1271				args.v4.acConfig.ucLinkSel = 1;
1272			if (dig_encoder & 1)
1273				args.v4.acConfig.ucEncoderSel = 1;
1274
1275			/* Select the PLL for the PHY
1276			 * DP PHY should be clocked from external src if there is
1277			 * one.
1278			 */
1279			/* On DCE5 DCPLL usually generates the DP ref clock */
1280			if (is_dp) {
1281				if (rdev->clock.dp_extclk)
1282					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1283				else
1284					args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1285			} else
1286				args.v4.acConfig.ucRefClkSource = pll_id;
1287
1288			switch (radeon_encoder->encoder_id) {
1289			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1290				args.v4.acConfig.ucTransmitterSel = 0;
1291				break;
1292			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1293				args.v4.acConfig.ucTransmitterSel = 1;
1294				break;
1295			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1296				args.v4.acConfig.ucTransmitterSel = 2;
1297				break;
1298			}
1299
1300			if (is_dp)
1301				args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1302			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1303				if (dig->coherent_mode)
1304					args.v4.acConfig.fCoherentMode = 1;
1305				if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1306					args.v4.acConfig.fDualLinkConnector = 1;
1307			}
1308			break;
1309		case 5:
1310			args.v5.ucAction = action;
1311			if (is_dp)
1312				args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1313			else
1314				args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1315
1316			switch (radeon_encoder->encoder_id) {
1317			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1318				if (dig->linkb)
1319					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1320				else
1321					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1322				break;
1323			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1324				if (dig->linkb)
1325					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1326				else
1327					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1328				break;
1329			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1330				if (dig->linkb)
1331					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1332				else
1333					args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1334				break;
1335			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1336				args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1337				break;
1338			}
1339			if (is_dp)
1340				args.v5.ucLaneNum = dp_lane_count;
1341			else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1342				args.v5.ucLaneNum = 8;
1343			else
1344				args.v5.ucLaneNum = 4;
1345			args.v5.ucConnObjId = connector_object_id;
1346			args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1347
1348			if (is_dp && rdev->clock.dp_extclk)
1349				args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1350			else
1351				args.v5.asConfig.ucPhyClkSrcId = pll_id;
1352
1353			if (is_dp)
1354				args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1355			else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1356				if (dig->coherent_mode)
1357					args.v5.asConfig.ucCoherentMode = 1;
1358			}
1359			if (hpd_id == RADEON_HPD_NONE)
1360				args.v5.asConfig.ucHPDSel = 0;
1361			else
1362				args.v5.asConfig.ucHPDSel = hpd_id + 1;
1363			args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1364			args.v5.ucDPLaneSet = lane_set;
1365			break;
1366		default:
1367			DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1368			break;
1369		}
1370		break;
1371	default:
1372		DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1373		break;
1374	}
1375
1376	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1377}
1378
1379void
1380atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1381{
1382	atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1383}
1384
1385bool
1386atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1387{
1388	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1389	struct drm_device *dev = radeon_connector->base.dev;
1390	struct radeon_device *rdev = dev->dev_private;
1391	union dig_transmitter_control args;
1392	int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1393	uint8_t frev, crev;
1394
1395	if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1396		goto done;
1397
1398	if (!ASIC_IS_DCE4(rdev))
1399		goto done;
1400
1401	if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1402	    (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1403		goto done;
1404
1405	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1406		goto done;
1407
1408	memset(&args, 0, sizeof(args));
1409
1410	args.v1.ucAction = action;
1411
1412	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1413
1414	/* wait for the panel to power up */
1415	if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1416		int i;
1417
1418		for (i = 0; i < 300; i++) {
1419			if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1420				return true;
1421			mdelay(1);
1422		}
1423		return false;
1424	}
1425done:
1426	return true;
1427}
1428
1429union external_encoder_control {
1430	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1431	EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1432};
1433
1434static void
1435atombios_external_encoder_setup(struct drm_encoder *encoder,
1436				struct drm_encoder *ext_encoder,
1437				int action)
1438{
1439	struct drm_device *dev = encoder->dev;
1440	struct radeon_device *rdev = dev->dev_private;
1441	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1442	struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1443	union external_encoder_control args;
1444	struct drm_connector *connector;
1445	int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1446	u8 frev, crev;
1447	int dp_clock = 0;
1448	int dp_lane_count = 0;
1449	int connector_object_id = 0;
1450	u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1451
1452	if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1453		connector = radeon_get_connector_for_encoder_init(encoder);
1454	else
1455		connector = radeon_get_connector_for_encoder(encoder);
1456
1457	if (connector) {
1458		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1459		struct radeon_connector_atom_dig *dig_connector =
1460			radeon_connector->con_priv;
1461
1462		dp_clock = dig_connector->dp_clock;
1463		dp_lane_count = dig_connector->dp_lane_count;
1464		connector_object_id =
1465			(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1466	}
1467
1468	memset(&args, 0, sizeof(args));
1469
1470	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1471		return;
1472
1473	switch (frev) {
1474	case 1:
1475		/* no params on frev 1 */
1476		break;
1477	case 2:
1478		switch (crev) {
1479		case 1:
1480		case 2:
1481			args.v1.sDigEncoder.ucAction = action;
1482			args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1483			args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1484
1485			if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1486				if (dp_clock == 270000)
1487					args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1488				args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1489			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1490				args.v1.sDigEncoder.ucLaneNum = 8;
1491			else
1492				args.v1.sDigEncoder.ucLaneNum = 4;
1493			break;
1494		case 3:
1495			args.v3.sExtEncoder.ucAction = action;
1496			if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1497				args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1498			else
1499				args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1500			args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1501
1502			if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1503				if (dp_clock == 270000)
1504					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1505				else if (dp_clock == 540000)
1506					args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1507				args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1508			} else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1509				args.v3.sExtEncoder.ucLaneNum = 8;
1510			else
1511				args.v3.sExtEncoder.ucLaneNum = 4;
1512			switch (ext_enum) {
1513			case GRAPH_OBJECT_ENUM_ID1:
1514				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1515				break;
1516			case GRAPH_OBJECT_ENUM_ID2:
1517				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1518				break;
1519			case GRAPH_OBJECT_ENUM_ID3:
1520				args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1521				break;
1522			}
1523			args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1524			break;
1525		default:
1526			DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1527			return;
1528		}
1529		break;
1530	default:
1531		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1532		return;
1533	}
1534	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1535}
1536
1537static void
1538atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1539{
1540	struct drm_device *dev = encoder->dev;
1541	struct radeon_device *rdev = dev->dev_private;
1542	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1543	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1544	ENABLE_YUV_PS_ALLOCATION args;
1545	int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1546	uint32_t temp, reg;
1547
1548	memset(&args, 0, sizeof(args));
1549
1550	if (rdev->family >= CHIP_R600)
1551		reg = R600_BIOS_3_SCRATCH;
1552	else
1553		reg = RADEON_BIOS_3_SCRATCH;
1554
1555	/* XXX: fix up scratch reg handling */
1556	temp = RREG32(reg);
1557	if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1558		WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1559			     (radeon_crtc->crtc_id << 18)));
1560	else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1561		WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1562	else
1563		WREG32(reg, 0);
1564
1565	if (enable)
1566		args.ucEnable = ATOM_ENABLE;
1567	args.ucCRTC = radeon_crtc->crtc_id;
1568
1569	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1570
1571	WREG32(reg, temp);
1572}
1573
1574static void
1575radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1576{
1577	struct drm_device *dev = encoder->dev;
1578	struct radeon_device *rdev = dev->dev_private;
1579	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1580	DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1581	int index = 0;
1582
1583	memset(&args, 0, sizeof(args));
1584
1585	switch (radeon_encoder->encoder_id) {
1586	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1587	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1588		index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1589		break;
1590	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1591	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1592	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1593		index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1594		break;
1595	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1596		index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1597		break;
1598	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1599		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1600			index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1601		else
1602			index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1603		break;
1604	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1605	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1606		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1607			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1608		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1609			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1610		else
1611			index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1612		break;
1613	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1614	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1615		if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1616			index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1617		else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1618			index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1619		else
1620			index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1621		break;
1622	default:
1623		return;
1624	}
1625
1626	switch (mode) {
1627	case DRM_MODE_DPMS_ON:
1628		args.ucAction = ATOM_ENABLE;
1629		/* workaround for DVOOutputControl on some RS690 systems */
1630		if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1631			u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1632			WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1633			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1634			WREG32(RADEON_BIOS_3_SCRATCH, reg);
1635		} else
1636			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1637		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1638			if (rdev->mode_info.bl_encoder) {
1639				struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1640
1641				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1642			} else {
1643				args.ucAction = ATOM_LCD_BLON;
1644				atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1645			}
1646		}
1647		break;
1648	case DRM_MODE_DPMS_STANDBY:
1649	case DRM_MODE_DPMS_SUSPEND:
1650	case DRM_MODE_DPMS_OFF:
1651		args.ucAction = ATOM_DISABLE;
1652		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1653		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1654			args.ucAction = ATOM_LCD_BLOFF;
1655			atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1656		}
1657		break;
1658	}
1659}
1660
1661static void
1662radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1663{
1664	struct drm_device *dev = encoder->dev;
1665	struct radeon_device *rdev = dev->dev_private;
1666	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1667	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1668	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1669	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1670	struct radeon_connector *radeon_connector = NULL;
1671	struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1672	bool travis_quirk = false;
1673
1674	if (connector) {
1675		radeon_connector = to_radeon_connector(connector);
1676		radeon_dig_connector = radeon_connector->con_priv;
1677		if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1678		     ENCODER_OBJECT_ID_TRAVIS) &&
1679		    (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1680		    !ASIC_IS_DCE5(rdev))
1681			travis_quirk = true;
1682	}
1683
1684	switch (mode) {
1685	case DRM_MODE_DPMS_ON:
1686		if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1687			if (!connector)
1688				dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1689			else
1690				dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1691
1692			/* setup and enable the encoder */
1693			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1694			atombios_dig_encoder_setup(encoder,
1695						   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1696						   dig->panel_mode);
1697			if (ext_encoder) {
1698				if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1699					atombios_external_encoder_setup(encoder, ext_encoder,
1700									EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1701			}
1702		} else if (ASIC_IS_DCE4(rdev)) {
1703			/* setup and enable the encoder */
1704			atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1705		} else {
1706			/* setup and enable the encoder and transmitter */
1707			atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1708			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1709		}
1710		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1711			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1712				atombios_set_edp_panel_power(connector,
1713							     ATOM_TRANSMITTER_ACTION_POWER_ON);
1714				radeon_dig_connector->edp_on = true;
1715			}
1716		}
1717		/* enable the transmitter */
1718		atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1719		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1720			/* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1721			radeon_dp_link_train(encoder, connector);
1722			if (ASIC_IS_DCE4(rdev))
1723				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1724		}
1725		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1726			if (rdev->mode_info.bl_encoder)
1727				atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1728			else
1729				atombios_dig_transmitter_setup(encoder,
1730							       ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1731		}
1732		if (ext_encoder)
1733			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1734		break;
1735	case DRM_MODE_DPMS_STANDBY:
1736	case DRM_MODE_DPMS_SUSPEND:
1737	case DRM_MODE_DPMS_OFF:
1738
1739		/* don't power off encoders with active MST links */
1740		if (dig->active_mst_links)
1741			return;
1742
1743		if (ASIC_IS_DCE4(rdev)) {
1744			if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1745				atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1746		}
1747		if (ext_encoder)
1748			atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1749		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1750			atombios_dig_transmitter_setup(encoder,
1751						       ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1752
1753		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1754		    connector && !travis_quirk)
1755			radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1756		if (ASIC_IS_DCE4(rdev)) {
1757			/* disable the transmitter */
1758			atombios_dig_transmitter_setup(encoder,
1759						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1760		} else {
1761			/* disable the encoder and transmitter */
1762			atombios_dig_transmitter_setup(encoder,
1763						       ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1764			atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1765		}
1766		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1767			if (travis_quirk)
1768				radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1769			if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1770				atombios_set_edp_panel_power(connector,
1771							     ATOM_TRANSMITTER_ACTION_POWER_OFF);
1772				radeon_dig_connector->edp_on = false;
1773			}
1774		}
1775		break;
1776	}
1777}
1778
1779static void
1780radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1781{
1782	struct drm_device *dev = encoder->dev;
1783	struct radeon_device *rdev = dev->dev_private;
1784	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1785	int encoder_mode = atombios_get_encoder_mode(encoder);
1786
1787	DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1788		  radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1789		  radeon_encoder->active_device);
1790
1791	if ((radeon_audio != 0) &&
1792	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1793	     ENCODER_MODE_IS_DP(encoder_mode)))
1794		radeon_audio_dpms(encoder, mode);
1795
1796	switch (radeon_encoder->encoder_id) {
1797	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1798	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1799	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1800	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1801	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1802	case ENCODER_OBJECT_ID_INTERNAL_DDI:
1803	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1804	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1805		radeon_atom_encoder_dpms_avivo(encoder, mode);
1806		break;
1807	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1808	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1809	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1810	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1811	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1812		radeon_atom_encoder_dpms_dig(encoder, mode);
1813		break;
1814	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1815		if (ASIC_IS_DCE5(rdev)) {
1816			switch (mode) {
1817			case DRM_MODE_DPMS_ON:
1818				atombios_dvo_setup(encoder, ATOM_ENABLE);
1819				break;
1820			case DRM_MODE_DPMS_STANDBY:
1821			case DRM_MODE_DPMS_SUSPEND:
1822			case DRM_MODE_DPMS_OFF:
1823				atombios_dvo_setup(encoder, ATOM_DISABLE);
1824				break;
1825			}
1826		} else if (ASIC_IS_DCE3(rdev))
1827			radeon_atom_encoder_dpms_dig(encoder, mode);
1828		else
1829			radeon_atom_encoder_dpms_avivo(encoder, mode);
1830		break;
1831	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1832	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1833		if (ASIC_IS_DCE5(rdev)) {
1834			switch (mode) {
1835			case DRM_MODE_DPMS_ON:
1836				atombios_dac_setup(encoder, ATOM_ENABLE);
1837				break;
1838			case DRM_MODE_DPMS_STANDBY:
1839			case DRM_MODE_DPMS_SUSPEND:
1840			case DRM_MODE_DPMS_OFF:
1841				atombios_dac_setup(encoder, ATOM_DISABLE);
1842				break;
1843			}
1844		} else
1845			radeon_atom_encoder_dpms_avivo(encoder, mode);
1846		break;
1847	default:
1848		return;
1849	}
1850
1851	radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1852
1853}
1854
1855union crtc_source_param {
1856	SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1857	SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1858};
1859
1860static void
1861atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1862{
1863	struct drm_device *dev = encoder->dev;
1864	struct radeon_device *rdev = dev->dev_private;
1865	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1866	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1867	union crtc_source_param args;
1868	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1869	uint8_t frev, crev;
1870	struct radeon_encoder_atom_dig *dig;
1871
1872	memset(&args, 0, sizeof(args));
1873
1874	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1875		return;
1876
1877	switch (frev) {
1878	case 1:
1879		switch (crev) {
1880		case 1:
1881		default:
1882			if (ASIC_IS_AVIVO(rdev))
1883				args.v1.ucCRTC = radeon_crtc->crtc_id;
1884			else {
1885				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1886					args.v1.ucCRTC = radeon_crtc->crtc_id;
1887				else
1888					args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1889			}
1890			switch (radeon_encoder->encoder_id) {
1891			case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1892			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1893				args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1894				break;
1895			case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1896			case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1897				if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1898					args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1899				else
1900					args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1901				break;
1902			case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1903			case ENCODER_OBJECT_ID_INTERNAL_DDI:
1904			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1905				args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1906				break;
1907			case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1908			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1909				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1910					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1911				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1912					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1913				else
1914					args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1915				break;
1916			case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1917			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1918				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1919					args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1920				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1921					args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1922				else
1923					args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1924				break;
1925			}
1926			break;
1927		case 2:
1928			args.v2.ucCRTC = radeon_crtc->crtc_id;
1929			if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1930				struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1931
1932				if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1933					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1934				else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1935					args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1936				else
1937					args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1938			} else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1939				args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1940			} else {
1941				args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1942			}
1943			switch (radeon_encoder->encoder_id) {
1944			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1945			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1946			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1947			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1948			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1949				dig = radeon_encoder->enc_priv;
1950				switch (dig->dig_encoder) {
1951				case 0:
1952					args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1953					break;
1954				case 1:
1955					args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1956					break;
1957				case 2:
1958					args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1959					break;
1960				case 3:
1961					args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1962					break;
1963				case 4:
1964					args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1965					break;
1966				case 5:
1967					args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1968					break;
1969				case 6:
1970					args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1971					break;
1972				}
1973				break;
1974			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1975				args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1976				break;
1977			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1978				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1979					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1980				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1981					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1982				else
1983					args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1984				break;
1985			case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1986				if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1987					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1988				else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1989					args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1990				else
1991					args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1992				break;
1993			}
1994			break;
1995		}
1996		break;
1997	default:
1998		DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1999		return;
2000	}
2001
2002	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2003
2004	/* update scratch regs with new routing */
2005	radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
2006}
2007
2008void
2009atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
2010{
2011	struct drm_device *dev = encoder->dev;
2012	struct radeon_device *rdev = dev->dev_private;
2013	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2014	int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2015	uint8_t frev, crev;
2016	union crtc_source_param args;
2017
2018	memset(&args, 0, sizeof(args));
2019
2020	if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2021		return;
2022
2023	if (frev != 1 && crev != 2)
2024		DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2025
2026	args.v2.ucCRTC = radeon_crtc->crtc_id;
2027	args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2028
2029	switch (fe) {
2030	case 0:
2031		args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2032		break;
2033	case 1:
2034		args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2035		break;
2036	case 2:
2037		args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2038		break;
2039	case 3:
2040		args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2041		break;
2042	case 4:
2043		args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2044		break;
2045	case 5:
2046		args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2047		break;
2048	case 6:
2049		args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2050		break;
2051	}
2052	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2053}
2054
2055static void
2056atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2057			      struct drm_display_mode *mode)
2058{
2059	struct drm_device *dev = encoder->dev;
2060	struct radeon_device *rdev = dev->dev_private;
2061	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2062	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2063
2064	/* Funky macbooks */
2065	if ((rdev->pdev->device == 0x71C5) &&
2066	    (rdev->pdev->subsystem_vendor == 0x106b) &&
2067	    (rdev->pdev->subsystem_device == 0x0080)) {
2068		if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2069			uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2070
2071			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2072			lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2073
2074			WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2075		}
2076	}
2077
2078	/* set scaler clears this on some chips */
2079	if (ASIC_IS_AVIVO(rdev) &&
2080	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2081		if (ASIC_IS_DCE8(rdev)) {
2082			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2083				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2084				       CIK_INTERLEAVE_EN);
2085			else
2086				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2087		} else if (ASIC_IS_DCE4(rdev)) {
2088			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2089				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2090				       EVERGREEN_INTERLEAVE_EN);
2091			else
2092				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2093		} else {
2094			if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2095				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2096				       AVIVO_D1MODE_INTERLEAVE_EN);
2097			else
2098				WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2099		}
2100	}
2101}
2102
2103void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2104{
2105	if (enc_idx < 0)
2106		return;
2107	rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2108}
2109
2110int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2111{
2112	struct drm_device *dev = encoder->dev;
2113	struct radeon_device *rdev = dev->dev_private;
2114	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2115	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2116	struct drm_encoder *test_encoder;
2117	struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2118	uint32_t dig_enc_in_use = 0;
2119	int enc_idx = -1;
2120
2121	if (fe_idx >= 0) {
2122		enc_idx = fe_idx;
2123		goto assigned;
2124	}
2125	if (ASIC_IS_DCE6(rdev)) {
2126		/* DCE6 */
2127		switch (radeon_encoder->encoder_id) {
2128		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2129			if (dig->linkb)
2130				enc_idx = 1;
2131			else
2132				enc_idx = 0;
2133			break;
2134		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2135			if (dig->linkb)
2136				enc_idx = 3;
2137			else
2138				enc_idx = 2;
2139			break;
2140		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2141			if (dig->linkb)
2142				enc_idx = 5;
2143			else
2144				enc_idx = 4;
2145			break;
2146		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2147			enc_idx = 6;
2148			break;
2149		}
2150		goto assigned;
2151	} else if (ASIC_IS_DCE4(rdev)) {
2152		/* DCE4/5 */
2153		if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2154			/* ontario follows DCE4 */
2155			if (rdev->family == CHIP_PALM) {
2156				if (dig->linkb)
2157					enc_idx = 1;
2158				else
2159					enc_idx = 0;
2160			} else
2161				/* llano follows DCE3.2 */
2162				enc_idx = radeon_crtc->crtc_id;
2163		} else {
2164			switch (radeon_encoder->encoder_id) {
2165			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2166				if (dig->linkb)
2167					enc_idx = 1;
2168				else
2169					enc_idx = 0;
2170				break;
2171			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2172				if (dig->linkb)
2173					enc_idx = 3;
2174				else
2175					enc_idx = 2;
2176				break;
2177			case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2178				if (dig->linkb)
2179					enc_idx = 5;
2180				else
2181					enc_idx = 4;
2182				break;
2183			}
2184		}
2185		goto assigned;
2186	}
2187
2188	/*
2189	 * On DCE32 any encoder can drive any block so usually just use crtc id,
2190	 * but Apple thinks different at least on iMac10,1, so there use linkb,
2191	 * otherwise the internal eDP panel will stay dark.
2192	 */
2193	if (ASIC_IS_DCE32(rdev)) {
2194		if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2195			enc_idx = (dig->linkb) ? 1 : 0;
2196		else
2197			enc_idx = radeon_crtc->crtc_id;
2198
2199		goto assigned;
2200	}
2201
2202	/* on DCE3 - LVTMA can only be driven by DIGB */
2203	list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2204		struct radeon_encoder *radeon_test_encoder;
2205
2206		if (encoder == test_encoder)
2207			continue;
2208
2209		if (!radeon_encoder_is_digital(test_encoder))
2210			continue;
2211
2212		radeon_test_encoder = to_radeon_encoder(test_encoder);
2213		dig = radeon_test_encoder->enc_priv;
2214
2215		if (dig->dig_encoder >= 0)
2216			dig_enc_in_use |= (1 << dig->dig_encoder);
2217	}
2218
2219	if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2220		if (dig_enc_in_use & 0x2)
2221			DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2222		return 1;
2223	}
2224	if (!(dig_enc_in_use & 1))
2225		return 0;
2226	return 1;
2227
2228assigned:
2229	if (enc_idx == -1) {
2230		DRM_ERROR("Got encoder index incorrect - returning 0\n");
2231		return 0;
2232	}
2233	if (rdev->mode_info.active_encoders & (1 << enc_idx))
2234		DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2235
2236	rdev->mode_info.active_encoders |= (1 << enc_idx);
2237	return enc_idx;
2238}
2239
2240/* This only needs to be called once at startup */
2241void
2242radeon_atom_encoder_init(struct radeon_device *rdev)
2243{
2244	struct drm_device *dev = rdev->ddev;
2245	struct drm_encoder *encoder;
2246
2247	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2248		struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2249		struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2250
2251		switch (radeon_encoder->encoder_id) {
2252		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2253		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2254		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2255		case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2256		case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2257			atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2258			break;
2259		default:
2260			break;
2261		}
2262
2263		if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2264			atombios_external_encoder_setup(encoder, ext_encoder,
2265							EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2266	}
2267}
2268
2269static void
2270radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2271			     struct drm_display_mode *mode,
2272			     struct drm_display_mode *adjusted_mode)
2273{
2274	struct drm_device *dev = encoder->dev;
2275	struct radeon_device *rdev = dev->dev_private;
2276	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2277	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2278	int encoder_mode;
2279
2280	radeon_encoder->pixel_clock = adjusted_mode->clock;
2281
2282	/* need to call this here rather than in prepare() since we need some crtc info */
2283	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2284
2285	if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2286		if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2287			atombios_yuv_setup(encoder, true);
2288		else
2289			atombios_yuv_setup(encoder, false);
2290	}
2291
2292	switch (radeon_encoder->encoder_id) {
2293	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2294	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2295	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2296	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2297		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2298		break;
2299	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2300	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2301	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2302	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2303	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2304		/* handled in dpms */
2305		break;
2306	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2307	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2308	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2309		atombios_dvo_setup(encoder, ATOM_ENABLE);
2310		break;
2311	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2312	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2313	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2314	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2315		atombios_dac_setup(encoder, ATOM_ENABLE);
2316		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2317			if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2318				atombios_tv_setup(encoder, ATOM_ENABLE);
2319			else
2320				atombios_tv_setup(encoder, ATOM_DISABLE);
2321		}
2322		break;
2323	}
2324
2325	atombios_apply_encoder_quirks(encoder, adjusted_mode);
2326
2327	encoder_mode = atombios_get_encoder_mode(encoder);
2328	if (connector && (radeon_audio != 0) &&
2329	    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2330	     ENCODER_MODE_IS_DP(encoder_mode)))
2331		radeon_audio_mode_set(encoder, adjusted_mode);
2332}
2333
2334static bool
2335atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2336{
2337	struct drm_device *dev = encoder->dev;
2338	struct radeon_device *rdev = dev->dev_private;
2339	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2340	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2341
2342	if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2343				       ATOM_DEVICE_CV_SUPPORT |
2344				       ATOM_DEVICE_CRT_SUPPORT)) {
2345		DAC_LOAD_DETECTION_PS_ALLOCATION args;
2346		int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2347		uint8_t frev, crev;
2348
2349		memset(&args, 0, sizeof(args));
2350
2351		if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2352			return false;
2353
2354		args.sDacload.ucMisc = 0;
2355
2356		if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2357		    (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2358			args.sDacload.ucDacType = ATOM_DAC_A;
2359		else
2360			args.sDacload.ucDacType = ATOM_DAC_B;
2361
2362		if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2363			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2364		else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2365			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2366		else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2367			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2368			if (crev >= 3)
2369				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2370		} else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2371			args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2372			if (crev >= 3)
2373				args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2374		}
2375
2376		atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2377
2378		return true;
2379	} else
2380		return false;
2381}
2382
2383static enum drm_connector_status
2384radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2385{
2386	struct drm_device *dev = encoder->dev;
2387	struct radeon_device *rdev = dev->dev_private;
2388	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2389	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2390	uint32_t bios_0_scratch;
2391
2392	if (!atombios_dac_load_detect(encoder, connector)) {
2393		DRM_DEBUG_KMS("detect returned false \n");
2394		return connector_status_unknown;
2395	}
2396
2397	if (rdev->family >= CHIP_R600)
2398		bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2399	else
2400		bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2401
2402	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2403	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2404		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2405			return connector_status_connected;
2406	}
2407	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2408		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2409			return connector_status_connected;
2410	}
2411	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2412		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2413			return connector_status_connected;
2414	}
2415	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2416		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2417			return connector_status_connected; /* CTV */
2418		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2419			return connector_status_connected; /* STV */
2420	}
2421	return connector_status_disconnected;
2422}
2423
2424static enum drm_connector_status
2425radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2426{
2427	struct drm_device *dev = encoder->dev;
2428	struct radeon_device *rdev = dev->dev_private;
2429	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2430	struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2431	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2432	u32 bios_0_scratch;
2433
2434	if (!ASIC_IS_DCE4(rdev))
2435		return connector_status_unknown;
2436
2437	if (!ext_encoder)
2438		return connector_status_unknown;
2439
2440	if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2441		return connector_status_unknown;
2442
2443	/* load detect on the dp bridge */
2444	atombios_external_encoder_setup(encoder, ext_encoder,
2445					EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2446
2447	bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2448
2449	DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2450	if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2451		if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2452			return connector_status_connected;
2453	}
2454	if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2455		if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2456			return connector_status_connected;
2457	}
2458	if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2459		if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2460			return connector_status_connected;
2461	}
2462	if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2463		if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2464			return connector_status_connected; /* CTV */
2465		else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2466			return connector_status_connected; /* STV */
2467	}
2468	return connector_status_disconnected;
2469}
2470
2471void
2472radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2473{
2474	struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2475
2476	if (ext_encoder)
2477		/* ddc_setup on the dp bridge */
2478		atombios_external_encoder_setup(encoder, ext_encoder,
2479						EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2480
2481}
2482
2483static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2484{
2485	struct radeon_device *rdev = encoder->dev->dev_private;
2486	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2487	struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2488
2489	if ((radeon_encoder->active_device &
2490	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2491	    (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2492	     ENCODER_OBJECT_ID_NONE)) {
2493		struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2494		if (dig) {
2495			if (dig->dig_encoder >= 0)
2496				radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2497			dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2498			if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2499				if (rdev->family >= CHIP_R600)
2500					dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2501				else
2502					/* RS600/690/740 have only 1 afmt block */
2503					dig->afmt = rdev->mode_info.afmt[0];
2504			}
2505		}
2506	}
2507
2508	radeon_atom_output_lock(encoder, true);
2509
2510	if (connector) {
2511		struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2512
2513		/* select the clock/data port if it uses a router */
2514		if (radeon_connector->router.cd_valid)
2515			radeon_router_select_cd_port(radeon_connector);
2516
2517		/* turn eDP panel on for mode set */
2518		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2519			atombios_set_edp_panel_power(connector,
2520						     ATOM_TRANSMITTER_ACTION_POWER_ON);
2521	}
2522
2523	/* this is needed for the pll/ss setup to work correctly in some cases */
2524	atombios_set_encoder_crtc_source(encoder);
2525	/* set up the FMT blocks */
2526	if (ASIC_IS_DCE8(rdev))
2527		dce8_program_fmt(encoder);
2528	else if (ASIC_IS_DCE4(rdev))
2529		dce4_program_fmt(encoder);
2530	else if (ASIC_IS_DCE3(rdev))
2531		dce3_program_fmt(encoder);
2532	else if (ASIC_IS_AVIVO(rdev))
2533		avivo_program_fmt(encoder);
2534}
2535
2536static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2537{
2538	/* need to call this here as we need the crtc set up */
2539	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2540	radeon_atom_output_lock(encoder, false);
2541}
2542
2543static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2544{
2545	struct drm_device *dev = encoder->dev;
2546	struct radeon_device *rdev = dev->dev_private;
2547	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2548	struct radeon_encoder_atom_dig *dig;
2549
2550	/* check for pre-DCE3 cards with shared encoders;
2551	 * can't really use the links individually, so don't disable
2552	 * the encoder if it's in use by another connector
2553	 */
2554	if (!ASIC_IS_DCE3(rdev)) {
2555		struct drm_encoder *other_encoder;
2556		struct radeon_encoder *other_radeon_encoder;
2557
2558		list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2559			other_radeon_encoder = to_radeon_encoder(other_encoder);
2560			if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2561			    drm_helper_encoder_in_use(other_encoder))
2562				goto disable_done;
2563		}
2564	}
2565
2566	radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2567
2568	switch (radeon_encoder->encoder_id) {
2569	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2570	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2571	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2572	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2573		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2574		break;
2575	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2576	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2577	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2578	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2579	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2580		/* handled in dpms */
2581		break;
2582	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2583	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2584	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2585		atombios_dvo_setup(encoder, ATOM_DISABLE);
2586		break;
2587	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2588	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2589	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2590	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2591		atombios_dac_setup(encoder, ATOM_DISABLE);
2592		if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2593			atombios_tv_setup(encoder, ATOM_DISABLE);
2594		break;
2595	}
2596
2597disable_done:
2598	if (radeon_encoder_is_digital(encoder)) {
2599		if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2600			if (rdev->asic->display.hdmi_enable)
2601				radeon_hdmi_enable(rdev, encoder, false);
2602		}
2603		if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2604			dig = radeon_encoder->enc_priv;
2605			radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2606			dig->dig_encoder = -1;
2607			radeon_encoder->active_device = 0;
2608		}
2609	} else
2610		radeon_encoder->active_device = 0;
2611}
2612
2613/* these are handled by the primary encoders */
2614static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2615{
2616
2617}
2618
2619static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2620{
2621
2622}
2623
2624static void
2625radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2626			 struct drm_display_mode *mode,
2627			 struct drm_display_mode *adjusted_mode)
2628{
2629
2630}
2631
2632static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2633{
2634
2635}
2636
2637static void
2638radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2639{
2640
2641}
2642
2643static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2644	.dpms = radeon_atom_ext_dpms,
2645	.prepare = radeon_atom_ext_prepare,
2646	.mode_set = radeon_atom_ext_mode_set,
2647	.commit = radeon_atom_ext_commit,
2648	.disable = radeon_atom_ext_disable,
2649	/* no detect for TMDS/LVDS yet */
2650};
2651
2652static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2653	.dpms = radeon_atom_encoder_dpms,
2654	.mode_fixup = radeon_atom_mode_fixup,
2655	.prepare = radeon_atom_encoder_prepare,
2656	.mode_set = radeon_atom_encoder_mode_set,
2657	.commit = radeon_atom_encoder_commit,
2658	.disable = radeon_atom_encoder_disable,
2659	.detect = radeon_atom_dig_detect,
2660};
2661
2662static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2663	.dpms = radeon_atom_encoder_dpms,
2664	.mode_fixup = radeon_atom_mode_fixup,
2665	.prepare = radeon_atom_encoder_prepare,
2666	.mode_set = radeon_atom_encoder_mode_set,
2667	.commit = radeon_atom_encoder_commit,
2668	.detect = radeon_atom_dac_detect,
2669};
2670
2671void radeon_enc_destroy(struct drm_encoder *encoder)
2672{
2673	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2674	if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2675		radeon_atom_backlight_exit(radeon_encoder);
2676	kfree(radeon_encoder->enc_priv);
2677	drm_encoder_cleanup(encoder);
2678	kfree(radeon_encoder);
2679}
2680
2681static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2682	.destroy = radeon_enc_destroy,
2683};
2684
2685static struct radeon_encoder_atom_dac *
2686radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2687{
2688	struct drm_device *dev = radeon_encoder->base.dev;
2689	struct radeon_device *rdev = dev->dev_private;
2690	struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2691
2692	if (!dac)
2693		return NULL;
2694
2695	dac->tv_std = radeon_atombios_get_tv_info(rdev);
2696	return dac;
2697}
2698
2699static struct radeon_encoder_atom_dig *
2700radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2701{
2702	int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2703	struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2704
2705	if (!dig)
2706		return NULL;
2707
2708	/* coherent mode by default */
2709	dig->coherent_mode = true;
2710	dig->dig_encoder = -1;
2711
2712	if (encoder_enum == 2)
2713		dig->linkb = true;
2714	else
2715		dig->linkb = false;
2716
2717	return dig;
2718}
2719
2720void
2721radeon_add_atom_encoder(struct drm_device *dev,
2722			uint32_t encoder_enum,
2723			uint32_t supported_device,
2724			u16 caps)
2725{
2726	struct radeon_device *rdev = dev->dev_private;
2727	struct drm_encoder *encoder;
2728	struct radeon_encoder *radeon_encoder;
2729
2730	/* see if we already added it */
2731	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2732		radeon_encoder = to_radeon_encoder(encoder);
2733		if (radeon_encoder->encoder_enum == encoder_enum) {
2734			radeon_encoder->devices |= supported_device;
2735			return;
2736		}
2737
2738	}
2739
2740	/* add a new one */
2741	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2742	if (!radeon_encoder)
2743		return;
2744
2745	encoder = &radeon_encoder->base;
2746	switch (rdev->num_crtc) {
2747	case 1:
2748		encoder->possible_crtcs = 0x1;
2749		break;
2750	case 2:
2751	default:
2752		encoder->possible_crtcs = 0x3;
2753		break;
2754	case 4:
2755		encoder->possible_crtcs = 0xf;
2756		break;
2757	case 6:
2758		encoder->possible_crtcs = 0x3f;
2759		break;
2760	}
2761
2762	radeon_encoder->enc_priv = NULL;
2763
2764	radeon_encoder->encoder_enum = encoder_enum;
2765	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2766	radeon_encoder->devices = supported_device;
2767	radeon_encoder->rmx_type = RMX_OFF;
2768	radeon_encoder->underscan_type = UNDERSCAN_OFF;
2769	radeon_encoder->is_ext_encoder = false;
2770	radeon_encoder->caps = caps;
2771
2772	switch (radeon_encoder->encoder_id) {
2773	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2774	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2775	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2776	case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2777		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2778			radeon_encoder->rmx_type = RMX_FULL;
2779			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2780					 DRM_MODE_ENCODER_LVDS, NULL);
2781			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2782		} else {
2783			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2784					 DRM_MODE_ENCODER_TMDS, NULL);
2785			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2786		}
2787		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2788		break;
2789	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2790		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2791				 DRM_MODE_ENCODER_DAC, NULL);
2792		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2793		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2794		break;
2795	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2796	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2797	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2798		drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2799				 DRM_MODE_ENCODER_TVDAC, NULL);
2800		radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2801		drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2802		break;
2803	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2804	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2805	case ENCODER_OBJECT_ID_INTERNAL_DDI:
2806	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2807	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2808	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2809	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2810	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2811		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2812			radeon_encoder->rmx_type = RMX_FULL;
2813			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2814					 DRM_MODE_ENCODER_LVDS, NULL);
2815			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2816		} else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2817			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2818					 DRM_MODE_ENCODER_DAC, NULL);
2819			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2820		} else {
2821			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2822					 DRM_MODE_ENCODER_TMDS, NULL);
2823			radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2824		}
2825		drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2826		break;
2827	case ENCODER_OBJECT_ID_SI170B:
2828	case ENCODER_OBJECT_ID_CH7303:
2829	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2830	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2831	case ENCODER_OBJECT_ID_TITFP513:
2832	case ENCODER_OBJECT_ID_VT1623:
2833	case ENCODER_OBJECT_ID_HDMI_SI1930:
2834	case ENCODER_OBJECT_ID_TRAVIS:
2835	case ENCODER_OBJECT_ID_NUTMEG:
2836		/* these are handled by the primary encoders */
2837		radeon_encoder->is_ext_encoder = true;
2838		if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2839			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2840					 DRM_MODE_ENCODER_LVDS, NULL);
2841		else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2842			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2843					 DRM_MODE_ENCODER_DAC, NULL);
2844		else
2845			drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2846					 DRM_MODE_ENCODER_TMDS, NULL);
2847		drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2848		break;
2849	}
2850}