1/* SPDX-License-Identifier: MIT */
 2/*
 3 * Copyright © 2019 Intel Corporation
 4 */
 5
 6#ifndef __INTEL_PM_H__
 7#define __INTEL_PM_H__
 8
 9#include <linux/types.h>
10
11#include "display/intel_bw.h"
12#include "display/intel_display.h"
13#include "display/intel_global_state.h"
14
15#include "i915_drv.h"
16#include "i915_reg.h"
17
18struct drm_device;
19struct drm_i915_private;
20struct i915_request;
21struct intel_atomic_state;
22struct intel_crtc;
23struct intel_crtc_state;
24struct intel_plane;
25struct skl_ddb_entry;
26struct skl_pipe_wm;
27struct skl_wm_level;
28
29void intel_init_clock_gating(struct drm_i915_private *dev_priv);
30void intel_suspend_hw(struct drm_i915_private *dev_priv);
31int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
32void intel_update_watermarks(struct intel_crtc *crtc);
33void intel_init_pm(struct drm_i915_private *dev_priv);
34void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
35void intel_pm_setup(struct drm_i915_private *dev_priv);
36void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
37void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
38void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
39void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
40u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
41void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
42			       struct skl_ddb_entry *ddb_y,
43			       struct skl_ddb_entry *ddb_uv);
44void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
45u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
46			    const struct skl_ddb_entry *entry);
47void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
48			      struct skl_pipe_wm *out);
49void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
50void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
51bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
52			   const struct intel_bw_state *bw_state);
53void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
54void intel_sagv_post_plane_update(struct intel_atomic_state *state);
55const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
56					      enum plane_id plane_id,
57					      int level);
58const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
59					      enum plane_id plane_id);
60bool skl_wm_level_equals(const struct skl_wm_level *l1,
61			 const struct skl_wm_level *l2);
62bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
63				 const struct skl_ddb_entry *entries,
64				 int num_entries, int ignore_idx);
65void skl_write_plane_wm(struct intel_plane *plane,
66			const struct intel_crtc_state *crtc_state);
67void skl_write_cursor_wm(struct intel_plane *plane,
68			 const struct intel_crtc_state *crtc_state);
69bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv);
70void intel_init_ipc(struct drm_i915_private *dev_priv);
71void intel_enable_ipc(struct drm_i915_private *dev_priv);
72
73bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable);
74
75struct intel_dbuf_state {
76	struct intel_global_state base;
77
78	struct skl_ddb_entry ddb[I915_MAX_PIPES];
79	unsigned int weight[I915_MAX_PIPES];
80	u8 slices[I915_MAX_PIPES];
81	u8 enabled_slices;
82	u8 active_pipes;
83	bool joined_mbus;
84};
85
86struct intel_dbuf_state *
87intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
88
89#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
90#define intel_atomic_get_old_dbuf_state(state) \
91	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
92#define intel_atomic_get_new_dbuf_state(state) \
93	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
94
95int intel_dbuf_init(struct drm_i915_private *dev_priv);
96void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
97void intel_dbuf_post_plane_update(struct intel_atomic_state *state);
98
99#endif /* __INTEL_PM_H__ */