1/*
  2 * Copyright © 2012 Intel Corporation
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 *
 23 * Authors:
 24 *    Ben Widawsky <ben@bwidawsk.net>
 25 *
 26 */
 27
 28#include <linux/device.h>
 29#include <linux/module.h>
 30#include <linux/stat.h>
 31#include <linux/sysfs.h>
 32
 33#include "gt/intel_rc6.h"
 34#include "gt/intel_rps.h"
 35#include "gt/sysfs_engines.h"
 36
 37#include "i915_drv.h"
 38#include "i915_sysfs.h"
 39#include "intel_pm.h"
 40#include "intel_sideband.h"
 41
 42static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
 43{
 44	struct drm_minor *minor = dev_get_drvdata(kdev);
 45	return to_i915(minor->dev);
 46}
 47
 48#ifdef CONFIG_PM
 49static u32 calc_residency(struct drm_i915_private *dev_priv,
 50			  i915_reg_t reg)
 51{
 52	intel_wakeref_t wakeref;
 53	u64 res = 0;
 54
 55	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
 56		res = intel_rc6_residency_us(&dev_priv->gt.rc6, reg);
 57
 58	return DIV_ROUND_CLOSEST_ULL(res, 1000);
 59}
 60
 61static ssize_t rc6_enable_show(struct device *kdev,
 62			       struct device_attribute *attr, char *buf)
 63{
 64	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 65	unsigned int mask;
 66
 67	mask = 0;
 68	if (HAS_RC6(dev_priv))
 69		mask |= BIT(0);
 70	if (HAS_RC6p(dev_priv))
 71		mask |= BIT(1);
 72	if (HAS_RC6pp(dev_priv))
 73		mask |= BIT(2);
 74
 75	return sysfs_emit(buf, "%x\n", mask);
 76}
 77
 78static ssize_t rc6_residency_ms_show(struct device *kdev,
 79				     struct device_attribute *attr, char *buf)
 80{
 81	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 82	u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
 83	return sysfs_emit(buf, "%u\n", rc6_residency);
 84}
 85
 86static ssize_t rc6p_residency_ms_show(struct device *kdev,
 87				      struct device_attribute *attr, char *buf)
 88{
 89	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 90	u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
 91	return sysfs_emit(buf, "%u\n", rc6p_residency);
 92}
 93
 94static ssize_t rc6pp_residency_ms_show(struct device *kdev,
 95				       struct device_attribute *attr, char *buf)
 96{
 97	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 98	u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
 99	return sysfs_emit(buf, "%u\n", rc6pp_residency);
100}
101
102static ssize_t media_rc6_residency_ms_show(struct device *kdev,
103					   struct device_attribute *attr, char *buf)
104{
105	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
106	u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
107	return sysfs_emit(buf, "%u\n", rc6_residency);
108}
109
110static DEVICE_ATTR_RO(rc6_enable);
111static DEVICE_ATTR_RO(rc6_residency_ms);
112static DEVICE_ATTR_RO(rc6p_residency_ms);
113static DEVICE_ATTR_RO(rc6pp_residency_ms);
114static DEVICE_ATTR_RO(media_rc6_residency_ms);
115
116static struct attribute *rc6_attrs[] = {
117	&dev_attr_rc6_enable.attr,
118	&dev_attr_rc6_residency_ms.attr,
119	NULL
120};
121
122static const struct attribute_group rc6_attr_group = {
123	.name = power_group_name,
124	.attrs =  rc6_attrs
125};
126
127static struct attribute *rc6p_attrs[] = {
128	&dev_attr_rc6p_residency_ms.attr,
129	&dev_attr_rc6pp_residency_ms.attr,
130	NULL
131};
132
133static const struct attribute_group rc6p_attr_group = {
134	.name = power_group_name,
135	.attrs =  rc6p_attrs
136};
137
138static struct attribute *media_rc6_attrs[] = {
139	&dev_attr_media_rc6_residency_ms.attr,
140	NULL
141};
142
143static const struct attribute_group media_rc6_attr_group = {
144	.name = power_group_name,
145	.attrs =  media_rc6_attrs
146};
147#endif
148
149static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
150{
151	if (!HAS_L3_DPF(i915))
152		return -EPERM;
153
154	if (!IS_ALIGNED(offset, sizeof(u32)))
155		return -EINVAL;
156
157	if (offset >= GEN7_L3LOG_SIZE)
158		return -ENXIO;
159
160	return 0;
161}
162
163static ssize_t
164i915_l3_read(struct file *filp, struct kobject *kobj,
165	     struct bin_attribute *attr, char *buf,
166	     loff_t offset, size_t count)
167{
168	struct device *kdev = kobj_to_dev(kobj);
169	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
170	int slice = (int)(uintptr_t)attr->private;
171	int ret;
172
173	ret = l3_access_valid(i915, offset);
174	if (ret)
175		return ret;
176
177	count = round_down(count, sizeof(u32));
178	count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
179	memset(buf, 0, count);
180
181	spin_lock(&i915->gem.contexts.lock);
182	if (i915->l3_parity.remap_info[slice])
183		memcpy(buf,
184		       i915->l3_parity.remap_info[slice] + offset / sizeof(u32),
185		       count);
186	spin_unlock(&i915->gem.contexts.lock);
187
188	return count;
189}
190
191static ssize_t
192i915_l3_write(struct file *filp, struct kobject *kobj,
193	      struct bin_attribute *attr, char *buf,
194	      loff_t offset, size_t count)
195{
196	struct device *kdev = kobj_to_dev(kobj);
197	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
198	int slice = (int)(uintptr_t)attr->private;
199	u32 *remap_info, *freeme = NULL;
200	struct i915_gem_context *ctx;
201	int ret;
202
203	ret = l3_access_valid(i915, offset);
204	if (ret)
205		return ret;
206
207	if (count < sizeof(u32))
208		return -EINVAL;
209
210	remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
211	if (!remap_info)
212		return -ENOMEM;
213
214	spin_lock(&i915->gem.contexts.lock);
215
216	if (i915->l3_parity.remap_info[slice]) {
217		freeme = remap_info;
218		remap_info = i915->l3_parity.remap_info[slice];
219	} else {
220		i915->l3_parity.remap_info[slice] = remap_info;
221	}
222
223	count = round_down(count, sizeof(u32));
224	memcpy(remap_info + offset / sizeof(u32), buf, count);
225
226	/* NB: We defer the remapping until we switch to the context */
227	list_for_each_entry(ctx, &i915->gem.contexts.list, link)
228		ctx->remap_slice |= BIT(slice);
229
230	spin_unlock(&i915->gem.contexts.lock);
231	kfree(freeme);
232
233	/*
234	 * TODO: Ideally we really want a GPU reset here to make sure errors
235	 * aren't propagated. Since I cannot find a stable way to reset the GPU
236	 * at this point it is left as a TODO.
237	*/
238
239	return count;
240}
241
242static const struct bin_attribute dpf_attrs = {
243	.attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
244	.size = GEN7_L3LOG_SIZE,
245	.read = i915_l3_read,
246	.write = i915_l3_write,
247	.mmap = NULL,
248	.private = (void *)0
249};
250
251static const struct bin_attribute dpf_attrs_1 = {
252	.attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
253	.size = GEN7_L3LOG_SIZE,
254	.read = i915_l3_read,
255	.write = i915_l3_write,
256	.mmap = NULL,
257	.private = (void *)1
258};
259
260static ssize_t gt_act_freq_mhz_show(struct device *kdev,
261				    struct device_attribute *attr, char *buf)
262{
263	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
264	struct intel_rps *rps = &i915->gt.rps;
265
266	return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps));
267}
268
269static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
270				    struct device_attribute *attr, char *buf)
271{
272	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
273	struct intel_rps *rps = &i915->gt.rps;
274
275	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->cur_freq));
276}
277
278static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
279{
280	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
281	struct intel_rps *rps = &i915->gt.rps;
282
283	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->boost_freq));
284}
285
286static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
287				       struct device_attribute *attr,
288				       const char *buf, size_t count)
289{
290	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
291	struct intel_rps *rps = &dev_priv->gt.rps;
292	bool boost = false;
293	ssize_t ret;
294	u32 val;
295
296	ret = kstrtou32(buf, 0, &val);
297	if (ret)
298		return ret;
299
300	/* Validate against (static) hardware limits */
301	val = intel_freq_opcode(rps, val);
302	if (val < rps->min_freq || val > rps->max_freq)
303		return -EINVAL;
304
305	mutex_lock(&rps->lock);
306	if (val != rps->boost_freq) {
307		rps->boost_freq = val;
308		boost = atomic_read(&rps->num_waiters);
309	}
310	mutex_unlock(&rps->lock);
311	if (boost)
312		schedule_work(&rps->work);
313
314	return count;
315}
316
317static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
318				     struct device_attribute *attr, char *buf)
319{
320	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
321	struct intel_rps *rps = &dev_priv->gt.rps;
322
323	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq));
324}
325
326static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
327{
328	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
329	struct intel_rps *rps = &dev_priv->gt.rps;
330
331	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->max_freq_softlimit));
332}
333
334static ssize_t gt_max_freq_mhz_store(struct device *kdev,
335				     struct device_attribute *attr,
336				     const char *buf, size_t count)
337{
338	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
339	struct intel_rps *rps = &dev_priv->gt.rps;
340	ssize_t ret;
341	u32 val;
342
343	ret = kstrtou32(buf, 0, &val);
344	if (ret)
345		return ret;
346
347	mutex_lock(&rps->lock);
348
349	val = intel_freq_opcode(rps, val);
350	if (val < rps->min_freq ||
351	    val > rps->max_freq ||
352	    val < rps->min_freq_softlimit) {
353		ret = -EINVAL;
354		goto unlock;
355	}
356
357	if (val > rps->rp0_freq)
358		DRM_DEBUG("User requested overclocking to %d\n",
359			  intel_gpu_freq(rps, val));
360
361	rps->max_freq_softlimit = val;
362
363	val = clamp_t(int, rps->cur_freq,
364		      rps->min_freq_softlimit,
365		      rps->max_freq_softlimit);
366
367	/*
368	 * We still need *_set_rps to process the new max_delay and
369	 * update the interrupt limits and PMINTRMSK even though
370	 * frequency request may be unchanged.
371	 */
372	intel_rps_set(rps, val);
373
374unlock:
375	mutex_unlock(&rps->lock);
376
377	return ret ?: count;
378}
379
380static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
381{
382	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
383	struct intel_rps *rps = &dev_priv->gt.rps;
384
385	return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->min_freq_softlimit));
386}
387
388static ssize_t gt_min_freq_mhz_store(struct device *kdev,
389				     struct device_attribute *attr,
390				     const char *buf, size_t count)
391{
392	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
393	struct intel_rps *rps = &dev_priv->gt.rps;
394	ssize_t ret;
395	u32 val;
396
397	ret = kstrtou32(buf, 0, &val);
398	if (ret)
399		return ret;
400
401	mutex_lock(&rps->lock);
402
403	val = intel_freq_opcode(rps, val);
404	if (val < rps->min_freq ||
405	    val > rps->max_freq ||
406	    val > rps->max_freq_softlimit) {
407		ret = -EINVAL;
408		goto unlock;
409	}
410
411	rps->min_freq_softlimit = val;
412
413	val = clamp_t(int, rps->cur_freq,
414		      rps->min_freq_softlimit,
415		      rps->max_freq_softlimit);
416
417	/*
418	 * We still need *_set_rps to process the new min_delay and
419	 * update the interrupt limits and PMINTRMSK even though
420	 * frequency request may be unchanged.
421	 */
422	intel_rps_set(rps, val);
423
424unlock:
425	mutex_unlock(&rps->lock);
426
427	return ret ?: count;
428}
429
430static DEVICE_ATTR_RO(gt_act_freq_mhz);
431static DEVICE_ATTR_RO(gt_cur_freq_mhz);
432static DEVICE_ATTR_RW(gt_boost_freq_mhz);
433static DEVICE_ATTR_RW(gt_max_freq_mhz);
434static DEVICE_ATTR_RW(gt_min_freq_mhz);
435
436static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
437
438static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
439static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
440static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
441static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
442
443/* For now we have a static number of RP states */
444static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
445{
446	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
447	struct intel_rps *rps = &dev_priv->gt.rps;
448	u32 val;
449
450	if (attr == &dev_attr_gt_RP0_freq_mhz)
451		val = intel_gpu_freq(rps, rps->rp0_freq);
452	else if (attr == &dev_attr_gt_RP1_freq_mhz)
453		val = intel_gpu_freq(rps, rps->rp1_freq);
454	else if (attr == &dev_attr_gt_RPn_freq_mhz)
455		val = intel_gpu_freq(rps, rps->min_freq);
456	else
457		BUG();
458
459	return sysfs_emit(buf, "%d\n", val);
460}
461
462static const struct attribute * const gen6_attrs[] = {
463	&dev_attr_gt_act_freq_mhz.attr,
464	&dev_attr_gt_cur_freq_mhz.attr,
465	&dev_attr_gt_boost_freq_mhz.attr,
466	&dev_attr_gt_max_freq_mhz.attr,
467	&dev_attr_gt_min_freq_mhz.attr,
468	&dev_attr_gt_RP0_freq_mhz.attr,
469	&dev_attr_gt_RP1_freq_mhz.attr,
470	&dev_attr_gt_RPn_freq_mhz.attr,
471	NULL,
472};
473
474static const struct attribute * const vlv_attrs[] = {
475	&dev_attr_gt_act_freq_mhz.attr,
476	&dev_attr_gt_cur_freq_mhz.attr,
477	&dev_attr_gt_boost_freq_mhz.attr,
478	&dev_attr_gt_max_freq_mhz.attr,
479	&dev_attr_gt_min_freq_mhz.attr,
480	&dev_attr_gt_RP0_freq_mhz.attr,
481	&dev_attr_gt_RP1_freq_mhz.attr,
482	&dev_attr_gt_RPn_freq_mhz.attr,
483	&dev_attr_vlv_rpe_freq_mhz.attr,
484	NULL,
485};
486
487#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
488
489static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
490				struct bin_attribute *attr, char *buf,
491				loff_t off, size_t count)
492{
493
494	struct device *kdev = kobj_to_dev(kobj);
495	struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
496	struct i915_gpu_coredump *gpu;
497	ssize_t ret;
498
499	gpu = i915_first_error_state(i915);
500	if (IS_ERR(gpu)) {
501		ret = PTR_ERR(gpu);
502	} else if (gpu) {
503		ret = i915_gpu_coredump_copy_to_buffer(gpu, buf, off, count);
504		i915_gpu_coredump_put(gpu);
505	} else {
506		const char *str = "No error state collected\n";
507		size_t len = strlen(str);
508
509		ret = min_t(size_t, count, len - off);
510		memcpy(buf, str + off, ret);
511	}
512
513	return ret;
514}
515
516static ssize_t error_state_write(struct file *file, struct kobject *kobj,
517				 struct bin_attribute *attr, char *buf,
518				 loff_t off, size_t count)
519{
520	struct device *kdev = kobj_to_dev(kobj);
521	struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
522
523	drm_dbg(&dev_priv->drm, "Resetting error state\n");
524	i915_reset_error_state(dev_priv);
525
526	return count;
527}
528
529static const struct bin_attribute error_state_attr = {
530	.attr.name = "error",
531	.attr.mode = S_IRUSR | S_IWUSR,
532	.size = 0,
533	.read = error_state_read,
534	.write = error_state_write,
535};
536
537static void i915_setup_error_capture(struct device *kdev)
538{
539	if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
540		DRM_ERROR("error_state sysfs setup failed\n");
541}
542
543static void i915_teardown_error_capture(struct device *kdev)
544{
545	sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
546}
547#else
548static void i915_setup_error_capture(struct device *kdev) {}
549static void i915_teardown_error_capture(struct device *kdev) {}
550#endif
551
552void i915_setup_sysfs(struct drm_i915_private *dev_priv)
553{
554	struct device *kdev = dev_priv->drm.primary->kdev;
555	int ret;
556
557#ifdef CONFIG_PM
558	if (HAS_RC6(dev_priv)) {
559		ret = sysfs_merge_group(&kdev->kobj,
560					&rc6_attr_group);
561		if (ret)
562			drm_err(&dev_priv->drm,
563				"RC6 residency sysfs setup failed\n");
564	}
565	if (HAS_RC6p(dev_priv)) {
566		ret = sysfs_merge_group(&kdev->kobj,
567					&rc6p_attr_group);
568		if (ret)
569			drm_err(&dev_priv->drm,
570				"RC6p residency sysfs setup failed\n");
571	}
572	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
573		ret = sysfs_merge_group(&kdev->kobj,
574					&media_rc6_attr_group);
575		if (ret)
576			drm_err(&dev_priv->drm,
577				"Media RC6 residency sysfs setup failed\n");
578	}
579#endif
580	if (HAS_L3_DPF(dev_priv)) {
581		ret = device_create_bin_file(kdev, &dpf_attrs);
582		if (ret)
583			drm_err(&dev_priv->drm,
584				"l3 parity sysfs setup failed\n");
585
586		if (NUM_L3_SLICES(dev_priv) > 1) {
587			ret = device_create_bin_file(kdev,
588						     &dpf_attrs_1);
589			if (ret)
590				drm_err(&dev_priv->drm,
591					"l3 parity slice 1 setup failed\n");
592		}
593	}
594
595	ret = 0;
596	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
597		ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
598	else if (GRAPHICS_VER(dev_priv) >= 6)
599		ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
600	if (ret)
601		drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
602
603	i915_setup_error_capture(kdev);
604
605	intel_engines_add_sysfs(dev_priv);
606}
607
608void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
609{
610	struct device *kdev = dev_priv->drm.primary->kdev;
611
612	i915_teardown_error_capture(kdev);
613
614	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
615		sysfs_remove_files(&kdev->kobj, vlv_attrs);
616	else
617		sysfs_remove_files(&kdev->kobj, gen6_attrs);
618	device_remove_bin_file(kdev,  &dpf_attrs_1);
619	device_remove_bin_file(kdev,  &dpf_attrs);
620#ifdef CONFIG_PM
621	sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
622	sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
623#endif
624}