1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2019 Intel Corporation
  4 */
  5
  6#ifndef __I915_IRQ_H__
  7#define __I915_IRQ_H__
  8
  9#include <linux/ktime.h>
 10#include <linux/types.h>
 11
 12#include "display/intel_display.h"
 13#include "i915_reg.h"
 14
 15struct drm_crtc;
 16struct drm_device;
 17struct drm_display_mode;
 18struct drm_i915_private;
 19struct intel_crtc;
 20struct intel_uncore;
 21
 22void intel_irq_init(struct drm_i915_private *dev_priv);
 23void intel_irq_fini(struct drm_i915_private *dev_priv);
 24int intel_irq_install(struct drm_i915_private *dev_priv);
 25void intel_irq_uninstall(struct drm_i915_private *dev_priv);
 26
 27u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
 28			      enum pipe pipe);
 29void
 30i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 31		     u32 status_mask);
 32
 33void
 34i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 35		      u32 status_mask);
 36
 37void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
 38void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
 39
 40void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 41				   u32 mask,
 42				   u32 bits);
 43void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 44			    u32 interrupt_mask,
 45			    u32 enabled_irq_mask);
 46static inline void
 47ilk_enable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
 48{
 49	ilk_update_display_irq(dev_priv, bits, bits);
 50}
 51static inline void
 52ilk_disable_display_irq(struct drm_i915_private *dev_priv, u32 bits)
 53{
 54	ilk_update_display_irq(dev_priv, bits, 0);
 55}
 56void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 57			 enum pipe pipe,
 58			 u32 interrupt_mask,
 59			 u32 enabled_irq_mask);
 60static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
 61				       enum pipe pipe, u32 bits)
 62{
 63	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
 64}
 65static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
 66					enum pipe pipe, u32 bits)
 67{
 68	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
 69}
 70void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 71				  u32 interrupt_mask,
 72				  u32 enabled_irq_mask);
 73static inline void
 74ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
 75{
 76	ibx_display_interrupt_update(dev_priv, bits, bits);
 77}
 78static inline void
 79ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, u32 bits)
 80{
 81	ibx_display_interrupt_update(dev_priv, bits, 0);
 82}
 83
 84void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
 85void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, u32 mask);
 86void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 87void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
 88void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
 89void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
 90void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
 91u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask);
 92
 93void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
 94void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
 95bool intel_irqs_enabled(struct drm_i915_private *dev_priv);
 96void intel_synchronize_irq(struct drm_i915_private *i915);
 97void intel_synchronize_hardirq(struct drm_i915_private *i915);
 98
 99int intel_get_crtc_scanline(struct intel_crtc *crtc);
100void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
101				     u8 pipe_mask);
102void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
103				     u8 pipe_mask);
104u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
105
106bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
107				     ktime_t *vblank_time, bool in_vblank_irq);
108
109u32 i915_get_vblank_counter(struct drm_crtc *crtc);
110u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
111
112int i8xx_enable_vblank(struct drm_crtc *crtc);
113int i915gm_enable_vblank(struct drm_crtc *crtc);
114int i965_enable_vblank(struct drm_crtc *crtc);
115int ilk_enable_vblank(struct drm_crtc *crtc);
116int bdw_enable_vblank(struct drm_crtc *crtc);
117void i8xx_disable_vblank(struct drm_crtc *crtc);
118void i915gm_disable_vblank(struct drm_crtc *crtc);
119void i965_disable_vblank(struct drm_crtc *crtc);
120void ilk_disable_vblank(struct drm_crtc *crtc);
121void bdw_disable_vblank(struct drm_crtc *crtc);
122
123void gen2_irq_reset(struct intel_uncore *uncore);
124void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
125		    i915_reg_t iir, i915_reg_t ier);
126
127void gen2_irq_init(struct intel_uncore *uncore,
128		   u32 imr_val, u32 ier_val);
129void gen3_irq_init(struct intel_uncore *uncore,
130		   i915_reg_t imr, u32 imr_val,
131		   i915_reg_t ier, u32 ier_val,
132		   i915_reg_t iir);
133
134#define GEN8_IRQ_RESET_NDX(uncore, type, which) \
135({ \
136	unsigned int which_ = which; \
137	gen3_irq_reset((uncore), GEN8_##type##_IMR(which_), \
138		       GEN8_##type##_IIR(which_), GEN8_##type##_IER(which_)); \
139})
140
141#define GEN3_IRQ_RESET(uncore, type) \
142	gen3_irq_reset((uncore), type##IMR, type##IIR, type##IER)
143
144#define GEN2_IRQ_RESET(uncore) \
145	gen2_irq_reset(uncore)
146
147#define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
148({ \
149	unsigned int which_ = which; \
150	gen3_irq_init((uncore), \
151		      GEN8_##type##_IMR(which_), imr_val, \
152		      GEN8_##type##_IER(which_), ier_val, \
153		      GEN8_##type##_IIR(which_)); \
154})
155
156#define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
157	gen3_irq_init((uncore), \
158		      type##IMR, imr_val, \
159		      type##IER, ier_val, \
160		      type##IIR)
161
162#define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
163	gen2_irq_init((uncore), imr_val, ier_val)
164
165#endif /* __I915_IRQ_H__ */