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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/kernel.h>
26#include <linux/firmware.h>
27#include <linux/module.h>
28#include <linux/pci.h>
29#include "amdgpu.h"
30#include "amdgpu_gfx.h"
31#include "amdgpu_psp.h"
32#include "nv.h"
33#include "nvd.h"
34
35#include "gc/gc_10_1_0_offset.h"
36#include "gc/gc_10_1_0_sh_mask.h"
37#include "smuio/smuio_11_0_0_offset.h"
38#include "smuio/smuio_11_0_0_sh_mask.h"
39#include "navi10_enum.h"
40#include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42#include "soc15.h"
43#include "soc15d.h"
44#include "soc15_common.h"
45#include "clearstate_gfx10.h"
46#include "v10_structs.h"
47#include "gfx_v10_0.h"
48#include "nbio_v2_3.h"
49
50/*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55#define GFX10_NUM_GFX_RINGS_NV1X 1
56#define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 1
57#define GFX10_MEC_HPD_SIZE 2048
58
59#define F32_CE_PROGRAM_RAM_SIZE 65536
60#define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61
62#define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63#define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64#define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65#define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66#define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67#define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68
69#define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70#define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71
72#define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73#define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74#define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75#define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76
77#define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78#define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79#define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80#define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82#define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83#define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84#define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86#define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88#define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89#define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90#define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92#define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94#define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96#define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98#define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102#define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104
105#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
106#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
107#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
108#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
109#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
110#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
111#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
112#define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
113#define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
114#define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
115#define mmVGT_TF_RING_SIZE_Vangogh 0x224e
116#define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
117#define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
118#define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
119#define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
120#define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
121#define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
122#define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
123#define mmSPI_CONFIG_CNTL_Vangogh 0x2440
124#define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
125#define mmGCR_GENERAL_CNTL_Vangogh 0x1580
126#define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
127#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
128
129#define mmCP_HYP_PFP_UCODE_ADDR 0x5814
130#define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
131#define mmCP_HYP_PFP_UCODE_DATA 0x5815
132#define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
133#define mmCP_HYP_CE_UCODE_ADDR 0x5818
134#define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
135#define mmCP_HYP_CE_UCODE_DATA 0x5819
136#define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
137#define mmCP_HYP_ME_UCODE_ADDR 0x5816
138#define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
139#define mmCP_HYP_ME_UCODE_DATA 0x5817
140#define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
141
142#define mmCPG_PSP_DEBUG 0x5c10
143#define mmCPG_PSP_DEBUG_BASE_IDX 1
144#define mmCPC_PSP_DEBUG 0x5c11
145#define mmCPC_PSP_DEBUG_BASE_IDX 1
146#define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
147#define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
148
149//CC_GC_SA_UNIT_DISABLE
150#define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
151#define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
152#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
153#define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
154//GC_USER_SA_UNIT_DISABLE
155#define mmGC_USER_SA_UNIT_DISABLE 0x0fea
156#define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
157#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
158#define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
159//PA_SC_ENHANCE_3
160#define mmPA_SC_ENHANCE_3 0x1085
161#define mmPA_SC_ENHANCE_3_BASE_IDX 0
162#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
163#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
164
165#define mmCGTT_SPI_CS_CLK_CTRL 0x507c
166#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
167
168#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
169#define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
170#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
171#define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
172
173#define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
174#define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
175
176#define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
177#define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
178
179#define GFX_RLCG_GC_WRITE_OLD (0x8 << 28)
180#define GFX_RLCG_GC_WRITE (0x0 << 28)
181#define GFX_RLCG_GC_READ (0x1 << 28)
182#define GFX_RLCG_MMHUB_WRITE (0x2 << 28)
183
184MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
185MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
186MODULE_FIRMWARE("amdgpu/navi10_me.bin");
187MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
188MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
189MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
190
191MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
192MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
193MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
194MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
195MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
196MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
197MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
198MODULE_FIRMWARE("amdgpu/navi14_me.bin");
199MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
200MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
201MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
202
203MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
204MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
205MODULE_FIRMWARE("amdgpu/navi12_me.bin");
206MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
207MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
208MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
209
210MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
211MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
212MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
213MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
214MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
215MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
216
217MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
218MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
219MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
220MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
221MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
222MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
223
224MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
225MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
226MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
227MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
228MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
229MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
230
231MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
232MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
233MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
234MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
235MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
236MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
237
238MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
239MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
240MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
241MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
242MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
243MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
244
245MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
246MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
247MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
248MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
249MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
250MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
251
252static const struct soc15_reg_golden golden_settings_gc_10_1[] =
253{
254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
294};
295
296static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
297{
298 /* Pending on emulation bring up */
299};
300
301static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
302{
303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1355};
1356
1357static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1358{
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1397};
1398
1399static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1400{
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1443};
1444
1445static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
1446 int write, u32 *rlcg_flag)
1447{
1448 switch (hwip) {
1449 case GC_HWIP:
1450 if (amdgpu_sriov_reg_indirect_gc(adev)) {
1451 *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
1452
1453 return true;
1454 /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
1455 } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
1456 *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
1457
1458 return true;
1459 }
1460
1461 break;
1462 case MMHUB_HWIP:
1463 if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
1464 (acc_flags & AMDGPU_REGS_RLC) && write) {
1465 *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
1466 return true;
1467 }
1468
1469 break;
1470 default:
1471 DRM_DEBUG("Not program register by RLCG\n");
1472 }
1473
1474 return false;
1475}
1476
1477static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
1478{
1479 static void *scratch_reg0;
1480 static void *scratch_reg1;
1481 static void *scratch_reg2;
1482 static void *scratch_reg3;
1483 static void *spare_int;
1484 static uint32_t grbm_cntl;
1485 static uint32_t grbm_idx;
1486 uint32_t i = 0;
1487 uint32_t retries = 50000;
1488 u32 ret = 0;
1489
1490 scratch_reg0 = adev->rmmio +
1491 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0) * 4;
1492 scratch_reg1 = adev->rmmio +
1493 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1) * 4;
1494 scratch_reg2 = adev->rmmio +
1495 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG2) * 4;
1496 scratch_reg3 = adev->rmmio +
1497 (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3) * 4;
1498
1499 if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
1500 spare_int = adev->rmmio +
1501 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX]
1502 + mmRLC_SPARE_INT_0_Sienna_Cichlid) * 4;
1503 } else {
1504 spare_int = adev->rmmio +
1505 (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT) * 4;
1506 }
1507
1508 grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1509 grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1510
1511 if (offset == grbm_cntl || offset == grbm_idx) {
1512 if (offset == grbm_cntl)
1513 writel(v, scratch_reg2);
1514 else if (offset == grbm_idx)
1515 writel(v, scratch_reg3);
1516
1517 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
1518 } else {
1519 writel(v, scratch_reg0);
1520 writel(offset | flag, scratch_reg1);
1521 writel(1, spare_int);
1522 for (i = 0; i < retries; i++) {
1523 u32 tmp;
1524
1525 tmp = readl(scratch_reg1);
1526 if (!(tmp & flag))
1527 break;
1528
1529 udelay(10);
1530 }
1531
1532 if (i >= retries)
1533 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1534 }
1535
1536 ret = readl(scratch_reg0);
1537
1538 return ret;
1539}
1540
1541static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
1542{
1543 u32 rlcg_flag;
1544
1545 if (!amdgpu_sriov_runtime(adev) &&
1546 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
1547 gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
1548 return;
1549 }
1550
1551 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1552 WREG32_NO_KIQ(offset, value);
1553 else
1554 WREG32(offset, value);
1555}
1556
1557static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
1558{
1559 u32 rlcg_flag;
1560
1561 if (!amdgpu_sriov_runtime(adev) &&
1562 gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
1563 return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
1564
1565 if (acc_flags & AMDGPU_REGS_NO_KIQ)
1566 return RREG32_NO_KIQ(offset);
1567 else
1568 return RREG32(offset);
1569}
1570
1571static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1572{
1573 /* Pending on emulation bring up */
1574};
1575
1576static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1577{
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2198};
2199
2200static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2201{
2202 /* Pending on emulation bring up */
2203};
2204
2205static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2206{
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3259};
3260
3261static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3262{
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3271 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3306};
3307
3308static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3309{
3310 /* Pending on emulation bring up */
3311};
3312
3313static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3314{
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3356
3357 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3359};
3360
3361static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3362{
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3387
3388 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3390};
3391
3392static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3393{
3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3414};
3415
3416static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3417{
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3454};
3455
3456static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3489};
3490
3491#define DEFAULT_SH_MEM_CONFIG \
3492 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3493 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3494 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3495 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3496
3497
3498static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3499static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3500static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3501static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3502static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3503 struct amdgpu_cu_info *cu_info);
3504static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3505static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3506 u32 sh_num, u32 instance);
3507static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3508
3509static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3510static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3511static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3512static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3513static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3514static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3515static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3516static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3517static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3518static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3519
3520static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3521{
3522 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3523 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3524 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3525 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3526 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3527 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3528 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3529 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3530 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3531}
3532
3533static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3534 struct amdgpu_ring *ring)
3535{
3536 struct amdgpu_device *adev = kiq_ring->adev;
3537 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3538 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3539 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3540
3541 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3542 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3543 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3544 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3545 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3546 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3547 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3548 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3549 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3550 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3551 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3552 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3553 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3554 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3555 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3556 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3557 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3558}
3559
3560static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3561 struct amdgpu_ring *ring,
3562 enum amdgpu_unmap_queues_action action,
3563 u64 gpu_addr, u64 seq)
3564{
3565 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3566
3567 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3568 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3569 PACKET3_UNMAP_QUEUES_ACTION(action) |
3570 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3571 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3572 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3573 amdgpu_ring_write(kiq_ring,
3574 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3575
3576 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3577 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3578 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3579 amdgpu_ring_write(kiq_ring, seq);
3580 } else {
3581 amdgpu_ring_write(kiq_ring, 0);
3582 amdgpu_ring_write(kiq_ring, 0);
3583 amdgpu_ring_write(kiq_ring, 0);
3584 }
3585}
3586
3587static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3588 struct amdgpu_ring *ring,
3589 u64 addr,
3590 u64 seq)
3591{
3592 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3593
3594 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3595 amdgpu_ring_write(kiq_ring,
3596 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3597 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3598 PACKET3_QUERY_STATUS_COMMAND(2));
3599 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3600 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3601 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3602 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3603 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3604 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3605 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3606}
3607
3608static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3609 uint16_t pasid, uint32_t flush_type,
3610 bool all_hub)
3611{
3612 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3613 amdgpu_ring_write(kiq_ring,
3614 PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3615 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3616 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3617 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3618}
3619
3620static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3621 .kiq_set_resources = gfx10_kiq_set_resources,
3622 .kiq_map_queues = gfx10_kiq_map_queues,
3623 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3624 .kiq_query_status = gfx10_kiq_query_status,
3625 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3626 .set_resources_size = 8,
3627 .map_queues_size = 7,
3628 .unmap_queues_size = 6,
3629 .query_status_size = 7,
3630 .invalidate_tlbs_size = 2,
3631};
3632
3633static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3634{
3635 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3636}
3637
3638static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3639{
3640 switch (adev->asic_type) {
3641 case CHIP_NAVI10:
3642 soc15_program_register_sequence(adev,
3643 golden_settings_gc_rlc_spm_10_0_nv10,
3644 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3645 break;
3646 case CHIP_NAVI14:
3647 soc15_program_register_sequence(adev,
3648 golden_settings_gc_rlc_spm_10_1_nv14,
3649 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3650 break;
3651 case CHIP_NAVI12:
3652 soc15_program_register_sequence(adev,
3653 golden_settings_gc_rlc_spm_10_1_2_nv12,
3654 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3655 break;
3656 default:
3657 break;
3658 }
3659}
3660
3661static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3662{
3663 switch (adev->asic_type) {
3664 case CHIP_NAVI10:
3665 soc15_program_register_sequence(adev,
3666 golden_settings_gc_10_1,
3667 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3668 soc15_program_register_sequence(adev,
3669 golden_settings_gc_10_0_nv10,
3670 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3671 break;
3672 case CHIP_NAVI14:
3673 soc15_program_register_sequence(adev,
3674 golden_settings_gc_10_1_1,
3675 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3676 soc15_program_register_sequence(adev,
3677 golden_settings_gc_10_1_nv14,
3678 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3679 break;
3680 case CHIP_NAVI12:
3681 soc15_program_register_sequence(adev,
3682 golden_settings_gc_10_1_2,
3683 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3684 soc15_program_register_sequence(adev,
3685 golden_settings_gc_10_1_2_nv12,
3686 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3687 break;
3688 case CHIP_SIENNA_CICHLID:
3689 soc15_program_register_sequence(adev,
3690 golden_settings_gc_10_3,
3691 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3692 soc15_program_register_sequence(adev,
3693 golden_settings_gc_10_3_sienna_cichlid,
3694 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3695 break;
3696 case CHIP_NAVY_FLOUNDER:
3697 soc15_program_register_sequence(adev,
3698 golden_settings_gc_10_3_2,
3699 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3700 break;
3701 case CHIP_VANGOGH:
3702 soc15_program_register_sequence(adev,
3703 golden_settings_gc_10_3_vangogh,
3704 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3705 break;
3706 case CHIP_YELLOW_CARP:
3707 soc15_program_register_sequence(adev,
3708 golden_settings_gc_10_3_3,
3709 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3710 break;
3711 case CHIP_DIMGREY_CAVEFISH:
3712 soc15_program_register_sequence(adev,
3713 golden_settings_gc_10_3_4,
3714 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3715 break;
3716 case CHIP_BEIGE_GOBY:
3717 soc15_program_register_sequence(adev,
3718 golden_settings_gc_10_3_5,
3719 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3720 break;
3721 default:
3722 break;
3723 }
3724 gfx_v10_0_init_spm_golden_registers(adev);
3725}
3726
3727static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3728{
3729 adev->gfx.scratch.num_reg = 8;
3730 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3731 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3732}
3733
3734static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3735 bool wc, uint32_t reg, uint32_t val)
3736{
3737 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3738 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3739 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3740 amdgpu_ring_write(ring, reg);
3741 amdgpu_ring_write(ring, 0);
3742 amdgpu_ring_write(ring, val);
3743}
3744
3745static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3746 int mem_space, int opt, uint32_t addr0,
3747 uint32_t addr1, uint32_t ref, uint32_t mask,
3748 uint32_t inv)
3749{
3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3751 amdgpu_ring_write(ring,
3752 /* memory (1) or register (0) */
3753 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3754 WAIT_REG_MEM_OPERATION(opt) | /* wait */
3755 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3756 WAIT_REG_MEM_ENGINE(eng_sel)));
3757
3758 if (mem_space)
3759 BUG_ON(addr0 & 0x3); /* Dword align */
3760 amdgpu_ring_write(ring, addr0);
3761 amdgpu_ring_write(ring, addr1);
3762 amdgpu_ring_write(ring, ref);
3763 amdgpu_ring_write(ring, mask);
3764 amdgpu_ring_write(ring, inv); /* poll interval */
3765}
3766
3767static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3768{
3769 struct amdgpu_device *adev = ring->adev;
3770 uint32_t scratch;
3771 uint32_t tmp = 0;
3772 unsigned i;
3773 int r;
3774
3775 r = amdgpu_gfx_scratch_get(adev, &scratch);
3776 if (r) {
3777 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3778 return r;
3779 }
3780
3781 WREG32(scratch, 0xCAFEDEAD);
3782
3783 r = amdgpu_ring_alloc(ring, 3);
3784 if (r) {
3785 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3786 ring->idx, r);
3787 amdgpu_gfx_scratch_free(adev, scratch);
3788 return r;
3789 }
3790
3791 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3792 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3793 amdgpu_ring_write(ring, 0xDEADBEEF);
3794 amdgpu_ring_commit(ring);
3795
3796 for (i = 0; i < adev->usec_timeout; i++) {
3797 tmp = RREG32(scratch);
3798 if (tmp == 0xDEADBEEF)
3799 break;
3800 if (amdgpu_emu_mode == 1)
3801 msleep(1);
3802 else
3803 udelay(1);
3804 }
3805
3806 if (i >= adev->usec_timeout)
3807 r = -ETIMEDOUT;
3808
3809 amdgpu_gfx_scratch_free(adev, scratch);
3810
3811 return r;
3812}
3813
3814static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3815{
3816 struct amdgpu_device *adev = ring->adev;
3817 struct amdgpu_ib ib;
3818 struct dma_fence *f = NULL;
3819 unsigned index;
3820 uint64_t gpu_addr;
3821 uint32_t tmp;
3822 long r;
3823
3824 r = amdgpu_device_wb_get(adev, &index);
3825 if (r)
3826 return r;
3827
3828 gpu_addr = adev->wb.gpu_addr + (index * 4);
3829 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3830 memset(&ib, 0, sizeof(ib));
3831 r = amdgpu_ib_get(adev, NULL, 16,
3832 AMDGPU_IB_POOL_DIRECT, &ib);
3833 if (r)
3834 goto err1;
3835
3836 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3837 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3838 ib.ptr[2] = lower_32_bits(gpu_addr);
3839 ib.ptr[3] = upper_32_bits(gpu_addr);
3840 ib.ptr[4] = 0xDEADBEEF;
3841 ib.length_dw = 5;
3842
3843 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3844 if (r)
3845 goto err2;
3846
3847 r = dma_fence_wait_timeout(f, false, timeout);
3848 if (r == 0) {
3849 r = -ETIMEDOUT;
3850 goto err2;
3851 } else if (r < 0) {
3852 goto err2;
3853 }
3854
3855 tmp = adev->wb.wb[index];
3856 if (tmp == 0xDEADBEEF)
3857 r = 0;
3858 else
3859 r = -EINVAL;
3860err2:
3861 amdgpu_ib_free(adev, &ib, NULL);
3862 dma_fence_put(f);
3863err1:
3864 amdgpu_device_wb_free(adev, index);
3865 return r;
3866}
3867
3868static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3869{
3870 release_firmware(adev->gfx.pfp_fw);
3871 adev->gfx.pfp_fw = NULL;
3872 release_firmware(adev->gfx.me_fw);
3873 adev->gfx.me_fw = NULL;
3874 release_firmware(adev->gfx.ce_fw);
3875 adev->gfx.ce_fw = NULL;
3876 release_firmware(adev->gfx.rlc_fw);
3877 adev->gfx.rlc_fw = NULL;
3878 release_firmware(adev->gfx.mec_fw);
3879 adev->gfx.mec_fw = NULL;
3880 release_firmware(adev->gfx.mec2_fw);
3881 adev->gfx.mec2_fw = NULL;
3882
3883 kfree(adev->gfx.rlc.register_list_format);
3884}
3885
3886static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3887{
3888 adev->gfx.cp_fw_write_wait = false;
3889
3890 switch (adev->asic_type) {
3891 case CHIP_NAVI10:
3892 case CHIP_NAVI12:
3893 case CHIP_NAVI14:
3894 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3895 (adev->gfx.me_feature_version >= 27) &&
3896 (adev->gfx.pfp_fw_version >= 0x00000068) &&
3897 (adev->gfx.pfp_feature_version >= 27) &&
3898 (adev->gfx.mec_fw_version >= 0x0000005b) &&
3899 (adev->gfx.mec_feature_version >= 27))
3900 adev->gfx.cp_fw_write_wait = true;
3901 break;
3902 case CHIP_SIENNA_CICHLID:
3903 case CHIP_NAVY_FLOUNDER:
3904 case CHIP_VANGOGH:
3905 case CHIP_DIMGREY_CAVEFISH:
3906 case CHIP_BEIGE_GOBY:
3907 case CHIP_YELLOW_CARP:
3908 adev->gfx.cp_fw_write_wait = true;
3909 break;
3910 default:
3911 break;
3912 }
3913
3914 if (!adev->gfx.cp_fw_write_wait)
3915 DRM_WARN_ONCE("CP firmware version too old, please update!");
3916}
3917
3918
3919static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3920{
3921 const struct rlc_firmware_header_v2_1 *rlc_hdr;
3922
3923 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3924 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3925 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3926 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3927 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3928 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3929 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3930 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3931 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3932 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3933 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3934 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3935 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3936 adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3937 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3938}
3939
3940static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3941{
3942 const struct rlc_firmware_header_v2_2 *rlc_hdr;
3943
3944 rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3945 adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3946 adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3947 adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3948 adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3949}
3950
3951static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3952{
3953 bool ret = false;
3954
3955 switch (adev->pdev->revision) {
3956 case 0xc2:
3957 case 0xc3:
3958 ret = true;
3959 break;
3960 default:
3961 ret = false;
3962 break;
3963 }
3964
3965 return ret ;
3966}
3967
3968static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3969{
3970 switch (adev->asic_type) {
3971 case CHIP_NAVI10:
3972 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3973 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3974 break;
3975 default:
3976 break;
3977 }
3978}
3979
3980static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3981{
3982 const char *chip_name;
3983 char fw_name[40];
3984 char *wks = "";
3985 int err;
3986 struct amdgpu_firmware_info *info = NULL;
3987 const struct common_firmware_header *header = NULL;
3988 const struct gfx_firmware_header_v1_0 *cp_hdr;
3989 const struct rlc_firmware_header_v2_0 *rlc_hdr;
3990 unsigned int *tmp = NULL;
3991 unsigned int i = 0;
3992 uint16_t version_major;
3993 uint16_t version_minor;
3994
3995 DRM_DEBUG("\n");
3996
3997 switch (adev->asic_type) {
3998 case CHIP_NAVI10:
3999 chip_name = "navi10";
4000 break;
4001 case CHIP_NAVI14:
4002 chip_name = "navi14";
4003 if (!(adev->pdev->device == 0x7340 &&
4004 adev->pdev->revision != 0x00))
4005 wks = "_wks";
4006 break;
4007 case CHIP_NAVI12:
4008 chip_name = "navi12";
4009 break;
4010 case CHIP_SIENNA_CICHLID:
4011 chip_name = "sienna_cichlid";
4012 break;
4013 case CHIP_NAVY_FLOUNDER:
4014 chip_name = "navy_flounder";
4015 break;
4016 case CHIP_VANGOGH:
4017 chip_name = "vangogh";
4018 break;
4019 case CHIP_DIMGREY_CAVEFISH:
4020 chip_name = "dimgrey_cavefish";
4021 break;
4022 case CHIP_BEIGE_GOBY:
4023 chip_name = "beige_goby";
4024 break;
4025 case CHIP_YELLOW_CARP:
4026 chip_name = "yellow_carp";
4027 break;
4028 default:
4029 BUG();
4030 }
4031
4032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4033 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4034 if (err)
4035 goto out;
4036 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4037 if (err)
4038 goto out;
4039 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4040 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4041 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4042
4043 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4044 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4045 if (err)
4046 goto out;
4047 err = amdgpu_ucode_validate(adev->gfx.me_fw);
4048 if (err)
4049 goto out;
4050 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4051 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4052 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4053
4054 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4055 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4056 if (err)
4057 goto out;
4058 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4059 if (err)
4060 goto out;
4061 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4062 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4063 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4064
4065 if (!amdgpu_sriov_vf(adev)) {
4066 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4067 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4068 if (err)
4069 goto out;
4070 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4071 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4072 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4073 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4074
4075 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4076 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4077 adev->gfx.rlc.save_and_restore_offset =
4078 le32_to_cpu(rlc_hdr->save_and_restore_offset);
4079 adev->gfx.rlc.clear_state_descriptor_offset =
4080 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4081 adev->gfx.rlc.avail_scratch_ram_locations =
4082 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4083 adev->gfx.rlc.reg_restore_list_size =
4084 le32_to_cpu(rlc_hdr->reg_restore_list_size);
4085 adev->gfx.rlc.reg_list_format_start =
4086 le32_to_cpu(rlc_hdr->reg_list_format_start);
4087 adev->gfx.rlc.reg_list_format_separate_start =
4088 le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4089 adev->gfx.rlc.starting_offsets_start =
4090 le32_to_cpu(rlc_hdr->starting_offsets_start);
4091 adev->gfx.rlc.reg_list_format_size_bytes =
4092 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4093 adev->gfx.rlc.reg_list_size_bytes =
4094 le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4095 adev->gfx.rlc.register_list_format =
4096 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4097 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4098 if (!adev->gfx.rlc.register_list_format) {
4099 err = -ENOMEM;
4100 goto out;
4101 }
4102
4103 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4104 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4105 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4106 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4107
4108 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4109
4110 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4111 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4112 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4113 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4114
4115 if (version_major == 2) {
4116 if (version_minor >= 1)
4117 gfx_v10_0_init_rlc_ext_microcode(adev);
4118 if (version_minor == 2)
4119 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4120 }
4121 }
4122
4123 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4124 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4125 if (err)
4126 goto out;
4127 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4128 if (err)
4129 goto out;
4130 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4131 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4132 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4133
4134 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4135 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4136 if (!err) {
4137 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4138 if (err)
4139 goto out;
4140 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4141 adev->gfx.mec2_fw->data;
4142 adev->gfx.mec2_fw_version =
4143 le32_to_cpu(cp_hdr->header.ucode_version);
4144 adev->gfx.mec2_feature_version =
4145 le32_to_cpu(cp_hdr->ucode_feature_version);
4146 } else {
4147 err = 0;
4148 adev->gfx.mec2_fw = NULL;
4149 }
4150
4151 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4152 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4153 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4154 info->fw = adev->gfx.pfp_fw;
4155 header = (const struct common_firmware_header *)info->fw->data;
4156 adev->firmware.fw_size +=
4157 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4158
4159 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4160 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4161 info->fw = adev->gfx.me_fw;
4162 header = (const struct common_firmware_header *)info->fw->data;
4163 adev->firmware.fw_size +=
4164 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4165
4166 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4167 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4168 info->fw = adev->gfx.ce_fw;
4169 header = (const struct common_firmware_header *)info->fw->data;
4170 adev->firmware.fw_size +=
4171 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4172
4173 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4174 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4175 info->fw = adev->gfx.rlc_fw;
4176 if (info->fw) {
4177 header = (const struct common_firmware_header *)info->fw->data;
4178 adev->firmware.fw_size +=
4179 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4180 }
4181 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4182 adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4183 adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4184 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4185 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4186 info->fw = adev->gfx.rlc_fw;
4187 adev->firmware.fw_size +=
4188 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4189
4190 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4191 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4192 info->fw = adev->gfx.rlc_fw;
4193 adev->firmware.fw_size +=
4194 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4195
4196 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4197 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4198 info->fw = adev->gfx.rlc_fw;
4199 adev->firmware.fw_size +=
4200 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4201
4202 if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4203 adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4204 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4205 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4206 info->fw = adev->gfx.rlc_fw;
4207 adev->firmware.fw_size +=
4208 ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4209
4210 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4211 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4212 info->fw = adev->gfx.rlc_fw;
4213 adev->firmware.fw_size +=
4214 ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4215 }
4216 }
4217
4218 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4219 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4220 info->fw = adev->gfx.mec_fw;
4221 header = (const struct common_firmware_header *)info->fw->data;
4222 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4223 adev->firmware.fw_size +=
4224 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4225 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4226
4227 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4228 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4229 info->fw = adev->gfx.mec_fw;
4230 adev->firmware.fw_size +=
4231 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4232
4233 if (adev->gfx.mec2_fw) {
4234 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4235 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4236 info->fw = adev->gfx.mec2_fw;
4237 header = (const struct common_firmware_header *)info->fw->data;
4238 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4239 adev->firmware.fw_size +=
4240 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4241 le32_to_cpu(cp_hdr->jt_size) * 4,
4242 PAGE_SIZE);
4243 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4244 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4245 info->fw = adev->gfx.mec2_fw;
4246 adev->firmware.fw_size +=
4247 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4248 PAGE_SIZE);
4249 }
4250 }
4251
4252 gfx_v10_0_check_fw_write_wait(adev);
4253out:
4254 if (err) {
4255 dev_err(adev->dev,
4256 "gfx10: Failed to load firmware \"%s\"\n",
4257 fw_name);
4258 release_firmware(adev->gfx.pfp_fw);
4259 adev->gfx.pfp_fw = NULL;
4260 release_firmware(adev->gfx.me_fw);
4261 adev->gfx.me_fw = NULL;
4262 release_firmware(adev->gfx.ce_fw);
4263 adev->gfx.ce_fw = NULL;
4264 release_firmware(adev->gfx.rlc_fw);
4265 adev->gfx.rlc_fw = NULL;
4266 release_firmware(adev->gfx.mec_fw);
4267 adev->gfx.mec_fw = NULL;
4268 release_firmware(adev->gfx.mec2_fw);
4269 adev->gfx.mec2_fw = NULL;
4270 }
4271
4272 gfx_v10_0_check_gfxoff_flag(adev);
4273
4274 return err;
4275}
4276
4277static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4278{
4279 u32 count = 0;
4280 const struct cs_section_def *sect = NULL;
4281 const struct cs_extent_def *ext = NULL;
4282
4283 /* begin clear state */
4284 count += 2;
4285 /* context control state */
4286 count += 3;
4287
4288 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4289 for (ext = sect->section; ext->extent != NULL; ++ext) {
4290 if (sect->id == SECT_CONTEXT)
4291 count += 2 + ext->reg_count;
4292 else
4293 return 0;
4294 }
4295 }
4296
4297 /* set PA_SC_TILE_STEERING_OVERRIDE */
4298 count += 3;
4299 /* end clear state */
4300 count += 2;
4301 /* clear state */
4302 count += 2;
4303
4304 return count;
4305}
4306
4307static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4308 volatile u32 *buffer)
4309{
4310 u32 count = 0, i;
4311 const struct cs_section_def *sect = NULL;
4312 const struct cs_extent_def *ext = NULL;
4313 int ctx_reg_offset;
4314
4315 if (adev->gfx.rlc.cs_data == NULL)
4316 return;
4317 if (buffer == NULL)
4318 return;
4319
4320 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4321 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4322
4323 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4324 buffer[count++] = cpu_to_le32(0x80000000);
4325 buffer[count++] = cpu_to_le32(0x80000000);
4326
4327 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4328 for (ext = sect->section; ext->extent != NULL; ++ext) {
4329 if (sect->id == SECT_CONTEXT) {
4330 buffer[count++] =
4331 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4332 buffer[count++] = cpu_to_le32(ext->reg_index -
4333 PACKET3_SET_CONTEXT_REG_START);
4334 for (i = 0; i < ext->reg_count; i++)
4335 buffer[count++] = cpu_to_le32(ext->extent[i]);
4336 } else {
4337 return;
4338 }
4339 }
4340 }
4341
4342 ctx_reg_offset =
4343 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4344 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4345 buffer[count++] = cpu_to_le32(ctx_reg_offset);
4346 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4347
4348 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4349 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4350
4351 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4352 buffer[count++] = cpu_to_le32(0);
4353}
4354
4355static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4356{
4357 /* clear state block */
4358 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4359 &adev->gfx.rlc.clear_state_gpu_addr,
4360 (void **)&adev->gfx.rlc.cs_ptr);
4361
4362 /* jump table block */
4363 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4364 &adev->gfx.rlc.cp_table_gpu_addr,
4365 (void **)&adev->gfx.rlc.cp_table_ptr);
4366}
4367
4368static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4369{
4370 const struct cs_section_def *cs_data;
4371 int r;
4372
4373 adev->gfx.rlc.cs_data = gfx10_cs_data;
4374
4375 cs_data = adev->gfx.rlc.cs_data;
4376
4377 if (cs_data) {
4378 /* init clear state block */
4379 r = amdgpu_gfx_rlc_init_csb(adev);
4380 if (r)
4381 return r;
4382 }
4383
4384 /* init spm vmid with 0xf */
4385 if (adev->gfx.rlc.funcs->update_spm_vmid)
4386 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4387
4388 return 0;
4389}
4390
4391static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4392{
4393 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4394 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4395}
4396
4397static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4398{
4399 int r;
4400
4401 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4402
4403 amdgpu_gfx_graphics_queue_acquire(adev);
4404
4405 r = gfx_v10_0_init_microcode(adev);
4406 if (r)
4407 DRM_ERROR("Failed to load gfx firmware!\n");
4408
4409 return r;
4410}
4411
4412static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4413{
4414 int r;
4415 u32 *hpd;
4416 const __le32 *fw_data = NULL;
4417 unsigned fw_size;
4418 u32 *fw = NULL;
4419 size_t mec_hpd_size;
4420
4421 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4422
4423 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4424
4425 /* take ownership of the relevant compute queues */
4426 amdgpu_gfx_compute_queue_acquire(adev);
4427 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4428
4429 if (mec_hpd_size) {
4430 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4431 AMDGPU_GEM_DOMAIN_GTT,
4432 &adev->gfx.mec.hpd_eop_obj,
4433 &adev->gfx.mec.hpd_eop_gpu_addr,
4434 (void **)&hpd);
4435 if (r) {
4436 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4437 gfx_v10_0_mec_fini(adev);
4438 return r;
4439 }
4440
4441 memset(hpd, 0, mec_hpd_size);
4442
4443 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4444 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4445 }
4446
4447 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4448 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4449
4450 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4451 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4452 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4453
4454 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4455 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4456 &adev->gfx.mec.mec_fw_obj,
4457 &adev->gfx.mec.mec_fw_gpu_addr,
4458 (void **)&fw);
4459 if (r) {
4460 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4461 gfx_v10_0_mec_fini(adev);
4462 return r;
4463 }
4464
4465 memcpy(fw, fw_data, fw_size);
4466
4467 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4468 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4469 }
4470
4471 return 0;
4472}
4473
4474static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4475{
4476 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4477 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4478 (address << SQ_IND_INDEX__INDEX__SHIFT));
4479 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4480}
4481
4482static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4483 uint32_t thread, uint32_t regno,
4484 uint32_t num, uint32_t *out)
4485{
4486 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4487 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4488 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4489 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4490 (SQ_IND_INDEX__AUTO_INCR_MASK));
4491 while (num--)
4492 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4493}
4494
4495static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4496{
4497 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4498 * field when performing a select_se_sh so it should be
4499 * zero here */
4500 WARN_ON(simd != 0);
4501
4502 /* type 2 wave data */
4503 dst[(*no_fields)++] = 2;
4504 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4505 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4506 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4507 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4508 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4509 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4510 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4511 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4512 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4513 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4514 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4515 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4516 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4517 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4518 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4519}
4520
4521static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4522 uint32_t wave, uint32_t start,
4523 uint32_t size, uint32_t *dst)
4524{
4525 WARN_ON(simd != 0);
4526
4527 wave_read_regs(
4528 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4529 dst);
4530}
4531
4532static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4533 uint32_t wave, uint32_t thread,
4534 uint32_t start, uint32_t size,
4535 uint32_t *dst)
4536{
4537 wave_read_regs(
4538 adev, wave, thread,
4539 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4540}
4541
4542static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4543 u32 me, u32 pipe, u32 q, u32 vm)
4544{
4545 nv_grbm_select(adev, me, pipe, q, vm);
4546}
4547
4548static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4549 bool enable)
4550{
4551 uint32_t data, def;
4552
4553 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4554
4555 if (enable)
4556 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4557 else
4558 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4559
4560 if (data != def)
4561 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4562}
4563
4564static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4565 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4566 .select_se_sh = &gfx_v10_0_select_se_sh,
4567 .read_wave_data = &gfx_v10_0_read_wave_data,
4568 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4569 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4570 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4571 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4572 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4573};
4574
4575static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4576{
4577 u32 gb_addr_config;
4578
4579 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4580
4581 switch (adev->asic_type) {
4582 case CHIP_NAVI10:
4583 case CHIP_NAVI14:
4584 case CHIP_NAVI12:
4585 adev->gfx.config.max_hw_contexts = 8;
4586 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4587 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4588 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4589 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4590 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4591 break;
4592 case CHIP_SIENNA_CICHLID:
4593 case CHIP_NAVY_FLOUNDER:
4594 case CHIP_VANGOGH:
4595 case CHIP_DIMGREY_CAVEFISH:
4596 case CHIP_BEIGE_GOBY:
4597 case CHIP_YELLOW_CARP:
4598 adev->gfx.config.max_hw_contexts = 8;
4599 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4600 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4601 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4602 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4603 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4604 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4605 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4606 break;
4607 default:
4608 BUG();
4609 break;
4610 }
4611
4612 adev->gfx.config.gb_addr_config = gb_addr_config;
4613
4614 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4615 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4616 GB_ADDR_CONFIG, NUM_PIPES);
4617
4618 adev->gfx.config.max_tile_pipes =
4619 adev->gfx.config.gb_addr_config_fields.num_pipes;
4620
4621 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4622 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4623 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4624 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4625 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4626 GB_ADDR_CONFIG, NUM_RB_PER_SE);
4627 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4628 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4629 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4630 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4631 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4632 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4633}
4634
4635static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4636 int me, int pipe, int queue)
4637{
4638 int r;
4639 struct amdgpu_ring *ring;
4640 unsigned int irq_type;
4641
4642 ring = &adev->gfx.gfx_ring[ring_id];
4643
4644 ring->me = me;
4645 ring->pipe = pipe;
4646 ring->queue = queue;
4647
4648 ring->ring_obj = NULL;
4649 ring->use_doorbell = true;
4650
4651 if (!ring_id)
4652 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4653 else
4654 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4655 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4656
4657 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4658 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4659 AMDGPU_RING_PRIO_DEFAULT, NULL);
4660 if (r)
4661 return r;
4662 return 0;
4663}
4664
4665static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4666 int mec, int pipe, int queue)
4667{
4668 int r;
4669 unsigned irq_type;
4670 struct amdgpu_ring *ring;
4671 unsigned int hw_prio;
4672
4673 ring = &adev->gfx.compute_ring[ring_id];
4674
4675 /* mec0 is me1 */
4676 ring->me = mec + 1;
4677 ring->pipe = pipe;
4678 ring->queue = queue;
4679
4680 ring->ring_obj = NULL;
4681 ring->use_doorbell = true;
4682 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4683 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4684 + (ring_id * GFX10_MEC_HPD_SIZE);
4685 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4686
4687 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4688 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4689 + ring->pipe;
4690 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4691 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4692 /* type-2 packets are deprecated on MEC, use type-3 instead */
4693 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4694 hw_prio, NULL);
4695 if (r)
4696 return r;
4697
4698 return 0;
4699}
4700
4701static int gfx_v10_0_sw_init(void *handle)
4702{
4703 int i, j, k, r, ring_id = 0;
4704 struct amdgpu_kiq *kiq;
4705 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4706
4707 switch (adev->asic_type) {
4708 case CHIP_NAVI10:
4709 case CHIP_NAVI14:
4710 case CHIP_NAVI12:
4711 adev->gfx.me.num_me = 1;
4712 adev->gfx.me.num_pipe_per_me = 1;
4713 adev->gfx.me.num_queue_per_pipe = 1;
4714 adev->gfx.mec.num_mec = 2;
4715 adev->gfx.mec.num_pipe_per_mec = 4;
4716 adev->gfx.mec.num_queue_per_pipe = 8;
4717 break;
4718 case CHIP_SIENNA_CICHLID:
4719 case CHIP_NAVY_FLOUNDER:
4720 case CHIP_VANGOGH:
4721 case CHIP_DIMGREY_CAVEFISH:
4722 case CHIP_BEIGE_GOBY:
4723 case CHIP_YELLOW_CARP:
4724 adev->gfx.me.num_me = 1;
4725 adev->gfx.me.num_pipe_per_me = 1;
4726 adev->gfx.me.num_queue_per_pipe = 1;
4727 adev->gfx.mec.num_mec = 2;
4728 adev->gfx.mec.num_pipe_per_mec = 4;
4729 adev->gfx.mec.num_queue_per_pipe = 4;
4730 break;
4731 default:
4732 adev->gfx.me.num_me = 1;
4733 adev->gfx.me.num_pipe_per_me = 1;
4734 adev->gfx.me.num_queue_per_pipe = 1;
4735 adev->gfx.mec.num_mec = 1;
4736 adev->gfx.mec.num_pipe_per_mec = 4;
4737 adev->gfx.mec.num_queue_per_pipe = 8;
4738 break;
4739 }
4740
4741 /* KIQ event */
4742 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4743 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4744 &adev->gfx.kiq.irq);
4745 if (r)
4746 return r;
4747
4748 /* EOP Event */
4749 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4750 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4751 &adev->gfx.eop_irq);
4752 if (r)
4753 return r;
4754
4755 /* Privileged reg */
4756 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4757 &adev->gfx.priv_reg_irq);
4758 if (r)
4759 return r;
4760
4761 /* Privileged inst */
4762 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4763 &adev->gfx.priv_inst_irq);
4764 if (r)
4765 return r;
4766
4767 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4768
4769 gfx_v10_0_scratch_init(adev);
4770
4771 r = gfx_v10_0_me_init(adev);
4772 if (r)
4773 return r;
4774
4775 r = gfx_v10_0_rlc_init(adev);
4776 if (r) {
4777 DRM_ERROR("Failed to init rlc BOs!\n");
4778 return r;
4779 }
4780
4781 r = gfx_v10_0_mec_init(adev);
4782 if (r) {
4783 DRM_ERROR("Failed to init MEC BOs!\n");
4784 return r;
4785 }
4786
4787 /* set up the gfx ring */
4788 for (i = 0; i < adev->gfx.me.num_me; i++) {
4789 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4790 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4791 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4792 continue;
4793
4794 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4795 i, k, j);
4796 if (r)
4797 return r;
4798 ring_id++;
4799 }
4800 }
4801 }
4802
4803 ring_id = 0;
4804 /* set up the compute queues - allocate horizontally across pipes */
4805 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4806 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4807 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4808 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4809 j))
4810 continue;
4811
4812 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4813 i, k, j);
4814 if (r)
4815 return r;
4816
4817 ring_id++;
4818 }
4819 }
4820 }
4821
4822 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4823 if (r) {
4824 DRM_ERROR("Failed to init KIQ BOs!\n");
4825 return r;
4826 }
4827
4828 kiq = &adev->gfx.kiq;
4829 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4830 if (r)
4831 return r;
4832
4833 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4834 if (r)
4835 return r;
4836
4837 /* allocate visible FB for rlc auto-loading fw */
4838 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4839 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4840 if (r)
4841 return r;
4842 }
4843
4844 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4845
4846 gfx_v10_0_gpu_early_init(adev);
4847
4848 return 0;
4849}
4850
4851static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4852{
4853 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4854 &adev->gfx.pfp.pfp_fw_gpu_addr,
4855 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4856}
4857
4858static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4859{
4860 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4861 &adev->gfx.ce.ce_fw_gpu_addr,
4862 (void **)&adev->gfx.ce.ce_fw_ptr);
4863}
4864
4865static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4866{
4867 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4868 &adev->gfx.me.me_fw_gpu_addr,
4869 (void **)&adev->gfx.me.me_fw_ptr);
4870}
4871
4872static int gfx_v10_0_sw_fini(void *handle)
4873{
4874 int i;
4875 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4876
4877 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4878 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4879 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4880 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4881
4882 amdgpu_gfx_mqd_sw_fini(adev);
4883 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4884 amdgpu_gfx_kiq_fini(adev);
4885
4886 gfx_v10_0_pfp_fini(adev);
4887 gfx_v10_0_ce_fini(adev);
4888 gfx_v10_0_me_fini(adev);
4889 gfx_v10_0_rlc_fini(adev);
4890 gfx_v10_0_mec_fini(adev);
4891
4892 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4893 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4894
4895 gfx_v10_0_free_microcode(adev);
4896
4897 return 0;
4898}
4899
4900static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4901 u32 sh_num, u32 instance)
4902{
4903 u32 data;
4904
4905 if (instance == 0xffffffff)
4906 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4907 INSTANCE_BROADCAST_WRITES, 1);
4908 else
4909 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4910 instance);
4911
4912 if (se_num == 0xffffffff)
4913 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4914 1);
4915 else
4916 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4917
4918 if (sh_num == 0xffffffff)
4919 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4920 1);
4921 else
4922 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4923
4924 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4925}
4926
4927static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4928{
4929 u32 data, mask;
4930
4931 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4932 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4933
4934 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4935 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4936
4937 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4938 adev->gfx.config.max_sh_per_se);
4939
4940 return (~data) & mask;
4941}
4942
4943static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4944{
4945 int i, j;
4946 u32 data;
4947 u32 active_rbs = 0;
4948 u32 bitmap;
4949 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4950 adev->gfx.config.max_sh_per_se;
4951
4952 mutex_lock(&adev->grbm_idx_mutex);
4953 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4954 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4955 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4956 if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
4957 (adev->asic_type == CHIP_YELLOW_CARP)) &&
4958 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4959 continue;
4960 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4961 data = gfx_v10_0_get_rb_active_bitmap(adev);
4962 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4963 rb_bitmap_width_per_sh);
4964 }
4965 }
4966 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4967 mutex_unlock(&adev->grbm_idx_mutex);
4968
4969 adev->gfx.config.backend_enable_mask = active_rbs;
4970 adev->gfx.config.num_rbs = hweight32(active_rbs);
4971}
4972
4973static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4974{
4975 uint32_t num_sc;
4976 uint32_t enabled_rb_per_sh;
4977 uint32_t active_rb_bitmap;
4978 uint32_t num_rb_per_sc;
4979 uint32_t num_packer_per_sc;
4980 uint32_t pa_sc_tile_steering_override;
4981
4982 /* for ASICs that integrates GFX v10.3
4983 * pa_sc_tile_steering_override should be set to 0 */
4984 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4985 return 0;
4986
4987 /* init num_sc */
4988 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4989 adev->gfx.config.num_sc_per_sh;
4990 /* init num_rb_per_sc */
4991 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4992 enabled_rb_per_sh = hweight32(active_rb_bitmap);
4993 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4994 /* init num_packer_per_sc */
4995 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4996
4997 pa_sc_tile_steering_override = 0;
4998 pa_sc_tile_steering_override |=
4999 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5000 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5001 pa_sc_tile_steering_override |=
5002 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5003 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5004 pa_sc_tile_steering_override |=
5005 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5006 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5007
5008 return pa_sc_tile_steering_override;
5009}
5010
5011#define DEFAULT_SH_MEM_BASES (0x6000)
5012
5013static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5014{
5015 int i;
5016 uint32_t sh_mem_bases;
5017
5018 /*
5019 * Configure apertures:
5020 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
5021 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
5022 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
5023 */
5024 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5025
5026 mutex_lock(&adev->srbm_mutex);
5027 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5028 nv_grbm_select(adev, 0, 0, 0, i);
5029 /* CP and shaders */
5030 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5031 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5032 }
5033 nv_grbm_select(adev, 0, 0, 0, 0);
5034 mutex_unlock(&adev->srbm_mutex);
5035
5036 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5037 acccess. These should be enabled by FW for target VMIDs. */
5038 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5039 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5040 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5041 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5042 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5043 }
5044}
5045
5046static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5047{
5048 int vmid;
5049
5050 /*
5051 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5052 * access. Compute VMIDs should be enabled by FW for target VMIDs,
5053 * the driver can enable them for graphics. VMID0 should maintain
5054 * access so that HWS firmware can save/restore entries.
5055 */
5056 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5057 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5058 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5059 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5060 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5061 }
5062}
5063
5064
5065static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5066{
5067 int i, j, k;
5068 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5069 u32 tmp, wgp_active_bitmap = 0;
5070 u32 gcrd_targets_disable_tcp = 0;
5071 u32 utcl_invreq_disable = 0;
5072 /*
5073 * GCRD_TARGETS_DISABLE field contains
5074 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5075 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5076 */
5077 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5078 2 * max_wgp_per_sh + /* TCP */
5079 max_wgp_per_sh + /* SQC */
5080 4); /* GL1C */
5081 /*
5082 * UTCL1_UTCL0_INVREQ_DISABLE field contains
5083 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5084 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5085 */
5086 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5087 2 * max_wgp_per_sh + /* TCP */
5088 2 * max_wgp_per_sh + /* SQC */
5089 4 + /* RMI */
5090 1); /* SQG */
5091
5092 mutex_lock(&adev->grbm_idx_mutex);
5093 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5094 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5095 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5096 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5097 /*
5098 * Set corresponding TCP bits for the inactive WGPs in
5099 * GCRD_SA_TARGETS_DISABLE
5100 */
5101 gcrd_targets_disable_tcp = 0;
5102 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5103 utcl_invreq_disable = 0;
5104
5105 for (k = 0; k < max_wgp_per_sh; k++) {
5106 if (!(wgp_active_bitmap & (1 << k))) {
5107 gcrd_targets_disable_tcp |= 3 << (2 * k);
5108 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5109 utcl_invreq_disable |= (3 << (2 * k)) |
5110 (3 << (2 * (max_wgp_per_sh + k)));
5111 }
5112 }
5113
5114 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5115 /* only override TCP & SQC bits */
5116 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5117 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5118 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5119
5120 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5121 /* only override TCP & SQC bits */
5122 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5123 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5124 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5125 }
5126 }
5127
5128 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5129 mutex_unlock(&adev->grbm_idx_mutex);
5130}
5131
5132static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5133{
5134 /* TCCs are global (not instanced). */
5135 uint32_t tcc_disable;
5136
5137 if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
5138 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5139 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5140 } else {
5141 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5142 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5143 }
5144
5145 adev->gfx.config.tcc_disabled_mask =
5146 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5147 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5148}
5149
5150static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5151{
5152 u32 tmp;
5153 int i;
5154
5155 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5156
5157 gfx_v10_0_setup_rb(adev);
5158 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5159 gfx_v10_0_get_tcc_info(adev);
5160 adev->gfx.config.pa_sc_tile_steering_override =
5161 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5162
5163 /* XXX SH_MEM regs */
5164 /* where to put LDS, scratch, GPUVM in FSA64 space */
5165 mutex_lock(&adev->srbm_mutex);
5166 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5167 nv_grbm_select(adev, 0, 0, 0, i);
5168 /* CP and shaders */
5169 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5170 if (i != 0) {
5171 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5172 (adev->gmc.private_aperture_start >> 48));
5173 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5174 (adev->gmc.shared_aperture_start >> 48));
5175 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5176 }
5177 }
5178 nv_grbm_select(adev, 0, 0, 0, 0);
5179
5180 mutex_unlock(&adev->srbm_mutex);
5181
5182 gfx_v10_0_init_compute_vmid(adev);
5183 gfx_v10_0_init_gds_vmid(adev);
5184
5185}
5186
5187static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5188 bool enable)
5189{
5190 u32 tmp;
5191
5192 if (amdgpu_sriov_vf(adev))
5193 return;
5194
5195 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5196
5197 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5198 enable ? 1 : 0);
5199 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5200 enable ? 1 : 0);
5201 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5202 enable ? 1 : 0);
5203 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5204 enable ? 1 : 0);
5205
5206 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5207}
5208
5209static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5210{
5211 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5212
5213 /* csib */
5214 if (adev->asic_type == CHIP_NAVI12) {
5215 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5216 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5217 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5218 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5219 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5220 } else {
5221 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5222 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5223 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5224 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5225 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5226 }
5227 return 0;
5228}
5229
5230static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5231{
5232 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5233
5234 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5235 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5236}
5237
5238static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5239{
5240 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5241 udelay(50);
5242 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5243 udelay(50);
5244}
5245
5246static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5247 bool enable)
5248{
5249 uint32_t rlc_pg_cntl;
5250
5251 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5252
5253 if (!enable) {
5254 /* RLC_PG_CNTL[23] = 0 (default)
5255 * RLC will wait for handshake acks with SMU
5256 * GFXOFF will be enabled
5257 * RLC_PG_CNTL[23] = 1
5258 * RLC will not issue any message to SMU
5259 * hence no handshake between SMU & RLC
5260 * GFXOFF will be disabled
5261 */
5262 rlc_pg_cntl |= 0x800000;
5263 } else
5264 rlc_pg_cntl &= ~0x800000;
5265 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5266}
5267
5268static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5269{
5270 /* TODO: enable rlc & smu handshake until smu
5271 * and gfxoff feature works as expected */
5272 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5273 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5274
5275 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5276 udelay(50);
5277}
5278
5279static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5280{
5281 uint32_t tmp;
5282
5283 /* enable Save Restore Machine */
5284 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5285 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5286 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5287 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5288}
5289
5290static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5291{
5292 const struct rlc_firmware_header_v2_0 *hdr;
5293 const __le32 *fw_data;
5294 unsigned i, fw_size;
5295
5296 if (!adev->gfx.rlc_fw)
5297 return -EINVAL;
5298
5299 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5300 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5301
5302 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5303 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5304 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5305
5306 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5307 RLCG_UCODE_LOADING_START_ADDRESS);
5308
5309 for (i = 0; i < fw_size; i++)
5310 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5311 le32_to_cpup(fw_data++));
5312
5313 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5314
5315 return 0;
5316}
5317
5318static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5319{
5320 int r;
5321
5322 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5323
5324 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5325 if (r)
5326 return r;
5327
5328 gfx_v10_0_init_csb(adev);
5329
5330 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5331 gfx_v10_0_rlc_enable_srm(adev);
5332 } else {
5333 if (amdgpu_sriov_vf(adev)) {
5334 gfx_v10_0_init_csb(adev);
5335 return 0;
5336 }
5337
5338 adev->gfx.rlc.funcs->stop(adev);
5339
5340 /* disable CG */
5341 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5342
5343 /* disable PG */
5344 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5345
5346 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5347 /* legacy rlc firmware loading */
5348 r = gfx_v10_0_rlc_load_microcode(adev);
5349 if (r)
5350 return r;
5351 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5352 /* rlc backdoor autoload firmware */
5353 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5354 if (r)
5355 return r;
5356 }
5357
5358 gfx_v10_0_init_csb(adev);
5359
5360 adev->gfx.rlc.funcs->start(adev);
5361
5362 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5363 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5364 if (r)
5365 return r;
5366 }
5367 }
5368 return 0;
5369}
5370
5371static struct {
5372 FIRMWARE_ID id;
5373 unsigned int offset;
5374 unsigned int size;
5375} rlc_autoload_info[FIRMWARE_ID_MAX];
5376
5377static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5378{
5379 int ret;
5380 RLC_TABLE_OF_CONTENT *rlc_toc;
5381
5382 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5383 AMDGPU_GEM_DOMAIN_GTT,
5384 &adev->gfx.rlc.rlc_toc_bo,
5385 &adev->gfx.rlc.rlc_toc_gpu_addr,
5386 (void **)&adev->gfx.rlc.rlc_toc_buf);
5387 if (ret) {
5388 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5389 return ret;
5390 }
5391
5392 /* Copy toc from psp sos fw to rlc toc buffer */
5393 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5394
5395 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5396 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5397 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5398 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5399 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5400 /* Offset needs 4KB alignment */
5401 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5402 }
5403
5404 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5405 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5406 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5407
5408 rlc_toc++;
5409 }
5410
5411 return 0;
5412}
5413
5414static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5415{
5416 uint32_t total_size = 0;
5417 FIRMWARE_ID id;
5418 int ret;
5419
5420 ret = gfx_v10_0_parse_rlc_toc(adev);
5421 if (ret) {
5422 dev_err(adev->dev, "failed to parse rlc toc\n");
5423 return 0;
5424 }
5425
5426 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5427 total_size += rlc_autoload_info[id].size;
5428
5429 /* In case the offset in rlc toc ucode is aligned */
5430 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5431 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5432 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5433
5434 return total_size;
5435}
5436
5437static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5438{
5439 int r;
5440 uint32_t total_size;
5441
5442 total_size = gfx_v10_0_calc_toc_total_size(adev);
5443
5444 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5445 AMDGPU_GEM_DOMAIN_GTT,
5446 &adev->gfx.rlc.rlc_autoload_bo,
5447 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5448 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5449 if (r) {
5450 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5451 return r;
5452 }
5453
5454 return 0;
5455}
5456
5457static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5458{
5459 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5460 &adev->gfx.rlc.rlc_toc_gpu_addr,
5461 (void **)&adev->gfx.rlc.rlc_toc_buf);
5462 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5463 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5464 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5465}
5466
5467static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5468 FIRMWARE_ID id,
5469 const void *fw_data,
5470 uint32_t fw_size)
5471{
5472 uint32_t toc_offset;
5473 uint32_t toc_fw_size;
5474 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5475
5476 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5477 return;
5478
5479 toc_offset = rlc_autoload_info[id].offset;
5480 toc_fw_size = rlc_autoload_info[id].size;
5481
5482 if (fw_size == 0)
5483 fw_size = toc_fw_size;
5484
5485 if (fw_size > toc_fw_size)
5486 fw_size = toc_fw_size;
5487
5488 memcpy(ptr + toc_offset, fw_data, fw_size);
5489
5490 if (fw_size < toc_fw_size)
5491 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5492}
5493
5494static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5495{
5496 void *data;
5497 uint32_t size;
5498
5499 data = adev->gfx.rlc.rlc_toc_buf;
5500 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5501
5502 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5503 FIRMWARE_ID_RLC_TOC,
5504 data, size);
5505}
5506
5507static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5508{
5509 const __le32 *fw_data;
5510 uint32_t fw_size;
5511 const struct gfx_firmware_header_v1_0 *cp_hdr;
5512 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5513
5514 /* pfp ucode */
5515 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5516 adev->gfx.pfp_fw->data;
5517 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5518 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5519 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5520 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5521 FIRMWARE_ID_CP_PFP,
5522 fw_data, fw_size);
5523
5524 /* ce ucode */
5525 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5526 adev->gfx.ce_fw->data;
5527 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5528 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5529 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5530 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5531 FIRMWARE_ID_CP_CE,
5532 fw_data, fw_size);
5533
5534 /* me ucode */
5535 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5536 adev->gfx.me_fw->data;
5537 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5538 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5539 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5540 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5541 FIRMWARE_ID_CP_ME,
5542 fw_data, fw_size);
5543
5544 /* rlc ucode */
5545 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5546 adev->gfx.rlc_fw->data;
5547 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5548 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5549 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5550 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5551 FIRMWARE_ID_RLC_G_UCODE,
5552 fw_data, fw_size);
5553
5554 /* mec1 ucode */
5555 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5556 adev->gfx.mec_fw->data;
5557 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5558 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5559 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5560 cp_hdr->jt_size * 4;
5561 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5562 FIRMWARE_ID_CP_MEC,
5563 fw_data, fw_size);
5564 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5565}
5566
5567/* Temporarily put sdma part here */
5568static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5569{
5570 const __le32 *fw_data;
5571 uint32_t fw_size;
5572 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5573 int i;
5574
5575 for (i = 0; i < adev->sdma.num_instances; i++) {
5576 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5577 adev->sdma.instance[i].fw->data;
5578 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5579 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5580 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5581
5582 if (i == 0) {
5583 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5584 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5585 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5586 FIRMWARE_ID_SDMA0_JT,
5587 (uint32_t *)fw_data +
5588 sdma_hdr->jt_offset,
5589 sdma_hdr->jt_size * 4);
5590 } else if (i == 1) {
5591 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5592 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5593 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5594 FIRMWARE_ID_SDMA1_JT,
5595 (uint32_t *)fw_data +
5596 sdma_hdr->jt_offset,
5597 sdma_hdr->jt_size * 4);
5598 }
5599 }
5600}
5601
5602static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5603{
5604 uint32_t rlc_g_offset, rlc_g_size, tmp;
5605 uint64_t gpu_addr;
5606
5607 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5608 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5609 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5610
5611 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5612 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5613 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5614
5615 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5616 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5617 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5618
5619 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5620 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5621 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5622 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5623 return -EINVAL;
5624 }
5625
5626 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5627 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5628 DRM_ERROR("RLC ROM should halt itself\n");
5629 return -EINVAL;
5630 }
5631
5632 return 0;
5633}
5634
5635static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5636{
5637 uint32_t usec_timeout = 50000; /* wait for 50ms */
5638 uint32_t tmp;
5639 int i;
5640 uint64_t addr;
5641
5642 /* Trigger an invalidation of the L1 instruction caches */
5643 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5644 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5645 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5646
5647 /* Wait for invalidation complete */
5648 for (i = 0; i < usec_timeout; i++) {
5649 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5650 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5651 INVALIDATE_CACHE_COMPLETE))
5652 break;
5653 udelay(1);
5654 }
5655
5656 if (i >= usec_timeout) {
5657 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5658 return -EINVAL;
5659 }
5660
5661 /* Program me ucode address into intruction cache address register */
5662 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5663 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5664 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5665 lower_32_bits(addr) & 0xFFFFF000);
5666 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5667 upper_32_bits(addr));
5668
5669 return 0;
5670}
5671
5672static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5673{
5674 uint32_t usec_timeout = 50000; /* wait for 50ms */
5675 uint32_t tmp;
5676 int i;
5677 uint64_t addr;
5678
5679 /* Trigger an invalidation of the L1 instruction caches */
5680 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5681 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5682 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5683
5684 /* Wait for invalidation complete */
5685 for (i = 0; i < usec_timeout; i++) {
5686 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5687 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5688 INVALIDATE_CACHE_COMPLETE))
5689 break;
5690 udelay(1);
5691 }
5692
5693 if (i >= usec_timeout) {
5694 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5695 return -EINVAL;
5696 }
5697
5698 /* Program ce ucode address into intruction cache address register */
5699 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5700 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5701 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5702 lower_32_bits(addr) & 0xFFFFF000);
5703 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5704 upper_32_bits(addr));
5705
5706 return 0;
5707}
5708
5709static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5710{
5711 uint32_t usec_timeout = 50000; /* wait for 50ms */
5712 uint32_t tmp;
5713 int i;
5714 uint64_t addr;
5715
5716 /* Trigger an invalidation of the L1 instruction caches */
5717 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5718 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5719 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5720
5721 /* Wait for invalidation complete */
5722 for (i = 0; i < usec_timeout; i++) {
5723 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5724 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5725 INVALIDATE_CACHE_COMPLETE))
5726 break;
5727 udelay(1);
5728 }
5729
5730 if (i >= usec_timeout) {
5731 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5732 return -EINVAL;
5733 }
5734
5735 /* Program pfp ucode address into intruction cache address register */
5736 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5737 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5738 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5739 lower_32_bits(addr) & 0xFFFFF000);
5740 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5741 upper_32_bits(addr));
5742
5743 return 0;
5744}
5745
5746static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5747{
5748 uint32_t usec_timeout = 50000; /* wait for 50ms */
5749 uint32_t tmp;
5750 int i;
5751 uint64_t addr;
5752
5753 /* Trigger an invalidation of the L1 instruction caches */
5754 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5755 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5756 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5757
5758 /* Wait for invalidation complete */
5759 for (i = 0; i < usec_timeout; i++) {
5760 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5761 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5762 INVALIDATE_CACHE_COMPLETE))
5763 break;
5764 udelay(1);
5765 }
5766
5767 if (i >= usec_timeout) {
5768 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5769 return -EINVAL;
5770 }
5771
5772 /* Program mec1 ucode address into intruction cache address register */
5773 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5774 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5775 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5776 lower_32_bits(addr) & 0xFFFFF000);
5777 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5778 upper_32_bits(addr));
5779
5780 return 0;
5781}
5782
5783static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5784{
5785 uint32_t cp_status;
5786 uint32_t bootload_status;
5787 int i, r;
5788
5789 for (i = 0; i < adev->usec_timeout; i++) {
5790 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5791 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5792 if ((cp_status == 0) &&
5793 (REG_GET_FIELD(bootload_status,
5794 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5795 break;
5796 }
5797 udelay(1);
5798 }
5799
5800 if (i >= adev->usec_timeout) {
5801 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5802 return -ETIMEDOUT;
5803 }
5804
5805 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5806 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5807 if (r)
5808 return r;
5809
5810 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5811 if (r)
5812 return r;
5813
5814 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5815 if (r)
5816 return r;
5817
5818 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5819 if (r)
5820 return r;
5821 }
5822
5823 return 0;
5824}
5825
5826static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5827{
5828 int i;
5829 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5830
5831 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5832 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5833 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5834
5835 if (adev->asic_type == CHIP_NAVI12) {
5836 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5837 } else {
5838 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5839 }
5840
5841 for (i = 0; i < adev->usec_timeout; i++) {
5842 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5843 break;
5844 udelay(1);
5845 }
5846
5847 if (i >= adev->usec_timeout)
5848 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5849
5850 return 0;
5851}
5852
5853static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5854{
5855 int r;
5856 const struct gfx_firmware_header_v1_0 *pfp_hdr;
5857 const __le32 *fw_data;
5858 unsigned i, fw_size;
5859 uint32_t tmp;
5860 uint32_t usec_timeout = 50000; /* wait for 50ms */
5861
5862 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5863 adev->gfx.pfp_fw->data;
5864
5865 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5866
5867 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5868 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5869 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5870
5871 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5872 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5873 &adev->gfx.pfp.pfp_fw_obj,
5874 &adev->gfx.pfp.pfp_fw_gpu_addr,
5875 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5876 if (r) {
5877 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5878 gfx_v10_0_pfp_fini(adev);
5879 return r;
5880 }
5881
5882 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5883
5884 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5885 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5886
5887 /* Trigger an invalidation of the L1 instruction caches */
5888 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5889 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5890 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5891
5892 /* Wait for invalidation complete */
5893 for (i = 0; i < usec_timeout; i++) {
5894 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5895 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5896 INVALIDATE_CACHE_COMPLETE))
5897 break;
5898 udelay(1);
5899 }
5900
5901 if (i >= usec_timeout) {
5902 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5903 return -EINVAL;
5904 }
5905
5906 if (amdgpu_emu_mode == 1)
5907 adev->hdp.funcs->flush_hdp(adev, NULL);
5908
5909 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5910 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5911 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5912 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5913 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5914 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5915 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5916 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5917 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5918 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5919
5920 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5921
5922 for (i = 0; i < pfp_hdr->jt_size; i++)
5923 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5924 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5925
5926 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5927
5928 return 0;
5929}
5930
5931static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5932{
5933 int r;
5934 const struct gfx_firmware_header_v1_0 *ce_hdr;
5935 const __le32 *fw_data;
5936 unsigned i, fw_size;
5937 uint32_t tmp;
5938 uint32_t usec_timeout = 50000; /* wait for 50ms */
5939
5940 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5941 adev->gfx.ce_fw->data;
5942
5943 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5944
5945 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5946 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5947 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5948
5949 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5950 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5951 &adev->gfx.ce.ce_fw_obj,
5952 &adev->gfx.ce.ce_fw_gpu_addr,
5953 (void **)&adev->gfx.ce.ce_fw_ptr);
5954 if (r) {
5955 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5956 gfx_v10_0_ce_fini(adev);
5957 return r;
5958 }
5959
5960 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5961
5962 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5963 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5964
5965 /* Trigger an invalidation of the L1 instruction caches */
5966 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5967 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5968 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5969
5970 /* Wait for invalidation complete */
5971 for (i = 0; i < usec_timeout; i++) {
5972 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5973 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5974 INVALIDATE_CACHE_COMPLETE))
5975 break;
5976 udelay(1);
5977 }
5978
5979 if (i >= usec_timeout) {
5980 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5981 return -EINVAL;
5982 }
5983
5984 if (amdgpu_emu_mode == 1)
5985 adev->hdp.funcs->flush_hdp(adev, NULL);
5986
5987 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5988 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5989 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5990 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5991 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5992 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5993 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5994 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5995 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5996
5997 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5998
5999 for (i = 0; i < ce_hdr->jt_size; i++)
6000 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6001 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6002
6003 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6004
6005 return 0;
6006}
6007
6008static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6009{
6010 int r;
6011 const struct gfx_firmware_header_v1_0 *me_hdr;
6012 const __le32 *fw_data;
6013 unsigned i, fw_size;
6014 uint32_t tmp;
6015 uint32_t usec_timeout = 50000; /* wait for 50ms */
6016
6017 me_hdr = (const struct gfx_firmware_header_v1_0 *)
6018 adev->gfx.me_fw->data;
6019
6020 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6021
6022 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6023 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6024 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6025
6026 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6027 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6028 &adev->gfx.me.me_fw_obj,
6029 &adev->gfx.me.me_fw_gpu_addr,
6030 (void **)&adev->gfx.me.me_fw_ptr);
6031 if (r) {
6032 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6033 gfx_v10_0_me_fini(adev);
6034 return r;
6035 }
6036
6037 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6038
6039 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6040 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6041
6042 /* Trigger an invalidation of the L1 instruction caches */
6043 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6044 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6045 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6046
6047 /* Wait for invalidation complete */
6048 for (i = 0; i < usec_timeout; i++) {
6049 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6050 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6051 INVALIDATE_CACHE_COMPLETE))
6052 break;
6053 udelay(1);
6054 }
6055
6056 if (i >= usec_timeout) {
6057 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6058 return -EINVAL;
6059 }
6060
6061 if (amdgpu_emu_mode == 1)
6062 adev->hdp.funcs->flush_hdp(adev, NULL);
6063
6064 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6065 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6066 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6067 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6068 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6069 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6070 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6071 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6072 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6073
6074 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6075
6076 for (i = 0; i < me_hdr->jt_size; i++)
6077 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6078 le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6079
6080 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6081
6082 return 0;
6083}
6084
6085static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6086{
6087 int r;
6088
6089 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6090 return -EINVAL;
6091
6092 gfx_v10_0_cp_gfx_enable(adev, false);
6093
6094 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6095 if (r) {
6096 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6097 return r;
6098 }
6099
6100 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6101 if (r) {
6102 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6103 return r;
6104 }
6105
6106 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6107 if (r) {
6108 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6109 return r;
6110 }
6111
6112 return 0;
6113}
6114
6115static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6116{
6117 struct amdgpu_ring *ring;
6118 const struct cs_section_def *sect = NULL;
6119 const struct cs_extent_def *ext = NULL;
6120 int r, i;
6121 int ctx_reg_offset;
6122
6123 /* init the CP */
6124 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6125 adev->gfx.config.max_hw_contexts - 1);
6126 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6127
6128 gfx_v10_0_cp_gfx_enable(adev, true);
6129
6130 ring = &adev->gfx.gfx_ring[0];
6131 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6132 if (r) {
6133 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6134 return r;
6135 }
6136
6137 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6138 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6139
6140 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6141 amdgpu_ring_write(ring, 0x80000000);
6142 amdgpu_ring_write(ring, 0x80000000);
6143
6144 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6145 for (ext = sect->section; ext->extent != NULL; ++ext) {
6146 if (sect->id == SECT_CONTEXT) {
6147 amdgpu_ring_write(ring,
6148 PACKET3(PACKET3_SET_CONTEXT_REG,
6149 ext->reg_count));
6150 amdgpu_ring_write(ring, ext->reg_index -
6151 PACKET3_SET_CONTEXT_REG_START);
6152 for (i = 0; i < ext->reg_count; i++)
6153 amdgpu_ring_write(ring, ext->extent[i]);
6154 }
6155 }
6156 }
6157
6158 ctx_reg_offset =
6159 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6160 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6161 amdgpu_ring_write(ring, ctx_reg_offset);
6162 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6163
6164 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6165 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6166
6167 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6168 amdgpu_ring_write(ring, 0);
6169
6170 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6171 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6172 amdgpu_ring_write(ring, 0x8000);
6173 amdgpu_ring_write(ring, 0x8000);
6174
6175 amdgpu_ring_commit(ring);
6176
6177 /* submit cs packet to copy state 0 to next available state */
6178 if (adev->gfx.num_gfx_rings > 1) {
6179 /* maximum supported gfx ring is 2 */
6180 ring = &adev->gfx.gfx_ring[1];
6181 r = amdgpu_ring_alloc(ring, 2);
6182 if (r) {
6183 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6184 return r;
6185 }
6186
6187 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6188 amdgpu_ring_write(ring, 0);
6189
6190 amdgpu_ring_commit(ring);
6191 }
6192 return 0;
6193}
6194
6195static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6196 CP_PIPE_ID pipe)
6197{
6198 u32 tmp;
6199
6200 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6201 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6202
6203 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6204}
6205
6206static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6207 struct amdgpu_ring *ring)
6208{
6209 u32 tmp;
6210
6211 if (!amdgpu_async_gfx_ring) {
6212 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6213 if (ring->use_doorbell) {
6214 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6215 DOORBELL_OFFSET, ring->doorbell_index);
6216 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6217 DOORBELL_EN, 1);
6218 } else {
6219 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6220 DOORBELL_EN, 0);
6221 }
6222 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6223 }
6224 switch (adev->asic_type) {
6225 case CHIP_SIENNA_CICHLID:
6226 case CHIP_NAVY_FLOUNDER:
6227 case CHIP_VANGOGH:
6228 case CHIP_DIMGREY_CAVEFISH:
6229 case CHIP_BEIGE_GOBY:
6230 case CHIP_YELLOW_CARP:
6231 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6232 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6233 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6234
6235 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6236 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6237 break;
6238 default:
6239 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6240 DOORBELL_RANGE_LOWER, ring->doorbell_index);
6241 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6242
6243 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6244 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6245 break;
6246 }
6247}
6248
6249static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6250{
6251 struct amdgpu_ring *ring;
6252 u32 tmp;
6253 u32 rb_bufsz;
6254 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6255 u32 i;
6256
6257 /* Set the write pointer delay */
6258 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6259
6260 /* set the RB to use vmid 0 */
6261 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6262
6263 /* Init gfx ring 0 for pipe 0 */
6264 mutex_lock(&adev->srbm_mutex);
6265 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6266
6267 /* Set ring buffer size */
6268 ring = &adev->gfx.gfx_ring[0];
6269 rb_bufsz = order_base_2(ring->ring_size / 8);
6270 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6271 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6272#ifdef __BIG_ENDIAN
6273 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6274#endif
6275 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6276
6277 /* Initialize the ring buffer's write pointers */
6278 ring->wptr = 0;
6279 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6280 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6281
6282 /* set the wb address wether it's enabled or not */
6283 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6284 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6285 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6286 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6287
6288 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6289 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6290 lower_32_bits(wptr_gpu_addr));
6291 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6292 upper_32_bits(wptr_gpu_addr));
6293
6294 mdelay(1);
6295 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6296
6297 rb_addr = ring->gpu_addr >> 8;
6298 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6299 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6300
6301 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6302
6303 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6304 mutex_unlock(&adev->srbm_mutex);
6305
6306 /* Init gfx ring 1 for pipe 1 */
6307 if (adev->gfx.num_gfx_rings > 1) {
6308 mutex_lock(&adev->srbm_mutex);
6309 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6310 /* maximum supported gfx ring is 2 */
6311 ring = &adev->gfx.gfx_ring[1];
6312 rb_bufsz = order_base_2(ring->ring_size / 8);
6313 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6314 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6315 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6316 /* Initialize the ring buffer's write pointers */
6317 ring->wptr = 0;
6318 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6319 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6320 /* Set the wb address wether it's enabled or not */
6321 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6322 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6323 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6324 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6325 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6326 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6327 lower_32_bits(wptr_gpu_addr));
6328 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6329 upper_32_bits(wptr_gpu_addr));
6330
6331 mdelay(1);
6332 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6333
6334 rb_addr = ring->gpu_addr >> 8;
6335 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6336 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6337 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6338
6339 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6340 mutex_unlock(&adev->srbm_mutex);
6341 }
6342 /* Switch to pipe 0 */
6343 mutex_lock(&adev->srbm_mutex);
6344 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6345 mutex_unlock(&adev->srbm_mutex);
6346
6347 /* start the ring */
6348 gfx_v10_0_cp_gfx_start(adev);
6349
6350 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6351 ring = &adev->gfx.gfx_ring[i];
6352 ring->sched.ready = true;
6353 }
6354
6355 return 0;
6356}
6357
6358static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6359{
6360 if (enable) {
6361 switch (adev->asic_type) {
6362 case CHIP_SIENNA_CICHLID:
6363 case CHIP_NAVY_FLOUNDER:
6364 case CHIP_VANGOGH:
6365 case CHIP_DIMGREY_CAVEFISH:
6366 case CHIP_BEIGE_GOBY:
6367 case CHIP_YELLOW_CARP:
6368 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6369 break;
6370 default:
6371 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6372 break;
6373 }
6374 } else {
6375 switch (adev->asic_type) {
6376 case CHIP_SIENNA_CICHLID:
6377 case CHIP_NAVY_FLOUNDER:
6378 case CHIP_VANGOGH:
6379 case CHIP_DIMGREY_CAVEFISH:
6380 case CHIP_BEIGE_GOBY:
6381 case CHIP_YELLOW_CARP:
6382 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6383 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6384 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6385 break;
6386 default:
6387 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6388 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6389 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6390 break;
6391 }
6392 adev->gfx.kiq.ring.sched.ready = false;
6393 }
6394 udelay(50);
6395}
6396
6397static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6398{
6399 const struct gfx_firmware_header_v1_0 *mec_hdr;
6400 const __le32 *fw_data;
6401 unsigned i;
6402 u32 tmp;
6403 u32 usec_timeout = 50000; /* Wait for 50 ms */
6404
6405 if (!adev->gfx.mec_fw)
6406 return -EINVAL;
6407
6408 gfx_v10_0_cp_compute_enable(adev, false);
6409
6410 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6411 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6412
6413 fw_data = (const __le32 *)
6414 (adev->gfx.mec_fw->data +
6415 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6416
6417 /* Trigger an invalidation of the L1 instruction caches */
6418 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6419 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6420 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6421
6422 /* Wait for invalidation complete */
6423 for (i = 0; i < usec_timeout; i++) {
6424 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6425 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6426 INVALIDATE_CACHE_COMPLETE))
6427 break;
6428 udelay(1);
6429 }
6430
6431 if (i >= usec_timeout) {
6432 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6433 return -EINVAL;
6434 }
6435
6436 if (amdgpu_emu_mode == 1)
6437 adev->hdp.funcs->flush_hdp(adev, NULL);
6438
6439 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6440 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6441 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6442 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6443 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6444
6445 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6446 0xFFFFF000);
6447 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6448 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6449
6450 /* MEC1 */
6451 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6452
6453 for (i = 0; i < mec_hdr->jt_size; i++)
6454 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6455 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6456
6457 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6458
6459 /*
6460 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6461 * different microcode than MEC1.
6462 */
6463
6464 return 0;
6465}
6466
6467static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6468{
6469 uint32_t tmp;
6470 struct amdgpu_device *adev = ring->adev;
6471
6472 /* tell RLC which is KIQ queue */
6473 switch (adev->asic_type) {
6474 case CHIP_SIENNA_CICHLID:
6475 case CHIP_NAVY_FLOUNDER:
6476 case CHIP_VANGOGH:
6477 case CHIP_DIMGREY_CAVEFISH:
6478 case CHIP_BEIGE_GOBY:
6479 case CHIP_YELLOW_CARP:
6480 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6481 tmp &= 0xffffff00;
6482 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6483 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6484 tmp |= 0x80;
6485 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6486 break;
6487 default:
6488 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6489 tmp &= 0xffffff00;
6490 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6491 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6492 tmp |= 0x80;
6493 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6494 break;
6495 }
6496}
6497
6498static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6499{
6500 struct amdgpu_device *adev = ring->adev;
6501 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6502 uint64_t hqd_gpu_addr, wb_gpu_addr;
6503 uint32_t tmp;
6504 uint32_t rb_bufsz;
6505
6506 /* set up gfx hqd wptr */
6507 mqd->cp_gfx_hqd_wptr = 0;
6508 mqd->cp_gfx_hqd_wptr_hi = 0;
6509
6510 /* set the pointer to the MQD */
6511 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6512 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6513
6514 /* set up mqd control */
6515 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6516 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6517 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6518 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6519 mqd->cp_gfx_mqd_control = tmp;
6520
6521 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6522 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6523 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6524 mqd->cp_gfx_hqd_vmid = 0;
6525
6526 /* set up default queue priority level
6527 * 0x0 = low priority, 0x1 = high priority */
6528 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6529 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6530 mqd->cp_gfx_hqd_queue_priority = tmp;
6531
6532 /* set up time quantum */
6533 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6534 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6535 mqd->cp_gfx_hqd_quantum = tmp;
6536
6537 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6538 hqd_gpu_addr = ring->gpu_addr >> 8;
6539 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6540 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6541
6542 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6543 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6544 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6545 mqd->cp_gfx_hqd_rptr_addr_hi =
6546 upper_32_bits(wb_gpu_addr) & 0xffff;
6547
6548 /* set up rb_wptr_poll addr */
6549 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6550 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6551 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6552
6553 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6554 rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6555 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6556 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6557 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6558#ifdef __BIG_ENDIAN
6559 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6560#endif
6561 mqd->cp_gfx_hqd_cntl = tmp;
6562
6563 /* set up cp_doorbell_control */
6564 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6565 if (ring->use_doorbell) {
6566 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6567 DOORBELL_OFFSET, ring->doorbell_index);
6568 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6569 DOORBELL_EN, 1);
6570 } else
6571 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6572 DOORBELL_EN, 0);
6573 mqd->cp_rb_doorbell_control = tmp;
6574
6575 /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6576 *otherwise the range of the second ring will override the first ring */
6577 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6578 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6579
6580 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6581 ring->wptr = 0;
6582 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6583
6584 /* active the queue */
6585 mqd->cp_gfx_hqd_active = 1;
6586
6587 return 0;
6588}
6589
6590#ifdef BRING_UP_DEBUG
6591static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6592{
6593 struct amdgpu_device *adev = ring->adev;
6594 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6595
6596 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6597 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6598 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6599
6600 /* set GFX_MQD_BASE */
6601 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6602 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6603
6604 /* set GFX_MQD_CONTROL */
6605 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6606
6607 /* set GFX_HQD_VMID to 0 */
6608 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6609
6610 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6611 mqd->cp_gfx_hqd_queue_priority);
6612 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6613
6614 /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6615 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6616 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6617
6618 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6619 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6620 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6621
6622 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6623 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6624
6625 /* set RB_WPTR_POLL_ADDR */
6626 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6627 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6628
6629 /* set RB_DOORBELL_CONTROL */
6630 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6631
6632 /* active the queue */
6633 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6634
6635 return 0;
6636}
6637#endif
6638
6639static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6640{
6641 struct amdgpu_device *adev = ring->adev;
6642 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6643 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6644
6645 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6646 memset((void *)mqd, 0, sizeof(*mqd));
6647 mutex_lock(&adev->srbm_mutex);
6648 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6649 gfx_v10_0_gfx_mqd_init(ring);
6650#ifdef BRING_UP_DEBUG
6651 gfx_v10_0_gfx_queue_init_register(ring);
6652#endif
6653 nv_grbm_select(adev, 0, 0, 0, 0);
6654 mutex_unlock(&adev->srbm_mutex);
6655 if (adev->gfx.me.mqd_backup[mqd_idx])
6656 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6657 } else if (amdgpu_in_reset(adev)) {
6658 /* reset mqd with the backup copy */
6659 if (adev->gfx.me.mqd_backup[mqd_idx])
6660 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6661 /* reset the ring */
6662 ring->wptr = 0;
6663 adev->wb.wb[ring->wptr_offs] = 0;
6664 amdgpu_ring_clear_ring(ring);
6665#ifdef BRING_UP_DEBUG
6666 mutex_lock(&adev->srbm_mutex);
6667 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6668 gfx_v10_0_gfx_queue_init_register(ring);
6669 nv_grbm_select(adev, 0, 0, 0, 0);
6670 mutex_unlock(&adev->srbm_mutex);
6671#endif
6672 } else {
6673 amdgpu_ring_clear_ring(ring);
6674 }
6675
6676 return 0;
6677}
6678
6679#ifndef BRING_UP_DEBUG
6680static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6681{
6682 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6683 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6684 int r, i;
6685
6686 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6687 return -EINVAL;
6688
6689 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6690 adev->gfx.num_gfx_rings);
6691 if (r) {
6692 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6693 return r;
6694 }
6695
6696 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6697 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6698
6699 return amdgpu_ring_test_helper(kiq_ring);
6700}
6701#endif
6702
6703static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6704{
6705 int r, i;
6706 struct amdgpu_ring *ring;
6707
6708 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6709 ring = &adev->gfx.gfx_ring[i];
6710
6711 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6712 if (unlikely(r != 0))
6713 goto done;
6714
6715 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6716 if (!r) {
6717 r = gfx_v10_0_gfx_init_queue(ring);
6718 amdgpu_bo_kunmap(ring->mqd_obj);
6719 ring->mqd_ptr = NULL;
6720 }
6721 amdgpu_bo_unreserve(ring->mqd_obj);
6722 if (r)
6723 goto done;
6724 }
6725#ifndef BRING_UP_DEBUG
6726 r = gfx_v10_0_kiq_enable_kgq(adev);
6727 if (r)
6728 goto done;
6729#endif
6730 r = gfx_v10_0_cp_gfx_start(adev);
6731 if (r)
6732 goto done;
6733
6734 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6735 ring = &adev->gfx.gfx_ring[i];
6736 ring->sched.ready = true;
6737 }
6738done:
6739 return r;
6740}
6741
6742static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6743{
6744 struct amdgpu_device *adev = ring->adev;
6745
6746 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6747 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6748 mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6749 mqd->cp_hqd_queue_priority =
6750 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6751 }
6752 }
6753}
6754
6755static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6756{
6757 struct amdgpu_device *adev = ring->adev;
6758 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6759 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6760 uint32_t tmp;
6761
6762 mqd->header = 0xC0310800;
6763 mqd->compute_pipelinestat_enable = 0x00000001;
6764 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6765 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6766 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6767 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6768 mqd->compute_misc_reserved = 0x00000003;
6769
6770 eop_base_addr = ring->eop_gpu_addr >> 8;
6771 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6772 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6773
6774 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6775 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6776 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6777 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6778
6779 mqd->cp_hqd_eop_control = tmp;
6780
6781 /* enable doorbell? */
6782 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6783
6784 if (ring->use_doorbell) {
6785 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6786 DOORBELL_OFFSET, ring->doorbell_index);
6787 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6788 DOORBELL_EN, 1);
6789 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6790 DOORBELL_SOURCE, 0);
6791 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6792 DOORBELL_HIT, 0);
6793 } else {
6794 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6795 DOORBELL_EN, 0);
6796 }
6797
6798 mqd->cp_hqd_pq_doorbell_control = tmp;
6799
6800 /* disable the queue if it's active */
6801 ring->wptr = 0;
6802 mqd->cp_hqd_dequeue_request = 0;
6803 mqd->cp_hqd_pq_rptr = 0;
6804 mqd->cp_hqd_pq_wptr_lo = 0;
6805 mqd->cp_hqd_pq_wptr_hi = 0;
6806
6807 /* set the pointer to the MQD */
6808 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6809 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6810
6811 /* set MQD vmid to 0 */
6812 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6813 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6814 mqd->cp_mqd_control = tmp;
6815
6816 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6817 hqd_gpu_addr = ring->gpu_addr >> 8;
6818 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6819 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6820
6821 /* set up the HQD, this is similar to CP_RB0_CNTL */
6822 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6823 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6824 (order_base_2(ring->ring_size / 4) - 1));
6825 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6826 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6827#ifdef __BIG_ENDIAN
6828 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6829#endif
6830 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6831 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6832 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6833 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6834 mqd->cp_hqd_pq_control = tmp;
6835
6836 /* set the wb address whether it's enabled or not */
6837 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6838 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6839 mqd->cp_hqd_pq_rptr_report_addr_hi =
6840 upper_32_bits(wb_gpu_addr) & 0xffff;
6841
6842 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6843 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6844 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6845 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6846
6847 tmp = 0;
6848 /* enable the doorbell if requested */
6849 if (ring->use_doorbell) {
6850 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6851 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6852 DOORBELL_OFFSET, ring->doorbell_index);
6853
6854 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6855 DOORBELL_EN, 1);
6856 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6857 DOORBELL_SOURCE, 0);
6858 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6859 DOORBELL_HIT, 0);
6860 }
6861
6862 mqd->cp_hqd_pq_doorbell_control = tmp;
6863
6864 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6865 ring->wptr = 0;
6866 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6867
6868 /* set the vmid for the queue */
6869 mqd->cp_hqd_vmid = 0;
6870
6871 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6872 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6873 mqd->cp_hqd_persistent_state = tmp;
6874
6875 /* set MIN_IB_AVAIL_SIZE */
6876 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6877 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6878 mqd->cp_hqd_ib_control = tmp;
6879
6880 /* set static priority for a compute queue/ring */
6881 gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6882
6883 /* map_queues packet doesn't need activate the queue,
6884 * so only kiq need set this field.
6885 */
6886 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6887 mqd->cp_hqd_active = 1;
6888
6889 return 0;
6890}
6891
6892static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6893{
6894 struct amdgpu_device *adev = ring->adev;
6895 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6896 int j;
6897
6898 /* inactivate the queue */
6899 if (amdgpu_sriov_vf(adev))
6900 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6901
6902 /* disable wptr polling */
6903 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6904
6905 /* write the EOP addr */
6906 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6907 mqd->cp_hqd_eop_base_addr_lo);
6908 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6909 mqd->cp_hqd_eop_base_addr_hi);
6910
6911 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6912 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6913 mqd->cp_hqd_eop_control);
6914
6915 /* enable doorbell? */
6916 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6917 mqd->cp_hqd_pq_doorbell_control);
6918
6919 /* disable the queue if it's active */
6920 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6921 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6922 for (j = 0; j < adev->usec_timeout; j++) {
6923 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6924 break;
6925 udelay(1);
6926 }
6927 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6928 mqd->cp_hqd_dequeue_request);
6929 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6930 mqd->cp_hqd_pq_rptr);
6931 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6932 mqd->cp_hqd_pq_wptr_lo);
6933 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6934 mqd->cp_hqd_pq_wptr_hi);
6935 }
6936
6937 /* set the pointer to the MQD */
6938 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6939 mqd->cp_mqd_base_addr_lo);
6940 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6941 mqd->cp_mqd_base_addr_hi);
6942
6943 /* set MQD vmid to 0 */
6944 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6945 mqd->cp_mqd_control);
6946
6947 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6948 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6949 mqd->cp_hqd_pq_base_lo);
6950 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6951 mqd->cp_hqd_pq_base_hi);
6952
6953 /* set up the HQD, this is similar to CP_RB0_CNTL */
6954 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6955 mqd->cp_hqd_pq_control);
6956
6957 /* set the wb address whether it's enabled or not */
6958 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6959 mqd->cp_hqd_pq_rptr_report_addr_lo);
6960 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6961 mqd->cp_hqd_pq_rptr_report_addr_hi);
6962
6963 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6964 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6965 mqd->cp_hqd_pq_wptr_poll_addr_lo);
6966 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6967 mqd->cp_hqd_pq_wptr_poll_addr_hi);
6968
6969 /* enable the doorbell if requested */
6970 if (ring->use_doorbell) {
6971 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6972 (adev->doorbell_index.kiq * 2) << 2);
6973 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6974 (adev->doorbell_index.userqueue_end * 2) << 2);
6975 }
6976
6977 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6978 mqd->cp_hqd_pq_doorbell_control);
6979
6980 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6981 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6982 mqd->cp_hqd_pq_wptr_lo);
6983 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6984 mqd->cp_hqd_pq_wptr_hi);
6985
6986 /* set the vmid for the queue */
6987 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6988
6989 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6990 mqd->cp_hqd_persistent_state);
6991
6992 /* activate the queue */
6993 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6994 mqd->cp_hqd_active);
6995
6996 if (ring->use_doorbell)
6997 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6998
6999 return 0;
7000}
7001
7002static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7003{
7004 struct amdgpu_device *adev = ring->adev;
7005 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7006 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7007
7008 gfx_v10_0_kiq_setting(ring);
7009
7010 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7011 /* reset MQD to a clean status */
7012 if (adev->gfx.mec.mqd_backup[mqd_idx])
7013 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7014
7015 /* reset ring buffer */
7016 ring->wptr = 0;
7017 amdgpu_ring_clear_ring(ring);
7018
7019 mutex_lock(&adev->srbm_mutex);
7020 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7021 gfx_v10_0_kiq_init_register(ring);
7022 nv_grbm_select(adev, 0, 0, 0, 0);
7023 mutex_unlock(&adev->srbm_mutex);
7024 } else {
7025 memset((void *)mqd, 0, sizeof(*mqd));
7026 mutex_lock(&adev->srbm_mutex);
7027 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7028 gfx_v10_0_compute_mqd_init(ring);
7029 gfx_v10_0_kiq_init_register(ring);
7030 nv_grbm_select(adev, 0, 0, 0, 0);
7031 mutex_unlock(&adev->srbm_mutex);
7032
7033 if (adev->gfx.mec.mqd_backup[mqd_idx])
7034 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7035 }
7036
7037 return 0;
7038}
7039
7040static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7041{
7042 struct amdgpu_device *adev = ring->adev;
7043 struct v10_compute_mqd *mqd = ring->mqd_ptr;
7044 int mqd_idx = ring - &adev->gfx.compute_ring[0];
7045
7046 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7047 memset((void *)mqd, 0, sizeof(*mqd));
7048 mutex_lock(&adev->srbm_mutex);
7049 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7050 gfx_v10_0_compute_mqd_init(ring);
7051 nv_grbm_select(adev, 0, 0, 0, 0);
7052 mutex_unlock(&adev->srbm_mutex);
7053
7054 if (adev->gfx.mec.mqd_backup[mqd_idx])
7055 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7056 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7057 /* reset MQD to a clean status */
7058 if (adev->gfx.mec.mqd_backup[mqd_idx])
7059 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7060
7061 /* reset ring buffer */
7062 ring->wptr = 0;
7063 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
7064 amdgpu_ring_clear_ring(ring);
7065 } else {
7066 amdgpu_ring_clear_ring(ring);
7067 }
7068
7069 return 0;
7070}
7071
7072static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7073{
7074 struct amdgpu_ring *ring;
7075 int r;
7076
7077 ring = &adev->gfx.kiq.ring;
7078
7079 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7080 if (unlikely(r != 0))
7081 return r;
7082
7083 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7084 if (unlikely(r != 0))
7085 return r;
7086
7087 gfx_v10_0_kiq_init_queue(ring);
7088 amdgpu_bo_kunmap(ring->mqd_obj);
7089 ring->mqd_ptr = NULL;
7090 amdgpu_bo_unreserve(ring->mqd_obj);
7091 ring->sched.ready = true;
7092 return 0;
7093}
7094
7095static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7096{
7097 struct amdgpu_ring *ring = NULL;
7098 int r = 0, i;
7099
7100 gfx_v10_0_cp_compute_enable(adev, true);
7101
7102 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7103 ring = &adev->gfx.compute_ring[i];
7104
7105 r = amdgpu_bo_reserve(ring->mqd_obj, false);
7106 if (unlikely(r != 0))
7107 goto done;
7108 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7109 if (!r) {
7110 r = gfx_v10_0_kcq_init_queue(ring);
7111 amdgpu_bo_kunmap(ring->mqd_obj);
7112 ring->mqd_ptr = NULL;
7113 }
7114 amdgpu_bo_unreserve(ring->mqd_obj);
7115 if (r)
7116 goto done;
7117 }
7118
7119 r = amdgpu_gfx_enable_kcq(adev);
7120done:
7121 return r;
7122}
7123
7124static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7125{
7126 int r, i;
7127 struct amdgpu_ring *ring;
7128
7129 if (!(adev->flags & AMD_IS_APU))
7130 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7131
7132 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7133 /* legacy firmware loading */
7134 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7135 if (r)
7136 return r;
7137
7138 r = gfx_v10_0_cp_compute_load_microcode(adev);
7139 if (r)
7140 return r;
7141 }
7142
7143 r = gfx_v10_0_kiq_resume(adev);
7144 if (r)
7145 return r;
7146
7147 r = gfx_v10_0_kcq_resume(adev);
7148 if (r)
7149 return r;
7150
7151 if (!amdgpu_async_gfx_ring) {
7152 r = gfx_v10_0_cp_gfx_resume(adev);
7153 if (r)
7154 return r;
7155 } else {
7156 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7157 if (r)
7158 return r;
7159 }
7160
7161 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7162 ring = &adev->gfx.gfx_ring[i];
7163 r = amdgpu_ring_test_helper(ring);
7164 if (r)
7165 return r;
7166 }
7167
7168 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7169 ring = &adev->gfx.compute_ring[i];
7170 r = amdgpu_ring_test_helper(ring);
7171 if (r)
7172 return r;
7173 }
7174
7175 return 0;
7176}
7177
7178static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7179{
7180 gfx_v10_0_cp_gfx_enable(adev, enable);
7181 gfx_v10_0_cp_compute_enable(adev, enable);
7182}
7183
7184static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7185{
7186 uint32_t data, pattern = 0xDEADBEEF;
7187
7188 /* check if mmVGT_ESGS_RING_SIZE_UMD
7189 * has been remapped to mmVGT_ESGS_RING_SIZE */
7190 switch (adev->asic_type) {
7191 case CHIP_SIENNA_CICHLID:
7192 case CHIP_NAVY_FLOUNDER:
7193 case CHIP_DIMGREY_CAVEFISH:
7194 case CHIP_BEIGE_GOBY:
7195 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7196 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7197 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7198
7199 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7200 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7201 return true;
7202 } else {
7203 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7204 return false;
7205 }
7206 break;
7207 case CHIP_VANGOGH:
7208 case CHIP_YELLOW_CARP:
7209 return true;
7210 default:
7211 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7212 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7213 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7214
7215 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7216 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7217 return true;
7218 } else {
7219 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7220 return false;
7221 }
7222 break;
7223 }
7224}
7225
7226static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7227{
7228 uint32_t data;
7229
7230 if (amdgpu_sriov_vf(adev))
7231 return;
7232
7233 /* initialize cam_index to 0
7234 * index will auto-inc after each data writting */
7235 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7236
7237 switch (adev->asic_type) {
7238 case CHIP_SIENNA_CICHLID:
7239 case CHIP_NAVY_FLOUNDER:
7240 case CHIP_VANGOGH:
7241 case CHIP_DIMGREY_CAVEFISH:
7242 case CHIP_BEIGE_GOBY:
7243 case CHIP_YELLOW_CARP:
7244 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7245 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7246 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7247 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7248 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7249 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7250 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7251
7252 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7253 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7254 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7255 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7256 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7257 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7258 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7259
7260 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7261 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7262 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7263 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7264 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7265 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7266 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7267
7268 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7269 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7270 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7271 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7272 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7273 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7274 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7275
7276 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7277 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7278 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7279 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7280 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7281 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7282 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7283
7284 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7285 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7286 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7287 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7288 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7289 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7290 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7291
7292 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7293 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7294 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7295 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7296 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7297 break;
7298 default:
7299 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7300 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7301 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7302 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7303 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7304 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7305 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7306
7307 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7308 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7309 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7310 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7311 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7312 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7313 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7314
7315 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7316 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7317 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7318 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7319 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7320 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7321 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7322
7323 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7324 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7325 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7326 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7327 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7328 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7329 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7330
7331 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7332 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7333 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7334 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7335 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7336 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7337 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7338
7339 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7340 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7341 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7342 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7343 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7344 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7345 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7346
7347 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7348 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7349 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7350 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7351 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7352 break;
7353 }
7354
7355 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7356 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7357}
7358
7359static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7360{
7361 uint32_t data;
7362 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7363 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7364 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7365
7366 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7367 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7368 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7369}
7370
7371static int gfx_v10_0_hw_init(void *handle)
7372{
7373 int r;
7374 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7375
7376 if (!amdgpu_emu_mode)
7377 gfx_v10_0_init_golden_registers(adev);
7378
7379 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7380 /**
7381 * For gfx 10, rlc firmware loading relies on smu firmware is
7382 * loaded firstly, so in direct type, it has to load smc ucode
7383 * here before rlc.
7384 */
7385 if (!(adev->flags & AMD_IS_APU)) {
7386 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7387 if (r)
7388 return r;
7389 }
7390 gfx_v10_0_disable_gpa_mode(adev);
7391 }
7392
7393 /* if GRBM CAM not remapped, set up the remapping */
7394 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7395 gfx_v10_0_setup_grbm_cam_remapping(adev);
7396
7397 gfx_v10_0_constants_init(adev);
7398
7399 r = gfx_v10_0_rlc_resume(adev);
7400 if (r)
7401 return r;
7402
7403 /*
7404 * init golden registers and rlc resume may override some registers,
7405 * reconfig them here
7406 */
7407 if (adev->asic_type == CHIP_NAVI10 ||
7408 adev->asic_type == CHIP_NAVI14 ||
7409 adev->asic_type == CHIP_NAVI12)
7410 gfx_v10_0_tcp_harvest(adev);
7411
7412 r = gfx_v10_0_cp_resume(adev);
7413 if (r)
7414 return r;
7415
7416 if (adev->asic_type == CHIP_SIENNA_CICHLID)
7417 gfx_v10_3_program_pbb_mode(adev);
7418
7419 if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7420 gfx_v10_3_set_power_brake_sequence(adev);
7421
7422 return r;
7423}
7424
7425#ifndef BRING_UP_DEBUG
7426static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7427{
7428 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7429 struct amdgpu_ring *kiq_ring = &kiq->ring;
7430 int i;
7431
7432 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7433 return -EINVAL;
7434
7435 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7436 adev->gfx.num_gfx_rings))
7437 return -ENOMEM;
7438
7439 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7440 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7441 PREEMPT_QUEUES, 0, 0);
7442
7443 return amdgpu_ring_test_helper(kiq_ring);
7444}
7445#endif
7446
7447static int gfx_v10_0_hw_fini(void *handle)
7448{
7449 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7450 int r;
7451 uint32_t tmp;
7452
7453 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7454 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7455
7456 if (!adev->no_hw_access) {
7457#ifndef BRING_UP_DEBUG
7458 if (amdgpu_async_gfx_ring) {
7459 r = gfx_v10_0_kiq_disable_kgq(adev);
7460 if (r)
7461 DRM_ERROR("KGQ disable failed\n");
7462 }
7463#endif
7464 if (amdgpu_gfx_disable_kcq(adev))
7465 DRM_ERROR("KCQ disable failed\n");
7466 }
7467
7468 if (amdgpu_sriov_vf(adev)) {
7469 gfx_v10_0_cp_gfx_enable(adev, false);
7470 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7471 if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
7472 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7473 tmp &= 0xffffff00;
7474 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7475 } else {
7476 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7477 tmp &= 0xffffff00;
7478 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7479 }
7480
7481 return 0;
7482 }
7483 gfx_v10_0_cp_enable(adev, false);
7484 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7485
7486 return 0;
7487}
7488
7489static int gfx_v10_0_suspend(void *handle)
7490{
7491 return gfx_v10_0_hw_fini(handle);
7492}
7493
7494static int gfx_v10_0_resume(void *handle)
7495{
7496 return gfx_v10_0_hw_init(handle);
7497}
7498
7499static bool gfx_v10_0_is_idle(void *handle)
7500{
7501 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7502
7503 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7504 GRBM_STATUS, GUI_ACTIVE))
7505 return false;
7506 else
7507 return true;
7508}
7509
7510static int gfx_v10_0_wait_for_idle(void *handle)
7511{
7512 unsigned i;
7513 u32 tmp;
7514 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7515
7516 for (i = 0; i < adev->usec_timeout; i++) {
7517 /* read MC_STATUS */
7518 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7519 GRBM_STATUS__GUI_ACTIVE_MASK;
7520
7521 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7522 return 0;
7523 udelay(1);
7524 }
7525 return -ETIMEDOUT;
7526}
7527
7528static int gfx_v10_0_soft_reset(void *handle)
7529{
7530 u32 grbm_soft_reset = 0;
7531 u32 tmp;
7532 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7533
7534 /* GRBM_STATUS */
7535 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7536 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7537 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7538 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7539 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7540 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7541 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7542 GRBM_SOFT_RESET, SOFT_RESET_CP,
7543 1);
7544 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7545 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7546 1);
7547 }
7548
7549 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7550 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7551 GRBM_SOFT_RESET, SOFT_RESET_CP,
7552 1);
7553 }
7554
7555 /* GRBM_STATUS2 */
7556 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7557 switch (adev->asic_type) {
7558 case CHIP_SIENNA_CICHLID:
7559 case CHIP_NAVY_FLOUNDER:
7560 case CHIP_VANGOGH:
7561 case CHIP_DIMGREY_CAVEFISH:
7562 case CHIP_BEIGE_GOBY:
7563 case CHIP_YELLOW_CARP:
7564 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7565 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7566 GRBM_SOFT_RESET,
7567 SOFT_RESET_RLC,
7568 1);
7569 break;
7570 default:
7571 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7572 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7573 GRBM_SOFT_RESET,
7574 SOFT_RESET_RLC,
7575 1);
7576 break;
7577 }
7578
7579 if (grbm_soft_reset) {
7580 /* stop the rlc */
7581 gfx_v10_0_rlc_stop(adev);
7582
7583 /* Disable GFX parsing/prefetching */
7584 gfx_v10_0_cp_gfx_enable(adev, false);
7585
7586 /* Disable MEC parsing/prefetching */
7587 gfx_v10_0_cp_compute_enable(adev, false);
7588
7589 if (grbm_soft_reset) {
7590 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7591 tmp |= grbm_soft_reset;
7592 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7593 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7594 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7595
7596 udelay(50);
7597
7598 tmp &= ~grbm_soft_reset;
7599 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7600 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7601 }
7602
7603 /* Wait a little for things to settle down */
7604 udelay(50);
7605 }
7606 return 0;
7607}
7608
7609static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7610{
7611 uint64_t clock;
7612
7613 amdgpu_gfx_off_ctrl(adev, false);
7614 mutex_lock(&adev->gfx.gpu_clock_mutex);
7615 switch (adev->asic_type) {
7616 case CHIP_VANGOGH:
7617 case CHIP_YELLOW_CARP:
7618 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7619 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7620 break;
7621 default:
7622 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7623 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7624 break;
7625 }
7626 mutex_unlock(&adev->gfx.gpu_clock_mutex);
7627 amdgpu_gfx_off_ctrl(adev, true);
7628 return clock;
7629}
7630
7631static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7632 uint32_t vmid,
7633 uint32_t gds_base, uint32_t gds_size,
7634 uint32_t gws_base, uint32_t gws_size,
7635 uint32_t oa_base, uint32_t oa_size)
7636{
7637 struct amdgpu_device *adev = ring->adev;
7638
7639 /* GDS Base */
7640 gfx_v10_0_write_data_to_reg(ring, 0, false,
7641 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7642 gds_base);
7643
7644 /* GDS Size */
7645 gfx_v10_0_write_data_to_reg(ring, 0, false,
7646 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7647 gds_size);
7648
7649 /* GWS */
7650 gfx_v10_0_write_data_to_reg(ring, 0, false,
7651 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7652 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7653
7654 /* OA */
7655 gfx_v10_0_write_data_to_reg(ring, 0, false,
7656 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7657 (1 << (oa_size + oa_base)) - (1 << oa_base));
7658}
7659
7660static int gfx_v10_0_early_init(void *handle)
7661{
7662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7663
7664 switch (adev->asic_type) {
7665 case CHIP_NAVI10:
7666 case CHIP_NAVI14:
7667 case CHIP_NAVI12:
7668 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7669 break;
7670 case CHIP_SIENNA_CICHLID:
7671 case CHIP_NAVY_FLOUNDER:
7672 case CHIP_VANGOGH:
7673 case CHIP_DIMGREY_CAVEFISH:
7674 case CHIP_BEIGE_GOBY:
7675 case CHIP_YELLOW_CARP:
7676 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7677 break;
7678 default:
7679 break;
7680 }
7681
7682 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7683 AMDGPU_MAX_COMPUTE_RINGS);
7684
7685 gfx_v10_0_set_kiq_pm4_funcs(adev);
7686 gfx_v10_0_set_ring_funcs(adev);
7687 gfx_v10_0_set_irq_funcs(adev);
7688 gfx_v10_0_set_gds_init(adev);
7689 gfx_v10_0_set_rlc_funcs(adev);
7690
7691 return 0;
7692}
7693
7694static int gfx_v10_0_late_init(void *handle)
7695{
7696 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7697 int r;
7698
7699 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7700 if (r)
7701 return r;
7702
7703 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7704 if (r)
7705 return r;
7706
7707 return 0;
7708}
7709
7710static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7711{
7712 uint32_t rlc_cntl;
7713
7714 /* if RLC is not enabled, do nothing */
7715 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7716 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7717}
7718
7719static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7720{
7721 uint32_t data;
7722 unsigned i;
7723
7724 data = RLC_SAFE_MODE__CMD_MASK;
7725 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7726
7727 switch (adev->asic_type) {
7728 case CHIP_SIENNA_CICHLID:
7729 case CHIP_NAVY_FLOUNDER:
7730 case CHIP_VANGOGH:
7731 case CHIP_DIMGREY_CAVEFISH:
7732 case CHIP_BEIGE_GOBY:
7733 case CHIP_YELLOW_CARP:
7734 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7735
7736 /* wait for RLC_SAFE_MODE */
7737 for (i = 0; i < adev->usec_timeout; i++) {
7738 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7739 RLC_SAFE_MODE, CMD))
7740 break;
7741 udelay(1);
7742 }
7743 break;
7744 default:
7745 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7746
7747 /* wait for RLC_SAFE_MODE */
7748 for (i = 0; i < adev->usec_timeout; i++) {
7749 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7750 RLC_SAFE_MODE, CMD))
7751 break;
7752 udelay(1);
7753 }
7754 break;
7755 }
7756}
7757
7758static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7759{
7760 uint32_t data;
7761
7762 data = RLC_SAFE_MODE__CMD_MASK;
7763 switch (adev->asic_type) {
7764 case CHIP_SIENNA_CICHLID:
7765 case CHIP_NAVY_FLOUNDER:
7766 case CHIP_VANGOGH:
7767 case CHIP_DIMGREY_CAVEFISH:
7768 case CHIP_BEIGE_GOBY:
7769 case CHIP_YELLOW_CARP:
7770 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7771 break;
7772 default:
7773 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7774 break;
7775 }
7776}
7777
7778static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7779 bool enable)
7780{
7781 uint32_t data, def;
7782
7783 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7784 return;
7785
7786 /* It is disabled by HW by default */
7787 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7788 /* 0 - Disable some blocks' MGCG */
7789 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7790 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7791 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7792 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7793
7794 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7795 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7796 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7797 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7798 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7799 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7800 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7801 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7802
7803 if (def != data)
7804 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7805
7806 /* MGLS is a global flag to control all MGLS in GFX */
7807 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7808 /* 2 - RLC memory Light sleep */
7809 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7810 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7811 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7812 if (def != data)
7813 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7814 }
7815 /* 3 - CP memory Light sleep */
7816 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7817 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7818 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7819 if (def != data)
7820 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7821 }
7822 }
7823 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7824 /* 1 - MGCG_OVERRIDE */
7825 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7826 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7827 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7828 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7829 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7830 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7831 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7832 if (def != data)
7833 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7834
7835 /* 2 - disable MGLS in CP */
7836 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7837 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7838 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7839 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7840 }
7841
7842 /* 3 - disable MGLS in RLC */
7843 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7844 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7845 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7846 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7847 }
7848
7849 }
7850}
7851
7852static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7853 bool enable)
7854{
7855 uint32_t data, def;
7856
7857 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7858 return;
7859
7860 /* Enable 3D CGCG/CGLS */
7861 if (enable) {
7862 /* write cmd to clear cgcg/cgls ov */
7863 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7864
7865 /* unset CGCG override */
7866 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7867 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7868
7869 /* update CGCG and CGLS override bits */
7870 if (def != data)
7871 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7872
7873 /* enable 3Dcgcg FSM(0x0000363f) */
7874 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7875 data = 0;
7876
7877 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7878 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7879 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7880
7881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7882 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7883 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7884
7885 if (def != data)
7886 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7887
7888 /* set IDLE_POLL_COUNT(0x00900100) */
7889 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7890 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7891 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7892 if (def != data)
7893 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7894 } else {
7895 /* Disable CGCG/CGLS */
7896 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7897
7898 /* disable cgcg, cgls should be disabled */
7899 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7900 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7901
7902 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7903 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7904
7905 /* disable cgcg and cgls in FSM */
7906 if (def != data)
7907 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7908 }
7909}
7910
7911static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7912 bool enable)
7913{
7914 uint32_t def, data;
7915
7916 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7917 return;
7918
7919 if (enable) {
7920 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7921
7922 /* unset CGCG override */
7923 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7924 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7925
7926 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7927 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7928
7929 /* update CGCG and CGLS override bits */
7930 if (def != data)
7931 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7932
7933 /* enable cgcg FSM(0x0000363F) */
7934 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7935 data = 0;
7936
7937 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7938 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7939 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7940
7941 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7942 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7943 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7944
7945 if (def != data)
7946 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7947
7948 /* set IDLE_POLL_COUNT(0x00900100) */
7949 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7950 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7951 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7952 if (def != data)
7953 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7954 } else {
7955 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7956
7957 /* reset CGCG/CGLS bits */
7958 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7959 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7960
7961 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7962 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7963
7964 /* disable cgcg and cgls in FSM */
7965 if (def != data)
7966 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7967 }
7968}
7969
7970static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7971 bool enable)
7972{
7973 uint32_t def, data;
7974
7975 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7976 return;
7977
7978 if (enable) {
7979 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7980 /* unset FGCG override */
7981 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7982 /* update FGCG override bits */
7983 if (def != data)
7984 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7985
7986 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7987 /* unset RLC SRAM CLK GATER override */
7988 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7989 /* update RLC SRAM CLK GATER override bits */
7990 if (def != data)
7991 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7992 } else {
7993 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7994 /* reset FGCG bits */
7995 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7996 /* disable FGCG*/
7997 if (def != data)
7998 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7999
8000 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8001 /* reset RLC SRAM CLK GATER bits */
8002 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8003 /* disable RLC SRAM CLK*/
8004 if (def != data)
8005 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8006 }
8007}
8008
8009static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8010{
8011 uint32_t reg_data = 0;
8012 uint32_t reg_idx = 0;
8013 uint32_t i;
8014
8015 const uint32_t tcp_ctrl_regs[] = {
8016 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8017 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8018 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8019 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8020 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8021 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8022 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8023 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8024 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8025 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8026 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8027 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8028 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8029 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8030 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8031 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8032 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8033 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8034 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8035 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8036 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8037 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8038 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8039 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8040 };
8041
8042 const uint32_t tcp_ctrl_regs_nv12[] = {
8043 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8044 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8045 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8046 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8047 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8048 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8049 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8050 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8051 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8052 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8053 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8054 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8055 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8056 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8057 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8058 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8059 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8060 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8061 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8062 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8063 };
8064
8065 const uint32_t sm_ctlr_regs[] = {
8066 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8067 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8068 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8069 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8070 };
8071
8072 if (adev->asic_type == CHIP_NAVI12) {
8073 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8074 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8075 tcp_ctrl_regs_nv12[i];
8076 reg_data = RREG32(reg_idx);
8077 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8078 WREG32(reg_idx, reg_data);
8079 }
8080 } else {
8081 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8082 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8083 tcp_ctrl_regs[i];
8084 reg_data = RREG32(reg_idx);
8085 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8086 WREG32(reg_idx, reg_data);
8087 }
8088 }
8089
8090 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8091 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8092 sm_ctlr_regs[i];
8093 reg_data = RREG32(reg_idx);
8094 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8095 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8096 WREG32(reg_idx, reg_data);
8097 }
8098}
8099
8100static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8101 bool enable)
8102{
8103 amdgpu_gfx_rlc_enter_safe_mode(adev);
8104
8105 if (enable) {
8106 /* enable FGCG firstly*/
8107 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8108 /* CGCG/CGLS should be enabled after MGCG/MGLS
8109 * === MGCG + MGLS ===
8110 */
8111 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8112 /* === CGCG /CGLS for GFX 3D Only === */
8113 gfx_v10_0_update_3d_clock_gating(adev, enable);
8114 /* === CGCG + CGLS === */
8115 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8116
8117 if ((adev->asic_type >= CHIP_NAVI10) &&
8118 (adev->asic_type <= CHIP_NAVI12))
8119 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8120 } else {
8121 /* CGCG/CGLS should be disabled before MGCG/MGLS
8122 * === CGCG + CGLS ===
8123 */
8124 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8125 /* === CGCG /CGLS for GFX 3D Only === */
8126 gfx_v10_0_update_3d_clock_gating(adev, enable);
8127 /* === MGCG + MGLS === */
8128 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8129 /* disable fgcg at last*/
8130 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8131 }
8132
8133 if (adev->cg_flags &
8134 (AMD_CG_SUPPORT_GFX_MGCG |
8135 AMD_CG_SUPPORT_GFX_CGLS |
8136 AMD_CG_SUPPORT_GFX_CGCG |
8137 AMD_CG_SUPPORT_GFX_3D_CGCG |
8138 AMD_CG_SUPPORT_GFX_3D_CGLS))
8139 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8140
8141 amdgpu_gfx_rlc_exit_safe_mode(adev);
8142
8143 return 0;
8144}
8145
8146static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8147{
8148 u32 reg, data;
8149 /* not for *_SOC15 */
8150 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8151 if (amdgpu_sriov_is_pp_one_vf(adev))
8152 data = RREG32_NO_KIQ(reg);
8153 else
8154 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8155
8156 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8157 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8158
8159 if (amdgpu_sriov_is_pp_one_vf(adev))
8160 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8161 else
8162 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8163}
8164
8165static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8166 uint32_t offset,
8167 struct soc15_reg_rlcg *entries, int arr_size)
8168{
8169 int i;
8170 uint32_t reg;
8171
8172 if (!entries)
8173 return false;
8174
8175 for (i = 0; i < arr_size; i++) {
8176 const struct soc15_reg_rlcg *entry;
8177
8178 entry = &entries[i];
8179 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8180 if (offset == reg)
8181 return true;
8182 }
8183
8184 return false;
8185}
8186
8187static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8188{
8189 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8190}
8191
8192static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8193{
8194 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8195
8196 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8197 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8198 else
8199 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8200
8201 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8202
8203 /*
8204 * CGPG enablement required and the register to program the hysteresis value
8205 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8206 * in refclk count. Note that RLC FW is modified to take 16 bits from
8207 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8208 *
8209 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8210 * of CGPG enablement starting point.
8211 * Power/performance team will optimize it and might give a new value later.
8212 */
8213 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8214 switch (adev->asic_type) {
8215 case CHIP_VANGOGH:
8216 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8217 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8218 break;
8219 case CHIP_YELLOW_CARP:
8220 data = 0x1388 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8221 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8222 break;
8223 default:
8224 break;
8225 }
8226 }
8227}
8228
8229static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8230{
8231 amdgpu_gfx_rlc_enter_safe_mode(adev);
8232
8233 gfx_v10_cntl_power_gating(adev, enable);
8234
8235 amdgpu_gfx_rlc_exit_safe_mode(adev);
8236}
8237
8238static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8239 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8240 .set_safe_mode = gfx_v10_0_set_safe_mode,
8241 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8242 .init = gfx_v10_0_rlc_init,
8243 .get_csb_size = gfx_v10_0_get_csb_size,
8244 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8245 .resume = gfx_v10_0_rlc_resume,
8246 .stop = gfx_v10_0_rlc_stop,
8247 .reset = gfx_v10_0_rlc_reset,
8248 .start = gfx_v10_0_rlc_start,
8249 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8250};
8251
8252static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8253 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8254 .set_safe_mode = gfx_v10_0_set_safe_mode,
8255 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8256 .init = gfx_v10_0_rlc_init,
8257 .get_csb_size = gfx_v10_0_get_csb_size,
8258 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8259 .resume = gfx_v10_0_rlc_resume,
8260 .stop = gfx_v10_0_rlc_stop,
8261 .reset = gfx_v10_0_rlc_reset,
8262 .start = gfx_v10_0_rlc_start,
8263 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8264 .rlcg_wreg = gfx_v10_rlcg_wreg,
8265 .rlcg_rreg = gfx_v10_rlcg_rreg,
8266 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8267};
8268
8269static int gfx_v10_0_set_powergating_state(void *handle,
8270 enum amd_powergating_state state)
8271{
8272 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8273 bool enable = (state == AMD_PG_STATE_GATE);
8274
8275 if (amdgpu_sriov_vf(adev))
8276 return 0;
8277
8278 switch (adev->asic_type) {
8279 case CHIP_NAVI10:
8280 case CHIP_NAVI14:
8281 case CHIP_NAVI12:
8282 case CHIP_SIENNA_CICHLID:
8283 case CHIP_NAVY_FLOUNDER:
8284 case CHIP_DIMGREY_CAVEFISH:
8285 case CHIP_BEIGE_GOBY:
8286 amdgpu_gfx_off_ctrl(adev, enable);
8287 break;
8288 case CHIP_VANGOGH:
8289 case CHIP_YELLOW_CARP:
8290 gfx_v10_cntl_pg(adev, enable);
8291 amdgpu_gfx_off_ctrl(adev, enable);
8292 break;
8293 default:
8294 break;
8295 }
8296 return 0;
8297}
8298
8299static int gfx_v10_0_set_clockgating_state(void *handle,
8300 enum amd_clockgating_state state)
8301{
8302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8303
8304 if (amdgpu_sriov_vf(adev))
8305 return 0;
8306
8307 switch (adev->asic_type) {
8308 case CHIP_NAVI10:
8309 case CHIP_NAVI14:
8310 case CHIP_NAVI12:
8311 case CHIP_SIENNA_CICHLID:
8312 case CHIP_NAVY_FLOUNDER:
8313 case CHIP_VANGOGH:
8314 case CHIP_DIMGREY_CAVEFISH:
8315 case CHIP_BEIGE_GOBY:
8316 case CHIP_YELLOW_CARP:
8317 gfx_v10_0_update_gfx_clock_gating(adev,
8318 state == AMD_CG_STATE_GATE);
8319 break;
8320 default:
8321 break;
8322 }
8323 return 0;
8324}
8325
8326static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
8327{
8328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8329 int data;
8330
8331 /* AMD_CG_SUPPORT_GFX_FGCG */
8332 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8333 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8334 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8335
8336 /* AMD_CG_SUPPORT_GFX_MGCG */
8337 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8338 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8339 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8340
8341 /* AMD_CG_SUPPORT_GFX_CGCG */
8342 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8343 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8344 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8345
8346 /* AMD_CG_SUPPORT_GFX_CGLS */
8347 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8348 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8349
8350 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8351 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8352 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8353 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8354
8355 /* AMD_CG_SUPPORT_GFX_CP_LS */
8356 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8357 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8358 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8359
8360 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8361 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8362 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8363 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8364
8365 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8366 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8367 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8368}
8369
8370static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8371{
8372 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
8373}
8374
8375static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8376{
8377 struct amdgpu_device *adev = ring->adev;
8378 u64 wptr;
8379
8380 /* XXX check if swapping is necessary on BE */
8381 if (ring->use_doorbell) {
8382 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8383 } else {
8384 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8385 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8386 }
8387
8388 return wptr;
8389}
8390
8391static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8392{
8393 struct amdgpu_device *adev = ring->adev;
8394
8395 if (ring->use_doorbell) {
8396 /* XXX check if swapping is necessary on BE */
8397 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8398 WDOORBELL64(ring->doorbell_index, ring->wptr);
8399 } else {
8400 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8401 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8402 }
8403}
8404
8405static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8406{
8407 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8408}
8409
8410static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8411{
8412 u64 wptr;
8413
8414 /* XXX check if swapping is necessary on BE */
8415 if (ring->use_doorbell)
8416 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8417 else
8418 BUG();
8419 return wptr;
8420}
8421
8422static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8423{
8424 struct amdgpu_device *adev = ring->adev;
8425
8426 /* XXX check if swapping is necessary on BE */
8427 if (ring->use_doorbell) {
8428 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8429 WDOORBELL64(ring->doorbell_index, ring->wptr);
8430 } else {
8431 BUG(); /* only DOORBELL method supported on gfx10 now */
8432 }
8433}
8434
8435static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8436{
8437 struct amdgpu_device *adev = ring->adev;
8438 u32 ref_and_mask, reg_mem_engine;
8439 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8440
8441 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8442 switch (ring->me) {
8443 case 1:
8444 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8445 break;
8446 case 2:
8447 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8448 break;
8449 default:
8450 return;
8451 }
8452 reg_mem_engine = 0;
8453 } else {
8454 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8455 reg_mem_engine = 1; /* pfp */
8456 }
8457
8458 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8459 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8460 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8461 ref_and_mask, ref_and_mask, 0x20);
8462}
8463
8464static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8465 struct amdgpu_job *job,
8466 struct amdgpu_ib *ib,
8467 uint32_t flags)
8468{
8469 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8470 u32 header, control = 0;
8471
8472 if (ib->flags & AMDGPU_IB_FLAG_CE)
8473 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8474 else
8475 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8476
8477 control |= ib->length_dw | (vmid << 24);
8478
8479 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8480 control |= INDIRECT_BUFFER_PRE_ENB(1);
8481
8482 if (flags & AMDGPU_IB_PREEMPTED)
8483 control |= INDIRECT_BUFFER_PRE_RESUME(1);
8484
8485 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8486 gfx_v10_0_ring_emit_de_meta(ring,
8487 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8488 }
8489
8490 amdgpu_ring_write(ring, header);
8491 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8492 amdgpu_ring_write(ring,
8493#ifdef __BIG_ENDIAN
8494 (2 << 0) |
8495#endif
8496 lower_32_bits(ib->gpu_addr));
8497 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8498 amdgpu_ring_write(ring, control);
8499}
8500
8501static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8502 struct amdgpu_job *job,
8503 struct amdgpu_ib *ib,
8504 uint32_t flags)
8505{
8506 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8507 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8508
8509 /* Currently, there is a high possibility to get wave ID mismatch
8510 * between ME and GDS, leading to a hw deadlock, because ME generates
8511 * different wave IDs than the GDS expects. This situation happens
8512 * randomly when at least 5 compute pipes use GDS ordered append.
8513 * The wave IDs generated by ME are also wrong after suspend/resume.
8514 * Those are probably bugs somewhere else in the kernel driver.
8515 *
8516 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8517 * GDS to 0 for this ring (me/pipe).
8518 */
8519 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8520 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8521 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8522 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8523 }
8524
8525 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8526 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8527 amdgpu_ring_write(ring,
8528#ifdef __BIG_ENDIAN
8529 (2 << 0) |
8530#endif
8531 lower_32_bits(ib->gpu_addr));
8532 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8533 amdgpu_ring_write(ring, control);
8534}
8535
8536static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8537 u64 seq, unsigned flags)
8538{
8539 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8540 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8541
8542 /* RELEASE_MEM - flush caches, send int */
8543 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8544 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8545 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8546 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8547 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8548 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8549 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8550 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8551 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8552 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8553
8554 /*
8555 * the address should be Qword aligned if 64bit write, Dword
8556 * aligned if only send 32bit data low (discard data high)
8557 */
8558 if (write64bit)
8559 BUG_ON(addr & 0x7);
8560 else
8561 BUG_ON(addr & 0x3);
8562 amdgpu_ring_write(ring, lower_32_bits(addr));
8563 amdgpu_ring_write(ring, upper_32_bits(addr));
8564 amdgpu_ring_write(ring, lower_32_bits(seq));
8565 amdgpu_ring_write(ring, upper_32_bits(seq));
8566 amdgpu_ring_write(ring, 0);
8567}
8568
8569static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8570{
8571 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8572 uint32_t seq = ring->fence_drv.sync_seq;
8573 uint64_t addr = ring->fence_drv.gpu_addr;
8574
8575 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8576 upper_32_bits(addr), seq, 0xffffffff, 4);
8577}
8578
8579static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8580 unsigned vmid, uint64_t pd_addr)
8581{
8582 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8583
8584 /* compute doesn't have PFP */
8585 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8586 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8587 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8588 amdgpu_ring_write(ring, 0x0);
8589 }
8590}
8591
8592static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8593 u64 seq, unsigned int flags)
8594{
8595 struct amdgpu_device *adev = ring->adev;
8596
8597 /* we only allocate 32bit for each seq wb address */
8598 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8599
8600 /* write fence seq to the "addr" */
8601 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8602 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8603 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8604 amdgpu_ring_write(ring, lower_32_bits(addr));
8605 amdgpu_ring_write(ring, upper_32_bits(addr));
8606 amdgpu_ring_write(ring, lower_32_bits(seq));
8607
8608 if (flags & AMDGPU_FENCE_FLAG_INT) {
8609 /* set register to trigger INT */
8610 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8611 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8612 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8613 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8614 amdgpu_ring_write(ring, 0);
8615 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8616 }
8617}
8618
8619static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8620{
8621 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8622 amdgpu_ring_write(ring, 0);
8623}
8624
8625static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8626 uint32_t flags)
8627{
8628 uint32_t dw2 = 0;
8629
8630 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8631 gfx_v10_0_ring_emit_ce_meta(ring,
8632 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8633
8634 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8635 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8636 /* set load_global_config & load_global_uconfig */
8637 dw2 |= 0x8001;
8638 /* set load_cs_sh_regs */
8639 dw2 |= 0x01000000;
8640 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8641 dw2 |= 0x10002;
8642
8643 /* set load_ce_ram if preamble presented */
8644 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8645 dw2 |= 0x10000000;
8646 } else {
8647 /* still load_ce_ram if this is the first time preamble presented
8648 * although there is no context switch happens.
8649 */
8650 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8651 dw2 |= 0x10000000;
8652 }
8653
8654 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8655 amdgpu_ring_write(ring, dw2);
8656 amdgpu_ring_write(ring, 0);
8657}
8658
8659static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8660{
8661 unsigned ret;
8662
8663 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8664 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8665 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8666 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8667 ret = ring->wptr & ring->buf_mask;
8668 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8669
8670 return ret;
8671}
8672
8673static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8674{
8675 unsigned cur;
8676 BUG_ON(offset > ring->buf_mask);
8677 BUG_ON(ring->ring[offset] != 0x55aa55aa);
8678
8679 cur = (ring->wptr - 1) & ring->buf_mask;
8680 if (likely(cur > offset))
8681 ring->ring[offset] = cur - offset;
8682 else
8683 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8684}
8685
8686static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8687{
8688 int i, r = 0;
8689 struct amdgpu_device *adev = ring->adev;
8690 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8691 struct amdgpu_ring *kiq_ring = &kiq->ring;
8692 unsigned long flags;
8693
8694 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8695 return -EINVAL;
8696
8697 spin_lock_irqsave(&kiq->ring_lock, flags);
8698
8699 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8700 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8701 return -ENOMEM;
8702 }
8703
8704 /* assert preemption condition */
8705 amdgpu_ring_set_preempt_cond_exec(ring, false);
8706
8707 /* assert IB preemption, emit the trailing fence */
8708 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8709 ring->trail_fence_gpu_addr,
8710 ++ring->trail_seq);
8711 amdgpu_ring_commit(kiq_ring);
8712
8713 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8714
8715 /* poll the trailing fence */
8716 for (i = 0; i < adev->usec_timeout; i++) {
8717 if (ring->trail_seq ==
8718 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8719 break;
8720 udelay(1);
8721 }
8722
8723 if (i >= adev->usec_timeout) {
8724 r = -EINVAL;
8725 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8726 }
8727
8728 /* deassert preemption condition */
8729 amdgpu_ring_set_preempt_cond_exec(ring, true);
8730 return r;
8731}
8732
8733static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8734{
8735 struct amdgpu_device *adev = ring->adev;
8736 struct v10_ce_ib_state ce_payload = {0};
8737 uint64_t csa_addr;
8738 int cnt;
8739
8740 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8741 csa_addr = amdgpu_csa_vaddr(ring->adev);
8742
8743 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8744 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8745 WRITE_DATA_DST_SEL(8) |
8746 WR_CONFIRM) |
8747 WRITE_DATA_CACHE_POLICY(0));
8748 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8749 offsetof(struct v10_gfx_meta_data, ce_payload)));
8750 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8751 offsetof(struct v10_gfx_meta_data, ce_payload)));
8752
8753 if (resume)
8754 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8755 offsetof(struct v10_gfx_meta_data,
8756 ce_payload),
8757 sizeof(ce_payload) >> 2);
8758 else
8759 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8760 sizeof(ce_payload) >> 2);
8761}
8762
8763static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8764{
8765 struct amdgpu_device *adev = ring->adev;
8766 struct v10_de_ib_state de_payload = {0};
8767 uint64_t csa_addr, gds_addr;
8768 int cnt;
8769
8770 csa_addr = amdgpu_csa_vaddr(ring->adev);
8771 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8772 PAGE_SIZE);
8773 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8774 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8775
8776 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8777 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8778 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8779 WRITE_DATA_DST_SEL(8) |
8780 WR_CONFIRM) |
8781 WRITE_DATA_CACHE_POLICY(0));
8782 amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8783 offsetof(struct v10_gfx_meta_data, de_payload)));
8784 amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8785 offsetof(struct v10_gfx_meta_data, de_payload)));
8786
8787 if (resume)
8788 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8789 offsetof(struct v10_gfx_meta_data,
8790 de_payload),
8791 sizeof(de_payload) >> 2);
8792 else
8793 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8794 sizeof(de_payload) >> 2);
8795}
8796
8797static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8798 bool secure)
8799{
8800 uint32_t v = secure ? FRAME_TMZ : 0;
8801
8802 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8803 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8804}
8805
8806static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8807 uint32_t reg_val_offs)
8808{
8809 struct amdgpu_device *adev = ring->adev;
8810
8811 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8812 amdgpu_ring_write(ring, 0 | /* src: register*/
8813 (5 << 8) | /* dst: memory */
8814 (1 << 20)); /* write confirm */
8815 amdgpu_ring_write(ring, reg);
8816 amdgpu_ring_write(ring, 0);
8817 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8818 reg_val_offs * 4));
8819 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8820 reg_val_offs * 4));
8821}
8822
8823static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8824 uint32_t val)
8825{
8826 uint32_t cmd = 0;
8827
8828 switch (ring->funcs->type) {
8829 case AMDGPU_RING_TYPE_GFX:
8830 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8831 break;
8832 case AMDGPU_RING_TYPE_KIQ:
8833 cmd = (1 << 16); /* no inc addr */
8834 break;
8835 default:
8836 cmd = WR_CONFIRM;
8837 break;
8838 }
8839 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8840 amdgpu_ring_write(ring, cmd);
8841 amdgpu_ring_write(ring, reg);
8842 amdgpu_ring_write(ring, 0);
8843 amdgpu_ring_write(ring, val);
8844}
8845
8846static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8847 uint32_t val, uint32_t mask)
8848{
8849 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8850}
8851
8852static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8853 uint32_t reg0, uint32_t reg1,
8854 uint32_t ref, uint32_t mask)
8855{
8856 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8857 struct amdgpu_device *adev = ring->adev;
8858 bool fw_version_ok = false;
8859
8860 fw_version_ok = adev->gfx.cp_fw_write_wait;
8861
8862 if (fw_version_ok)
8863 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8864 ref, mask, 0x20);
8865 else
8866 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8867 ref, mask);
8868}
8869
8870static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8871 unsigned vmid)
8872{
8873 struct amdgpu_device *adev = ring->adev;
8874 uint32_t value = 0;
8875
8876 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8877 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8878 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8879 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8880 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8881}
8882
8883static void
8884gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8885 uint32_t me, uint32_t pipe,
8886 enum amdgpu_interrupt_state state)
8887{
8888 uint32_t cp_int_cntl, cp_int_cntl_reg;
8889
8890 if (!me) {
8891 switch (pipe) {
8892 case 0:
8893 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8894 break;
8895 case 1:
8896 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8897 break;
8898 default:
8899 DRM_DEBUG("invalid pipe %d\n", pipe);
8900 return;
8901 }
8902 } else {
8903 DRM_DEBUG("invalid me %d\n", me);
8904 return;
8905 }
8906
8907 switch (state) {
8908 case AMDGPU_IRQ_STATE_DISABLE:
8909 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8910 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8911 TIME_STAMP_INT_ENABLE, 0);
8912 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8913 break;
8914 case AMDGPU_IRQ_STATE_ENABLE:
8915 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8916 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8917 TIME_STAMP_INT_ENABLE, 1);
8918 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8919 break;
8920 default:
8921 break;
8922 }
8923}
8924
8925static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8926 int me, int pipe,
8927 enum amdgpu_interrupt_state state)
8928{
8929 u32 mec_int_cntl, mec_int_cntl_reg;
8930
8931 /*
8932 * amdgpu controls only the first MEC. That's why this function only
8933 * handles the setting of interrupts for this specific MEC. All other
8934 * pipes' interrupts are set by amdkfd.
8935 */
8936
8937 if (me == 1) {
8938 switch (pipe) {
8939 case 0:
8940 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8941 break;
8942 case 1:
8943 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8944 break;
8945 case 2:
8946 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8947 break;
8948 case 3:
8949 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8950 break;
8951 default:
8952 DRM_DEBUG("invalid pipe %d\n", pipe);
8953 return;
8954 }
8955 } else {
8956 DRM_DEBUG("invalid me %d\n", me);
8957 return;
8958 }
8959
8960 switch (state) {
8961 case AMDGPU_IRQ_STATE_DISABLE:
8962 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8963 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8964 TIME_STAMP_INT_ENABLE, 0);
8965 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8966 break;
8967 case AMDGPU_IRQ_STATE_ENABLE:
8968 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
8969 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8970 TIME_STAMP_INT_ENABLE, 1);
8971 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
8972 break;
8973 default:
8974 break;
8975 }
8976}
8977
8978static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8979 struct amdgpu_irq_src *src,
8980 unsigned type,
8981 enum amdgpu_interrupt_state state)
8982{
8983 switch (type) {
8984 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8985 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8986 break;
8987 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8988 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8989 break;
8990 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8991 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8992 break;
8993 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8994 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8995 break;
8996 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8997 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8998 break;
8999 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9000 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9001 break;
9002 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9003 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9004 break;
9005 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9006 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9007 break;
9008 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9009 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9010 break;
9011 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9012 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9013 break;
9014 default:
9015 break;
9016 }
9017 return 0;
9018}
9019
9020static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9021 struct amdgpu_irq_src *source,
9022 struct amdgpu_iv_entry *entry)
9023{
9024 int i;
9025 u8 me_id, pipe_id, queue_id;
9026 struct amdgpu_ring *ring;
9027
9028 DRM_DEBUG("IH: CP EOP\n");
9029 me_id = (entry->ring_id & 0x0c) >> 2;
9030 pipe_id = (entry->ring_id & 0x03) >> 0;
9031 queue_id = (entry->ring_id & 0x70) >> 4;
9032
9033 switch (me_id) {
9034 case 0:
9035 if (pipe_id == 0)
9036 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9037 else
9038 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9039 break;
9040 case 1:
9041 case 2:
9042 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9043 ring = &adev->gfx.compute_ring[i];
9044 /* Per-queue interrupt is supported for MEC starting from VI.
9045 * The interrupt can only be enabled/disabled per pipe instead of per queue.
9046 */
9047 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
9048 amdgpu_fence_process(ring);
9049 }
9050 break;
9051 }
9052 return 0;
9053}
9054
9055static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9056 struct amdgpu_irq_src *source,
9057 unsigned type,
9058 enum amdgpu_interrupt_state state)
9059{
9060 switch (state) {
9061 case AMDGPU_IRQ_STATE_DISABLE:
9062 case AMDGPU_IRQ_STATE_ENABLE:
9063 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9064 PRIV_REG_INT_ENABLE,
9065 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9066 break;
9067 default:
9068 break;
9069 }
9070
9071 return 0;
9072}
9073
9074static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9075 struct amdgpu_irq_src *source,
9076 unsigned type,
9077 enum amdgpu_interrupt_state state)
9078{
9079 switch (state) {
9080 case AMDGPU_IRQ_STATE_DISABLE:
9081 case AMDGPU_IRQ_STATE_ENABLE:
9082 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9083 PRIV_INSTR_INT_ENABLE,
9084 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9085 break;
9086 default:
9087 break;
9088 }
9089
9090 return 0;
9091}
9092
9093static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9094 struct amdgpu_iv_entry *entry)
9095{
9096 u8 me_id, pipe_id, queue_id;
9097 struct amdgpu_ring *ring;
9098 int i;
9099
9100 me_id = (entry->ring_id & 0x0c) >> 2;
9101 pipe_id = (entry->ring_id & 0x03) >> 0;
9102 queue_id = (entry->ring_id & 0x70) >> 4;
9103
9104 switch (me_id) {
9105 case 0:
9106 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9107 ring = &adev->gfx.gfx_ring[i];
9108 /* we only enabled 1 gfx queue per pipe for now */
9109 if (ring->me == me_id && ring->pipe == pipe_id)
9110 drm_sched_fault(&ring->sched);
9111 }
9112 break;
9113 case 1:
9114 case 2:
9115 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9116 ring = &adev->gfx.compute_ring[i];
9117 if (ring->me == me_id && ring->pipe == pipe_id &&
9118 ring->queue == queue_id)
9119 drm_sched_fault(&ring->sched);
9120 }
9121 break;
9122 default:
9123 BUG();
9124 }
9125}
9126
9127static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9128 struct amdgpu_irq_src *source,
9129 struct amdgpu_iv_entry *entry)
9130{
9131 DRM_ERROR("Illegal register access in command stream\n");
9132 gfx_v10_0_handle_priv_fault(adev, entry);
9133 return 0;
9134}
9135
9136static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9137 struct amdgpu_irq_src *source,
9138 struct amdgpu_iv_entry *entry)
9139{
9140 DRM_ERROR("Illegal instruction in command stream\n");
9141 gfx_v10_0_handle_priv_fault(adev, entry);
9142 return 0;
9143}
9144
9145static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9146 struct amdgpu_irq_src *src,
9147 unsigned int type,
9148 enum amdgpu_interrupt_state state)
9149{
9150 uint32_t tmp, target;
9151 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9152
9153 if (ring->me == 1)
9154 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9155 else
9156 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9157 target += ring->pipe;
9158
9159 switch (type) {
9160 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9161 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9162 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9163 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9164 GENERIC2_INT_ENABLE, 0);
9165 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9166
9167 tmp = RREG32_SOC15_IP(GC, target);
9168 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9169 GENERIC2_INT_ENABLE, 0);
9170 WREG32_SOC15_IP(GC, target, tmp);
9171 } else {
9172 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9173 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9174 GENERIC2_INT_ENABLE, 1);
9175 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9176
9177 tmp = RREG32_SOC15_IP(GC, target);
9178 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9179 GENERIC2_INT_ENABLE, 1);
9180 WREG32_SOC15_IP(GC, target, tmp);
9181 }
9182 break;
9183 default:
9184 BUG(); /* kiq only support GENERIC2_INT now */
9185 break;
9186 }
9187 return 0;
9188}
9189
9190static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9191 struct amdgpu_irq_src *source,
9192 struct amdgpu_iv_entry *entry)
9193{
9194 u8 me_id, pipe_id, queue_id;
9195 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9196
9197 me_id = (entry->ring_id & 0x0c) >> 2;
9198 pipe_id = (entry->ring_id & 0x03) >> 0;
9199 queue_id = (entry->ring_id & 0x70) >> 4;
9200 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9201 me_id, pipe_id, queue_id);
9202
9203 amdgpu_fence_process(ring);
9204 return 0;
9205}
9206
9207static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9208{
9209 const unsigned int gcr_cntl =
9210 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9211 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9212 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9213 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9214 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9215 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9216 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9217 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9218
9219 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9220 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9221 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9222 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9223 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9224 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9225 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9226 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9227 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9228}
9229
9230static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9231 .name = "gfx_v10_0",
9232 .early_init = gfx_v10_0_early_init,
9233 .late_init = gfx_v10_0_late_init,
9234 .sw_init = gfx_v10_0_sw_init,
9235 .sw_fini = gfx_v10_0_sw_fini,
9236 .hw_init = gfx_v10_0_hw_init,
9237 .hw_fini = gfx_v10_0_hw_fini,
9238 .suspend = gfx_v10_0_suspend,
9239 .resume = gfx_v10_0_resume,
9240 .is_idle = gfx_v10_0_is_idle,
9241 .wait_for_idle = gfx_v10_0_wait_for_idle,
9242 .soft_reset = gfx_v10_0_soft_reset,
9243 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9244 .set_powergating_state = gfx_v10_0_set_powergating_state,
9245 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9246};
9247
9248static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9249 .type = AMDGPU_RING_TYPE_GFX,
9250 .align_mask = 0xff,
9251 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9252 .support_64bit_ptrs = true,
9253 .vmhub = AMDGPU_GFXHUB_0,
9254 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9255 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9256 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9257 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9258 5 + /* COND_EXEC */
9259 7 + /* PIPELINE_SYNC */
9260 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9261 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9262 2 + /* VM_FLUSH */
9263 8 + /* FENCE for VM_FLUSH */
9264 20 + /* GDS switch */
9265 4 + /* double SWITCH_BUFFER,
9266 * the first COND_EXEC jump to the place
9267 * just prior to this double SWITCH_BUFFER
9268 */
9269 5 + /* COND_EXEC */
9270 7 + /* HDP_flush */
9271 4 + /* VGT_flush */
9272 14 + /* CE_META */
9273 31 + /* DE_META */
9274 3 + /* CNTX_CTRL */
9275 5 + /* HDP_INVL */
9276 8 + 8 + /* FENCE x2 */
9277 2 + /* SWITCH_BUFFER */
9278 8, /* gfx_v10_0_emit_mem_sync */
9279 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9280 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9281 .emit_fence = gfx_v10_0_ring_emit_fence,
9282 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9283 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9284 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9285 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9286 .test_ring = gfx_v10_0_ring_test_ring,
9287 .test_ib = gfx_v10_0_ring_test_ib,
9288 .insert_nop = amdgpu_ring_insert_nop,
9289 .pad_ib = amdgpu_ring_generic_pad_ib,
9290 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9291 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9292 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9293 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9294 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9295 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9296 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9297 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9298 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9299 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9300 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9301};
9302
9303static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9304 .type = AMDGPU_RING_TYPE_COMPUTE,
9305 .align_mask = 0xff,
9306 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9307 .support_64bit_ptrs = true,
9308 .vmhub = AMDGPU_GFXHUB_0,
9309 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9310 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9311 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9312 .emit_frame_size =
9313 20 + /* gfx_v10_0_ring_emit_gds_switch */
9314 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9315 5 + /* hdp invalidate */
9316 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9317 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9318 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9319 2 + /* gfx_v10_0_ring_emit_vm_flush */
9320 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9321 8, /* gfx_v10_0_emit_mem_sync */
9322 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9323 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9324 .emit_fence = gfx_v10_0_ring_emit_fence,
9325 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9326 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9327 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9328 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9329 .test_ring = gfx_v10_0_ring_test_ring,
9330 .test_ib = gfx_v10_0_ring_test_ib,
9331 .insert_nop = amdgpu_ring_insert_nop,
9332 .pad_ib = amdgpu_ring_generic_pad_ib,
9333 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9334 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9335 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9336 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9337};
9338
9339static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9340 .type = AMDGPU_RING_TYPE_KIQ,
9341 .align_mask = 0xff,
9342 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9343 .support_64bit_ptrs = true,
9344 .vmhub = AMDGPU_GFXHUB_0,
9345 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9346 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9347 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9348 .emit_frame_size =
9349 20 + /* gfx_v10_0_ring_emit_gds_switch */
9350 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9351 5 + /*hdp invalidate */
9352 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9353 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9354 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9355 2 + /* gfx_v10_0_ring_emit_vm_flush */
9356 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9357 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9358 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9359 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9360 .test_ring = gfx_v10_0_ring_test_ring,
9361 .test_ib = gfx_v10_0_ring_test_ib,
9362 .insert_nop = amdgpu_ring_insert_nop,
9363 .pad_ib = amdgpu_ring_generic_pad_ib,
9364 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9365 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9366 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9367 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9368};
9369
9370static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9371{
9372 int i;
9373
9374 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9375
9376 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9377 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9378
9379 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9380 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9381}
9382
9383static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9384 .set = gfx_v10_0_set_eop_interrupt_state,
9385 .process = gfx_v10_0_eop_irq,
9386};
9387
9388static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9389 .set = gfx_v10_0_set_priv_reg_fault_state,
9390 .process = gfx_v10_0_priv_reg_irq,
9391};
9392
9393static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9394 .set = gfx_v10_0_set_priv_inst_fault_state,
9395 .process = gfx_v10_0_priv_inst_irq,
9396};
9397
9398static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9399 .set = gfx_v10_0_kiq_set_interrupt_state,
9400 .process = gfx_v10_0_kiq_irq,
9401};
9402
9403static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9404{
9405 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9406 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9407
9408 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9409 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9410
9411 adev->gfx.priv_reg_irq.num_types = 1;
9412 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9413
9414 adev->gfx.priv_inst_irq.num_types = 1;
9415 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9416}
9417
9418static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9419{
9420 switch (adev->asic_type) {
9421 case CHIP_NAVI10:
9422 case CHIP_NAVI14:
9423 case CHIP_NAVY_FLOUNDER:
9424 case CHIP_VANGOGH:
9425 case CHIP_DIMGREY_CAVEFISH:
9426 case CHIP_BEIGE_GOBY:
9427 case CHIP_YELLOW_CARP:
9428 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9429 break;
9430 case CHIP_NAVI12:
9431 case CHIP_SIENNA_CICHLID:
9432 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9433 break;
9434 default:
9435 break;
9436 }
9437}
9438
9439static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9440{
9441 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9442 adev->gfx.config.max_sh_per_se *
9443 adev->gfx.config.max_shader_engines;
9444
9445 adev->gds.gds_size = 0x10000;
9446 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9447 adev->gds.gws_size = 64;
9448 adev->gds.oa_size = 16;
9449}
9450
9451static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9452 u32 bitmap)
9453{
9454 u32 data;
9455
9456 if (!bitmap)
9457 return;
9458
9459 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9460 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9461
9462 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9463}
9464
9465static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9466{
9467 u32 disabled_mask =
9468 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9469 u32 efuse_setting = 0;
9470 u32 vbios_setting = 0;
9471
9472 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9473 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9474 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9475
9476 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9477 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9478 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9479
9480 disabled_mask |= efuse_setting | vbios_setting;
9481
9482 return (~disabled_mask);
9483}
9484
9485static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9486{
9487 u32 wgp_idx, wgp_active_bitmap;
9488 u32 cu_bitmap_per_wgp, cu_active_bitmap;
9489
9490 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9491 cu_active_bitmap = 0;
9492
9493 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9494 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9495 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9496 if (wgp_active_bitmap & (1 << wgp_idx))
9497 cu_active_bitmap |= cu_bitmap_per_wgp;
9498 }
9499
9500 return cu_active_bitmap;
9501}
9502
9503static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9504 struct amdgpu_cu_info *cu_info)
9505{
9506 int i, j, k, counter, active_cu_number = 0;
9507 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9508 unsigned disable_masks[4 * 2];
9509
9510 if (!adev || !cu_info)
9511 return -EINVAL;
9512
9513 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9514
9515 mutex_lock(&adev->grbm_idx_mutex);
9516 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9517 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9518 bitmap = i * adev->gfx.config.max_sh_per_se + j;
9519 if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
9520 (adev->asic_type == CHIP_YELLOW_CARP)) &&
9521 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9522 continue;
9523 mask = 1;
9524 ao_bitmap = 0;
9525 counter = 0;
9526 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9527 if (i < 4 && j < 2)
9528 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9529 adev, disable_masks[i * 2 + j]);
9530 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9531 cu_info->bitmap[i][j] = bitmap;
9532
9533 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9534 if (bitmap & mask) {
9535 if (counter < adev->gfx.config.max_cu_per_sh)
9536 ao_bitmap |= mask;
9537 counter++;
9538 }
9539 mask <<= 1;
9540 }
9541 active_cu_number += counter;
9542 if (i < 2 && j < 2)
9543 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9544 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9545 }
9546 }
9547 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9548 mutex_unlock(&adev->grbm_idx_mutex);
9549
9550 cu_info->number = active_cu_number;
9551 cu_info->ao_cu_mask = ao_cu_mask;
9552 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9553
9554 return 0;
9555}
9556
9557static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9558{
9559 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9560
9561 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9562 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9563 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9564
9565 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9566 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9567 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9568
9569 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9570 adev->gfx.config.max_shader_engines);
9571 disabled_sa = efuse_setting | vbios_setting;
9572 disabled_sa &= max_sa_mask;
9573
9574 return disabled_sa;
9575}
9576
9577static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9578{
9579 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9580 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9581
9582 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9583
9584 max_sa_per_se = adev->gfx.config.max_sh_per_se;
9585 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9586 max_shader_engines = adev->gfx.config.max_shader_engines;
9587
9588 for (se_index = 0; max_shader_engines > se_index; se_index++) {
9589 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9590 disabled_sa_per_se &= max_sa_per_se_mask;
9591 if (disabled_sa_per_se == max_sa_per_se_mask) {
9592 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9593 break;
9594 }
9595 }
9596}
9597
9598static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9599{
9600 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9601 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9602 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9603 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9604
9605 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9606 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9607 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9608 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9609 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9610 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9611
9612 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9613 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9614 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9615 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9616
9617 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9618
9619 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9620 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9621}
9622
9623const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9624{
9625 .type = AMD_IP_BLOCK_TYPE_GFX,
9626 .major = 10,
9627 .minor = 0,
9628 .rev = 0,
9629 .funcs = &gfx_v10_0_ip_funcs,
9630};