1#include <linux/threads.h>
 
 
  2#include <linux/cpumask.h>
  3#include <linux/string.h>
  4#include <linux/kernel.h>
  5#include <linux/ctype.h>
  6#include <linux/init.h>
  7#include <linux/dmar.h>
  8#include <linux/cpu.h>
  9
 10#include <asm/smp.h>
 11#include <asm/x2apic.h>
 
 
 
 12
 13static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
 14static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
 15static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
 
 
 16
 17static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 18{
 19	return x2apic_enabled();
 20}
 21
 22static inline u32 x2apic_cluster(int cpu)
 23{
 24	return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
 
 
 
 
 25}
 26
 27static void
 28__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
 29{
 30	struct cpumask *cpus_in_cluster_ptr;
 31	struct cpumask *ipi_mask_ptr;
 32	unsigned int cpu, this_cpu;
 33	unsigned long flags;
 34	u32 dest;
 35
 36	x2apic_wrmsr_fence();
 37
 38	local_irq_save(flags);
 39
 40	this_cpu = smp_processor_id();
 41
 42	/*
 43	 * We are to modify mask, so we need an own copy
 44	 * and be sure it's manipulated with irq off.
 45	 */
 46	ipi_mask_ptr = __raw_get_cpu_var(ipi_mask);
 47	cpumask_copy(ipi_mask_ptr, mask);
 48
 49	/*
 50	 * The idea is to send one IPI per cluster.
 51	 */
 52	for_each_cpu(cpu, ipi_mask_ptr) {
 53		unsigned long i;
 54
 55		cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
 56		dest = 0;
 57
 58		/* Collect cpus in cluster. */
 59		for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
 60			if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
 61				dest |= per_cpu(x86_cpu_to_logical_apicid, i);
 62		}
 63
 64		if (!dest)
 65			continue;
 66
 67		__x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
 68		/*
 69		 * Cluster sibling cpus should be discared now so
 70		 * we would not send IPI them second time.
 71		 */
 72		cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
 73	}
 74
 75	local_irq_restore(flags);
 76}
 77
 78static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
 79{
 80	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
 81}
 82
 83static void
 84 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 85{
 86	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
 87}
 88
 89static void x2apic_send_IPI_allbutself(int vector)
 90{
 91	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
 92}
 93
 94static void x2apic_send_IPI_all(int vector)
 95{
 96	__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
 97}
 98
 99static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
100{
101	/*
102	 * We're using fixed IRQ delivery, can only return one logical APIC ID.
103	 * May as well be the first.
104	 */
105	int cpu = cpumask_first(cpumask);
106
107	if ((unsigned)cpu < nr_cpu_ids)
108		return per_cpu(x86_cpu_to_logical_apicid, cpu);
109	else
110		return BAD_APICID;
111}
112
113static unsigned int
114x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
115			      const struct cpumask *andmask)
116{
117	int cpu;
118
119	/*
120	 * We're using fixed IRQ delivery, can only return one logical APIC ID.
121	 * May as well be the first.
122	 */
123	for_each_cpu_and(cpu, cpumask, andmask) {
124		if (cpumask_test_cpu(cpu, cpu_online_mask))
125			break;
126	}
127
128	return per_cpu(x86_cpu_to_logical_apicid, cpu);
129}
130
131static void init_x2apic_ldr(void)
132{
133	unsigned int this_cpu = smp_processor_id();
 
134	unsigned int cpu;
135
136	per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
 
 
 
137
138	__cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
139	for_each_online_cpu(cpu) {
140		if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
141			continue;
142		__cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu));
143		__cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu));
144	}
 
 
 
 
 
 
145}
146
147 /*
148  * At CPU state changes, update the x2apic cluster sibling info.
149  */
150static int __cpuinit
151update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu)
152{
153	unsigned int this_cpu = (unsigned long)hcpu;
154	unsigned int cpu;
155	int err = 0;
156
157	switch (action) {
158	case CPU_UP_PREPARE:
159		if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu),
160					GFP_KERNEL)) {
161			err = -ENOMEM;
162		} else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu),
163					       GFP_KERNEL)) {
164			free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
165			err = -ENOMEM;
166		}
167		break;
168	case CPU_UP_CANCELED:
169	case CPU_UP_CANCELED_FROZEN:
170	case CPU_DEAD:
171		for_each_online_cpu(cpu) {
172			if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
173				continue;
174			__cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu));
175			__cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu));
176		}
177		free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
178		free_cpumask_var(per_cpu(ipi_mask, this_cpu));
179		break;
180	}
181
182	return notifier_from_errno(err);
 
 
 
 
 
183}
184
185static struct notifier_block __refdata x2apic_cpu_notifier = {
186	.notifier_call = update_clusterinfo,
187};
188
189static int x2apic_init_cpu_notifier(void)
190{
191	int cpu = smp_processor_id();
192
193	zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL);
194	zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL);
 
 
195
196	BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu));
 
 
197
198	__cpu_set(cpu, per_cpu(cpus_in_cluster, cpu));
199	register_hotcpu_notifier(&x2apic_cpu_notifier);
200	return 1;
 
201}
202
203static int x2apic_cluster_probe(void)
204{
205	if (x2apic_mode)
206		return x2apic_init_cpu_notifier();
207	else
 
 
 
208		return 0;
 
 
 
209}
210
211static struct apic apic_x2apic_cluster = {
212
213	.name				= "cluster x2apic",
214	.probe				= x2apic_cluster_probe,
215	.acpi_madt_oem_check		= x2apic_acpi_madt_oem_check,
 
216	.apic_id_registered		= x2apic_apic_id_registered,
217
218	.irq_delivery_mode		= dest_LowestPrio,
219	.irq_dest_mode			= 1, /* logical */
220
221	.target_cpus			= x2apic_target_cpus,
222	.disable_esr			= 0,
223	.dest_logical			= APIC_DEST_LOGICAL,
224	.check_apicid_used		= NULL,
225	.check_apicid_present		= NULL,
226
227	.vector_allocation_domain	= x2apic_vector_allocation_domain,
228	.init_apic_ldr			= init_x2apic_ldr,
229
230	.ioapic_phys_id_map		= NULL,
231	.setup_apic_routing		= NULL,
232	.multi_timer_check		= NULL,
233	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
234	.apicid_to_cpu_present		= NULL,
235	.setup_portio_remap		= NULL,
236	.check_phys_apicid_present	= default_check_phys_apicid_present,
237	.enable_apic_mode		= NULL,
238	.phys_pkg_id			= x2apic_phys_pkg_id,
239	.mps_oem_check			= NULL,
240
241	.get_apic_id			= x2apic_get_apic_id,
242	.set_apic_id			= x2apic_set_apic_id,
243	.apic_id_mask			= 0xFFFFFFFFu,
244
245	.cpu_mask_to_apicid		= x2apic_cpu_mask_to_apicid,
246	.cpu_mask_to_apicid_and		= x2apic_cpu_mask_to_apicid_and,
247
 
248	.send_IPI_mask			= x2apic_send_IPI_mask,
249	.send_IPI_mask_allbutself	= x2apic_send_IPI_mask_allbutself,
250	.send_IPI_allbutself		= x2apic_send_IPI_allbutself,
251	.send_IPI_all			= x2apic_send_IPI_all,
252	.send_IPI_self			= x2apic_send_IPI_self,
253
254	.trampoline_phys_low		= DEFAULT_TRAMPOLINE_PHYS_LOW,
255	.trampoline_phys_high		= DEFAULT_TRAMPOLINE_PHYS_HIGH,
256	.wait_for_init_deassert		= NULL,
257	.smp_callin_clear_local_apic	= NULL,
258	.inquire_remote_apic		= NULL,
259
260	.read				= native_apic_msr_read,
261	.write				= native_apic_msr_write,
 
262	.icr_read			= native_x2apic_icr_read,
263	.icr_write			= native_x2apic_icr_write,
264	.wait_icr_idle			= native_x2apic_wait_icr_idle,
265	.safe_wait_icr_idle		= native_safe_x2apic_wait_icr_idle,
266};
267
268apic_driver(apic_x2apic_cluster);

  1// SPDX-License-Identifier: GPL-2.0
  2
  3#include <linux/cpuhotplug.h>
  4#include <linux/cpumask.h>
  5#include <linux/slab.h>
  6#include <linux/mm.h>
  7
  8#include <asm/apic.h>
  9
 10#include "local.h"
 11
 12struct cluster_mask {
 13	unsigned int	clusterid;
 14	int		node;
 15	struct cpumask	mask;
 16};
 17
 18static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
 
 19static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
 20static DEFINE_PER_CPU(struct cluster_mask *, cluster_masks);
 21static struct cluster_mask *cluster_hotplug_mask;
 22
 23static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 24{
 25	return x2apic_enabled();
 26}
 27
 28static void x2apic_send_IPI(int cpu, int vector)
 29{
 30	u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu);
 31
 32	/* x2apic MSRs are special and need a special fence: */
 33	weak_wrmsr_fence();
 34	__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 35}
 36
 37static void
 38__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
 39{
 40	unsigned int cpu, clustercpu;
 41	struct cpumask *tmpmsk;
 
 42	unsigned long flags;
 43	u32 dest;
 44
 45	/* x2apic MSRs are special and need a special fence: */
 46	weak_wrmsr_fence();
 47	local_irq_save(flags);
 48
 49	tmpmsk = this_cpu_cpumask_var_ptr(ipi_mask);
 50	cpumask_copy(tmpmsk, mask);
 51	/* If IPI should not be sent to self, clear current CPU */
 52	if (apic_dest != APIC_DEST_ALLINC)
 53		__cpumask_clear_cpu(smp_processor_id(), tmpmsk);
 54
 55	/* Collapse cpus in a cluster so a single IPI per cluster is sent */
 56	for_each_cpu(cpu, tmpmsk) {
 57		struct cluster_mask *cmsk = per_cpu(cluster_masks, cpu);
 
 
 
 
 
 58
 
 59		dest = 0;
 60		for_each_cpu_and(clustercpu, tmpmsk, &cmsk->mask)
 61			dest |= per_cpu(x86_cpu_to_logical_apicid, clustercpu);
 
 
 
 
 62
 63		if (!dest)
 64			continue;
 65
 66		__x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL);
 67		/* Remove cluster CPUs from tmpmask */
 68		cpumask_andnot(tmpmsk, tmpmsk, &cmsk->mask);
 
 
 
 69	}
 70
 71	local_irq_restore(flags);
 72}
 73
 74static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
 75{
 76	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
 77}
 78
 79static void
 80x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 81{
 82	__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
 83}
 84
 85static void x2apic_send_IPI_allbutself(int vector)
 86{
 87	__x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLBUT);
 88}
 89
 90static void x2apic_send_IPI_all(int vector)
 91{
 92	__x2apic_send_IPI_shorthand(vector, APIC_DEST_ALLINC);
 93}
 94
 95static u32 x2apic_calc_apicid(unsigned int cpu)
 96{
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 97	return per_cpu(x86_cpu_to_logical_apicid, cpu);
 98}
 99
100static void init_x2apic_ldr(void)
101{
102	struct cluster_mask *cmsk = this_cpu_read(cluster_masks);
103	u32 cluster, apicid = apic_read(APIC_LDR);
104	unsigned int cpu;
105
106	this_cpu_write(x86_cpu_to_logical_apicid, apicid);
107
108	if (cmsk)
109		goto update;
110
111	cluster = apicid >> 16;
112	for_each_online_cpu(cpu) {
113		cmsk = per_cpu(cluster_masks, cpu);
114		/* Matching cluster found. Link and update it. */
115		if (cmsk && cmsk->clusterid == cluster)
116			goto update;
117	}
118	cmsk = cluster_hotplug_mask;
119	cmsk->clusterid = cluster;
120	cluster_hotplug_mask = NULL;
121update:
122	this_cpu_write(cluster_masks, cmsk);
123	cpumask_set_cpu(smp_processor_id(), &cmsk->mask);
124}
125
126static int alloc_clustermask(unsigned int cpu, int node)
 
 
 
 
127{
128	if (per_cpu(cluster_masks, cpu))
129		return 0;
130	/*
131	 * If a hotplug spare mask exists, check whether it's on the right
132	 * node. If not, free it and allocate a new one.
133	 */
134	if (cluster_hotplug_mask) {
135		if (cluster_hotplug_mask->node == node)
136			return 0;
137		kfree(cluster_hotplug_mask);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
138	}
139
140	cluster_hotplug_mask = kzalloc_node(sizeof(*cluster_hotplug_mask),
141					    GFP_KERNEL, node);
142	if (!cluster_hotplug_mask)
143		return -ENOMEM;
144	cluster_hotplug_mask->node = node;
145	return 0;
146}
147
148static int x2apic_prepare_cpu(unsigned int cpu)
 
 
 
 
149{
150	if (alloc_clustermask(cpu, cpu_to_node(cpu)) < 0)
151		return -ENOMEM;
152	if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL))
153		return -ENOMEM;
154	return 0;
155}
156
157static int x2apic_dead_cpu(unsigned int dead_cpu)
158{
159	struct cluster_mask *cmsk = per_cpu(cluster_masks, dead_cpu);
160
161	if (cmsk)
162		cpumask_clear_cpu(dead_cpu, &cmsk->mask);
163	free_cpumask_var(per_cpu(ipi_mask, dead_cpu));
164	return 0;
165}
166
167static int x2apic_cluster_probe(void)
168{
169	if (!x2apic_mode)
170		return 0;
171
172	if (cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare",
173			      x2apic_prepare_cpu, x2apic_dead_cpu) < 0) {
174		pr_err("Failed to register X2APIC_PREPARE\n");
175		return 0;
176	}
177	init_x2apic_ldr();
178	return 1;
179}
180
181static struct apic apic_x2apic_cluster __ro_after_init = {
182
183	.name				= "cluster x2apic",
184	.probe				= x2apic_cluster_probe,
185	.acpi_madt_oem_check		= x2apic_acpi_madt_oem_check,
186	.apic_id_valid			= x2apic_apic_id_valid,
187	.apic_id_registered		= x2apic_apic_id_registered,
188
189	.delivery_mode			= APIC_DELIVERY_MODE_FIXED,
190	.dest_mode_logical		= true,
191
 
192	.disable_esr			= 0,
 
 
 
193
194	.check_apicid_used		= NULL,
195	.init_apic_ldr			= init_x2apic_ldr,
 
196	.ioapic_phys_id_map		= NULL,
197	.setup_apic_routing		= NULL,
 
198	.cpu_present_to_apicid		= default_cpu_present_to_apicid,
199	.apicid_to_cpu_present		= NULL,
 
200	.check_phys_apicid_present	= default_check_phys_apicid_present,
 
201	.phys_pkg_id			= x2apic_phys_pkg_id,
 
202
203	.get_apic_id			= x2apic_get_apic_id,
204	.set_apic_id			= x2apic_set_apic_id,
 
205
206	.calc_dest_apicid		= x2apic_calc_apicid,
 
207
208	.send_IPI			= x2apic_send_IPI,
209	.send_IPI_mask			= x2apic_send_IPI_mask,
210	.send_IPI_mask_allbutself	= x2apic_send_IPI_mask_allbutself,
211	.send_IPI_allbutself		= x2apic_send_IPI_allbutself,
212	.send_IPI_all			= x2apic_send_IPI_all,
213	.send_IPI_self			= x2apic_send_IPI_self,
214
 
 
 
 
215	.inquire_remote_apic		= NULL,
216
217	.read				= native_apic_msr_read,
218	.write				= native_apic_msr_write,
219	.eoi_write			= native_apic_msr_eoi_write,
220	.icr_read			= native_x2apic_icr_read,
221	.icr_write			= native_x2apic_icr_write,
222	.wait_icr_idle			= native_x2apic_wait_icr_idle,
223	.safe_wait_icr_idle		= native_safe_x2apic_wait_icr_idle,
224};
225
226apic_driver(apic_x2apic_cluster);