Loading...
1/* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/pci.h>
18#include <linux/msi.h>
19#include <linux/irq.h>
20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23
24#include <asm/uaccess.h>
25#include <asm/pgtable.h>
26#include <asm/irq.h>
27#include <asm/prom.h>
28#include <asm/apb.h>
29
30#include "pci_impl.h"
31
32/* List of all PCI controllers found in the system. */
33struct pci_pbm_info *pci_pbm_root = NULL;
34
35/* Each PBM found gets a unique index. */
36int pci_num_pbms = 0;
37
38volatile int pci_poke_in_progress;
39volatile int pci_poke_cpu = -1;
40volatile int pci_poke_faulted;
41
42static DEFINE_SPINLOCK(pci_poke_lock);
43
44void pci_config_read8(u8 *addr, u8 *ret)
45{
46 unsigned long flags;
47 u8 byte;
48
49 spin_lock_irqsave(&pci_poke_lock, flags);
50 pci_poke_cpu = smp_processor_id();
51 pci_poke_in_progress = 1;
52 pci_poke_faulted = 0;
53 __asm__ __volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
55 "membar #Sync"
56 : "=r" (byte)
57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
58 : "memory");
59 pci_poke_in_progress = 0;
60 pci_poke_cpu = -1;
61 if (!pci_poke_faulted)
62 *ret = byte;
63 spin_unlock_irqrestore(&pci_poke_lock, flags);
64}
65
66void pci_config_read16(u16 *addr, u16 *ret)
67{
68 unsigned long flags;
69 u16 word;
70
71 spin_lock_irqsave(&pci_poke_lock, flags);
72 pci_poke_cpu = smp_processor_id();
73 pci_poke_in_progress = 1;
74 pci_poke_faulted = 0;
75 __asm__ __volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
77 "membar #Sync"
78 : "=r" (word)
79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
80 : "memory");
81 pci_poke_in_progress = 0;
82 pci_poke_cpu = -1;
83 if (!pci_poke_faulted)
84 *ret = word;
85 spin_unlock_irqrestore(&pci_poke_lock, flags);
86}
87
88void pci_config_read32(u32 *addr, u32 *ret)
89{
90 unsigned long flags;
91 u32 dword;
92
93 spin_lock_irqsave(&pci_poke_lock, flags);
94 pci_poke_cpu = smp_processor_id();
95 pci_poke_in_progress = 1;
96 pci_poke_faulted = 0;
97 __asm__ __volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
99 "membar #Sync"
100 : "=r" (dword)
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
102 : "memory");
103 pci_poke_in_progress = 0;
104 pci_poke_cpu = -1;
105 if (!pci_poke_faulted)
106 *ret = dword;
107 spin_unlock_irqrestore(&pci_poke_lock, flags);
108}
109
110void pci_config_write8(u8 *addr, u8 val)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&pci_poke_lock, flags);
115 pci_poke_cpu = smp_processor_id();
116 pci_poke_in_progress = 1;
117 pci_poke_faulted = 0;
118 __asm__ __volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* no outputs */
122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 : "memory");
124 pci_poke_in_progress = 0;
125 pci_poke_cpu = -1;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write16(u16 *addr, u16 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write32(u32 *addr, u32 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167static int ofpci_verbose;
168
169static int __init ofpci_debug(char *str)
170{
171 int val = 0;
172
173 get_option(&str, &val);
174 if (val)
175 ofpci_verbose = 1;
176 return 1;
177}
178
179__setup("ofpci_debug=", ofpci_debug);
180
181static unsigned long pci_parse_of_flags(u32 addr0)
182{
183 unsigned long flags = 0;
184
185 if (addr0 & 0x02000000) {
186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x40000000)
190 flags |= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 } else if (addr0 & 0x01000000)
193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
194 return flags;
195}
196
197/* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
199 * mapping.
200 */
201static void pci_parse_of_addrs(struct platform_device *op,
202 struct device_node *node,
203 struct pci_dev *dev)
204{
205 struct resource *op_res;
206 const u32 *addrs;
207 int proplen;
208
209 addrs = of_get_property(node, "assigned-addresses", &proplen);
210 if (!addrs)
211 return;
212 if (ofpci_verbose)
213 printk(" parse addresses (%d bytes) @ %p\n",
214 proplen, addrs);
215 op_res = &op->resource[0];
216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 struct resource *res;
218 unsigned long flags;
219 int i;
220
221 flags = pci_parse_of_flags(addrs[0]);
222 if (!flags)
223 continue;
224 i = addrs[0] & 0xff;
225 if (ofpci_verbose)
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res->start, op_res->end, i);
228
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 | IORESOURCE_SIZEALIGN;
235 } else {
236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
237 continue;
238 }
239 res->start = op_res->start;
240 res->end = op_res->end;
241 res->flags = flags;
242 res->name = pci_name(dev);
243 }
244}
245
246static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct device_node *node,
248 struct pci_bus *bus, int devfn)
249{
250 struct dev_archdata *sd;
251 struct pci_slot *slot;
252 struct platform_device *op;
253 struct pci_dev *dev;
254 const char *type;
255 u32 class;
256
257 dev = alloc_pci_dev();
258 if (!dev)
259 return NULL;
260
261 sd = &dev->dev.archdata;
262 sd->iommu = pbm->iommu;
263 sd->stc = &pbm->stc;
264 sd->host_controller = pbm;
265 sd->op = op = of_find_device_by_node(node);
266 sd->numa_node = pbm->numa_node;
267
268 sd = &op->dev.archdata;
269 sd->iommu = pbm->iommu;
270 sd->stc = &pbm->stc;
271 sd->numa_node = pbm->numa_node;
272
273 if (!strcmp(node->name, "ebus"))
274 of_propagate_archdata(op);
275
276 type = of_get_property(node, "device_type", NULL);
277 if (type == NULL)
278 type = "";
279
280 if (ofpci_verbose)
281 printk(" create device, devfn: %x, type: %s\n",
282 devfn, type);
283
284 dev->bus = bus;
285 dev->sysdata = node;
286 dev->dev.parent = bus->bridge;
287 dev->dev.bus = &pci_bus_type;
288 dev->dev.of_node = of_node_get(node);
289 dev->devfn = devfn;
290 dev->multifunction = 0; /* maybe a lie? */
291 set_pcie_port_type(dev);
292
293 list_for_each_entry(slot, &dev->bus->slots, list)
294 if (PCI_SLOT(dev->devfn) == slot->number)
295 dev->slot = slot;
296
297 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
298 dev->device = of_getintprop_default(node, "device-id", 0xffff);
299 dev->subsystem_vendor =
300 of_getintprop_default(node, "subsystem-vendor-id", 0);
301 dev->subsystem_device =
302 of_getintprop_default(node, "subsystem-id", 0);
303
304 dev->cfg_size = pci_cfg_space_size(dev);
305
306 /* We can't actually use the firmware value, we have
307 * to read what is in the register right now. One
308 * reason is that in the case of IDE interfaces the
309 * firmware can sample the value before the the IDE
310 * interface is programmed into native mode.
311 */
312 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
313 dev->class = class >> 8;
314 dev->revision = class & 0xff;
315
316 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
317 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
318
319 if (ofpci_verbose)
320 printk(" class: 0x%x device name: %s\n",
321 dev->class, pci_name(dev));
322
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
325 * disabled.
326 */
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 pci_set_master(dev);
329
330 dev->current_state = 4; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
333
334 if (!strcmp(node->name, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (!strcmp(type, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 } else {
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
343
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
347 }
348
349 pci_parse_of_addrs(sd->op, node, dev);
350
351 if (ofpci_verbose)
352 printk(" adding to system ...\n");
353
354 pci_device_add(dev, bus);
355
356 return dev;
357}
358
359static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
360{
361 u32 idx, first, last;
362
363 first = 8;
364 last = 0;
365 for (idx = 0; idx < 8; idx++) {
366 if ((map & (1 << idx)) != 0) {
367 if (first > idx)
368 first = idx;
369 if (last < idx)
370 last = idx;
371 }
372 }
373
374 *first_p = first;
375 *last_p = last;
376}
377
378static void pci_resource_adjust(struct resource *res,
379 struct resource *root)
380{
381 res->start += root->start;
382 res->end += root->start;
383}
384
385/* For PCI bus devices which lack a 'ranges' property we interrogate
386 * the config space values to set the resources, just like the generic
387 * Linux PCI probing code does.
388 */
389static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
390 struct pci_bus *bus,
391 struct pci_pbm_info *pbm)
392{
393 struct resource *res;
394 u8 io_base_lo, io_limit_lo;
395 u16 mem_base_lo, mem_limit_lo;
396 unsigned long base, limit;
397
398 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
399 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
400 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
401 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
402
403 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
404 u16 io_base_hi, io_limit_hi;
405
406 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
407 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
408 base |= (io_base_hi << 16);
409 limit |= (io_limit_hi << 16);
410 }
411
412 res = bus->resource[0];
413 if (base <= limit) {
414 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
415 if (!res->start)
416 res->start = base;
417 if (!res->end)
418 res->end = limit + 0xfff;
419 pci_resource_adjust(res, &pbm->io_space);
420 }
421
422 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
423 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
424 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
425 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
426
427 res = bus->resource[1];
428 if (base <= limit) {
429 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
430 IORESOURCE_MEM);
431 res->start = base;
432 res->end = limit + 0xfffff;
433 pci_resource_adjust(res, &pbm->mem_space);
434 }
435
436 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
437 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
438 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
439 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
440
441 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
442 u32 mem_base_hi, mem_limit_hi;
443
444 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
445 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
446
447 /*
448 * Some bridges set the base > limit by default, and some
449 * (broken) BIOSes do not initialize them. If we find
450 * this, just assume they are not being used.
451 */
452 if (mem_base_hi <= mem_limit_hi) {
453 base |= ((long) mem_base_hi) << 32;
454 limit |= ((long) mem_limit_hi) << 32;
455 }
456 }
457
458 res = bus->resource[2];
459 if (base <= limit) {
460 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
461 IORESOURCE_MEM | IORESOURCE_PREFETCH);
462 res->start = base;
463 res->end = limit + 0xfffff;
464 pci_resource_adjust(res, &pbm->mem_space);
465 }
466}
467
468/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
469 * a proper 'ranges' property.
470 */
471static void __devinit apb_fake_ranges(struct pci_dev *dev,
472 struct pci_bus *bus,
473 struct pci_pbm_info *pbm)
474{
475 struct resource *res;
476 u32 first, last;
477 u8 map;
478
479 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
480 apb_calc_first_last(map, &first, &last);
481 res = bus->resource[0];
482 res->start = (first << 21);
483 res->end = (last << 21) + ((1 << 21) - 1);
484 res->flags = IORESOURCE_IO;
485 pci_resource_adjust(res, &pbm->io_space);
486
487 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
488 apb_calc_first_last(map, &first, &last);
489 res = bus->resource[1];
490 res->start = (first << 21);
491 res->end = (last << 21) + ((1 << 21) - 1);
492 res->flags = IORESOURCE_MEM;
493 pci_resource_adjust(res, &pbm->mem_space);
494}
495
496static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
497 struct device_node *node,
498 struct pci_bus *bus);
499
500#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
501
502static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
503 struct device_node *node,
504 struct pci_dev *dev)
505{
506 struct pci_bus *bus;
507 const u32 *busrange, *ranges;
508 int len, i, simba;
509 struct resource *res;
510 unsigned int flags;
511 u64 size;
512
513 if (ofpci_verbose)
514 printk("of_scan_pci_bridge(%s)\n", node->full_name);
515
516 /* parse bus-range property */
517 busrange = of_get_property(node, "bus-range", &len);
518 if (busrange == NULL || len != 8) {
519 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
520 node->full_name);
521 return;
522 }
523 ranges = of_get_property(node, "ranges", &len);
524 simba = 0;
525 if (ranges == NULL) {
526 const char *model = of_get_property(node, "model", NULL);
527 if (model && !strcmp(model, "SUNW,simba"))
528 simba = 1;
529 }
530
531 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
532 if (!bus) {
533 printk(KERN_ERR "Failed to create pci bus for %s\n",
534 node->full_name);
535 return;
536 }
537
538 bus->primary = dev->bus->number;
539 bus->subordinate = busrange[1];
540 bus->bridge_ctl = 0;
541
542 /* parse ranges property, or cook one up by hand for Simba */
543 /* PCI #address-cells == 3 and #size-cells == 2 always */
544 res = &dev->resource[PCI_BRIDGE_RESOURCES];
545 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
546 res->flags = 0;
547 bus->resource[i] = res;
548 ++res;
549 }
550 if (simba) {
551 apb_fake_ranges(dev, bus, pbm);
552 goto after_ranges;
553 } else if (ranges == NULL) {
554 pci_cfg_fake_ranges(dev, bus, pbm);
555 goto after_ranges;
556 }
557 i = 1;
558 for (; len >= 32; len -= 32, ranges += 8) {
559 struct resource *root;
560
561 flags = pci_parse_of_flags(ranges[0]);
562 size = GET_64BIT(ranges, 6);
563 if (flags == 0 || size == 0)
564 continue;
565 if (flags & IORESOURCE_IO) {
566 res = bus->resource[0];
567 if (res->flags) {
568 printk(KERN_ERR "PCI: ignoring extra I/O range"
569 " for bridge %s\n", node->full_name);
570 continue;
571 }
572 root = &pbm->io_space;
573 } else {
574 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
575 printk(KERN_ERR "PCI: too many memory ranges"
576 " for bridge %s\n", node->full_name);
577 continue;
578 }
579 res = bus->resource[i];
580 ++i;
581 root = &pbm->mem_space;
582 }
583
584 res->start = GET_64BIT(ranges, 1);
585 res->end = res->start + size - 1;
586 res->flags = flags;
587
588 /* Another way to implement this would be to add an of_device
589 * layer routine that can calculate a resource for a given
590 * range property value in a PCI device.
591 */
592 pci_resource_adjust(res, root);
593 }
594after_ranges:
595 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
596 bus->number);
597 if (ofpci_verbose)
598 printk(" bus name: %s\n", bus->name);
599
600 pci_of_scan_bus(pbm, node, bus);
601}
602
603static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
604 struct device_node *node,
605 struct pci_bus *bus)
606{
607 struct device_node *child;
608 const u32 *reg;
609 int reglen, devfn, prev_devfn;
610 struct pci_dev *dev;
611
612 if (ofpci_verbose)
613 printk("PCI: scan_bus[%s] bus no %d\n",
614 node->full_name, bus->number);
615
616 child = NULL;
617 prev_devfn = -1;
618 while ((child = of_get_next_child(node, child)) != NULL) {
619 if (ofpci_verbose)
620 printk(" * %s\n", child->full_name);
621 reg = of_get_property(child, "reg", ®len);
622 if (reg == NULL || reglen < 20)
623 continue;
624
625 devfn = (reg[0] >> 8) & 0xff;
626
627 /* This is a workaround for some device trees
628 * which list PCI devices twice. On the V100
629 * for example, device number 3 is listed twice.
630 * Once as "pm" and once again as "lomp".
631 */
632 if (devfn == prev_devfn)
633 continue;
634 prev_devfn = devfn;
635
636 /* create a new pci_dev for this device */
637 dev = of_create_pci_dev(pbm, child, bus, devfn);
638 if (!dev)
639 continue;
640 if (ofpci_verbose)
641 printk("PCI: dev header type: %x\n",
642 dev->hdr_type);
643
644 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
645 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
646 of_scan_pci_bridge(pbm, child, dev);
647 }
648}
649
650static ssize_t
651show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
652{
653 struct pci_dev *pdev;
654 struct device_node *dp;
655
656 pdev = to_pci_dev(dev);
657 dp = pdev->dev.of_node;
658
659 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
660}
661
662static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
663
664static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
665{
666 struct pci_dev *dev;
667 struct pci_bus *child_bus;
668 int err;
669
670 list_for_each_entry(dev, &bus->devices, bus_list) {
671 /* we don't really care if we can create this file or
672 * not, but we need to assign the result of the call
673 * or the world will fall under alien invasion and
674 * everybody will be frozen on a spaceship ready to be
675 * eaten on alpha centauri by some green and jelly
676 * humanoid.
677 */
678 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
679 (void) err;
680 }
681 list_for_each_entry(child_bus, &bus->children, node)
682 pci_bus_register_of_sysfs(child_bus);
683}
684
685struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
686 struct device *parent)
687{
688 struct device_node *node = pbm->op->dev.of_node;
689 struct pci_bus *bus;
690
691 printk("PCI: Scanning PBM %s\n", node->full_name);
692
693 bus = pci_create_bus(parent, pbm->pci_first_busno, pbm->pci_ops, pbm);
694 if (!bus) {
695 printk(KERN_ERR "Failed to create bus for %s\n",
696 node->full_name);
697 return NULL;
698 }
699 bus->secondary = pbm->pci_first_busno;
700 bus->subordinate = pbm->pci_last_busno;
701
702 bus->resource[0] = &pbm->io_space;
703 bus->resource[1] = &pbm->mem_space;
704
705 pci_of_scan_bus(pbm, node, bus);
706 pci_bus_add_devices(bus);
707 pci_bus_register_of_sysfs(bus);
708
709 return bus;
710}
711
712void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
713{
714 struct pci_pbm_info *pbm = pbus->sysdata;
715
716 /* Generic PCI bus probing sets these to point at
717 * &io{port,mem}_resouce which is wrong for us.
718 */
719 pbus->resource[0] = &pbm->io_space;
720 pbus->resource[1] = &pbm->mem_space;
721}
722
723void pcibios_update_irq(struct pci_dev *pdev, int irq)
724{
725}
726
727resource_size_t pcibios_align_resource(void *data, const struct resource *res,
728 resource_size_t size, resource_size_t align)
729{
730 return res->start;
731}
732
733int pcibios_enable_device(struct pci_dev *dev, int mask)
734{
735 u16 cmd, oldcmd;
736 int i;
737
738 pci_read_config_word(dev, PCI_COMMAND, &cmd);
739 oldcmd = cmd;
740
741 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
742 struct resource *res = &dev->resource[i];
743
744 /* Only set up the requested stuff */
745 if (!(mask & (1<<i)))
746 continue;
747
748 if (res->flags & IORESOURCE_IO)
749 cmd |= PCI_COMMAND_IO;
750 if (res->flags & IORESOURCE_MEM)
751 cmd |= PCI_COMMAND_MEMORY;
752 }
753
754 if (cmd != oldcmd) {
755 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
756 pci_name(dev), cmd);
757 /* Enable the appropriate bits in the PCI command register. */
758 pci_write_config_word(dev, PCI_COMMAND, cmd);
759 }
760 return 0;
761}
762
763void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
764 struct resource *res)
765{
766 struct pci_pbm_info *pbm = pdev->bus->sysdata;
767 struct resource zero_res, *root;
768
769 zero_res.start = 0;
770 zero_res.end = 0;
771 zero_res.flags = res->flags;
772
773 if (res->flags & IORESOURCE_IO)
774 root = &pbm->io_space;
775 else
776 root = &pbm->mem_space;
777
778 pci_resource_adjust(&zero_res, root);
779
780 region->start = res->start - zero_res.start;
781 region->end = res->end - zero_res.start;
782}
783EXPORT_SYMBOL(pcibios_resource_to_bus);
784
785void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
786 struct pci_bus_region *region)
787{
788 struct pci_pbm_info *pbm = pdev->bus->sysdata;
789 struct resource *root;
790
791 res->start = region->start;
792 res->end = region->end;
793
794 if (res->flags & IORESOURCE_IO)
795 root = &pbm->io_space;
796 else
797 root = &pbm->mem_space;
798
799 pci_resource_adjust(res, root);
800}
801EXPORT_SYMBOL(pcibios_bus_to_resource);
802
803char * __devinit pcibios_setup(char *str)
804{
805 return str;
806}
807
808/* Platform support for /proc/bus/pci/X/Y mmap()s. */
809
810/* If the user uses a host-bridge as the PCI device, he may use
811 * this to perform a raw mmap() of the I/O or MEM space behind
812 * that controller.
813 *
814 * This can be useful for execution of x86 PCI bios initialization code
815 * on a PCI card, like the xfree86 int10 stuff does.
816 */
817static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
818 enum pci_mmap_state mmap_state)
819{
820 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
821 unsigned long space_size, user_offset, user_size;
822
823 if (mmap_state == pci_mmap_io) {
824 space_size = resource_size(&pbm->io_space);
825 } else {
826 space_size = resource_size(&pbm->mem_space);
827 }
828
829 /* Make sure the request is in range. */
830 user_offset = vma->vm_pgoff << PAGE_SHIFT;
831 user_size = vma->vm_end - vma->vm_start;
832
833 if (user_offset >= space_size ||
834 (user_offset + user_size) > space_size)
835 return -EINVAL;
836
837 if (mmap_state == pci_mmap_io) {
838 vma->vm_pgoff = (pbm->io_space.start +
839 user_offset) >> PAGE_SHIFT;
840 } else {
841 vma->vm_pgoff = (pbm->mem_space.start +
842 user_offset) >> PAGE_SHIFT;
843 }
844
845 return 0;
846}
847
848/* Adjust vm_pgoff of VMA such that it is the physical page offset
849 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
850 *
851 * Basically, the user finds the base address for his device which he wishes
852 * to mmap. They read the 32-bit value from the config space base register,
853 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
854 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
855 *
856 * Returns negative error code on failure, zero on success.
857 */
858static int __pci_mmap_make_offset(struct pci_dev *pdev,
859 struct vm_area_struct *vma,
860 enum pci_mmap_state mmap_state)
861{
862 unsigned long user_paddr, user_size;
863 int i, err;
864
865 /* First compute the physical address in vma->vm_pgoff,
866 * making sure the user offset is within range in the
867 * appropriate PCI space.
868 */
869 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
870 if (err)
871 return err;
872
873 /* If this is a mapping on a host bridge, any address
874 * is OK.
875 */
876 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
877 return err;
878
879 /* Otherwise make sure it's in the range for one of the
880 * device's resources.
881 */
882 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
883 user_size = vma->vm_end - vma->vm_start;
884
885 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
886 struct resource *rp = &pdev->resource[i];
887 resource_size_t aligned_end;
888
889 /* Active? */
890 if (!rp->flags)
891 continue;
892
893 /* Same type? */
894 if (i == PCI_ROM_RESOURCE) {
895 if (mmap_state != pci_mmap_mem)
896 continue;
897 } else {
898 if ((mmap_state == pci_mmap_io &&
899 (rp->flags & IORESOURCE_IO) == 0) ||
900 (mmap_state == pci_mmap_mem &&
901 (rp->flags & IORESOURCE_MEM) == 0))
902 continue;
903 }
904
905 /* Align the resource end to the next page address.
906 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
907 * because actually we need the address of the next byte
908 * after rp->end.
909 */
910 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
911
912 if ((rp->start <= user_paddr) &&
913 (user_paddr + user_size) <= aligned_end)
914 break;
915 }
916
917 if (i > PCI_ROM_RESOURCE)
918 return -EINVAL;
919
920 return 0;
921}
922
923/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
924 * mapping.
925 */
926static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
927 enum pci_mmap_state mmap_state)
928{
929 vma->vm_flags |= (VM_IO | VM_RESERVED);
930}
931
932/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
933 * device mapping.
934 */
935static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
936 enum pci_mmap_state mmap_state)
937{
938 /* Our io_remap_pfn_range takes care of this, do nothing. */
939}
940
941/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
942 * for this architecture. The region in the process to map is described by vm_start
943 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
944 * The pci device structure is provided so that architectures may make mapping
945 * decisions on a per-device or per-bus basis.
946 *
947 * Returns a negative error code on failure, zero on success.
948 */
949int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
950 enum pci_mmap_state mmap_state,
951 int write_combine)
952{
953 int ret;
954
955 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
956 if (ret < 0)
957 return ret;
958
959 __pci_mmap_set_flags(dev, vma, mmap_state);
960 __pci_mmap_set_pgprot(dev, vma, mmap_state);
961
962 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
963 ret = io_remap_pfn_range(vma, vma->vm_start,
964 vma->vm_pgoff,
965 vma->vm_end - vma->vm_start,
966 vma->vm_page_prot);
967 if (ret)
968 return ret;
969
970 return 0;
971}
972
973#ifdef CONFIG_NUMA
974int pcibus_to_node(struct pci_bus *pbus)
975{
976 struct pci_pbm_info *pbm = pbus->sysdata;
977
978 return pbm->numa_node;
979}
980EXPORT_SYMBOL(pcibus_to_node);
981#endif
982
983/* Return the domain number for this pci bus */
984
985int pci_domain_nr(struct pci_bus *pbus)
986{
987 struct pci_pbm_info *pbm = pbus->sysdata;
988 int ret;
989
990 if (!pbm) {
991 ret = -ENXIO;
992 } else {
993 ret = pbm->index;
994 }
995
996 return ret;
997}
998EXPORT_SYMBOL(pci_domain_nr);
999
1000#ifdef CONFIG_PCI_MSI
1001int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1002{
1003 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1004 unsigned int irq;
1005
1006 if (!pbm->setup_msi_irq)
1007 return -EINVAL;
1008
1009 return pbm->setup_msi_irq(&irq, pdev, desc);
1010}
1011
1012void arch_teardown_msi_irq(unsigned int irq)
1013{
1014 struct msi_desc *entry = irq_get_msi_desc(irq);
1015 struct pci_dev *pdev = entry->dev;
1016 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1017
1018 if (pbm->teardown_msi_irq)
1019 pbm->teardown_msi_irq(irq, pdev);
1020}
1021#endif /* !(CONFIG_PCI_MSI) */
1022
1023static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1024{
1025 struct pci_dev *ali_isa_bridge;
1026 u8 val;
1027
1028 /* ALI sound chips generate 31-bits of DMA, a special register
1029 * determines what bit 31 is emitted as.
1030 */
1031 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1032 PCI_DEVICE_ID_AL_M1533,
1033 NULL);
1034
1035 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1036 if (set_bit)
1037 val |= 0x01;
1038 else
1039 val &= ~0x01;
1040 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1041 pci_dev_put(ali_isa_bridge);
1042}
1043
1044int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
1045{
1046 u64 dma_addr_mask;
1047
1048 if (pdev == NULL) {
1049 dma_addr_mask = 0xffffffff;
1050 } else {
1051 struct iommu *iommu = pdev->dev.archdata.iommu;
1052
1053 dma_addr_mask = iommu->dma_addr_mask;
1054
1055 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1056 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1057 device_mask == 0x7fffffff) {
1058 ali_sound_dma_hack(pdev,
1059 (dma_addr_mask & 0x80000000) != 0);
1060 return 1;
1061 }
1062 }
1063
1064 if (device_mask >= (1UL << 32UL))
1065 return 0;
1066
1067 return (device_mask & dma_addr_mask) == dma_addr_mask;
1068}
1069
1070void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1071 const struct resource *rp, resource_size_t *start,
1072 resource_size_t *end)
1073{
1074 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1075 unsigned long offset;
1076
1077 if (rp->flags & IORESOURCE_IO)
1078 offset = pbm->io_space.start;
1079 else
1080 offset = pbm->mem_space.start;
1081
1082 *start = rp->start - offset;
1083 *end = rp->end - offset;
1084}
1085
1086static int __init pcibios_init(void)
1087{
1088 pci_dfl_cache_line_size = 64 >> 2;
1089 return 0;
1090}
1091subsys_initcall(pcibios_init);
1092
1093#ifdef CONFIG_SYSFS
1094static void __devinit pci_bus_slot_names(struct device_node *node,
1095 struct pci_bus *bus)
1096{
1097 const struct pci_slot_names {
1098 u32 slot_mask;
1099 char names[0];
1100 } *prop;
1101 const char *sp;
1102 int len, i;
1103 u32 mask;
1104
1105 prop = of_get_property(node, "slot-names", &len);
1106 if (!prop)
1107 return;
1108
1109 mask = prop->slot_mask;
1110 sp = prop->names;
1111
1112 if (ofpci_verbose)
1113 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1114 node->full_name, mask);
1115
1116 i = 0;
1117 while (mask) {
1118 struct pci_slot *pci_slot;
1119 u32 this_bit = 1 << i;
1120
1121 if (!(mask & this_bit)) {
1122 i++;
1123 continue;
1124 }
1125
1126 if (ofpci_verbose)
1127 printk("PCI: Making slot [%s]\n", sp);
1128
1129 pci_slot = pci_create_slot(bus, i, sp, NULL);
1130 if (IS_ERR(pci_slot))
1131 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
1132 PTR_ERR(pci_slot));
1133
1134 sp += strlen(sp) + 1;
1135 mask &= ~this_bit;
1136 i++;
1137 }
1138}
1139
1140static int __init of_pci_slot_init(void)
1141{
1142 struct pci_bus *pbus = NULL;
1143
1144 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1145 struct device_node *node;
1146
1147 if (pbus->self) {
1148 /* PCI->PCI bridge */
1149 node = pbus->self->dev.of_node;
1150 } else {
1151 struct pci_pbm_info *pbm = pbus->sysdata;
1152
1153 /* Host PCI controller */
1154 node = pbm->op->dev.of_node;
1155 }
1156
1157 pci_bus_slot_names(node, pbus);
1158 }
1159
1160 return 0;
1161}
1162
1163module_init(of_pci_slot_init);
1164#endif
1// SPDX-License-Identifier: GPL-2.0
2/* pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 *
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
10 */
11
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/capability.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/msi.h>
20#include <linux/irq.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pgtable.h>
25
26#include <linux/uaccess.h>
27#include <asm/irq.h>
28#include <asm/prom.h>
29#include <asm/apb.h>
30
31#include "pci_impl.h"
32#include "kernel.h"
33
34/* List of all PCI controllers found in the system. */
35struct pci_pbm_info *pci_pbm_root = NULL;
36
37/* Each PBM found gets a unique index. */
38int pci_num_pbms = 0;
39
40volatile int pci_poke_in_progress;
41volatile int pci_poke_cpu = -1;
42volatile int pci_poke_faulted;
43
44static DEFINE_SPINLOCK(pci_poke_lock);
45
46void pci_config_read8(u8 *addr, u8 *ret)
47{
48 unsigned long flags;
49 u8 byte;
50
51 spin_lock_irqsave(&pci_poke_lock, flags);
52 pci_poke_cpu = smp_processor_id();
53 pci_poke_in_progress = 1;
54 pci_poke_faulted = 0;
55 __asm__ __volatile__("membar #Sync\n\t"
56 "lduba [%1] %2, %0\n\t"
57 "membar #Sync"
58 : "=r" (byte)
59 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
60 : "memory");
61 pci_poke_in_progress = 0;
62 pci_poke_cpu = -1;
63 if (!pci_poke_faulted)
64 *ret = byte;
65 spin_unlock_irqrestore(&pci_poke_lock, flags);
66}
67
68void pci_config_read16(u16 *addr, u16 *ret)
69{
70 unsigned long flags;
71 u16 word;
72
73 spin_lock_irqsave(&pci_poke_lock, flags);
74 pci_poke_cpu = smp_processor_id();
75 pci_poke_in_progress = 1;
76 pci_poke_faulted = 0;
77 __asm__ __volatile__("membar #Sync\n\t"
78 "lduha [%1] %2, %0\n\t"
79 "membar #Sync"
80 : "=r" (word)
81 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
82 : "memory");
83 pci_poke_in_progress = 0;
84 pci_poke_cpu = -1;
85 if (!pci_poke_faulted)
86 *ret = word;
87 spin_unlock_irqrestore(&pci_poke_lock, flags);
88}
89
90void pci_config_read32(u32 *addr, u32 *ret)
91{
92 unsigned long flags;
93 u32 dword;
94
95 spin_lock_irqsave(&pci_poke_lock, flags);
96 pci_poke_cpu = smp_processor_id();
97 pci_poke_in_progress = 1;
98 pci_poke_faulted = 0;
99 __asm__ __volatile__("membar #Sync\n\t"
100 "lduwa [%1] %2, %0\n\t"
101 "membar #Sync"
102 : "=r" (dword)
103 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
104 : "memory");
105 pci_poke_in_progress = 0;
106 pci_poke_cpu = -1;
107 if (!pci_poke_faulted)
108 *ret = dword;
109 spin_unlock_irqrestore(&pci_poke_lock, flags);
110}
111
112void pci_config_write8(u8 *addr, u8 val)
113{
114 unsigned long flags;
115
116 spin_lock_irqsave(&pci_poke_lock, flags);
117 pci_poke_cpu = smp_processor_id();
118 pci_poke_in_progress = 1;
119 pci_poke_faulted = 0;
120 __asm__ __volatile__("membar #Sync\n\t"
121 "stba %0, [%1] %2\n\t"
122 "membar #Sync"
123 : /* no outputs */
124 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
125 : "memory");
126 pci_poke_in_progress = 0;
127 pci_poke_cpu = -1;
128 spin_unlock_irqrestore(&pci_poke_lock, flags);
129}
130
131void pci_config_write16(u16 *addr, u16 val)
132{
133 unsigned long flags;
134
135 spin_lock_irqsave(&pci_poke_lock, flags);
136 pci_poke_cpu = smp_processor_id();
137 pci_poke_in_progress = 1;
138 pci_poke_faulted = 0;
139 __asm__ __volatile__("membar #Sync\n\t"
140 "stha %0, [%1] %2\n\t"
141 "membar #Sync"
142 : /* no outputs */
143 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
144 : "memory");
145 pci_poke_in_progress = 0;
146 pci_poke_cpu = -1;
147 spin_unlock_irqrestore(&pci_poke_lock, flags);
148}
149
150void pci_config_write32(u32 *addr, u32 val)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&pci_poke_lock, flags);
155 pci_poke_cpu = smp_processor_id();
156 pci_poke_in_progress = 1;
157 pci_poke_faulted = 0;
158 __asm__ __volatile__("membar #Sync\n\t"
159 "stwa %0, [%1] %2\n\t"
160 "membar #Sync"
161 : /* no outputs */
162 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
163 : "memory");
164 pci_poke_in_progress = 0;
165 pci_poke_cpu = -1;
166 spin_unlock_irqrestore(&pci_poke_lock, flags);
167}
168
169static int ofpci_verbose;
170
171static int __init ofpci_debug(char *str)
172{
173 int val = 0;
174
175 get_option(&str, &val);
176 if (val)
177 ofpci_verbose = 1;
178 return 1;
179}
180
181__setup("ofpci_debug=", ofpci_debug);
182
183static unsigned long pci_parse_of_flags(u32 addr0)
184{
185 unsigned long flags = 0;
186
187 if (addr0 & 0x02000000) {
188 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
189 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
190 if (addr0 & 0x01000000)
191 flags |= IORESOURCE_MEM_64
192 | PCI_BASE_ADDRESS_MEM_TYPE_64;
193 if (addr0 & 0x40000000)
194 flags |= IORESOURCE_PREFETCH
195 | PCI_BASE_ADDRESS_MEM_PREFETCH;
196 } else if (addr0 & 0x01000000)
197 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
198 return flags;
199}
200
201/* The of_device layer has translated all of the assigned-address properties
202 * into physical address resources, we only have to figure out the register
203 * mapping.
204 */
205static void pci_parse_of_addrs(struct platform_device *op,
206 struct device_node *node,
207 struct pci_dev *dev)
208{
209 struct resource *op_res;
210 const u32 *addrs;
211 int proplen;
212
213 addrs = of_get_property(node, "assigned-addresses", &proplen);
214 if (!addrs)
215 return;
216 if (ofpci_verbose)
217 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
218 proplen, addrs);
219 op_res = &op->resource[0];
220 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
221 struct resource *res;
222 unsigned long flags;
223 int i;
224
225 flags = pci_parse_of_flags(addrs[0]);
226 if (!flags)
227 continue;
228 i = addrs[0] & 0xff;
229 if (ofpci_verbose)
230 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
231 op_res->start, op_res->end, i);
232
233 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
234 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
235 } else if (i == dev->rom_base_reg) {
236 res = &dev->resource[PCI_ROM_RESOURCE];
237 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
238 } else {
239 pci_err(dev, "bad cfg reg num 0x%x\n", i);
240 continue;
241 }
242 res->start = op_res->start;
243 res->end = op_res->end;
244 res->flags = flags;
245 res->name = pci_name(dev);
246
247 pci_info(dev, "reg 0x%x: %pR\n", i, res);
248 }
249}
250
251static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
252 void *stc, void *host_controller,
253 struct platform_device *op,
254 int numa_node)
255{
256 sd->iommu = iommu;
257 sd->stc = stc;
258 sd->host_controller = host_controller;
259 sd->op = op;
260 sd->numa_node = numa_node;
261}
262
263static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
264 struct device_node *node,
265 struct pci_bus *bus, int devfn)
266{
267 struct dev_archdata *sd;
268 struct platform_device *op;
269 struct pci_dev *dev;
270 u32 class;
271
272 dev = pci_alloc_dev(bus);
273 if (!dev)
274 return NULL;
275
276 op = of_find_device_by_node(node);
277 sd = &dev->dev.archdata;
278 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
279 pbm->numa_node);
280 sd = &op->dev.archdata;
281 sd->iommu = pbm->iommu;
282 sd->stc = &pbm->stc;
283 sd->numa_node = pbm->numa_node;
284
285 if (of_node_name_eq(node, "ebus"))
286 of_propagate_archdata(op);
287
288 if (ofpci_verbose)
289 pci_info(bus," create device, devfn: %x, type: %s\n",
290 devfn, of_node_get_device_type(node));
291
292 dev->sysdata = node;
293 dev->dev.parent = bus->bridge;
294 dev->dev.bus = &pci_bus_type;
295 dev->dev.of_node = of_node_get(node);
296 dev->devfn = devfn;
297 dev->multifunction = 0; /* maybe a lie? */
298 set_pcie_port_type(dev);
299
300 pci_dev_assign_slot(dev);
301 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
302 dev->device = of_getintprop_default(node, "device-id", 0xffff);
303 dev->subsystem_vendor =
304 of_getintprop_default(node, "subsystem-vendor-id", 0);
305 dev->subsystem_device =
306 of_getintprop_default(node, "subsystem-id", 0);
307
308 dev->cfg_size = pci_cfg_space_size(dev);
309
310 /* We can't actually use the firmware value, we have
311 * to read what is in the register right now. One
312 * reason is that in the case of IDE interfaces the
313 * firmware can sample the value before the the IDE
314 * interface is programmed into native mode.
315 */
316 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
317 dev->class = class >> 8;
318 dev->revision = class & 0xff;
319
320 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
321 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
322
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
325 * disabled.
326 */
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 pci_set_master(dev);
329
330 dev->current_state = PCI_UNKNOWN; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
333
334 if (of_node_name_eq(node, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (of_node_is_type(node, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 } else {
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
343
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
347 }
348
349 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
350 dev->vendor, dev->device, dev->hdr_type, dev->class);
351
352 pci_parse_of_addrs(sd->op, node, dev);
353
354 if (ofpci_verbose)
355 pci_info(dev, " adding to system ...\n");
356
357 pci_device_add(dev, bus);
358
359 return dev;
360}
361
362static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
363{
364 u32 idx, first, last;
365
366 first = 8;
367 last = 0;
368 for (idx = 0; idx < 8; idx++) {
369 if ((map & (1 << idx)) != 0) {
370 if (first > idx)
371 first = idx;
372 if (last < idx)
373 last = idx;
374 }
375 }
376
377 *first_p = first;
378 *last_p = last;
379}
380
381/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
382 * a proper 'ranges' property.
383 */
384static void apb_fake_ranges(struct pci_dev *dev,
385 struct pci_bus *bus,
386 struct pci_pbm_info *pbm)
387{
388 struct pci_bus_region region;
389 struct resource *res;
390 u32 first, last;
391 u8 map;
392
393 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
394 apb_calc_first_last(map, &first, &last);
395 res = bus->resource[0];
396 res->flags = IORESOURCE_IO;
397 region.start = (first << 21);
398 region.end = (last << 21) + ((1 << 21) - 1);
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400
401 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
402 apb_calc_first_last(map, &first, &last);
403 res = bus->resource[1];
404 res->flags = IORESOURCE_MEM;
405 region.start = (first << 29);
406 region.end = (last << 29) + ((1 << 29) - 1);
407 pcibios_bus_to_resource(dev->bus, res, ®ion);
408}
409
410static void pci_of_scan_bus(struct pci_pbm_info *pbm,
411 struct device_node *node,
412 struct pci_bus *bus);
413
414#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
415
416static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
417 struct device_node *node,
418 struct pci_dev *dev)
419{
420 struct pci_bus *bus;
421 const u32 *busrange, *ranges;
422 int len, i, simba;
423 struct pci_bus_region region;
424 struct resource *res;
425 unsigned int flags;
426 u64 size;
427
428 if (ofpci_verbose)
429 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
430
431 /* parse bus-range property */
432 busrange = of_get_property(node, "bus-range", &len);
433 if (busrange == NULL || len != 8) {
434 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
435 node);
436 return;
437 }
438
439 if (ofpci_verbose)
440 pci_info(dev, " Bridge bus range [%u --> %u]\n",
441 busrange[0], busrange[1]);
442
443 ranges = of_get_property(node, "ranges", &len);
444 simba = 0;
445 if (ranges == NULL) {
446 const char *model = of_get_property(node, "model", NULL);
447 if (model && !strcmp(model, "SUNW,simba"))
448 simba = 1;
449 }
450
451 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
452 if (!bus) {
453 pci_err(dev, "Failed to create pci bus for %pOF\n",
454 node);
455 return;
456 }
457
458 bus->primary = dev->bus->number;
459 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
460 bus->bridge_ctl = 0;
461
462 if (ofpci_verbose)
463 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
464 ranges, simba);
465
466 /* parse ranges property, or cook one up by hand for Simba */
467 /* PCI #address-cells == 3 and #size-cells == 2 always */
468 res = &dev->resource[PCI_BRIDGE_RESOURCES];
469 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
470 res->flags = 0;
471 bus->resource[i] = res;
472 ++res;
473 }
474 if (simba) {
475 apb_fake_ranges(dev, bus, pbm);
476 goto after_ranges;
477 } else if (ranges == NULL) {
478 pci_read_bridge_bases(bus);
479 goto after_ranges;
480 }
481 i = 1;
482 for (; len >= 32; len -= 32, ranges += 8) {
483 u64 start;
484
485 if (ofpci_verbose)
486 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
487 "%08x:%08x]\n",
488 ranges[0], ranges[1], ranges[2], ranges[3],
489 ranges[4], ranges[5], ranges[6], ranges[7]);
490
491 flags = pci_parse_of_flags(ranges[0]);
492 size = GET_64BIT(ranges, 6);
493 if (flags == 0 || size == 0)
494 continue;
495
496 /* On PCI-Express systems, PCI bridges that have no devices downstream
497 * have a bogus size value where the first 32-bit cell is 0xffffffff.
498 * This results in a bogus range where start + size overflows.
499 *
500 * Just skip these otherwise the kernel will complain when the resource
501 * tries to be claimed.
502 */
503 if (size >> 32 == 0xffffffff)
504 continue;
505
506 if (flags & IORESOURCE_IO) {
507 res = bus->resource[0];
508 if (res->flags) {
509 pci_err(dev, "ignoring extra I/O range"
510 " for bridge %pOF\n", node);
511 continue;
512 }
513 } else {
514 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
515 pci_err(dev, "too many memory ranges"
516 " for bridge %pOF\n", node);
517 continue;
518 }
519 res = bus->resource[i];
520 ++i;
521 }
522
523 res->flags = flags;
524 region.start = start = GET_64BIT(ranges, 1);
525 region.end = region.start + size - 1;
526
527 if (ofpci_verbose)
528 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
529 flags, start, size);
530
531 pcibios_bus_to_resource(dev->bus, res, ®ion);
532 }
533after_ranges:
534 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
535 bus->number);
536 if (ofpci_verbose)
537 pci_info(dev, " bus name: %s\n", bus->name);
538
539 pci_of_scan_bus(pbm, node, bus);
540}
541
542static void pci_of_scan_bus(struct pci_pbm_info *pbm,
543 struct device_node *node,
544 struct pci_bus *bus)
545{
546 struct device_node *child;
547 const u32 *reg;
548 int reglen, devfn, prev_devfn;
549 struct pci_dev *dev;
550
551 if (ofpci_verbose)
552 pci_info(bus, "scan_bus[%pOF] bus no %d\n",
553 node, bus->number);
554
555 prev_devfn = -1;
556 for_each_child_of_node(node, child) {
557 if (ofpci_verbose)
558 pci_info(bus, " * %pOF\n", child);
559 reg = of_get_property(child, "reg", ®len);
560 if (reg == NULL || reglen < 20)
561 continue;
562
563 devfn = (reg[0] >> 8) & 0xff;
564
565 /* This is a workaround for some device trees
566 * which list PCI devices twice. On the V100
567 * for example, device number 3 is listed twice.
568 * Once as "pm" and once again as "lomp".
569 */
570 if (devfn == prev_devfn)
571 continue;
572 prev_devfn = devfn;
573
574 /* create a new pci_dev for this device */
575 dev = of_create_pci_dev(pbm, child, bus, devfn);
576 if (!dev)
577 continue;
578 if (ofpci_verbose)
579 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
580
581 if (pci_is_bridge(dev))
582 of_scan_pci_bridge(pbm, child, dev);
583 }
584}
585
586static ssize_t
587show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
588{
589 struct pci_dev *pdev;
590 struct device_node *dp;
591
592 pdev = to_pci_dev(dev);
593 dp = pdev->dev.of_node;
594
595 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
596}
597
598static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
599
600static void pci_bus_register_of_sysfs(struct pci_bus *bus)
601{
602 struct pci_dev *dev;
603 struct pci_bus *child_bus;
604 int err;
605
606 list_for_each_entry(dev, &bus->devices, bus_list) {
607 /* we don't really care if we can create this file or
608 * not, but we need to assign the result of the call
609 * or the world will fall under alien invasion and
610 * everybody will be frozen on a spaceship ready to be
611 * eaten on alpha centauri by some green and jelly
612 * humanoid.
613 */
614 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
615 (void) err;
616 }
617 list_for_each_entry(child_bus, &bus->children, node)
618 pci_bus_register_of_sysfs(child_bus);
619}
620
621static void pci_claim_legacy_resources(struct pci_dev *dev)
622{
623 struct pci_bus_region region;
624 struct resource *p, *root, *conflict;
625
626 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
627 return;
628
629 p = kzalloc(sizeof(*p), GFP_KERNEL);
630 if (!p)
631 return;
632
633 p->name = "Video RAM area";
634 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
635
636 region.start = 0xa0000UL;
637 region.end = region.start + 0x1ffffUL;
638 pcibios_bus_to_resource(dev->bus, p, ®ion);
639
640 root = pci_find_parent_resource(dev, p);
641 if (!root) {
642 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
643 goto err;
644 }
645
646 conflict = request_resource_conflict(root, p);
647 if (conflict) {
648 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
649 p, conflict->name, conflict);
650 goto err;
651 }
652
653 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
654 return;
655
656err:
657 kfree(p);
658}
659
660static void pci_claim_bus_resources(struct pci_bus *bus)
661{
662 struct pci_bus *child_bus;
663 struct pci_dev *dev;
664
665 list_for_each_entry(dev, &bus->devices, bus_list) {
666 int i;
667
668 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
669 struct resource *r = &dev->resource[i];
670
671 if (r->parent || !r->start || !r->flags)
672 continue;
673
674 if (ofpci_verbose)
675 pci_info(dev, "Claiming Resource %d: %pR\n",
676 i, r);
677
678 pci_claim_resource(dev, i);
679 }
680
681 pci_claim_legacy_resources(dev);
682 }
683
684 list_for_each_entry(child_bus, &bus->children, node)
685 pci_claim_bus_resources(child_bus);
686}
687
688struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
689 struct device *parent)
690{
691 LIST_HEAD(resources);
692 struct device_node *node = pbm->op->dev.of_node;
693 struct pci_bus *bus;
694
695 printk("PCI: Scanning PBM %pOF\n", node);
696
697 pci_add_resource_offset(&resources, &pbm->io_space,
698 pbm->io_offset);
699 pci_add_resource_offset(&resources, &pbm->mem_space,
700 pbm->mem_offset);
701 if (pbm->mem64_space.flags)
702 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->mem64_offset);
704 pbm->busn.start = pbm->pci_first_busno;
705 pbm->busn.end = pbm->pci_last_busno;
706 pbm->busn.flags = IORESOURCE_BUS;
707 pci_add_resource(&resources, &pbm->busn);
708 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
709 pbm, &resources);
710 if (!bus) {
711 printk(KERN_ERR "Failed to create bus for %pOF\n", node);
712 pci_free_resource_list(&resources);
713 return NULL;
714 }
715
716 pci_of_scan_bus(pbm, node, bus);
717 pci_bus_register_of_sysfs(bus);
718
719 pci_claim_bus_resources(bus);
720
721 pci_bus_add_devices(bus);
722 return bus;
723}
724
725int pcibios_enable_device(struct pci_dev *dev, int mask)
726{
727 u16 cmd, oldcmd;
728 int i;
729
730 pci_read_config_word(dev, PCI_COMMAND, &cmd);
731 oldcmd = cmd;
732
733 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
734 struct resource *res = &dev->resource[i];
735
736 /* Only set up the requested stuff */
737 if (!(mask & (1<<i)))
738 continue;
739
740 if (res->flags & IORESOURCE_IO)
741 cmd |= PCI_COMMAND_IO;
742 if (res->flags & IORESOURCE_MEM)
743 cmd |= PCI_COMMAND_MEMORY;
744 }
745
746 if (cmd != oldcmd) {
747 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
748 pci_write_config_word(dev, PCI_COMMAND, cmd);
749 }
750 return 0;
751}
752
753/* Platform support for /proc/bus/pci/X/Y mmap()s. */
754
755/* If the user uses a host-bridge as the PCI device, he may use
756 * this to perform a raw mmap() of the I/O or MEM space behind
757 * that controller.
758 *
759 * This can be useful for execution of x86 PCI bios initialization code
760 * on a PCI card, like the xfree86 int10 stuff does.
761 */
762static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
763 enum pci_mmap_state mmap_state)
764{
765 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
766 unsigned long space_size, user_offset, user_size;
767
768 if (mmap_state == pci_mmap_io) {
769 space_size = resource_size(&pbm->io_space);
770 } else {
771 space_size = resource_size(&pbm->mem_space);
772 }
773
774 /* Make sure the request is in range. */
775 user_offset = vma->vm_pgoff << PAGE_SHIFT;
776 user_size = vma->vm_end - vma->vm_start;
777
778 if (user_offset >= space_size ||
779 (user_offset + user_size) > space_size)
780 return -EINVAL;
781
782 if (mmap_state == pci_mmap_io) {
783 vma->vm_pgoff = (pbm->io_space.start +
784 user_offset) >> PAGE_SHIFT;
785 } else {
786 vma->vm_pgoff = (pbm->mem_space.start +
787 user_offset) >> PAGE_SHIFT;
788 }
789
790 return 0;
791}
792
793/* Adjust vm_pgoff of VMA such that it is the physical page offset
794 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
795 *
796 * Basically, the user finds the base address for his device which he wishes
797 * to mmap. They read the 32-bit value from the config space base register,
798 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
799 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
800 *
801 * Returns negative error code on failure, zero on success.
802 */
803static int __pci_mmap_make_offset(struct pci_dev *pdev,
804 struct vm_area_struct *vma,
805 enum pci_mmap_state mmap_state)
806{
807 unsigned long user_paddr, user_size;
808 int i, err;
809
810 /* First compute the physical address in vma->vm_pgoff,
811 * making sure the user offset is within range in the
812 * appropriate PCI space.
813 */
814 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
815 if (err)
816 return err;
817
818 /* If this is a mapping on a host bridge, any address
819 * is OK.
820 */
821 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
822 return err;
823
824 /* Otherwise make sure it's in the range for one of the
825 * device's resources.
826 */
827 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
828 user_size = vma->vm_end - vma->vm_start;
829
830 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
831 struct resource *rp = &pdev->resource[i];
832 resource_size_t aligned_end;
833
834 /* Active? */
835 if (!rp->flags)
836 continue;
837
838 /* Same type? */
839 if (i == PCI_ROM_RESOURCE) {
840 if (mmap_state != pci_mmap_mem)
841 continue;
842 } else {
843 if ((mmap_state == pci_mmap_io &&
844 (rp->flags & IORESOURCE_IO) == 0) ||
845 (mmap_state == pci_mmap_mem &&
846 (rp->flags & IORESOURCE_MEM) == 0))
847 continue;
848 }
849
850 /* Align the resource end to the next page address.
851 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
852 * because actually we need the address of the next byte
853 * after rp->end.
854 */
855 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
856
857 if ((rp->start <= user_paddr) &&
858 (user_paddr + user_size) <= aligned_end)
859 break;
860 }
861
862 if (i > PCI_ROM_RESOURCE)
863 return -EINVAL;
864
865 return 0;
866}
867
868/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
869 * device mapping.
870 */
871static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
872 enum pci_mmap_state mmap_state)
873{
874 /* Our io_remap_pfn_range takes care of this, do nothing. */
875}
876
877/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
878 * for this architecture. The region in the process to map is described by vm_start
879 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
880 * The pci device structure is provided so that architectures may make mapping
881 * decisions on a per-device or per-bus basis.
882 *
883 * Returns a negative error code on failure, zero on success.
884 */
885int pci_mmap_page_range(struct pci_dev *dev, int bar,
886 struct vm_area_struct *vma,
887 enum pci_mmap_state mmap_state, int write_combine)
888{
889 int ret;
890
891 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
892 if (ret < 0)
893 return ret;
894
895 __pci_mmap_set_pgprot(dev, vma, mmap_state);
896
897 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
898 ret = io_remap_pfn_range(vma, vma->vm_start,
899 vma->vm_pgoff,
900 vma->vm_end - vma->vm_start,
901 vma->vm_page_prot);
902 if (ret)
903 return ret;
904
905 return 0;
906}
907
908#ifdef CONFIG_NUMA
909int pcibus_to_node(struct pci_bus *pbus)
910{
911 struct pci_pbm_info *pbm = pbus->sysdata;
912
913 return pbm->numa_node;
914}
915EXPORT_SYMBOL(pcibus_to_node);
916#endif
917
918/* Return the domain number for this pci bus */
919
920int pci_domain_nr(struct pci_bus *pbus)
921{
922 struct pci_pbm_info *pbm = pbus->sysdata;
923 int ret;
924
925 if (!pbm) {
926 ret = -ENXIO;
927 } else {
928 ret = pbm->index;
929 }
930
931 return ret;
932}
933EXPORT_SYMBOL(pci_domain_nr);
934
935#ifdef CONFIG_PCI_MSI
936int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
937{
938 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
939 unsigned int irq;
940
941 if (!pbm->setup_msi_irq)
942 return -EINVAL;
943
944 return pbm->setup_msi_irq(&irq, pdev, desc);
945}
946
947void arch_teardown_msi_irq(unsigned int irq)
948{
949 struct msi_desc *entry = irq_get_msi_desc(irq);
950 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
951 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
952
953 if (pbm->teardown_msi_irq)
954 pbm->teardown_msi_irq(irq, pdev);
955}
956#endif /* !(CONFIG_PCI_MSI) */
957
958/* ALI sound chips generate 31-bits of DMA, a special register
959 * determines what bit 31 is emitted as.
960 */
961int ali_sound_dma_hack(struct device *dev, u64 device_mask)
962{
963 struct iommu *iommu = dev->archdata.iommu;
964 struct pci_dev *ali_isa_bridge;
965 u8 val;
966
967 if (!dev_is_pci(dev))
968 return 0;
969
970 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
971 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
972 device_mask != 0x7fffffff)
973 return 0;
974
975 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
976 PCI_DEVICE_ID_AL_M1533,
977 NULL);
978
979 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
980 if (iommu->dma_addr_mask & 0x80000000)
981 val |= 0x01;
982 else
983 val &= ~0x01;
984 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
985 pci_dev_put(ali_isa_bridge);
986 return 1;
987}
988
989void pci_resource_to_user(const struct pci_dev *pdev, int bar,
990 const struct resource *rp, resource_size_t *start,
991 resource_size_t *end)
992{
993 struct pci_bus_region region;
994
995 /*
996 * "User" addresses are shown in /sys/devices/pci.../.../resource
997 * and /proc/bus/pci/devices and used as mmap offsets for
998 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
999 *
1000 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
1001 */
1002 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
1003 *start = region.start;
1004 *end = region.end;
1005}
1006
1007void pcibios_set_master(struct pci_dev *dev)
1008{
1009 /* No special bus mastering setup handling */
1010}
1011
1012#ifdef CONFIG_PCI_IOV
1013int pcibios_add_device(struct pci_dev *dev)
1014{
1015 struct pci_dev *pdev;
1016
1017 /* Add sriov arch specific initialization here.
1018 * Copy dev_archdata from PF to VF
1019 */
1020 if (dev->is_virtfn) {
1021 struct dev_archdata *psd;
1022
1023 pdev = dev->physfn;
1024 psd = &pdev->dev.archdata;
1025 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
1026 psd->stc, psd->host_controller, NULL,
1027 psd->numa_node);
1028 }
1029 return 0;
1030}
1031#endif /* CONFIG_PCI_IOV */
1032
1033static int __init pcibios_init(void)
1034{
1035 pci_dfl_cache_line_size = 64 >> 2;
1036 return 0;
1037}
1038subsys_initcall(pcibios_init);
1039
1040#ifdef CONFIG_SYSFS
1041
1042#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
1043
1044static void pcie_bus_slot_names(struct pci_bus *pbus)
1045{
1046 struct pci_dev *pdev;
1047 struct pci_bus *bus;
1048
1049 list_for_each_entry(pdev, &pbus->devices, bus_list) {
1050 char name[SLOT_NAME_SIZE];
1051 struct pci_slot *pci_slot;
1052 const u32 *slot_num;
1053 int len;
1054
1055 slot_num = of_get_property(pdev->dev.of_node,
1056 "physical-slot#", &len);
1057
1058 if (slot_num == NULL || len != 4)
1059 continue;
1060
1061 snprintf(name, sizeof(name), "%u", slot_num[0]);
1062 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
1063
1064 if (IS_ERR(pci_slot))
1065 pr_err("PCI: pci_create_slot returned %ld.\n",
1066 PTR_ERR(pci_slot));
1067 }
1068
1069 list_for_each_entry(bus, &pbus->children, node)
1070 pcie_bus_slot_names(bus);
1071}
1072
1073static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
1074{
1075 const struct pci_slot_names {
1076 u32 slot_mask;
1077 char names[0];
1078 } *prop;
1079 const char *sp;
1080 int len, i;
1081 u32 mask;
1082
1083 prop = of_get_property(node, "slot-names", &len);
1084 if (!prop)
1085 return;
1086
1087 mask = prop->slot_mask;
1088 sp = prop->names;
1089
1090 if (ofpci_verbose)
1091 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
1092 node, mask);
1093
1094 i = 0;
1095 while (mask) {
1096 struct pci_slot *pci_slot;
1097 u32 this_bit = 1 << i;
1098
1099 if (!(mask & this_bit)) {
1100 i++;
1101 continue;
1102 }
1103
1104 if (ofpci_verbose)
1105 pci_info(bus, "Making slot [%s]\n", sp);
1106
1107 pci_slot = pci_create_slot(bus, i, sp, NULL);
1108 if (IS_ERR(pci_slot))
1109 pci_err(bus, "pci_create_slot returned %ld\n",
1110 PTR_ERR(pci_slot));
1111
1112 sp += strlen(sp) + 1;
1113 mask &= ~this_bit;
1114 i++;
1115 }
1116}
1117
1118static int __init of_pci_slot_init(void)
1119{
1120 struct pci_bus *pbus = NULL;
1121
1122 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1123 struct device_node *node;
1124 struct pci_dev *pdev;
1125
1126 pdev = list_first_entry(&pbus->devices, struct pci_dev,
1127 bus_list);
1128
1129 if (pdev && pci_is_pcie(pdev)) {
1130 pcie_bus_slot_names(pbus);
1131 } else {
1132
1133 if (pbus->self) {
1134
1135 /* PCI->PCI bridge */
1136 node = pbus->self->dev.of_node;
1137
1138 } else {
1139 struct pci_pbm_info *pbm = pbus->sysdata;
1140
1141 /* Host PCI controller */
1142 node = pbm->op->dev.of_node;
1143 }
1144
1145 pci_bus_slot_names(node, pbus);
1146 }
1147 }
1148
1149 return 0;
1150}
1151device_initcall(of_pci_slot_init);
1152#endif