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1comment "Processor Type"
2
3# Select CPU types depending on the architecture selected. This selects
4# which CPUs we support in the kernel image, and the compiler instruction
5# optimiser behaviour.
6
7# ARM610
8config CPU_ARM610
9 bool "Support ARM610 processor" if ARCH_RPC
10 select CPU_32v3
11 select CPU_CACHE_V3
12 select CPU_CACHE_VIVT
13 select CPU_CP15_MMU
14 select CPU_COPY_V3 if MMU
15 select CPU_TLB_V3 if MMU
16 select CPU_PABRT_LEGACY
17 help
18 The ARM610 is the successor to the ARM3 processor
19 and was produced by VLSI Technology Inc.
20
21 Say Y if you want support for the ARM610 processor.
22 Otherwise, say N.
23
24# ARM7TDMI
25config CPU_ARM7TDMI
26 bool "Support ARM7TDMI processor"
27 depends on !MMU
28 select CPU_32v4T
29 select CPU_ABRT_LV4T
30 select CPU_PABRT_LEGACY
31 select CPU_CACHE_V4
32 help
33 A 32-bit RISC microprocessor based on the ARM7 processor core
34 which has no memory control unit and cache.
35
36 Say Y if you want support for the ARM7TDMI processor.
37 Otherwise, say N.
38
39# ARM710
40config CPU_ARM710
41 bool "Support ARM710 processor" if ARCH_RPC
42 select CPU_32v3
43 select CPU_CACHE_V3
44 select CPU_CACHE_VIVT
45 select CPU_CP15_MMU
46 select CPU_COPY_V3 if MMU
47 select CPU_TLB_V3 if MMU
48 select CPU_PABRT_LEGACY
49 help
50 A 32-bit RISC microprocessor based on the ARM7 processor core
51 designed by Advanced RISC Machines Ltd. The ARM710 is the
52 successor to the ARM610 processor. It was released in
53 July 1994 by VLSI Technology Inc.
54
55 Say Y if you want support for the ARM710 processor.
56 Otherwise, say N.
57
58# ARM720T
59config CPU_ARM720T
60 bool "Support ARM720T processor" if ARCH_INTEGRATOR
61 select CPU_32v4T
62 select CPU_ABRT_LV4T
63 select CPU_PABRT_LEGACY
64 select CPU_CACHE_V4
65 select CPU_CACHE_VIVT
66 select CPU_CP15_MMU
67 select CPU_COPY_V4WT if MMU
68 select CPU_TLB_V4WT if MMU
69 help
70 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
71 MMU built around an ARM7TDMI core.
72
73 Say Y if you want support for the ARM720T processor.
74 Otherwise, say N.
75
76# ARM740T
77config CPU_ARM740T
78 bool "Support ARM740T processor" if ARCH_INTEGRATOR
79 depends on !MMU
80 select CPU_32v4T
81 select CPU_ABRT_LV4T
82 select CPU_PABRT_LEGACY
83 select CPU_CACHE_V3 # although the core is v4t
84 select CPU_CP15_MPU
85 help
86 A 32-bit RISC processor with 8KB cache or 4KB variants,
87 write buffer and MPU(Protection Unit) built around
88 an ARM7TDMI core.
89
90 Say Y if you want support for the ARM740T processor.
91 Otherwise, say N.
92
93# ARM9TDMI
94config CPU_ARM9TDMI
95 bool "Support ARM9TDMI processor"
96 depends on !MMU
97 select CPU_32v4T
98 select CPU_ABRT_NOMMU
99 select CPU_PABRT_LEGACY
100 select CPU_CACHE_V4
101 help
102 A 32-bit RISC microprocessor based on the ARM9 processor core
103 which has no memory control unit and cache.
104
105 Say Y if you want support for the ARM9TDMI processor.
106 Otherwise, say N.
107
108# ARM920T
109config CPU_ARM920T
110 bool "Support ARM920T processor" if ARCH_INTEGRATOR
111 select CPU_32v4T
112 select CPU_ABRT_EV4T
113 select CPU_PABRT_LEGACY
114 select CPU_CACHE_V4WT
115 select CPU_CACHE_VIVT
116 select CPU_CP15_MMU
117 select CPU_COPY_V4WB if MMU
118 select CPU_TLB_V4WBI if MMU
119 help
120 The ARM920T is licensed to be produced by numerous vendors,
121 and is used in the Cirrus EP93xx and the Samsung S3C2410.
122
123 Say Y if you want support for the ARM920T processor.
124 Otherwise, say N.
125
126# ARM922T
127config CPU_ARM922T
128 bool "Support ARM922T processor" if ARCH_INTEGRATOR
129 select CPU_32v4T
130 select CPU_ABRT_EV4T
131 select CPU_PABRT_LEGACY
132 select CPU_CACHE_V4WT
133 select CPU_CACHE_VIVT
134 select CPU_CP15_MMU
135 select CPU_COPY_V4WB if MMU
136 select CPU_TLB_V4WBI if MMU
137 help
138 The ARM922T is a version of the ARM920T, but with smaller
139 instruction and data caches. It is used in Altera's
140 Excalibur XA device family and Micrel's KS8695 Centaur.
141
142 Say Y if you want support for the ARM922T processor.
143 Otherwise, say N.
144
145# ARM925T
146config CPU_ARM925T
147 bool "Support ARM925T processor" if ARCH_OMAP1
148 select CPU_32v4T
149 select CPU_ABRT_EV4T
150 select CPU_PABRT_LEGACY
151 select CPU_CACHE_V4WT
152 select CPU_CACHE_VIVT
153 select CPU_CP15_MMU
154 select CPU_COPY_V4WB if MMU
155 select CPU_TLB_V4WBI if MMU
156 help
157 The ARM925T is a mix between the ARM920T and ARM926T, but with
158 different instruction and data caches. It is used in TI's OMAP
159 device family.
160
161 Say Y if you want support for the ARM925T processor.
162 Otherwise, say N.
163
164# ARM926T
165config CPU_ARM926T
166 bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
167 select CPU_32v5
168 select CPU_ABRT_EV5TJ
169 select CPU_PABRT_LEGACY
170 select CPU_CACHE_VIVT
171 select CPU_CP15_MMU
172 select CPU_COPY_V4WB if MMU
173 select CPU_TLB_V4WBI if MMU
174 help
175 This is a variant of the ARM920. It has slightly different
176 instruction sequences for cache and TLB operations. Curiously,
177 there is no documentation on it at the ARM corporate website.
178
179 Say Y if you want support for the ARM926T processor.
180 Otherwise, say N.
181
182# FA526
183config CPU_FA526
184 bool
185 select CPU_32v4
186 select CPU_ABRT_EV4
187 select CPU_PABRT_LEGACY
188 select CPU_CACHE_VIVT
189 select CPU_CP15_MMU
190 select CPU_CACHE_FA
191 select CPU_COPY_FA if MMU
192 select CPU_TLB_FA if MMU
193 help
194 The FA526 is a version of the ARMv4 compatible processor with
195 Branch Target Buffer, Unified TLB and cache line size 16.
196
197 Say Y if you want support for the FA526 processor.
198 Otherwise, say N.
199
200# ARM940T
201config CPU_ARM940T
202 bool "Support ARM940T processor" if ARCH_INTEGRATOR
203 depends on !MMU
204 select CPU_32v4T
205 select CPU_ABRT_NOMMU
206 select CPU_PABRT_LEGACY
207 select CPU_CACHE_VIVT
208 select CPU_CP15_MPU
209 help
210 ARM940T is a member of the ARM9TDMI family of general-
211 purpose microprocessors with MPU and separate 4KB
212 instruction and 4KB data cases, each with a 4-word line
213 length.
214
215 Say Y if you want support for the ARM940T processor.
216 Otherwise, say N.
217
218# ARM946E-S
219config CPU_ARM946E
220 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
221 depends on !MMU
222 select CPU_32v5
223 select CPU_ABRT_NOMMU
224 select CPU_PABRT_LEGACY
225 select CPU_CACHE_VIVT
226 select CPU_CP15_MPU
227 help
228 ARM946E-S is a member of the ARM9E-S family of high-
229 performance, 32-bit system-on-chip processor solutions.
230 The TCM and ARMv5TE 32-bit instruction set is supported.
231
232 Say Y if you want support for the ARM946E-S processor.
233 Otherwise, say N.
234
235# ARM1020 - needs validating
236config CPU_ARM1020
237 bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
238 select CPU_32v5
239 select CPU_ABRT_EV4T
240 select CPU_PABRT_LEGACY
241 select CPU_CACHE_V4WT
242 select CPU_CACHE_VIVT
243 select CPU_CP15_MMU
244 select CPU_COPY_V4WB if MMU
245 select CPU_TLB_V4WBI if MMU
246 help
247 The ARM1020 is the 32K cached version of the ARM10 processor,
248 with an addition of a floating-point unit.
249
250 Say Y if you want support for the ARM1020 processor.
251 Otherwise, say N.
252
253# ARM1020E - needs validating
254config CPU_ARM1020E
255 bool "Support ARM1020E processor" if ARCH_INTEGRATOR
256 select CPU_32v5
257 select CPU_ABRT_EV4T
258 select CPU_PABRT_LEGACY
259 select CPU_CACHE_V4WT
260 select CPU_CACHE_VIVT
261 select CPU_CP15_MMU
262 select CPU_COPY_V4WB if MMU
263 select CPU_TLB_V4WBI if MMU
264 depends on n
265
266# ARM1022E
267config CPU_ARM1022
268 bool "Support ARM1022E processor" if ARCH_INTEGRATOR
269 select CPU_32v5
270 select CPU_ABRT_EV4T
271 select CPU_PABRT_LEGACY
272 select CPU_CACHE_VIVT
273 select CPU_CP15_MMU
274 select CPU_COPY_V4WB if MMU # can probably do better
275 select CPU_TLB_V4WBI if MMU
276 help
277 The ARM1022E is an implementation of the ARMv5TE architecture
278 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
279 embedded trace macrocell, and a floating-point unit.
280
281 Say Y if you want support for the ARM1022E processor.
282 Otherwise, say N.
283
284# ARM1026EJ-S
285config CPU_ARM1026
286 bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
287 select CPU_32v5
288 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
289 select CPU_PABRT_LEGACY
290 select CPU_CACHE_VIVT
291 select CPU_CP15_MMU
292 select CPU_COPY_V4WB if MMU # can probably do better
293 select CPU_TLB_V4WBI if MMU
294 help
295 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
296 based upon the ARM10 integer core.
297
298 Say Y if you want support for the ARM1026EJ-S processor.
299 Otherwise, say N.
300
301# SA110
302config CPU_SA110
303 bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
304 select CPU_32v3 if ARCH_RPC
305 select CPU_32v4 if !ARCH_RPC
306 select CPU_ABRT_EV4
307 select CPU_PABRT_LEGACY
308 select CPU_CACHE_V4WB
309 select CPU_CACHE_VIVT
310 select CPU_CP15_MMU
311 select CPU_COPY_V4WB if MMU
312 select CPU_TLB_V4WB if MMU
313 help
314 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
315 is available at five speeds ranging from 100 MHz to 233 MHz.
316 More information is available at
317 <http://developer.intel.com/design/strong/sa110.htm>.
318
319 Say Y if you want support for the SA-110 processor.
320 Otherwise, say N.
321
322# SA1100
323config CPU_SA1100
324 bool
325 select CPU_32v4
326 select CPU_ABRT_EV4
327 select CPU_PABRT_LEGACY
328 select CPU_CACHE_V4WB
329 select CPU_CACHE_VIVT
330 select CPU_CP15_MMU
331 select CPU_TLB_V4WB if MMU
332
333# XScale
334config CPU_XSCALE
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_PABRT_LEGACY
339 select CPU_CACHE_VIVT
340 select CPU_CP15_MMU
341 select CPU_TLB_V4WBI if MMU
342
343# XScale Core Version 3
344config CPU_XSC3
345 bool
346 select CPU_32v5
347 select CPU_ABRT_EV5T
348 select CPU_PABRT_LEGACY
349 select CPU_CACHE_VIVT
350 select CPU_CP15_MMU
351 select CPU_TLB_V4WBI if MMU
352 select IO_36
353
354# Marvell PJ1 (Mohawk)
355config CPU_MOHAWK
356 bool
357 select CPU_32v5
358 select CPU_ABRT_EV5T
359 select CPU_PABRT_LEGACY
360 select CPU_CACHE_VIVT
361 select CPU_CP15_MMU
362 select CPU_TLB_V4WBI if MMU
363 select CPU_COPY_V4WB if MMU
364
365# Feroceon
366config CPU_FEROCEON
367 bool
368 select CPU_32v5
369 select CPU_ABRT_EV5T
370 select CPU_PABRT_LEGACY
371 select CPU_CACHE_VIVT
372 select CPU_CP15_MMU
373 select CPU_COPY_FEROCEON if MMU
374 select CPU_TLB_FEROCEON if MMU
375
376config CPU_FEROCEON_OLD_ID
377 bool "Accept early Feroceon cores with an ARM926 ID"
378 depends on CPU_FEROCEON && !CPU_ARM926T
379 default y
380 help
381 This enables the usage of some old Feroceon cores
382 for which the CPU ID is equal to the ARM926 ID.
383 Relevant for Feroceon-1850 and early Feroceon-2850.
384
385# Marvell PJ4
386config CPU_PJ4
387 bool
388 select CPU_V7
389 select ARM_THUMBEE
390
391# ARMv6
392config CPU_V6
393 bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
394 select CPU_32v6
395 select CPU_ABRT_EV6
396 select CPU_PABRT_V6
397 select CPU_CACHE_V6
398 select CPU_CACHE_VIPT
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_COPY_V6 if MMU
402 select CPU_TLB_V6 if MMU
403
404# ARMv6k
405config CPU_V6K
406 bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
407 select CPU_32v6
408 select CPU_32v6K
409 select CPU_ABRT_EV6
410 select CPU_PABRT_V6
411 select CPU_CACHE_V6
412 select CPU_CACHE_VIPT
413 select CPU_CP15_MMU
414 select CPU_HAS_ASID if MMU
415 select CPU_COPY_V6 if MMU
416 select CPU_TLB_V6 if MMU
417
418# ARMv7
419config CPU_V7
420 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
421 select CPU_32v6K
422 select CPU_32v7
423 select CPU_ABRT_EV7
424 select CPU_PABRT_V7
425 select CPU_CACHE_V7
426 select CPU_CACHE_VIPT
427 select CPU_CP15_MMU
428 select CPU_HAS_ASID if MMU
429 select CPU_COPY_V6 if MMU
430 select CPU_TLB_V7 if MMU
431
432# Figure out what processor architecture version we should be using.
433# This defines the compiler instruction set which depends on the machine type.
434config CPU_32v3
435 bool
436 select TLS_REG_EMUL if SMP || !MMU
437 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
438 select CPU_USE_DOMAINS if MMU
439
440config CPU_32v4
441 bool
442 select TLS_REG_EMUL if SMP || !MMU
443 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444 select CPU_USE_DOMAINS if MMU
445
446config CPU_32v4T
447 bool
448 select TLS_REG_EMUL if SMP || !MMU
449 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
450 select CPU_USE_DOMAINS if MMU
451
452config CPU_32v5
453 bool
454 select TLS_REG_EMUL if SMP || !MMU
455 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
456 select CPU_USE_DOMAINS if MMU
457
458config CPU_32v6
459 bool
460 select TLS_REG_EMUL if !CPU_32v6K && !MMU
461 select CPU_USE_DOMAINS if CPU_V6 && MMU
462
463config CPU_32v6K
464 bool
465
466config CPU_32v7
467 bool
468
469# The abort model
470config CPU_ABRT_NOMMU
471 bool
472
473config CPU_ABRT_EV4
474 bool
475
476config CPU_ABRT_EV4T
477 bool
478
479config CPU_ABRT_LV4T
480 bool
481
482config CPU_ABRT_EV5T
483 bool
484
485config CPU_ABRT_EV5TJ
486 bool
487
488config CPU_ABRT_EV6
489 bool
490
491config CPU_ABRT_EV7
492 bool
493
494config CPU_PABRT_LEGACY
495 bool
496
497config CPU_PABRT_V6
498 bool
499
500config CPU_PABRT_V7
501 bool
502
503# The cache model
504config CPU_CACHE_V3
505 bool
506
507config CPU_CACHE_V4
508 bool
509
510config CPU_CACHE_V4WT
511 bool
512
513config CPU_CACHE_V4WB
514 bool
515
516config CPU_CACHE_V6
517 bool
518
519config CPU_CACHE_V7
520 bool
521
522config CPU_CACHE_VIVT
523 bool
524
525config CPU_CACHE_VIPT
526 bool
527
528config CPU_CACHE_FA
529 bool
530
531if MMU
532# The copy-page model
533config CPU_COPY_V3
534 bool
535
536config CPU_COPY_V4WT
537 bool
538
539config CPU_COPY_V4WB
540 bool
541
542config CPU_COPY_FEROCEON
543 bool
544
545config CPU_COPY_FA
546 bool
547
548config CPU_COPY_V6
549 bool
550
551# This selects the TLB model
552config CPU_TLB_V3
553 bool
554 help
555 ARM Architecture Version 3 TLB.
556
557config CPU_TLB_V4WT
558 bool
559 help
560 ARM Architecture Version 4 TLB with writethrough cache.
561
562config CPU_TLB_V4WB
563 bool
564 help
565 ARM Architecture Version 4 TLB with writeback cache.
566
567config CPU_TLB_V4WBI
568 bool
569 help
570 ARM Architecture Version 4 TLB with writeback cache and invalidate
571 instruction cache entry.
572
573config CPU_TLB_FEROCEON
574 bool
575 help
576 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
577
578config CPU_TLB_FA
579 bool
580 help
581 Faraday ARM FA526 architecture, unified TLB with writeback cache
582 and invalidate instruction cache entry. Branch target buffer is
583 also supported.
584
585config CPU_TLB_V6
586 bool
587
588config CPU_TLB_V7
589 bool
590
591config VERIFY_PERMISSION_FAULT
592 bool
593endif
594
595config CPU_HAS_ASID
596 bool
597 help
598 This indicates whether the CPU has the ASID register; used to
599 tag TLB and possibly cache entries.
600
601config CPU_CP15
602 bool
603 help
604 Processor has the CP15 register.
605
606config CPU_CP15_MMU
607 bool
608 select CPU_CP15
609 help
610 Processor has the CP15 register, which has MMU related registers.
611
612config CPU_CP15_MPU
613 bool
614 select CPU_CP15
615 help
616 Processor has the CP15 register, which has MPU related registers.
617
618config CPU_USE_DOMAINS
619 bool
620 help
621 This option enables or disables the use of domain switching
622 via the set_fs() function.
623
624#
625# CPU supports 36-bit I/O
626#
627config IO_36
628 bool
629
630comment "Processor Features"
631
632config ARM_THUMB
633 bool "Support Thumb user binaries"
634 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
635 default y
636 help
637 Say Y if you want to include kernel support for running user space
638 Thumb binaries.
639
640 The Thumb instruction set is a compressed form of the standard ARM
641 instruction set resulting in smaller binaries at the expense of
642 slightly less efficient code.
643
644 If you don't know what this all is, saying Y is a safe choice.
645
646config ARM_THUMBEE
647 bool "Enable ThumbEE CPU extension"
648 depends on CPU_V7
649 help
650 Say Y here if you have a CPU with the ThumbEE extension and code to
651 make use of it. Say N for code that can run on CPUs without ThumbEE.
652
653config SWP_EMULATE
654 bool "Emulate SWP/SWPB instructions"
655 depends on !CPU_USE_DOMAINS && CPU_V7
656 select HAVE_PROC_CPU if PROC_FS
657 default y if SMP
658 help
659 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
660 ARMv7 multiprocessing extensions introduce the ability to disable
661 these instructions, triggering an undefined instruction exception
662 when executed. Say Y here to enable software emulation of these
663 instructions for userspace (not kernel) using LDREX/STREX.
664 Also creates /proc/cpu/swp_emulation for statistics.
665
666 In some older versions of glibc [<=2.8] SWP is used during futex
667 trylock() operations with the assumption that the code will not
668 be preempted. This invalid assumption may be more likely to fail
669 with SWP emulation enabled, leading to deadlock of the user
670 application.
671
672 NOTE: when accessing uncached shared regions, LDREX/STREX rely
673 on an external transaction monitoring block called a global
674 monitor to maintain update atomicity. If your system does not
675 implement a global monitor, this option can cause programs that
676 perform SWP operations to uncached memory to deadlock.
677
678 If unsure, say Y.
679
680config CPU_BIG_ENDIAN
681 bool "Build big-endian kernel"
682 depends on ARCH_SUPPORTS_BIG_ENDIAN
683 help
684 Say Y if you plan on running a kernel in big-endian mode.
685 Note that your board must be properly built and your board
686 port must properly enable any big-endian related features
687 of your chipset/board/processor.
688
689config CPU_ENDIAN_BE8
690 bool
691 depends on CPU_BIG_ENDIAN
692 default CPU_V6 || CPU_V6K || CPU_V7
693 help
694 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
695
696config CPU_ENDIAN_BE32
697 bool
698 depends on CPU_BIG_ENDIAN
699 default !CPU_ENDIAN_BE8
700 help
701 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
702
703config CPU_HIGH_VECTOR
704 depends on !MMU && CPU_CP15 && !CPU_ARM740T
705 bool "Select the High exception vector"
706 help
707 Say Y here to select high exception vector(0xFFFF0000~).
708 The exception vector can be vary depending on the platform
709 design in nommu mode. If your platform needs to select
710 high exception vector, say Y.
711 Otherwise or if you are unsure, say N, and the low exception
712 vector (0x00000000~) will be used.
713
714config CPU_ICACHE_DISABLE
715 bool "Disable I-Cache (I-bit)"
716 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
717 help
718 Say Y here to disable the processor instruction cache. Unless
719 you have a reason not to or are unsure, say N.
720
721config CPU_DCACHE_DISABLE
722 bool "Disable D-Cache (C-bit)"
723 depends on CPU_CP15
724 help
725 Say Y here to disable the processor data cache. Unless
726 you have a reason not to or are unsure, say N.
727
728config CPU_DCACHE_SIZE
729 hex
730 depends on CPU_ARM740T || CPU_ARM946E
731 default 0x00001000 if CPU_ARM740T
732 default 0x00002000 # default size for ARM946E-S
733 help
734 Some cores are synthesizable to have various sized cache. For
735 ARM946E-S case, it can vary from 0KB to 1MB.
736 To support such cache operations, it is efficient to know the size
737 before compile time.
738 If your SoC is configured to have a different size, define the value
739 here with proper conditions.
740
741config CPU_DCACHE_WRITETHROUGH
742 bool "Force write through D-cache"
743 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
744 default y if CPU_ARM925T
745 help
746 Say Y here to use the data cache in writethrough mode. Unless you
747 specifically require this or are unsure, say N.
748
749config CPU_CACHE_ROUND_ROBIN
750 bool "Round robin I and D cache replacement algorithm"
751 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
752 help
753 Say Y here to use the predictable round-robin cache replacement
754 policy. Unless you specifically require this or are unsure, say N.
755
756config CPU_BPREDICT_DISABLE
757 bool "Disable branch prediction"
758 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
759 help
760 Say Y here to disable branch prediction. If unsure, say N.
761
762config TLS_REG_EMUL
763 bool
764 help
765 An SMP system using a pre-ARMv6 processor (there are apparently
766 a few prototypes like that in existence) and therefore access to
767 that required register must be emulated.
768
769config NEEDS_SYSCALL_FOR_CMPXCHG
770 bool
771 help
772 SMP on a pre-ARMv6 processor? Well OK then.
773 Forget about fast user space cmpxchg support.
774 It is just not possible.
775
776config DMA_CACHE_RWFO
777 bool "Enable read/write for ownership DMA cache maintenance"
778 depends on CPU_V6K && SMP
779 default y
780 help
781 The Snoop Control Unit on ARM11MPCore does not detect the
782 cache maintenance operations and the dma_{map,unmap}_area()
783 functions may leave stale cache entries on other CPUs. By
784 enabling this option, Read or Write For Ownership in the ARMv6
785 DMA cache maintenance functions is performed. These LDR/STR
786 instructions change the cache line state to shared or modified
787 so that the cache operation has the desired effect.
788
789 Note that the workaround is only valid on processors that do
790 not perform speculative loads into the D-cache. For such
791 processors, if cache maintenance operations are not broadcast
792 in hardware, other workarounds are needed (e.g. cache
793 maintenance broadcasting in software via FIQ).
794
795config OUTER_CACHE
796 bool
797
798config OUTER_CACHE_SYNC
799 bool
800 help
801 The outer cache has a outer_cache_fns.sync function pointer
802 that can be used to drain the write buffer of the outer cache.
803
804config CACHE_FEROCEON_L2
805 bool "Enable the Feroceon L2 cache controller"
806 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
807 default y
808 select OUTER_CACHE
809 help
810 This option enables the Feroceon L2 cache controller.
811
812config CACHE_FEROCEON_L2_WRITETHROUGH
813 bool "Force Feroceon L2 cache write through"
814 depends on CACHE_FEROCEON_L2
815 help
816 Say Y here to use the Feroceon L2 cache in writethrough mode.
817 Unless you specifically require this, say N for writeback mode.
818
819config CACHE_L2X0
820 bool "Enable the L2x0 outer cache controller"
821 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
822 REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
823 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
824 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
825 ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
826 default y
827 select OUTER_CACHE
828 select OUTER_CACHE_SYNC
829 help
830 This option enables the L2x0 PrimeCell.
831
832config CACHE_PL310
833 bool
834 depends on CACHE_L2X0
835 default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
836 help
837 This option enables optimisations for the PL310 cache
838 controller.
839
840config CACHE_TAUROS2
841 bool "Enable the Tauros2 L2 cache controller"
842 depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
843 default y
844 select OUTER_CACHE
845 help
846 This option enables the Tauros2 L2 cache controller (as
847 found on PJ1/PJ4).
848
849config CACHE_XSC3L2
850 bool "Enable the L2 cache on XScale3"
851 depends on CPU_XSC3
852 default y
853 select OUTER_CACHE
854 help
855 This option enables the L2 cache on XScale3.
856
857config ARM_L1_CACHE_SHIFT_6
858 bool
859 help
860 Setting ARM L1 cache line size to 64 Bytes.
861
862config ARM_L1_CACHE_SHIFT
863 int
864 default 6 if ARM_L1_CACHE_SHIFT_6
865 default 5
866
867config ARM_DMA_MEM_BUFFERABLE
868 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
869 depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
870 MACH_REALVIEW_PB11MP)
871 default y if CPU_V6 || CPU_V6K || CPU_V7
872 help
873 Historically, the kernel has used strongly ordered mappings to
874 provide DMA coherent memory. With the advent of ARMv7, mapping
875 memory with differing types results in unpredictable behaviour,
876 so on these CPUs, this option is forced on.
877
878 Multiple mappings with differing attributes is also unpredictable
879 on ARMv6 CPUs, but since they do not have aggressive speculative
880 prefetch, no harm appears to occur.
881
882 However, drivers may be missing the necessary barriers for ARMv6,
883 and therefore turning this on may result in unpredictable driver
884 behaviour. Therefore, we offer this as an option.
885
886 You are recommended say 'Y' here and debug any affected drivers.
887
888config ARCH_HAS_BARRIERS
889 bool
890 help
891 This option allows the use of custom mandatory barriers
892 included via the mach/barriers.h file.
1# SPDX-License-Identifier: GPL-2.0
2comment "Processor Type"
3
4# Select CPU types depending on the architecture selected. This selects
5# which CPUs we support in the kernel image, and the compiler instruction
6# optimiser behaviour.
7
8# ARM7TDMI
9config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
19
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
22
23# ARM720T
24config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
38
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
41
42# ARM740T
43config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
56
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
59
60# ARM9TDMI
61config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
71
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
74
75# ARM920T
76config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
90
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
93
94# ARM922T
95config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and the ARM Integrator.
110
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
113
114# ARM925T
115config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
130
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
133
134# ARM926T
135config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
149
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
152
153# FA526
154config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
167
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
170
171# ARM940T
172config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
186
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
189
190# ARM946E-S
191config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
204
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
207
208# ARM1020 - needs validating
209config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
223
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
226
227# ARM1020E - needs validating
228config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
240
241# ARM1022E
242config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
256
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
259
260# ARM1026EJ-S
261config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
274
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
277
278# SA110
279config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
295
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
298
299# SA1100
300config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
309
310# XScale
311config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
320
321# XScale Core Version 3
322config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
332
333# Marvell PJ1 (Mohawk)
334config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
344
345# Feroceon
346config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
356
357config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
365
366# Marvell PJ4
367config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
371
372config CPU_PJ4B
373 bool
374 select CPU_V7
375
376# ARMv6
377config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
389
390# ARMv6k
391config CPU_V6K
392 bool
393 select CPU_32v6
394 select CPU_32v6K
395 select CPU_ABRT_EV6
396 select CPU_CACHE_V6
397 select CPU_CACHE_VIPT
398 select CPU_COPY_V6 if MMU
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_PABRT_V6
402 select CPU_THUMB_CAPABLE
403 select CPU_TLB_V6 if MMU
404
405# ARMv7
406config CPU_V7
407 bool
408 select CPU_32v6K
409 select CPU_32v7
410 select CPU_ABRT_EV7
411 select CPU_CACHE_V7
412 select CPU_CACHE_VIPT
413 select CPU_COPY_V6 if MMU
414 select CPU_CP15_MMU if MMU
415 select CPU_CP15_MPU if !MMU
416 select CPU_HAS_ASID if MMU
417 select CPU_PABRT_V7
418 select CPU_SPECTRE if MMU
419 select CPU_THUMB_CAPABLE
420 select CPU_TLB_V7 if MMU
421
422# ARMv7M
423config CPU_V7M
424 bool
425 select CPU_32v7M
426 select CPU_ABRT_NOMMU
427 select CPU_CACHE_V7M
428 select CPU_CACHE_NOP
429 select CPU_PABRT_LEGACY
430 select CPU_THUMBONLY
431
432config CPU_THUMBONLY
433 bool
434 select CPU_THUMB_CAPABLE
435 # There are no CPUs available with MMU that don't implement an ARM ISA:
436 depends on !MMU
437 help
438 Select this if your CPU doesn't support the 32 bit ARM instructions.
439
440config CPU_THUMB_CAPABLE
441 bool
442 help
443 Select this if your CPU can support Thumb mode.
444
445# Figure out what processor architecture version we should be using.
446# This defines the compiler instruction set which depends on the machine type.
447config CPU_32v3
448 bool
449 select CPU_USE_DOMAINS if MMU
450 select NEED_KUSER_HELPERS
451 select TLS_REG_EMUL if SMP || !MMU
452 select CPU_NO_EFFICIENT_FFS
453
454config CPU_32v4
455 bool
456 select CPU_USE_DOMAINS if MMU
457 select NEED_KUSER_HELPERS
458 select TLS_REG_EMUL if SMP || !MMU
459 select CPU_NO_EFFICIENT_FFS
460
461config CPU_32v4T
462 bool
463 select CPU_USE_DOMAINS if MMU
464 select NEED_KUSER_HELPERS
465 select TLS_REG_EMUL if SMP || !MMU
466 select CPU_NO_EFFICIENT_FFS
467
468config CPU_32v5
469 bool
470 select CPU_USE_DOMAINS if MMU
471 select NEED_KUSER_HELPERS
472 select TLS_REG_EMUL if SMP || !MMU
473
474config CPU_32v6
475 bool
476 select TLS_REG_EMUL if !CPU_32v6K && !MMU
477
478config CPU_32v6K
479 bool
480
481config CPU_32v7
482 bool
483
484config CPU_32v7M
485 bool
486
487# The abort model
488config CPU_ABRT_NOMMU
489 bool
490
491config CPU_ABRT_EV4
492 bool
493
494config CPU_ABRT_EV4T
495 bool
496
497config CPU_ABRT_LV4T
498 bool
499
500config CPU_ABRT_EV5T
501 bool
502
503config CPU_ABRT_EV5TJ
504 bool
505
506config CPU_ABRT_EV6
507 bool
508
509config CPU_ABRT_EV7
510 bool
511
512config CPU_PABRT_LEGACY
513 bool
514
515config CPU_PABRT_V6
516 bool
517
518config CPU_PABRT_V7
519 bool
520
521# The cache model
522config CPU_CACHE_V4
523 bool
524
525config CPU_CACHE_V4WT
526 bool
527
528config CPU_CACHE_V4WB
529 bool
530
531config CPU_CACHE_V6
532 bool
533
534config CPU_CACHE_V7
535 bool
536
537config CPU_CACHE_NOP
538 bool
539
540config CPU_CACHE_VIVT
541 bool
542
543config CPU_CACHE_VIPT
544 bool
545
546config CPU_CACHE_FA
547 bool
548
549config CPU_CACHE_V7M
550 bool
551
552if MMU
553# The copy-page model
554config CPU_COPY_V4WT
555 bool
556
557config CPU_COPY_V4WB
558 bool
559
560config CPU_COPY_FEROCEON
561 bool
562
563config CPU_COPY_FA
564 bool
565
566config CPU_COPY_V6
567 bool
568
569# This selects the TLB model
570config CPU_TLB_V4WT
571 bool
572 help
573 ARM Architecture Version 4 TLB with writethrough cache.
574
575config CPU_TLB_V4WB
576 bool
577 help
578 ARM Architecture Version 4 TLB with writeback cache.
579
580config CPU_TLB_V4WBI
581 bool
582 help
583 ARM Architecture Version 4 TLB with writeback cache and invalidate
584 instruction cache entry.
585
586config CPU_TLB_FEROCEON
587 bool
588 help
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
590
591config CPU_TLB_FA
592 bool
593 help
594 Faraday ARM FA526 architecture, unified TLB with writeback cache
595 and invalidate instruction cache entry. Branch target buffer is
596 also supported.
597
598config CPU_TLB_V6
599 bool
600
601config CPU_TLB_V7
602 bool
603
604endif
605
606config CPU_HAS_ASID
607 bool
608 help
609 This indicates whether the CPU has the ASID register; used to
610 tag TLB and possibly cache entries.
611
612config CPU_CP15
613 bool
614 help
615 Processor has the CP15 register.
616
617config CPU_CP15_MMU
618 bool
619 select CPU_CP15
620 help
621 Processor has the CP15 register, which has MMU related registers.
622
623config CPU_CP15_MPU
624 bool
625 select CPU_CP15
626 help
627 Processor has the CP15 register, which has MPU related registers.
628
629config CPU_USE_DOMAINS
630 bool
631 help
632 This option enables or disables the use of domain switching
633 via the set_fs() function.
634
635config CPU_V7M_NUM_IRQ
636 int "Number of external interrupts connected to the NVIC"
637 depends on CPU_V7M
638 default 90 if ARCH_STM32
639 default 112 if SOC_VF610
640 default 240
641 help
642 This option indicates the number of interrupts connected to the NVIC.
643 The value can be larger than the real number of interrupts supported
644 by the system, but must not be lower.
645 The default value is 240, corresponding to the maximum number of
646 interrupts supported by the NVIC on Cortex-M family.
647
648 If unsure, keep default value.
649
650#
651# CPU supports 36-bit I/O
652#
653config IO_36
654 bool
655
656comment "Processor Features"
657
658config ARM_LPAE
659 bool "Support for the Large Physical Address Extension"
660 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
661 !CPU_32v4 && !CPU_32v3
662 select PHYS_ADDR_T_64BIT
663 select SWIOTLB
664 help
665 Say Y if you have an ARMv7 processor supporting the LPAE page
666 table format and you would like to access memory beyond the
667 4GB limit. The resulting kernel image will not run on
668 processors without the LPA extension.
669
670 If unsure, say N.
671
672config ARM_PV_FIXUP
673 def_bool y
674 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
675
676config ARM_THUMB
677 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
678 depends on CPU_THUMB_CAPABLE
679 default y
680 help
681 Say Y if you want to include kernel support for running user space
682 Thumb binaries.
683
684 The Thumb instruction set is a compressed form of the standard ARM
685 instruction set resulting in smaller binaries at the expense of
686 slightly less efficient code.
687
688 If this option is disabled, and you run userspace that switches to
689 Thumb mode, signal handling will not work correctly, resulting in
690 segmentation faults or illegal instruction aborts.
691
692 If you don't know what this all is, saying Y is a safe choice.
693
694config ARM_THUMBEE
695 bool "Enable ThumbEE CPU extension"
696 depends on CPU_V7
697 help
698 Say Y here if you have a CPU with the ThumbEE extension and code to
699 make use of it. Say N for code that can run on CPUs without ThumbEE.
700
701config ARM_VIRT_EXT
702 bool
703 default y if CPU_V7
704 help
705 Enable the kernel to make use of the ARM Virtualization
706 Extensions to install hypervisors without run-time firmware
707 assistance.
708
709 A compliant bootloader is required in order to make maximum
710 use of this feature. Refer to Documentation/arm/booting.rst for
711 details.
712
713config SWP_EMULATE
714 bool "Emulate SWP/SWPB instructions" if !SMP
715 depends on CPU_V7
716 default y if SMP
717 select HAVE_PROC_CPU if PROC_FS
718 help
719 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
720 ARMv7 multiprocessing extensions introduce the ability to disable
721 these instructions, triggering an undefined instruction exception
722 when executed. Say Y here to enable software emulation of these
723 instructions for userspace (not kernel) using LDREX/STREX.
724 Also creates /proc/cpu/swp_emulation for statistics.
725
726 In some older versions of glibc [<=2.8] SWP is used during futex
727 trylock() operations with the assumption that the code will not
728 be preempted. This invalid assumption may be more likely to fail
729 with SWP emulation enabled, leading to deadlock of the user
730 application.
731
732 NOTE: when accessing uncached shared regions, LDREX/STREX rely
733 on an external transaction monitoring block called a global
734 monitor to maintain update atomicity. If your system does not
735 implement a global monitor, this option can cause programs that
736 perform SWP operations to uncached memory to deadlock.
737
738 If unsure, say Y.
739
740config CPU_BIG_ENDIAN
741 bool "Build big-endian kernel"
742 depends on ARCH_SUPPORTS_BIG_ENDIAN
743 depends on !LD_IS_LLD
744 help
745 Say Y if you plan on running a kernel in big-endian mode.
746 Note that your board must be properly built and your board
747 port must properly enable any big-endian related features
748 of your chipset/board/processor.
749
750config CPU_ENDIAN_BE8
751 bool
752 depends on CPU_BIG_ENDIAN
753 default CPU_V6 || CPU_V6K || CPU_V7
754 help
755 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
756
757config CPU_ENDIAN_BE32
758 bool
759 depends on CPU_BIG_ENDIAN
760 default !CPU_ENDIAN_BE8
761 help
762 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
763
764config CPU_HIGH_VECTOR
765 depends on !MMU && CPU_CP15 && !CPU_ARM740T
766 bool "Select the High exception vector"
767 help
768 Say Y here to select high exception vector(0xFFFF0000~).
769 The exception vector can vary depending on the platform
770 design in nommu mode. If your platform needs to select
771 high exception vector, say Y.
772 Otherwise or if you are unsure, say N, and the low exception
773 vector (0x00000000~) will be used.
774
775config CPU_ICACHE_DISABLE
776 bool "Disable I-Cache (I-bit)"
777 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
778 help
779 Say Y here to disable the processor instruction cache. Unless
780 you have a reason not to or are unsure, say N.
781
782config CPU_ICACHE_MISMATCH_WORKAROUND
783 bool "Workaround for I-Cache line size mismatch between CPU cores"
784 depends on SMP && CPU_V7
785 help
786 Some big.LITTLE systems have I-Cache line size mismatch between
787 LITTLE and big cores. Say Y here to enable a workaround for
788 proper I-Cache support on such systems. If unsure, say N.
789
790config CPU_DCACHE_DISABLE
791 bool "Disable D-Cache (C-bit)"
792 depends on (CPU_CP15 && !SMP) || CPU_V7M
793 help
794 Say Y here to disable the processor data cache. Unless
795 you have a reason not to or are unsure, say N.
796
797config CPU_DCACHE_SIZE
798 hex
799 depends on CPU_ARM740T || CPU_ARM946E
800 default 0x00001000 if CPU_ARM740T
801 default 0x00002000 # default size for ARM946E-S
802 help
803 Some cores are synthesizable to have various sized cache. For
804 ARM946E-S case, it can vary from 0KB to 1MB.
805 To support such cache operations, it is efficient to know the size
806 before compile time.
807 If your SoC is configured to have a different size, define the value
808 here with proper conditions.
809
810config CPU_DCACHE_WRITETHROUGH
811 bool "Force write through D-cache"
812 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
813 default y if CPU_ARM925T
814 help
815 Say Y here to use the data cache in writethrough mode. Unless you
816 specifically require this or are unsure, say N.
817
818config CPU_CACHE_ROUND_ROBIN
819 bool "Round robin I and D cache replacement algorithm"
820 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
821 help
822 Say Y here to use the predictable round-robin cache replacement
823 policy. Unless you specifically require this or are unsure, say N.
824
825config CPU_BPREDICT_DISABLE
826 bool "Disable branch prediction"
827 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
828 help
829 Say Y here to disable branch prediction. If unsure, say N.
830
831config CPU_SPECTRE
832 bool
833
834config HARDEN_BRANCH_PREDICTOR
835 bool "Harden the branch predictor against aliasing attacks" if EXPERT
836 depends on CPU_SPECTRE
837 default y
838 help
839 Speculation attacks against some high-performance processors rely
840 on being able to manipulate the branch predictor for a victim
841 context by executing aliasing branches in the attacker context.
842 Such attacks can be partially mitigated against by clearing
843 internal branch predictor state and limiting the prediction
844 logic in some situations.
845
846 This config option will take CPU-specific actions to harden
847 the branch predictor against aliasing attacks and may rely on
848 specific instruction sequences or control bits being set by
849 the system firmware.
850
851 If unsure, say Y.
852
853config TLS_REG_EMUL
854 bool
855 select NEED_KUSER_HELPERS
856 help
857 An SMP system using a pre-ARMv6 processor (there are apparently
858 a few prototypes like that in existence) and therefore access to
859 that required register must be emulated.
860
861config NEED_KUSER_HELPERS
862 bool
863
864config KUSER_HELPERS
865 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
866 depends on MMU
867 default y
868 help
869 Warning: disabling this option may break user programs.
870
871 Provide kuser helpers in the vector page. The kernel provides
872 helper code to userspace in read only form at a fixed location
873 in the high vector page to allow userspace to be independent of
874 the CPU type fitted to the system. This permits binaries to be
875 run on ARMv4 through to ARMv7 without modification.
876
877 See Documentation/arm/kernel_user_helpers.rst for details.
878
879 However, the fixed address nature of these helpers can be used
880 by ROP (return orientated programming) authors when creating
881 exploits.
882
883 If all of the binaries and libraries which run on your platform
884 are built specifically for your platform, and make no use of
885 these helpers, then you can turn this option off to hinder
886 such exploits. However, in that case, if a binary or library
887 relying on those helpers is run, it will receive a SIGILL signal,
888 which will terminate the program.
889
890 Say N here only if you are absolutely certain that you do not
891 need these helpers; otherwise, the safe option is to say Y.
892
893config VDSO
894 bool "Enable VDSO for acceleration of some system calls"
895 depends on AEABI && MMU && CPU_V7
896 default y if ARM_ARCH_TIMER
897 select HAVE_GENERIC_VDSO
898 select GENERIC_TIME_VSYSCALL
899 select GENERIC_VDSO_32
900 select GENERIC_GETTIMEOFDAY
901 help
902 Place in the process address space an ELF shared object
903 providing fast implementations of gettimeofday and
904 clock_gettime. Systems that implement the ARM architected
905 timer will receive maximum benefit.
906
907 You must have glibc 2.22 or later for programs to seamlessly
908 take advantage of this.
909
910config DMA_CACHE_RWFO
911 bool "Enable read/write for ownership DMA cache maintenance"
912 depends on CPU_V6K && SMP
913 default y
914 help
915 The Snoop Control Unit on ARM11MPCore does not detect the
916 cache maintenance operations and the dma_{map,unmap}_area()
917 functions may leave stale cache entries on other CPUs. By
918 enabling this option, Read or Write For Ownership in the ARMv6
919 DMA cache maintenance functions is performed. These LDR/STR
920 instructions change the cache line state to shared or modified
921 so that the cache operation has the desired effect.
922
923 Note that the workaround is only valid on processors that do
924 not perform speculative loads into the D-cache. For such
925 processors, if cache maintenance operations are not broadcast
926 in hardware, other workarounds are needed (e.g. cache
927 maintenance broadcasting in software via FIQ).
928
929config OUTER_CACHE
930 bool
931
932config OUTER_CACHE_SYNC
933 bool
934 select ARM_HEAVY_MB
935 help
936 The outer cache has a outer_cache_fns.sync function pointer
937 that can be used to drain the write buffer of the outer cache.
938
939config CACHE_B15_RAC
940 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
941 depends on ARCH_BRCMSTB
942 default y
943 help
944 This option enables the Broadcom Brahma-B15 read-ahead cache
945 controller. If disabled, the read-ahead cache remains off.
946
947config CACHE_FEROCEON_L2
948 bool "Enable the Feroceon L2 cache controller"
949 depends on ARCH_MV78XX0 || ARCH_MVEBU
950 default y
951 select OUTER_CACHE
952 help
953 This option enables the Feroceon L2 cache controller.
954
955config CACHE_FEROCEON_L2_WRITETHROUGH
956 bool "Force Feroceon L2 cache write through"
957 depends on CACHE_FEROCEON_L2
958 help
959 Say Y here to use the Feroceon L2 cache in writethrough mode.
960 Unless you specifically require this, say N for writeback mode.
961
962config MIGHT_HAVE_CACHE_L2X0
963 bool
964 help
965 This option should be selected by machines which have a L2x0
966 or PL310 cache controller, but where its use is optional.
967
968 The only effect of this option is to make CACHE_L2X0 and
969 related options available to the user for configuration.
970
971 Boards or SoCs which always require the cache controller
972 support to be present should select CACHE_L2X0 directly
973 instead of this option, thus preventing the user from
974 inadvertently configuring a broken kernel.
975
976config CACHE_L2X0
977 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
978 default MIGHT_HAVE_CACHE_L2X0
979 select OUTER_CACHE
980 select OUTER_CACHE_SYNC
981 help
982 This option enables the L2x0 PrimeCell.
983
984config CACHE_L2X0_PMU
985 bool "L2x0 performance monitor support" if CACHE_L2X0
986 depends on PERF_EVENTS
987 help
988 This option enables support for the performance monitoring features
989 of the L220 and PL310 outer cache controllers.
990
991if CACHE_L2X0
992
993config PL310_ERRATA_588369
994 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
995 help
996 The PL310 L2 cache controller implements three types of Clean &
997 Invalidate maintenance operations: by Physical Address
998 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
999 They are architecturally defined to behave as the execution of a
1000 clean operation followed immediately by an invalidate operation,
1001 both performing to the same memory location. This functionality
1002 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1003 as clean lines are not invalidated as a result of these operations.
1004
1005config PL310_ERRATA_727915
1006 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1007 help
1008 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1009 operation (offset 0x7FC). This operation runs in background so that
1010 PL310 can handle normal accesses while it is in progress. Under very
1011 rare circumstances, due to this erratum, write data can be lost when
1012 PL310 treats a cacheable write transaction during a Clean &
1013 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1014 this errata (fixed in r3p1).
1015
1016config PL310_ERRATA_753970
1017 bool "PL310 errata: cache sync operation may be faulty"
1018 help
1019 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1020
1021 Under some condition the effect of cache sync operation on
1022 the store buffer still remains when the operation completes.
1023 This means that the store buffer is always asked to drain and
1024 this prevents it from merging any further writes. The workaround
1025 is to replace the normal offset of cache sync operation (0x730)
1026 by another offset targeting an unmapped PL310 register 0x740.
1027 This has the same effect as the cache sync operation: store buffer
1028 drain and waiting for all buffers empty.
1029
1030config PL310_ERRATA_769419
1031 bool "PL310 errata: no automatic Store Buffer drain"
1032 help
1033 On revisions of the PL310 prior to r3p2, the Store Buffer does
1034 not automatically drain. This can cause normal, non-cacheable
1035 writes to be retained when the memory system is idle, leading
1036 to suboptimal I/O performance for drivers using coherent DMA.
1037 This option adds a write barrier to the cpu_idle loop so that,
1038 on systems with an outer cache, the store buffer is drained
1039 explicitly.
1040
1041endif
1042
1043config CACHE_TAUROS2
1044 bool "Enable the Tauros2 L2 cache controller"
1045 depends on (CPU_MOHAWK || CPU_PJ4)
1046 default y
1047 select OUTER_CACHE
1048 help
1049 This option enables the Tauros2 L2 cache controller (as
1050 found on PJ1/PJ4).
1051
1052config CACHE_UNIPHIER
1053 bool "Enable the UniPhier outer cache controller"
1054 depends on ARCH_UNIPHIER
1055 select ARM_L1_CACHE_SHIFT_7
1056 select OUTER_CACHE
1057 select OUTER_CACHE_SYNC
1058 help
1059 This option enables the UniPhier outer cache (system cache)
1060 controller.
1061
1062config CACHE_XSC3L2
1063 bool "Enable the L2 cache on XScale3"
1064 depends on CPU_XSC3
1065 default y
1066 select OUTER_CACHE
1067 help
1068 This option enables the L2 cache on XScale3.
1069
1070config ARM_L1_CACHE_SHIFT_6
1071 bool
1072 default y if CPU_V7
1073 help
1074 Setting ARM L1 cache line size to 64 Bytes.
1075
1076config ARM_L1_CACHE_SHIFT_7
1077 bool
1078 help
1079 Setting ARM L1 cache line size to 128 Bytes.
1080
1081config ARM_L1_CACHE_SHIFT
1082 int
1083 default 7 if ARM_L1_CACHE_SHIFT_7
1084 default 6 if ARM_L1_CACHE_SHIFT_6
1085 default 5
1086
1087config ARM_DMA_MEM_BUFFERABLE
1088 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1089 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1090 help
1091 Historically, the kernel has used strongly ordered mappings to
1092 provide DMA coherent memory. With the advent of ARMv7, mapping
1093 memory with differing types results in unpredictable behaviour,
1094 so on these CPUs, this option is forced on.
1095
1096 Multiple mappings with differing attributes is also unpredictable
1097 on ARMv6 CPUs, but since they do not have aggressive speculative
1098 prefetch, no harm appears to occur.
1099
1100 However, drivers may be missing the necessary barriers for ARMv6,
1101 and therefore turning this on may result in unpredictable driver
1102 behaviour. Therefore, we offer this as an option.
1103
1104 On some of the beefier ARMv7-M machines (with DMA and write
1105 buffers) you likely want this enabled, while those that
1106 didn't need it until now also won't need it in the future.
1107
1108 You are recommended say 'Y' here and debug any affected drivers.
1109
1110config ARM_HEAVY_MB
1111 bool
1112
1113config ARCH_SUPPORTS_BIG_ENDIAN
1114 bool
1115 help
1116 This option specifies the architecture can support big endian
1117 operation.
1118
1119config DEBUG_ALIGN_RODATA
1120 bool "Make rodata strictly non-executable"
1121 depends on STRICT_KERNEL_RWX
1122 default y
1123 help
1124 If this is set, rodata will be made explicitly non-executable. This
1125 provides protection on the rare chance that attackers might find and
1126 use ROP gadgets that exist in the rodata section. This adds an
1127 additional section-aligned split of rodata from kernel text so it
1128 can be made explicitly non-executable. This padding may waste memory
1129 space to gain the additional protection.