1/*
 2 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 3 *
 4 * This program is free software; you can redistribute it and/or modify it
 5 * under the terms and conditions of the GNU General Public License,
 6 * version 2, as published by the Free Software Foundation.
 7 *
 8 * This program is distributed in the hope it will be useful, but WITHOUT
 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#ifndef __SOC_TEGRA_FUSE_H__
18#define __SOC_TEGRA_FUSE_H__
19
20#define TEGRA20		0x20
21#define TEGRA30		0x30
22#define TEGRA114	0x35
23#define TEGRA124	0x40
24#define TEGRA132	0x13
25#define TEGRA210	0x21
26
27#define TEGRA_FUSE_SKU_CALIB_0	0xf0
28#define TEGRA30_FUSE_SATA_CALIB	0x124
29
30#ifndef __ASSEMBLY__
31
32u32 tegra_read_chipid(void);
33u8 tegra_get_chip_id(void);
34
35enum tegra_revision {
36	TEGRA_REVISION_UNKNOWN = 0,
37	TEGRA_REVISION_A01,
38	TEGRA_REVISION_A02,
39	TEGRA_REVISION_A03,
40	TEGRA_REVISION_A03p,
41	TEGRA_REVISION_A04,
42	TEGRA_REVISION_MAX,
43};
44
45struct tegra_sku_info {
46	int sku_id;
47	int cpu_process_id;
48	int cpu_speedo_id;
49	int cpu_speedo_value;
50	int cpu_iddq_value;
51	int soc_process_id;
52	int soc_speedo_id;
53	int soc_speedo_value;
54	int gpu_process_id;
55	int gpu_speedo_id;
56	int gpu_speedo_value;
57	enum tegra_revision revision;
58};
59
60u32 tegra_read_straps(void);
61u32 tegra_read_ram_code(void);
62u32 tegra_read_chipid(void);
63int tegra_fuse_readl(unsigned long offset, u32 *value);
64
65extern struct tegra_sku_info tegra_sku_info;
66
67#endif /* __ASSEMBLY__ */
68
69#endif /* __SOC_TEGRA_FUSE_H__ */