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1/*
2 * MediaTek xHCI Host Controller Driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author:
6 * Chunfeng Yun <chunfeng.yun@mediatek.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/iopoll.h>
22#include <linux/kernel.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/phy/phy.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/regmap.h>
30#include <linux/regulator/consumer.h>
31
32#include "xhci.h"
33#include "xhci-mtk.h"
34
35/* ip_pw_ctrl0 register */
36#define CTRL0_IP_SW_RST BIT(0)
37
38/* ip_pw_ctrl1 register */
39#define CTRL1_IP_HOST_PDN BIT(0)
40
41/* ip_pw_ctrl2 register */
42#define CTRL2_IP_DEV_PDN BIT(0)
43
44/* ip_pw_sts1 register */
45#define STS1_IP_SLEEP_STS BIT(30)
46#define STS1_XHCI_RST BIT(11)
47#define STS1_SYS125_RST BIT(10)
48#define STS1_REF_RST BIT(8)
49#define STS1_SYSPLL_STABLE BIT(0)
50
51/* ip_xhci_cap register */
52#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
53#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
54
55/* u3_ctrl_p register */
56#define CTRL_U3_PORT_HOST_SEL BIT(2)
57#define CTRL_U3_PORT_PDN BIT(1)
58#define CTRL_U3_PORT_DIS BIT(0)
59
60/* u2_ctrl_p register */
61#define CTRL_U2_PORT_HOST_SEL BIT(2)
62#define CTRL_U2_PORT_PDN BIT(1)
63#define CTRL_U2_PORT_DIS BIT(0)
64
65/* u2_phy_pll register */
66#define CTRL_U2_FORCE_PLL_STB BIT(28)
67
68#define PERI_WK_CTRL0 0x400
69#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
70#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
71#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
72#define UWK_CTL1_1P_LS_E BIT(0)
73
74#define PERI_WK_CTRL1 0x404
75#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
76#define UWK_CTL1_IS_E BIT(25)
77#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
78#define UWK_CTL1_0P_LS_E BIT(20)
79#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
80#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
81#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
82#define UWK_CTL1_0P_LS_P BIT(7)
83#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
84
85enum ssusb_wakeup_src {
86 SSUSB_WK_IP_SLEEP = 1,
87 SSUSB_WK_LINE_STATE = 2,
88};
89
90static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
91{
92 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
93 u32 value, check_val;
94 int ret;
95 int i;
96
97 /* power on host ip */
98 value = readl(&ippc->ip_pw_ctr1);
99 value &= ~CTRL1_IP_HOST_PDN;
100 writel(value, &ippc->ip_pw_ctr1);
101
102 /* power on and enable all u3 ports */
103 for (i = 0; i < mtk->num_u3_ports; i++) {
104 value = readl(&ippc->u3_ctrl_p[i]);
105 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
106 value |= CTRL_U3_PORT_HOST_SEL;
107 writel(value, &ippc->u3_ctrl_p[i]);
108 }
109
110 /* power on and enable all u2 ports */
111 for (i = 0; i < mtk->num_u2_ports; i++) {
112 value = readl(&ippc->u2_ctrl_p[i]);
113 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
114 value |= CTRL_U2_PORT_HOST_SEL;
115 writel(value, &ippc->u2_ctrl_p[i]);
116 }
117
118 /*
119 * wait for clocks to be stable, and clock domains reset to
120 * be inactive after power on and enable ports
121 */
122 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
123 STS1_SYS125_RST | STS1_XHCI_RST;
124
125 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
126 (check_val == (value & check_val)), 100, 20000);
127 if (ret) {
128 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
129 return ret;
130 }
131
132 return 0;
133}
134
135static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
136{
137 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
138 u32 value;
139 int ret;
140 int i;
141
142 /* power down all u3 ports */
143 for (i = 0; i < mtk->num_u3_ports; i++) {
144 value = readl(&ippc->u3_ctrl_p[i]);
145 value |= CTRL_U3_PORT_PDN;
146 writel(value, &ippc->u3_ctrl_p[i]);
147 }
148
149 /* power down all u2 ports */
150 for (i = 0; i < mtk->num_u2_ports; i++) {
151 value = readl(&ippc->u2_ctrl_p[i]);
152 value |= CTRL_U2_PORT_PDN;
153 writel(value, &ippc->u2_ctrl_p[i]);
154 }
155
156 /* power down host ip */
157 value = readl(&ippc->ip_pw_ctr1);
158 value |= CTRL1_IP_HOST_PDN;
159 writel(value, &ippc->ip_pw_ctr1);
160
161 /* wait for host ip to sleep */
162 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
163 (value & STS1_IP_SLEEP_STS), 100, 100000);
164 if (ret) {
165 dev_err(mtk->dev, "ip sleep failed!!!\n");
166 return ret;
167 }
168 return 0;
169}
170
171static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
172{
173 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
174 u32 value;
175
176 /* reset whole ip */
177 value = readl(&ippc->ip_pw_ctr0);
178 value |= CTRL0_IP_SW_RST;
179 writel(value, &ippc->ip_pw_ctr0);
180 udelay(1);
181 value = readl(&ippc->ip_pw_ctr0);
182 value &= ~CTRL0_IP_SW_RST;
183 writel(value, &ippc->ip_pw_ctr0);
184
185 /*
186 * device ip is default power-on in fact
187 * power down device ip, otherwise ip-sleep will fail
188 */
189 value = readl(&ippc->ip_pw_ctr2);
190 value |= CTRL2_IP_DEV_PDN;
191 writel(value, &ippc->ip_pw_ctr2);
192
193 value = readl(&ippc->ip_xhci_cap);
194 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
195 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
196 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
197 mtk->num_u2_ports, mtk->num_u3_ports);
198
199 return xhci_mtk_host_enable(mtk);
200}
201
202static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
203{
204 int ret;
205
206 ret = clk_prepare_enable(mtk->sys_clk);
207 if (ret) {
208 dev_err(mtk->dev, "failed to enable sys_clk\n");
209 goto sys_clk_err;
210 }
211
212 if (mtk->wakeup_src) {
213 ret = clk_prepare_enable(mtk->wk_deb_p0);
214 if (ret) {
215 dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
216 goto usb_p0_err;
217 }
218
219 ret = clk_prepare_enable(mtk->wk_deb_p1);
220 if (ret) {
221 dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
222 goto usb_p1_err;
223 }
224 }
225 return 0;
226
227usb_p1_err:
228 clk_disable_unprepare(mtk->wk_deb_p0);
229usb_p0_err:
230 clk_disable_unprepare(mtk->sys_clk);
231sys_clk_err:
232 return -EINVAL;
233}
234
235static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
236{
237 if (mtk->wakeup_src) {
238 clk_disable_unprepare(mtk->wk_deb_p1);
239 clk_disable_unprepare(mtk->wk_deb_p0);
240 }
241 clk_disable_unprepare(mtk->sys_clk);
242}
243
244/* only clocks can be turn off for ip-sleep wakeup mode */
245static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
246{
247 u32 tmp;
248 struct regmap *pericfg = mtk->pericfg;
249
250 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
251 tmp &= ~UWK_CTL1_IS_P;
252 tmp &= ~(UWK_CTL1_IS_C(0xf));
253 tmp |= UWK_CTL1_IS_C(0x8);
254 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
255 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
256
257 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
258 dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
259 __func__, tmp);
260}
261
262static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
263{
264 u32 tmp;
265
266 regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
267 tmp &= ~UWK_CTL1_IS_E;
268 regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
269}
270
271/*
272* for line-state wakeup mode, phy's power should not power-down
273* and only support cable plug in/out
274*/
275static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
276{
277 u32 tmp;
278 struct regmap *pericfg = mtk->pericfg;
279
280 /* line-state of u2-port0 */
281 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
282 tmp &= ~UWK_CTL1_0P_LS_P;
283 tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
284 tmp |= UWK_CTL1_0P_LS_C(0x8);
285 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
286 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
287 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
288
289 /* line-state of u2-port1 */
290 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
291 tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
292 tmp |= UWK_CTL1_1P_LS_C(0x8);
293 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
294 regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
295}
296
297static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
298{
299 u32 tmp;
300 struct regmap *pericfg = mtk->pericfg;
301
302 /* line-state of u2-port0 */
303 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
304 tmp &= ~UWK_CTL1_0P_LS_E;
305 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
306
307 /* line-state of u2-port1 */
308 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
309 tmp &= ~UWK_CTL1_1P_LS_E;
310 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
311}
312
313static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
314{
315 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
316 usb_wakeup_ip_sleep_en(mtk);
317 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
318 usb_wakeup_line_state_en(mtk);
319}
320
321static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
322{
323 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
324 usb_wakeup_ip_sleep_dis(mtk);
325 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
326 usb_wakeup_line_state_dis(mtk);
327}
328
329static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
330 struct device_node *dn)
331{
332 struct device *dev = mtk->dev;
333
334 /*
335 * wakeup function is optional, so it is not an error if this property
336 * does not exist, and in such case, no need to get relative
337 * properties anymore.
338 */
339 of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
340 if (!mtk->wakeup_src)
341 return 0;
342
343 mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
344 if (IS_ERR(mtk->wk_deb_p0)) {
345 dev_err(dev, "fail to get wakeup_deb_p0\n");
346 return PTR_ERR(mtk->wk_deb_p0);
347 }
348
349 mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
350 if (IS_ERR(mtk->wk_deb_p1)) {
351 dev_err(dev, "fail to get wakeup_deb_p1\n");
352 return PTR_ERR(mtk->wk_deb_p1);
353 }
354
355 mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
356 "mediatek,syscon-wakeup");
357 if (IS_ERR(mtk->pericfg)) {
358 dev_err(dev, "fail to get pericfg regs\n");
359 return PTR_ERR(mtk->pericfg);
360 }
361
362 return 0;
363}
364
365static int xhci_mtk_setup(struct usb_hcd *hcd);
366static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
367 .extra_priv_size = sizeof(struct xhci_hcd),
368 .reset = xhci_mtk_setup,
369};
370
371static struct hc_driver __read_mostly xhci_mtk_hc_driver;
372
373static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
374{
375 int i;
376 int ret;
377
378 for (i = 0; i < mtk->num_phys; i++) {
379 ret = phy_init(mtk->phys[i]);
380 if (ret)
381 goto exit_phy;
382 }
383 return 0;
384
385exit_phy:
386 for (; i > 0; i--)
387 phy_exit(mtk->phys[i - 1]);
388
389 return ret;
390}
391
392static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
393{
394 int i;
395
396 for (i = 0; i < mtk->num_phys; i++)
397 phy_exit(mtk->phys[i]);
398
399 return 0;
400}
401
402static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
403{
404 int i;
405 int ret;
406
407 for (i = 0; i < mtk->num_phys; i++) {
408 ret = phy_power_on(mtk->phys[i]);
409 if (ret)
410 goto power_off_phy;
411 }
412 return 0;
413
414power_off_phy:
415 for (; i > 0; i--)
416 phy_power_off(mtk->phys[i - 1]);
417
418 return ret;
419}
420
421static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
422{
423 unsigned int i;
424
425 for (i = 0; i < mtk->num_phys; i++)
426 phy_power_off(mtk->phys[i]);
427}
428
429static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
430{
431 int ret;
432
433 ret = regulator_enable(mtk->vbus);
434 if (ret) {
435 dev_err(mtk->dev, "failed to enable vbus\n");
436 return ret;
437 }
438
439 ret = regulator_enable(mtk->vusb33);
440 if (ret) {
441 dev_err(mtk->dev, "failed to enable vusb33\n");
442 regulator_disable(mtk->vbus);
443 return ret;
444 }
445 return 0;
446}
447
448static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
449{
450 regulator_disable(mtk->vbus);
451 regulator_disable(mtk->vusb33);
452}
453
454static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
455{
456 struct usb_hcd *hcd = xhci_to_hcd(xhci);
457 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
458
459 /*
460 * As of now platform drivers don't provide MSI support so we ensure
461 * here that the generic code does not try to make a pci_dev from our
462 * dev struct in order to setup MSI
463 */
464 xhci->quirks |= XHCI_PLAT;
465 xhci->quirks |= XHCI_MTK_HOST;
466 /*
467 * MTK host controller gives a spurious successful event after a
468 * short transfer. Ignore it.
469 */
470 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
471 if (mtk->lpm_support)
472 xhci->quirks |= XHCI_LPM_SUPPORT;
473}
474
475/* called during probe() after chip reset completes */
476static int xhci_mtk_setup(struct usb_hcd *hcd)
477{
478 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
479 int ret;
480
481 if (usb_hcd_is_primary_hcd(hcd)) {
482 ret = xhci_mtk_ssusb_config(mtk);
483 if (ret)
484 return ret;
485 ret = xhci_mtk_sch_init(mtk);
486 if (ret)
487 return ret;
488 }
489
490 return xhci_gen_setup(hcd, xhci_mtk_quirks);
491}
492
493static int xhci_mtk_probe(struct platform_device *pdev)
494{
495 struct device *dev = &pdev->dev;
496 struct device_node *node = dev->of_node;
497 struct xhci_hcd_mtk *mtk;
498 const struct hc_driver *driver;
499 struct xhci_hcd *xhci;
500 struct resource *res;
501 struct usb_hcd *hcd;
502 struct phy *phy;
503 int phy_num;
504 int ret = -ENODEV;
505 int irq;
506
507 if (usb_disabled())
508 return -ENODEV;
509
510 driver = &xhci_mtk_hc_driver;
511 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
512 if (!mtk)
513 return -ENOMEM;
514
515 mtk->dev = dev;
516 mtk->vbus = devm_regulator_get(dev, "vbus");
517 if (IS_ERR(mtk->vbus)) {
518 dev_err(dev, "fail to get vbus\n");
519 return PTR_ERR(mtk->vbus);
520 }
521
522 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
523 if (IS_ERR(mtk->vusb33)) {
524 dev_err(dev, "fail to get vusb33\n");
525 return PTR_ERR(mtk->vusb33);
526 }
527
528 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
529 if (IS_ERR(mtk->sys_clk)) {
530 dev_err(dev, "fail to get sys_ck\n");
531 return PTR_ERR(mtk->sys_clk);
532 }
533
534 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
535
536 ret = usb_wakeup_of_property_parse(mtk, node);
537 if (ret)
538 return ret;
539
540 mtk->num_phys = of_count_phandle_with_args(node,
541 "phys", "#phy-cells");
542 if (mtk->num_phys > 0) {
543 mtk->phys = devm_kcalloc(dev, mtk->num_phys,
544 sizeof(*mtk->phys), GFP_KERNEL);
545 if (!mtk->phys)
546 return -ENOMEM;
547 } else {
548 mtk->num_phys = 0;
549 }
550 pm_runtime_enable(dev);
551 pm_runtime_get_sync(dev);
552 device_enable_async_suspend(dev);
553
554 ret = xhci_mtk_ldos_enable(mtk);
555 if (ret)
556 goto disable_pm;
557
558 ret = xhci_mtk_clks_enable(mtk);
559 if (ret)
560 goto disable_ldos;
561
562 irq = platform_get_irq(pdev, 0);
563 if (irq < 0)
564 goto disable_clk;
565
566 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
567 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
568 if (ret)
569 goto disable_clk;
570
571 if (!dev->dma_mask)
572 dev->dma_mask = &dev->coherent_dma_mask;
573 else
574 dma_set_mask(dev, DMA_BIT_MASK(32));
575
576 hcd = usb_create_hcd(driver, dev, dev_name(dev));
577 if (!hcd) {
578 ret = -ENOMEM;
579 goto disable_clk;
580 }
581
582 /*
583 * USB 2.0 roothub is stored in the platform_device.
584 * Swap it with mtk HCD.
585 */
586 mtk->hcd = platform_get_drvdata(pdev);
587 platform_set_drvdata(pdev, mtk);
588
589 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
590 hcd->regs = devm_ioremap_resource(dev, res);
591 if (IS_ERR(hcd->regs)) {
592 ret = PTR_ERR(hcd->regs);
593 goto put_usb2_hcd;
594 }
595 hcd->rsrc_start = res->start;
596 hcd->rsrc_len = resource_size(res);
597
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
599 mtk->ippc_regs = devm_ioremap_resource(dev, res);
600 if (IS_ERR(mtk->ippc_regs)) {
601 ret = PTR_ERR(mtk->ippc_regs);
602 goto put_usb2_hcd;
603 }
604
605 for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
606 phy = devm_of_phy_get_by_index(dev, node, phy_num);
607 if (IS_ERR(phy)) {
608 ret = PTR_ERR(phy);
609 goto put_usb2_hcd;
610 }
611 mtk->phys[phy_num] = phy;
612 }
613
614 ret = xhci_mtk_phy_init(mtk);
615 if (ret)
616 goto put_usb2_hcd;
617
618 ret = xhci_mtk_phy_power_on(mtk);
619 if (ret)
620 goto exit_phys;
621
622 device_init_wakeup(dev, true);
623
624 xhci = hcd_to_xhci(hcd);
625 xhci->main_hcd = hcd;
626 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
627 dev_name(dev), hcd);
628 if (!xhci->shared_hcd) {
629 ret = -ENOMEM;
630 goto power_off_phys;
631 }
632
633 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
634 xhci->shared_hcd->can_do_streams = 1;
635
636 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
637 if (ret)
638 goto put_usb3_hcd;
639
640 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
641 if (ret)
642 goto dealloc_usb2_hcd;
643
644 return 0;
645
646dealloc_usb2_hcd:
647 usb_remove_hcd(hcd);
648
649put_usb3_hcd:
650 xhci_mtk_sch_exit(mtk);
651 usb_put_hcd(xhci->shared_hcd);
652
653power_off_phys:
654 xhci_mtk_phy_power_off(mtk);
655 device_init_wakeup(dev, false);
656
657exit_phys:
658 xhci_mtk_phy_exit(mtk);
659
660put_usb2_hcd:
661 usb_put_hcd(hcd);
662
663disable_clk:
664 xhci_mtk_clks_disable(mtk);
665
666disable_ldos:
667 xhci_mtk_ldos_disable(mtk);
668
669disable_pm:
670 pm_runtime_put_sync(dev);
671 pm_runtime_disable(dev);
672 return ret;
673}
674
675static int xhci_mtk_remove(struct platform_device *dev)
676{
677 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
678 struct usb_hcd *hcd = mtk->hcd;
679 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
680
681 usb_remove_hcd(xhci->shared_hcd);
682 xhci_mtk_phy_power_off(mtk);
683 xhci_mtk_phy_exit(mtk);
684 device_init_wakeup(&dev->dev, false);
685
686 usb_remove_hcd(hcd);
687 usb_put_hcd(xhci->shared_hcd);
688 usb_put_hcd(hcd);
689 xhci_mtk_sch_exit(mtk);
690 xhci_mtk_clks_disable(mtk);
691 xhci_mtk_ldos_disable(mtk);
692 pm_runtime_put_sync(&dev->dev);
693 pm_runtime_disable(&dev->dev);
694
695 return 0;
696}
697
698/*
699 * if ip sleep fails, and all clocks are disabled, access register will hang
700 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
701 * and no need to check whether ip sleep failed or not; this will cause SPM
702 * to wake up system immediately after system suspend complete if ip sleep
703 * fails, it is what we wanted.
704 */
705static int __maybe_unused xhci_mtk_suspend(struct device *dev)
706{
707 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
708 struct usb_hcd *hcd = mtk->hcd;
709 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
710
711 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
712 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
713 del_timer_sync(&hcd->rh_timer);
714 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
715 del_timer_sync(&xhci->shared_hcd->rh_timer);
716
717 xhci_mtk_host_disable(mtk);
718 xhci_mtk_phy_power_off(mtk);
719 xhci_mtk_clks_disable(mtk);
720 usb_wakeup_enable(mtk);
721 return 0;
722}
723
724static int __maybe_unused xhci_mtk_resume(struct device *dev)
725{
726 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
727 struct usb_hcd *hcd = mtk->hcd;
728 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
729
730 usb_wakeup_disable(mtk);
731 xhci_mtk_clks_enable(mtk);
732 xhci_mtk_phy_power_on(mtk);
733 xhci_mtk_host_enable(mtk);
734
735 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
736 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
737 usb_hcd_poll_rh_status(hcd);
738 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
739 usb_hcd_poll_rh_status(xhci->shared_hcd);
740 return 0;
741}
742
743static const struct dev_pm_ops xhci_mtk_pm_ops = {
744 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
745};
746#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
747
748#ifdef CONFIG_OF
749static const struct of_device_id mtk_xhci_of_match[] = {
750 { .compatible = "mediatek,mt8173-xhci"},
751 { },
752};
753MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
754#endif
755
756static struct platform_driver mtk_xhci_driver = {
757 .probe = xhci_mtk_probe,
758 .remove = xhci_mtk_remove,
759 .driver = {
760 .name = "xhci-mtk",
761 .pm = DEV_PM_OPS,
762 .of_match_table = of_match_ptr(mtk_xhci_of_match),
763 },
764};
765MODULE_ALIAS("platform:xhci-mtk");
766
767static int __init xhci_mtk_init(void)
768{
769 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
770 return platform_driver_register(&mtk_xhci_driver);
771}
772module_init(xhci_mtk_init);
773
774static void __exit xhci_mtk_exit(void)
775{
776 platform_driver_unregister(&mtk_xhci_driver);
777}
778module_exit(xhci_mtk_exit);
779
780MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
781MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
782MODULE_LICENSE("GPL v2");