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1/*
2 * Xilinx PS UART driver
3 *
4 * 2011 (c) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 */
13
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/console.h>
17#include <linux/serial.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/of.h>
21
22#define XUARTPS_TTY_NAME "ttyPS"
23#define XUARTPS_NAME "xuartps"
24#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
25#define XUARTPS_MINOR 0 /* works best with devtmpfs */
26#define XUARTPS_NR_PORTS 2
27#define XUARTPS_FIFO_SIZE 16 /* FIFO size */
28#define XUARTPS_REGISTER_SPACE 0xFFF
29
30#define xuartps_readl(offset) ioread32(port->membase + offset)
31#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
32
33/********************************Register Map********************************/
34/** UART
35 *
36 * Register offsets for the UART.
37 *
38 */
39#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
40#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
41#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
42#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
43#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
44#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
45#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
46#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
47#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
48#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
49#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
50#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
51#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
52#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
53#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
54#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
55 Width [15:0] */
56#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
57 Width [7:0] */
58#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
59
60/** Control Register
61 *
62 * The Control register (CR) controls the major functions of the device.
63 *
64 * Control Register Bit Definitions
65 */
66#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
67#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
68#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
69#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
70#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
71#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
72#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
73#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
74#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
75
76/** Mode Register
77 *
78 * The mode register (MR) defines the mode of transfer as well as the data
79 * format. If this register is modified during transmission or reception,
80 * data validity cannot be guaranteed.
81 *
82 * Mode Register Bit Definitions
83 *
84 */
85#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
86#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
87#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
88
89#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
90#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
91
92#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
93#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
94#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
95#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
96#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
97
98#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
99#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
100#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
101
102/** Interrupt Registers
103 *
104 * Interrupt control logic uses the interrupt enable register (IER) and the
105 * interrupt disable register (IDR) to set the value of the bits in the
106 * interrupt mask register (IMR). The IMR determines whether to pass an
107 * interrupt to the interrupt status register (ISR).
108 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
109 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
110 * Reading either IER or IDR returns 0x00.
111 *
112 * All four registers have the same bit definitions.
113 */
114#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
115#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
116#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
117#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
118#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
119#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
120#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
121#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
122#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
123#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
124#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
125
126/** Channel Status Register
127 *
128 * The channel status register (CSR) is provided to enable the control logic
129 * to monitor the status of bits in the channel interrupt status register,
130 * even if these are masked out by the interrupt mask register.
131 */
132#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
133#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
134#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
135#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
136
137/**
138 * xuartps_isr - Interrupt handler
139 * @irq: Irq number
140 * @dev_id: Id of the port
141 *
142 * Returns IRQHANDLED
143 **/
144static irqreturn_t xuartps_isr(int irq, void *dev_id)
145{
146 struct uart_port *port = (struct uart_port *)dev_id;
147 struct tty_struct *tty;
148 unsigned long flags;
149 unsigned int isrstatus, numbytes;
150 unsigned int data;
151 char status = TTY_NORMAL;
152
153 /* Get the tty which could be NULL so don't assume it's valid */
154 tty = tty_port_tty_get(&port->state->port);
155
156 spin_lock_irqsave(&port->lock, flags);
157
158 /* Read the interrupt status register to determine which
159 * interrupt(s) is/are active.
160 */
161 isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
162
163 /* drop byte with parity error if IGNPAR specified */
164 if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
165 isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
166
167 isrstatus &= port->read_status_mask;
168 isrstatus &= ~port->ignore_status_mask;
169
170 if ((isrstatus & XUARTPS_IXR_TOUT) ||
171 (isrstatus & XUARTPS_IXR_RXTRIG)) {
172 /* Receive Timeout Interrupt */
173 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
174 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
175 data = xuartps_readl(XUARTPS_FIFO_OFFSET);
176 port->icount.rx++;
177
178 if (isrstatus & XUARTPS_IXR_PARITY) {
179 port->icount.parity++;
180 status = TTY_PARITY;
181 } else if (isrstatus & XUARTPS_IXR_FRAMING) {
182 port->icount.frame++;
183 status = TTY_FRAME;
184 } else if (isrstatus & XUARTPS_IXR_OVERRUN)
185 port->icount.overrun++;
186
187 if (tty)
188 uart_insert_char(port, isrstatus,
189 XUARTPS_IXR_OVERRUN, data,
190 status);
191 }
192 spin_unlock(&port->lock);
193 if (tty)
194 tty_flip_buffer_push(tty);
195 spin_lock(&port->lock);
196 }
197
198 /* Dispatch an appropriate handler */
199 if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
200 if (uart_circ_empty(&port->state->xmit)) {
201 xuartps_writel(XUARTPS_IXR_TXEMPTY,
202 XUARTPS_IDR_OFFSET);
203 } else {
204 numbytes = port->fifosize;
205 /* Break if no more data available in the UART buffer */
206 while (numbytes--) {
207 if (uart_circ_empty(&port->state->xmit))
208 break;
209 /* Get the data from the UART circular buffer
210 * and write it to the xuartps's TX_FIFO
211 * register.
212 */
213 xuartps_writel(
214 port->state->xmit.buf[port->state->xmit.
215 tail], XUARTPS_FIFO_OFFSET);
216
217 port->icount.tx++;
218
219 /* Adjust the tail of the UART buffer and wrap
220 * the buffer if it reaches limit.
221 */
222 port->state->xmit.tail =
223 (port->state->xmit.tail + 1) & \
224 (UART_XMIT_SIZE - 1);
225 }
226
227 if (uart_circ_chars_pending(
228 &port->state->xmit) < WAKEUP_CHARS)
229 uart_write_wakeup(port);
230 }
231 }
232
233 xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
234
235 /* be sure to release the lock and tty before leaving */
236 spin_unlock_irqrestore(&port->lock, flags);
237 tty_kref_put(tty);
238
239 return IRQ_HANDLED;
240}
241
242/**
243 * xuartps_set_baud_rate - Calculate and set the baud rate
244 * @port: Handle to the uart port structure
245 * @baud: Baud rate to set
246 *
247 * Returns baud rate, requested baud when possible, or actual baud when there
248 * was too much error
249 **/
250static unsigned int xuartps_set_baud_rate(struct uart_port *port,
251 unsigned int baud)
252{
253 unsigned int sel_clk;
254 unsigned int calc_baud = 0;
255 unsigned int brgr_val, brdiv_val;
256 unsigned int bauderror;
257
258 /* Formula to obtain baud rate is
259 * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
260 * input_clk = (Uart User Defined Clock or Apb Clock)
261 * depends on UCLKEN in MR Reg
262 * sel_clk = input_clk or input_clk/8;
263 * depends on CLKS in MR reg
264 * CD and BDIV depends on values in
265 * baud rate generate register
266 * baud rate clock divisor register
267 */
268 sel_clk = port->uartclk;
269 if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
270 sel_clk = sel_clk / 8;
271
272 /* Find the best values for baud generation */
273 for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
274
275 brgr_val = sel_clk / (baud * (brdiv_val + 1));
276 if (brgr_val < 2 || brgr_val > 65535)
277 continue;
278
279 calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
280
281 if (baud > calc_baud)
282 bauderror = baud - calc_baud;
283 else
284 bauderror = calc_baud - baud;
285
286 /* use the values when percent error is acceptable */
287 if (((bauderror * 100) / baud) < 3) {
288 calc_baud = baud;
289 break;
290 }
291 }
292
293 /* Set the values for the new baud rate */
294 xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
295 xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
296
297 return calc_baud;
298}
299
300/*----------------------Uart Operations---------------------------*/
301
302/**
303 * xuartps_start_tx - Start transmitting bytes
304 * @port: Handle to the uart port structure
305 *
306 **/
307static void xuartps_start_tx(struct uart_port *port)
308{
309 unsigned int status, numbytes = port->fifosize;
310
311 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
312 return;
313
314 status = xuartps_readl(XUARTPS_CR_OFFSET);
315 /* Set the TX enable bit and clear the TX disable bit to enable the
316 * transmitter.
317 */
318 xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
319 XUARTPS_CR_OFFSET);
320
321 while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
322 & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
323
324 /* Break if no more data available in the UART buffer */
325 if (uart_circ_empty(&port->state->xmit))
326 break;
327
328 /* Get the data from the UART circular buffer and
329 * write it to the xuartps's TX_FIFO register.
330 */
331 xuartps_writel(
332 port->state->xmit.buf[port->state->xmit.tail],
333 XUARTPS_FIFO_OFFSET);
334 port->icount.tx++;
335
336 /* Adjust the tail of the UART buffer and wrap
337 * the buffer if it reaches limit.
338 */
339 port->state->xmit.tail = (port->state->xmit.tail + 1) &
340 (UART_XMIT_SIZE - 1);
341 }
342
343 /* Enable the TX Empty interrupt */
344 xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
345
346 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
347 uart_write_wakeup(port);
348}
349
350/**
351 * xuartps_stop_tx - Stop TX
352 * @port: Handle to the uart port structure
353 *
354 **/
355static void xuartps_stop_tx(struct uart_port *port)
356{
357 unsigned int regval;
358
359 regval = xuartps_readl(XUARTPS_CR_OFFSET);
360 regval |= XUARTPS_CR_TX_DIS;
361 /* Disable the transmitter */
362 xuartps_writel(regval, XUARTPS_CR_OFFSET);
363}
364
365/**
366 * xuartps_stop_rx - Stop RX
367 * @port: Handle to the uart port structure
368 *
369 **/
370static void xuartps_stop_rx(struct uart_port *port)
371{
372 unsigned int regval;
373
374 regval = xuartps_readl(XUARTPS_CR_OFFSET);
375 regval |= XUARTPS_CR_RX_DIS;
376 /* Disable the receiver */
377 xuartps_writel(regval, XUARTPS_CR_OFFSET);
378}
379
380/**
381 * xuartps_tx_empty - Check whether TX is empty
382 * @port: Handle to the uart port structure
383 *
384 * Returns TIOCSER_TEMT on success, 0 otherwise
385 **/
386static unsigned int xuartps_tx_empty(struct uart_port *port)
387{
388 unsigned int status;
389
390 status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
391 return status ? TIOCSER_TEMT : 0;
392}
393
394/**
395 * xuartps_break_ctl - Based on the input ctl we have to start or stop
396 * transmitting char breaks
397 * @port: Handle to the uart port structure
398 * @ctl: Value based on which start or stop decision is taken
399 *
400 **/
401static void xuartps_break_ctl(struct uart_port *port, int ctl)
402{
403 unsigned int status;
404 unsigned long flags;
405
406 spin_lock_irqsave(&port->lock, flags);
407
408 status = xuartps_readl(XUARTPS_CR_OFFSET);
409
410 if (ctl == -1)
411 xuartps_writel(XUARTPS_CR_STARTBRK | status,
412 XUARTPS_CR_OFFSET);
413 else {
414 if ((status & XUARTPS_CR_STOPBRK) == 0)
415 xuartps_writel(XUARTPS_CR_STOPBRK | status,
416 XUARTPS_CR_OFFSET);
417 }
418 spin_unlock_irqrestore(&port->lock, flags);
419}
420
421/**
422 * xuartps_set_termios - termios operations, handling data length, parity,
423 * stop bits, flow control, baud rate
424 * @port: Handle to the uart port structure
425 * @termios: Handle to the input termios structure
426 * @old: Values of the previously saved termios structure
427 *
428 **/
429static void xuartps_set_termios(struct uart_port *port,
430 struct ktermios *termios, struct ktermios *old)
431{
432 unsigned int cval = 0;
433 unsigned int baud;
434 unsigned long flags;
435 unsigned int ctrl_reg, mode_reg;
436
437 spin_lock_irqsave(&port->lock, flags);
438
439 /* Empty the receive FIFO 1st before making changes */
440 while ((xuartps_readl(XUARTPS_SR_OFFSET) &
441 XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
442 xuartps_readl(XUARTPS_FIFO_OFFSET);
443 }
444
445 /* Disable the TX and RX to set baud rate */
446 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
447 (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
448 XUARTPS_CR_OFFSET);
449
450 /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
451 baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
452 baud = xuartps_set_baud_rate(port, baud);
453 if (tty_termios_baud_rate(termios))
454 tty_termios_encode_baud_rate(termios, baud, baud);
455
456 /*
457 * Update the per-port timeout.
458 */
459 uart_update_timeout(port, termios->c_cflag, baud);
460
461 /* Set TX/RX Reset */
462 xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
463 (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
464 XUARTPS_CR_OFFSET);
465
466 ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
467
468 /* Clear the RX disable and TX disable bits and then set the TX enable
469 * bit and RX enable bit to enable the transmitter and receiver.
470 */
471 xuartps_writel(
472 (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
473 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
474 XUARTPS_CR_OFFSET);
475
476 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
477
478 port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
479 XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
480 port->ignore_status_mask = 0;
481
482 if (termios->c_iflag & INPCK)
483 port->read_status_mask |= XUARTPS_IXR_PARITY |
484 XUARTPS_IXR_FRAMING;
485
486 if (termios->c_iflag & IGNPAR)
487 port->ignore_status_mask |= XUARTPS_IXR_PARITY |
488 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
489
490 /* ignore all characters if CREAD is not set */
491 if ((termios->c_cflag & CREAD) == 0)
492 port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
493 XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
494 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
495
496 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
497
498 /* Handling Data Size */
499 switch (termios->c_cflag & CSIZE) {
500 case CS6:
501 cval |= XUARTPS_MR_CHARLEN_6_BIT;
502 break;
503 case CS7:
504 cval |= XUARTPS_MR_CHARLEN_7_BIT;
505 break;
506 default:
507 case CS8:
508 cval |= XUARTPS_MR_CHARLEN_8_BIT;
509 termios->c_cflag &= ~CSIZE;
510 termios->c_cflag |= CS8;
511 break;
512 }
513
514 /* Handling Parity and Stop Bits length */
515 if (termios->c_cflag & CSTOPB)
516 cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
517 else
518 cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
519
520 if (termios->c_cflag & PARENB) {
521 /* Mark or Space parity */
522 if (termios->c_cflag & CMSPAR) {
523 if (termios->c_cflag & PARODD)
524 cval |= XUARTPS_MR_PARITY_MARK;
525 else
526 cval |= XUARTPS_MR_PARITY_SPACE;
527 } else if (termios->c_cflag & PARODD)
528 cval |= XUARTPS_MR_PARITY_ODD;
529 else
530 cval |= XUARTPS_MR_PARITY_EVEN;
531 } else
532 cval |= XUARTPS_MR_PARITY_NONE;
533 xuartps_writel(cval , XUARTPS_MR_OFFSET);
534
535 spin_unlock_irqrestore(&port->lock, flags);
536}
537
538/**
539 * xuartps_startup - Called when an application opens a xuartps port
540 * @port: Handle to the uart port structure
541 *
542 * Returns 0 on success, negative error otherwise
543 **/
544static int xuartps_startup(struct uart_port *port)
545{
546 unsigned int retval = 0, status = 0;
547
548 retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
549 (void *)port);
550 if (retval)
551 return retval;
552
553 /* Disable the TX and RX */
554 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
555 XUARTPS_CR_OFFSET);
556
557 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
558 * no break chars.
559 */
560 xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
561 XUARTPS_CR_OFFSET);
562
563 status = xuartps_readl(XUARTPS_CR_OFFSET);
564
565 /* Clear the RX disable and TX disable bits and then set the TX enable
566 * bit and RX enable bit to enable the transmitter and receiver.
567 */
568 xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
569 | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
570 XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
571
572 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
573 * no parity.
574 */
575 xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
576 | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
577 XUARTPS_MR_OFFSET);
578
579 /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
580 xuartps_writel(14, XUARTPS_RXWM_OFFSET);
581
582 /* Receive Timeout register is enabled with value of 10 */
583 xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
584
585
586 /* Set the Interrupt Registers with desired interrupts */
587 xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
588 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
589 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
590 xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
591 XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
592 XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET);
593
594 return retval;
595}
596
597/**
598 * xuartps_shutdown - Called when an application closes a xuartps port
599 * @port: Handle to the uart port structure
600 *
601 **/
602static void xuartps_shutdown(struct uart_port *port)
603{
604 int status;
605
606 /* Disable interrupts */
607 status = xuartps_readl(XUARTPS_IMR_OFFSET);
608 xuartps_writel(status, XUARTPS_IDR_OFFSET);
609
610 /* Disable the TX and RX */
611 xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
612 XUARTPS_CR_OFFSET);
613 free_irq(port->irq, port);
614}
615
616/**
617 * xuartps_type - Set UART type to xuartps port
618 * @port: Handle to the uart port structure
619 *
620 * Returns string on success, NULL otherwise
621 **/
622static const char *xuartps_type(struct uart_port *port)
623{
624 return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
625}
626
627/**
628 * xuartps_verify_port - Verify the port params
629 * @port: Handle to the uart port structure
630 * @ser: Handle to the structure whose members are compared
631 *
632 * Returns 0 if success otherwise -EINVAL
633 **/
634static int xuartps_verify_port(struct uart_port *port,
635 struct serial_struct *ser)
636{
637 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
638 return -EINVAL;
639 if (port->irq != ser->irq)
640 return -EINVAL;
641 if (ser->io_type != UPIO_MEM)
642 return -EINVAL;
643 if (port->iobase != ser->port)
644 return -EINVAL;
645 if (ser->hub6 != 0)
646 return -EINVAL;
647 return 0;
648}
649
650/**
651 * xuartps_request_port - Claim the memory region attached to xuartps port,
652 * called when the driver adds a xuartps port via
653 * uart_add_one_port()
654 * @port: Handle to the uart port structure
655 *
656 * Returns 0, -ENOMEM if request fails
657 **/
658static int xuartps_request_port(struct uart_port *port)
659{
660 if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
661 XUARTPS_NAME)) {
662 return -ENOMEM;
663 }
664
665 port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
666 if (!port->membase) {
667 dev_err(port->dev, "Unable to map registers\n");
668 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
669 return -ENOMEM;
670 }
671 return 0;
672}
673
674/**
675 * xuartps_release_port - Release the memory region attached to a xuartps
676 * port, called when the driver removes a xuartps
677 * port via uart_remove_one_port().
678 * @port: Handle to the uart port structure
679 *
680 **/
681static void xuartps_release_port(struct uart_port *port)
682{
683 release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
684 iounmap(port->membase);
685 port->membase = NULL;
686}
687
688/**
689 * xuartps_config_port - Configure xuartps, called when the driver adds a
690 * xuartps port
691 * @port: Handle to the uart port structure
692 * @flags: If any
693 *
694 **/
695static void xuartps_config_port(struct uart_port *port, int flags)
696{
697 if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
698 port->type = PORT_XUARTPS;
699}
700
701/**
702 * xuartps_get_mctrl - Get the modem control state
703 *
704 * @port: Handle to the uart port structure
705 *
706 * Returns the modem control state
707 *
708 **/
709static unsigned int xuartps_get_mctrl(struct uart_port *port)
710{
711 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
712}
713
714static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
715{
716 /* N/A */
717}
718
719static void xuartps_enable_ms(struct uart_port *port)
720{
721 /* N/A */
722}
723
724/** The UART operations structure
725 */
726static struct uart_ops xuartps_ops = {
727 .set_mctrl = xuartps_set_mctrl,
728 .get_mctrl = xuartps_get_mctrl,
729 .enable_ms = xuartps_enable_ms,
730
731 .start_tx = xuartps_start_tx, /* Start transmitting */
732 .stop_tx = xuartps_stop_tx, /* Stop transmission */
733 .stop_rx = xuartps_stop_rx, /* Stop reception */
734 .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
735 .break_ctl = xuartps_break_ctl, /* Start/stop
736 * transmitting break
737 */
738 .set_termios = xuartps_set_termios, /* Set termios */
739 .startup = xuartps_startup, /* App opens xuartps */
740 .shutdown = xuartps_shutdown, /* App closes xuartps */
741 .type = xuartps_type, /* Set UART type */
742 .verify_port = xuartps_verify_port, /* Verification of port
743 * params
744 */
745 .request_port = xuartps_request_port, /* Claim resources
746 * associated with a
747 * xuartps port
748 */
749 .release_port = xuartps_release_port, /* Release resources
750 * associated with a
751 * xuartps port
752 */
753 .config_port = xuartps_config_port, /* Configure when driver
754 * adds a xuartps port
755 */
756};
757
758static struct uart_port xuartps_port[2];
759
760/**
761 * xuartps_get_port - Configure the port from the platform device resource
762 * info
763 *
764 * Returns a pointer to a uart_port or NULL for failure
765 **/
766static struct uart_port *xuartps_get_port(void)
767{
768 struct uart_port *port;
769 int id;
770
771 /* Find the next unused port */
772 for (id = 0; id < XUARTPS_NR_PORTS; id++)
773 if (xuartps_port[id].mapbase == 0)
774 break;
775
776 if (id >= XUARTPS_NR_PORTS)
777 return NULL;
778
779 port = &xuartps_port[id];
780
781 /* At this point, we've got an empty uart_port struct, initialize it */
782 spin_lock_init(&port->lock);
783 port->membase = NULL;
784 port->iobase = 1; /* mark port in use */
785 port->irq = 0;
786 port->type = PORT_UNKNOWN;
787 port->iotype = UPIO_MEM32;
788 port->flags = UPF_BOOT_AUTOCONF;
789 port->ops = &xuartps_ops;
790 port->fifosize = XUARTPS_FIFO_SIZE;
791 port->line = id;
792 port->dev = NULL;
793 return port;
794}
795
796/*-----------------------Console driver operations--------------------------*/
797
798#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
799/**
800 * xuartps_console_wait_tx - Wait for the TX to be full
801 * @port: Handle to the uart port structure
802 *
803 **/
804static void xuartps_console_wait_tx(struct uart_port *port)
805{
806 while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
807 != XUARTPS_SR_TXEMPTY)
808 barrier();
809}
810
811/**
812 * xuartps_console_putchar - write the character to the FIFO buffer
813 * @port: Handle to the uart port structure
814 * @ch: Character to be written
815 *
816 **/
817static void xuartps_console_putchar(struct uart_port *port, int ch)
818{
819 xuartps_console_wait_tx(port);
820 xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
821}
822
823/**
824 * xuartps_console_write - perform write operation
825 * @port: Handle to the uart port structure
826 * @s: Pointer to character array
827 * @count: No of characters
828 **/
829static void xuartps_console_write(struct console *co, const char *s,
830 unsigned int count)
831{
832 struct uart_port *port = &xuartps_port[co->index];
833 unsigned long flags;
834 unsigned int imr;
835 int locked = 1;
836
837 if (oops_in_progress)
838 locked = spin_trylock_irqsave(&port->lock, flags);
839 else
840 spin_lock_irqsave(&port->lock, flags);
841
842 /* save and disable interrupt */
843 imr = xuartps_readl(XUARTPS_IMR_OFFSET);
844 xuartps_writel(imr, XUARTPS_IDR_OFFSET);
845
846 uart_console_write(port, s, count, xuartps_console_putchar);
847 xuartps_console_wait_tx(port);
848
849 /* restore interrupt state, it seems like there may be a h/w bug
850 * in that the interrupt enable register should not need to be
851 * written based on the data sheet
852 */
853 xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
854 xuartps_writel(imr, XUARTPS_IER_OFFSET);
855
856 if (locked)
857 spin_unlock_irqrestore(&port->lock, flags);
858}
859
860/**
861 * xuartps_console_setup - Initialize the uart to default config
862 * @co: Console handle
863 * @options: Initial settings of uart
864 *
865 * Returns 0, -ENODEV if no device
866 **/
867static int __init xuartps_console_setup(struct console *co, char *options)
868{
869 struct uart_port *port = &xuartps_port[co->index];
870 int baud = 9600;
871 int bits = 8;
872 int parity = 'n';
873 int flow = 'n';
874
875 if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
876 return -EINVAL;
877
878 if (!port->mapbase) {
879 pr_debug("console on ttyPS%i not present\n", co->index);
880 return -ENODEV;
881 }
882
883 if (options)
884 uart_parse_options(options, &baud, &parity, &bits, &flow);
885
886 return uart_set_options(port, co, baud, parity, bits, flow);
887}
888
889static struct uart_driver xuartps_uart_driver;
890
891static struct console xuartps_console = {
892 .name = XUARTPS_TTY_NAME,
893 .write = xuartps_console_write,
894 .device = uart_console_device,
895 .setup = xuartps_console_setup,
896 .flags = CON_PRINTBUFFER,
897 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
898 .data = &xuartps_uart_driver,
899};
900
901/**
902 * xuartps_console_init - Initialization call
903 *
904 * Returns 0 on success, negative error otherwise
905 **/
906static int __init xuartps_console_init(void)
907{
908 register_console(&xuartps_console);
909 return 0;
910}
911
912console_initcall(xuartps_console_init);
913
914#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
915
916/** Structure Definitions
917 */
918static struct uart_driver xuartps_uart_driver = {
919 .owner = THIS_MODULE, /* Owner */
920 .driver_name = XUARTPS_NAME, /* Driver name */
921 .dev_name = XUARTPS_TTY_NAME, /* Node name */
922 .major = XUARTPS_MAJOR, /* Major number */
923 .minor = XUARTPS_MINOR, /* Minor number */
924 .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
925#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
926 .cons = &xuartps_console, /* Console */
927#endif
928};
929
930/* ---------------------------------------------------------------------
931 * Platform bus binding
932 */
933/**
934 * xuartps_probe - Platform driver probe
935 * @pdev: Pointer to the platform device structure
936 *
937 * Returns 0 on success, negative error otherwise
938 **/
939static int __devinit xuartps_probe(struct platform_device *pdev)
940{
941 int rc;
942 struct uart_port *port;
943 struct resource *res, *res2;
944 int clk = 0;
945
946#ifdef CONFIG_OF
947 const unsigned int *prop;
948
949 prop = of_get_property(pdev->dev.of_node, "clock", NULL);
950 if (prop)
951 clk = be32_to_cpup(prop);
952#else
953 clk = *((unsigned int *)(pdev->dev.platform_data));
954#endif
955 if (!clk) {
956 dev_err(&pdev->dev, "no clock specified\n");
957 return -ENODEV;
958 }
959
960 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
961 if (!res)
962 return -ENODEV;
963
964 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
965 if (!res2)
966 return -ENODEV;
967
968 /* Initialize the port structure */
969 port = xuartps_get_port();
970
971 if (!port) {
972 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
973 return -ENODEV;
974 } else {
975 /* Register the port.
976 * This function also registers this device with the tty layer
977 * and triggers invocation of the config_port() entry point.
978 */
979 port->mapbase = res->start;
980 port->irq = res2->start;
981 port->dev = &pdev->dev;
982 port->uartclk = clk;
983 dev_set_drvdata(&pdev->dev, port);
984 rc = uart_add_one_port(&xuartps_uart_driver, port);
985 if (rc) {
986 dev_err(&pdev->dev,
987 "uart_add_one_port() failed; err=%i\n", rc);
988 dev_set_drvdata(&pdev->dev, NULL);
989 return rc;
990 }
991 return 0;
992 }
993}
994
995/**
996 * xuartps_remove - called when the platform driver is unregistered
997 * @pdev: Pointer to the platform device structure
998 *
999 * Returns 0 on success, negative error otherwise
1000 **/
1001static int __devexit xuartps_remove(struct platform_device *pdev)
1002{
1003 struct uart_port *port = dev_get_drvdata(&pdev->dev);
1004 int rc = 0;
1005
1006 /* Remove the xuartps port from the serial core */
1007 if (port) {
1008 rc = uart_remove_one_port(&xuartps_uart_driver, port);
1009 dev_set_drvdata(&pdev->dev, NULL);
1010 port->mapbase = 0;
1011 }
1012 return rc;
1013}
1014
1015/**
1016 * xuartps_suspend - suspend event
1017 * @pdev: Pointer to the platform device structure
1018 * @state: State of the device
1019 *
1020 * Returns 0
1021 **/
1022static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
1023{
1024 /* Call the API provided in serial_core.c file which handles
1025 * the suspend.
1026 */
1027 uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1028 return 0;
1029}
1030
1031/**
1032 * xuartps_resume - Resume after a previous suspend
1033 * @pdev: Pointer to the platform device structure
1034 *
1035 * Returns 0
1036 **/
1037static int xuartps_resume(struct platform_device *pdev)
1038{
1039 uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
1040 return 0;
1041}
1042
1043/* Match table for of_platform binding */
1044
1045#ifdef CONFIG_OF
1046static struct of_device_id xuartps_of_match[] __devinitdata = {
1047 { .compatible = "xlnx,xuartps", },
1048 {}
1049};
1050MODULE_DEVICE_TABLE(of, xuartps_of_match);
1051#else
1052#define xuartps_of_match NULL
1053#endif
1054
1055static struct platform_driver xuartps_platform_driver = {
1056 .probe = xuartps_probe, /* Probe method */
1057 .remove = __exit_p(xuartps_remove), /* Detach method */
1058 .suspend = xuartps_suspend, /* Suspend */
1059 .resume = xuartps_resume, /* Resume after a suspend */
1060 .driver = {
1061 .owner = THIS_MODULE,
1062 .name = XUARTPS_NAME, /* Driver name */
1063 .of_match_table = xuartps_of_match,
1064 },
1065};
1066
1067/* ---------------------------------------------------------------------
1068 * Module Init and Exit
1069 */
1070/**
1071 * xuartps_init - Initial driver registration call
1072 *
1073 * Returns whether the registration was successful or not
1074 **/
1075static int __init xuartps_init(void)
1076{
1077 int retval = 0;
1078
1079 /* Register the xuartps driver with the serial core */
1080 retval = uart_register_driver(&xuartps_uart_driver);
1081 if (retval)
1082 return retval;
1083
1084 /* Register the platform driver */
1085 retval = platform_driver_register(&xuartps_platform_driver);
1086 if (retval)
1087 uart_unregister_driver(&xuartps_uart_driver);
1088
1089 return retval;
1090}
1091
1092/**
1093 * xuartps_exit - Driver unregistration call
1094 **/
1095static void __exit xuartps_exit(void)
1096{
1097 /* The order of unregistration is important. Unregister the
1098 * UART driver before the platform driver crashes the system.
1099 */
1100
1101 /* Unregister the platform driver */
1102 platform_driver_unregister(&xuartps_platform_driver);
1103
1104 /* Unregister the xuartps driver */
1105 uart_unregister_driver(&xuartps_uart_driver);
1106}
1107
1108module_init(xuartps_init);
1109module_exit(xuartps_exit);
1110
1111MODULE_DESCRIPTION("Driver for PS UART");
1112MODULE_AUTHOR("Xilinx Inc.");
1113MODULE_LICENSE("GPL");
1/*
2 * Cadence UART driver (found in Xilinx Zynq)
3 *
4 * 2011 - 2014 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
15 */
16
17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/console.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/module.h>
33
34#define CDNS_UART_TTY_NAME "ttyPS"
35#define CDNS_UART_NAME "xuartps"
36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38#define CDNS_UART_NR_PORTS 2
39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40#define CDNS_UART_REGISTER_SPACE 0x1000
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/* Register offsets for the UART. */
53#define CDNS_UART_CR 0x00 /* Control Register */
54#define CDNS_UART_MR 0x04 /* Mode Register */
55#define CDNS_UART_IER 0x08 /* Interrupt Enable */
56#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58#define CDNS_UART_ISR 0x14 /* Interrupt Status */
59#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64#define CDNS_UART_SR 0x2C /* Channel Status */
65#define CDNS_UART_FIFO 0x30 /* FIFO */
66#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71
72/* Control Register Bit Definitions */
73#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92
93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95
96#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101
102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
105
106/*
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
116 */
117#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
128
129#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \
130 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \
131 CDNS_UART_IXR_TOUT)
132
133/* Goes in read_status_mask for break detection as the HW doesn't do it*/
134#define CDNS_UART_IXR_BRK 0x80000000
135
136/*
137 * Modem Control register:
138 * The read/write Modem Control register controls the interface with the modem
139 * or data set, or a peripheral device emulating a modem.
140 */
141#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
142#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
143#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
144
145/*
146 * Channel Status Register:
147 * The channel status register (CSR) is provided to enable the control logic
148 * to monitor the status of bits in the channel interrupt status register,
149 * even if these are masked out by the interrupt mask register.
150 */
151#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
152#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
153#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
154#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
155
156/* baud dividers min/max values */
157#define CDNS_UART_BDIV_MIN 4
158#define CDNS_UART_BDIV_MAX 255
159#define CDNS_UART_CD_MAX 65535
160
161/**
162 * struct cdns_uart - device data
163 * @port: Pointer to the UART port
164 * @uartclk: Reference clock
165 * @pclk: APB clock
166 * @baud: Current baud rate
167 * @clk_rate_change_nb: Notifier block for clock changes
168 */
169struct cdns_uart {
170 struct uart_port *port;
171 struct clk *uartclk;
172 struct clk *pclk;
173 unsigned int baud;
174 struct notifier_block clk_rate_change_nb;
175};
176#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
177 clk_rate_change_nb);
178
179static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
180{
181 /*
182 * There is no hardware break detection, so we interpret framing
183 * error with all-zeros data as a break sequence. Most of the time,
184 * there's another non-zero byte at the end of the sequence.
185 */
186 if (isrstatus & CDNS_UART_IXR_FRAMING) {
187 while (!(readl(port->membase + CDNS_UART_SR) &
188 CDNS_UART_SR_RXEMPTY)) {
189 if (!readl(port->membase + CDNS_UART_FIFO)) {
190 port->read_status_mask |= CDNS_UART_IXR_BRK;
191 isrstatus &= ~CDNS_UART_IXR_FRAMING;
192 }
193 }
194 writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
195 }
196
197 /* drop byte with parity error if IGNPAR specified */
198 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
199 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
200
201 isrstatus &= port->read_status_mask;
202 isrstatus &= ~port->ignore_status_mask;
203
204 if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
205 return;
206
207 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
208 u32 data;
209 char status = TTY_NORMAL;
210
211 data = readl(port->membase + CDNS_UART_FIFO);
212
213 /* Non-NULL byte after BREAK is garbage (99%) */
214 if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
215 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
216 port->icount.brk++;
217 if (uart_handle_break(port))
218 continue;
219 }
220
221 if (uart_handle_sysrq_char(port, data))
222 continue;
223
224 port->icount.rx++;
225
226 if (isrstatus & CDNS_UART_IXR_PARITY) {
227 port->icount.parity++;
228 status = TTY_PARITY;
229 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
230 port->icount.frame++;
231 status = TTY_FRAME;
232 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
233 port->icount.overrun++;
234 }
235
236 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
237 data, status);
238 }
239 tty_flip_buffer_push(&port->state->port);
240}
241
242static void cdns_uart_handle_tx(struct uart_port *port)
243{
244 unsigned int numbytes;
245
246 if (uart_circ_empty(&port->state->xmit)) {
247 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
248 return;
249 }
250
251 numbytes = port->fifosize;
252 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
253 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
254 /*
255 * Get the data from the UART circular buffer
256 * and write it to the cdns_uart's TX_FIFO
257 * register.
258 */
259 writel(port->state->xmit.buf[port->state->xmit.tail],
260 port->membase + CDNS_UART_FIFO);
261 port->icount.tx++;
262
263 /*
264 * Adjust the tail of the UART buffer and wrap
265 * the buffer if it reaches limit.
266 */
267 port->state->xmit.tail =
268 (port->state->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
269
270 numbytes--;
271 }
272
273 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(port);
275}
276
277/**
278 * cdns_uart_isr - Interrupt handler
279 * @irq: Irq number
280 * @dev_id: Id of the port
281 *
282 * Return: IRQHANDLED
283 */
284static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
285{
286 struct uart_port *port = (struct uart_port *)dev_id;
287 unsigned long flags;
288 unsigned int isrstatus;
289
290 spin_lock_irqsave(&port->lock, flags);
291
292 /* Read the interrupt status register to determine which
293 * interrupt(s) is/are active.
294 */
295 isrstatus = readl(port->membase + CDNS_UART_ISR);
296
297 if (isrstatus & CDNS_UART_RX_IRQS)
298 cdns_uart_handle_rx(port, isrstatus);
299
300 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY)
301 cdns_uart_handle_tx(port);
302
303 writel(isrstatus, port->membase + CDNS_UART_ISR);
304
305 /* be sure to release the lock and tty before leaving */
306 spin_unlock_irqrestore(&port->lock, flags);
307
308 return IRQ_HANDLED;
309}
310
311/**
312 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
313 * @clk: UART module input clock
314 * @baud: Desired baud rate
315 * @rbdiv: BDIV value (return value)
316 * @rcd: CD value (return value)
317 * @div8: Value for clk_sel bit in mod (return value)
318 * Return: baud rate, requested baud when possible, or actual baud when there
319 * was too much error, zero if no valid divisors are found.
320 *
321 * Formula to obtain baud rate is
322 * baud_tx/rx rate = clk/CD * (BDIV + 1)
323 * input_clk = (Uart User Defined Clock or Apb Clock)
324 * depends on UCLKEN in MR Reg
325 * clk = input_clk or input_clk/8;
326 * depends on CLKS in MR reg
327 * CD and BDIV depends on values in
328 * baud rate generate register
329 * baud rate clock divisor register
330 */
331static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
332 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
333{
334 u32 cd, bdiv;
335 unsigned int calc_baud;
336 unsigned int bestbaud = 0;
337 unsigned int bauderror;
338 unsigned int besterror = ~0;
339
340 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
341 *div8 = 1;
342 clk /= 8;
343 } else {
344 *div8 = 0;
345 }
346
347 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
348 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
349 if (cd < 1 || cd > CDNS_UART_CD_MAX)
350 continue;
351
352 calc_baud = clk / (cd * (bdiv + 1));
353
354 if (baud > calc_baud)
355 bauderror = baud - calc_baud;
356 else
357 bauderror = calc_baud - baud;
358
359 if (besterror > bauderror) {
360 *rbdiv = bdiv;
361 *rcd = cd;
362 bestbaud = calc_baud;
363 besterror = bauderror;
364 }
365 }
366 /* use the values when percent error is acceptable */
367 if (((besterror * 100) / baud) < 3)
368 bestbaud = baud;
369
370 return bestbaud;
371}
372
373/**
374 * cdns_uart_set_baud_rate - Calculate and set the baud rate
375 * @port: Handle to the uart port structure
376 * @baud: Baud rate to set
377 * Return: baud rate, requested baud when possible, or actual baud when there
378 * was too much error, zero if no valid divisors are found.
379 */
380static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
381 unsigned int baud)
382{
383 unsigned int calc_baud;
384 u32 cd = 0, bdiv = 0;
385 u32 mreg;
386 int div8;
387 struct cdns_uart *cdns_uart = port->private_data;
388
389 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
390 &div8);
391
392 /* Write new divisors to hardware */
393 mreg = readl(port->membase + CDNS_UART_MR);
394 if (div8)
395 mreg |= CDNS_UART_MR_CLKSEL;
396 else
397 mreg &= ~CDNS_UART_MR_CLKSEL;
398 writel(mreg, port->membase + CDNS_UART_MR);
399 writel(cd, port->membase + CDNS_UART_BAUDGEN);
400 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
401 cdns_uart->baud = baud;
402
403 return calc_baud;
404}
405
406#ifdef CONFIG_COMMON_CLK
407/**
408 * cdns_uart_clk_notitifer_cb - Clock notifier callback
409 * @nb: Notifier block
410 * @event: Notify event
411 * @data: Notifier data
412 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
413 */
414static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
415 unsigned long event, void *data)
416{
417 u32 ctrl_reg;
418 struct uart_port *port;
419 int locked = 0;
420 struct clk_notifier_data *ndata = data;
421 unsigned long flags = 0;
422 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
423
424 port = cdns_uart->port;
425 if (port->suspended)
426 return NOTIFY_OK;
427
428 switch (event) {
429 case PRE_RATE_CHANGE:
430 {
431 u32 bdiv, cd;
432 int div8;
433
434 /*
435 * Find out if current baud-rate can be achieved with new clock
436 * frequency.
437 */
438 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
439 &bdiv, &cd, &div8)) {
440 dev_warn(port->dev, "clock rate change rejected\n");
441 return NOTIFY_BAD;
442 }
443
444 spin_lock_irqsave(&cdns_uart->port->lock, flags);
445
446 /* Disable the TX and RX to set baud rate */
447 ctrl_reg = readl(port->membase + CDNS_UART_CR);
448 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
449 writel(ctrl_reg, port->membase + CDNS_UART_CR);
450
451 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
452
453 return NOTIFY_OK;
454 }
455 case POST_RATE_CHANGE:
456 /*
457 * Set clk dividers to generate correct baud with new clock
458 * frequency.
459 */
460
461 spin_lock_irqsave(&cdns_uart->port->lock, flags);
462
463 locked = 1;
464 port->uartclk = ndata->new_rate;
465
466 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
467 cdns_uart->baud);
468 /* fall through */
469 case ABORT_RATE_CHANGE:
470 if (!locked)
471 spin_lock_irqsave(&cdns_uart->port->lock, flags);
472
473 /* Set TX/RX Reset */
474 ctrl_reg = readl(port->membase + CDNS_UART_CR);
475 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
476 writel(ctrl_reg, port->membase + CDNS_UART_CR);
477
478 while (readl(port->membase + CDNS_UART_CR) &
479 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
480 cpu_relax();
481
482 /*
483 * Clear the RX disable and TX disable bits and then set the TX
484 * enable bit and RX enable bit to enable the transmitter and
485 * receiver.
486 */
487 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
488 ctrl_reg = readl(port->membase + CDNS_UART_CR);
489 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
490 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
491 writel(ctrl_reg, port->membase + CDNS_UART_CR);
492
493 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
494
495 return NOTIFY_OK;
496 default:
497 return NOTIFY_DONE;
498 }
499}
500#endif
501
502/**
503 * cdns_uart_start_tx - Start transmitting bytes
504 * @port: Handle to the uart port structure
505 */
506static void cdns_uart_start_tx(struct uart_port *port)
507{
508 unsigned int status;
509
510 if (uart_tx_stopped(port))
511 return;
512
513 /*
514 * Set the TX enable bit and clear the TX disable bit to enable the
515 * transmitter.
516 */
517 status = readl(port->membase + CDNS_UART_CR);
518 status &= ~CDNS_UART_CR_TX_DIS;
519 status |= CDNS_UART_CR_TX_EN;
520 writel(status, port->membase + CDNS_UART_CR);
521
522 if (uart_circ_empty(&port->state->xmit))
523 return;
524
525 cdns_uart_handle_tx(port);
526
527 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
528 /* Enable the TX Empty interrupt */
529 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
530}
531
532/**
533 * cdns_uart_stop_tx - Stop TX
534 * @port: Handle to the uart port structure
535 */
536static void cdns_uart_stop_tx(struct uart_port *port)
537{
538 unsigned int regval;
539
540 regval = readl(port->membase + CDNS_UART_CR);
541 regval |= CDNS_UART_CR_TX_DIS;
542 /* Disable the transmitter */
543 writel(regval, port->membase + CDNS_UART_CR);
544}
545
546/**
547 * cdns_uart_stop_rx - Stop RX
548 * @port: Handle to the uart port structure
549 */
550static void cdns_uart_stop_rx(struct uart_port *port)
551{
552 unsigned int regval;
553
554 /* Disable RX IRQs */
555 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
556
557 /* Disable the receiver */
558 regval = readl(port->membase + CDNS_UART_CR);
559 regval |= CDNS_UART_CR_RX_DIS;
560 writel(regval, port->membase + CDNS_UART_CR);
561}
562
563/**
564 * cdns_uart_tx_empty - Check whether TX is empty
565 * @port: Handle to the uart port structure
566 *
567 * Return: TIOCSER_TEMT on success, 0 otherwise
568 */
569static unsigned int cdns_uart_tx_empty(struct uart_port *port)
570{
571 unsigned int status;
572
573 status = readl(port->membase + CDNS_UART_SR) &
574 CDNS_UART_SR_TXEMPTY;
575 return status ? TIOCSER_TEMT : 0;
576}
577
578/**
579 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
580 * transmitting char breaks
581 * @port: Handle to the uart port structure
582 * @ctl: Value based on which start or stop decision is taken
583 */
584static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
585{
586 unsigned int status;
587 unsigned long flags;
588
589 spin_lock_irqsave(&port->lock, flags);
590
591 status = readl(port->membase + CDNS_UART_CR);
592
593 if (ctl == -1)
594 writel(CDNS_UART_CR_STARTBRK | status,
595 port->membase + CDNS_UART_CR);
596 else {
597 if ((status & CDNS_UART_CR_STOPBRK) == 0)
598 writel(CDNS_UART_CR_STOPBRK | status,
599 port->membase + CDNS_UART_CR);
600 }
601 spin_unlock_irqrestore(&port->lock, flags);
602}
603
604/**
605 * cdns_uart_set_termios - termios operations, handling data length, parity,
606 * stop bits, flow control, baud rate
607 * @port: Handle to the uart port structure
608 * @termios: Handle to the input termios structure
609 * @old: Values of the previously saved termios structure
610 */
611static void cdns_uart_set_termios(struct uart_port *port,
612 struct ktermios *termios, struct ktermios *old)
613{
614 unsigned int cval = 0;
615 unsigned int baud, minbaud, maxbaud;
616 unsigned long flags;
617 unsigned int ctrl_reg, mode_reg;
618
619 spin_lock_irqsave(&port->lock, flags);
620
621 /* Wait for the transmit FIFO to empty before making changes */
622 if (!(readl(port->membase + CDNS_UART_CR) &
623 CDNS_UART_CR_TX_DIS)) {
624 while (!(readl(port->membase + CDNS_UART_SR) &
625 CDNS_UART_SR_TXEMPTY)) {
626 cpu_relax();
627 }
628 }
629
630 /* Disable the TX and RX to set baud rate */
631 ctrl_reg = readl(port->membase + CDNS_UART_CR);
632 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
633 writel(ctrl_reg, port->membase + CDNS_UART_CR);
634
635 /*
636 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
637 * min and max baud should be calculated here based on port->uartclk.
638 * this way we get a valid baud and can safely call set_baud()
639 */
640 minbaud = port->uartclk /
641 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
642 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
643 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
644 baud = cdns_uart_set_baud_rate(port, baud);
645 if (tty_termios_baud_rate(termios))
646 tty_termios_encode_baud_rate(termios, baud, baud);
647
648 /* Update the per-port timeout. */
649 uart_update_timeout(port, termios->c_cflag, baud);
650
651 /* Set TX/RX Reset */
652 ctrl_reg = readl(port->membase + CDNS_UART_CR);
653 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
654 writel(ctrl_reg, port->membase + CDNS_UART_CR);
655
656 /*
657 * Clear the RX disable and TX disable bits and then set the TX enable
658 * bit and RX enable bit to enable the transmitter and receiver.
659 */
660 ctrl_reg = readl(port->membase + CDNS_UART_CR);
661 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
662 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
663 writel(ctrl_reg, port->membase + CDNS_UART_CR);
664
665 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
666
667 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
668 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
669 port->ignore_status_mask = 0;
670
671 if (termios->c_iflag & INPCK)
672 port->read_status_mask |= CDNS_UART_IXR_PARITY |
673 CDNS_UART_IXR_FRAMING;
674
675 if (termios->c_iflag & IGNPAR)
676 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
677 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
678
679 /* ignore all characters if CREAD is not set */
680 if ((termios->c_cflag & CREAD) == 0)
681 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
682 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
683 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
684
685 mode_reg = readl(port->membase + CDNS_UART_MR);
686
687 /* Handling Data Size */
688 switch (termios->c_cflag & CSIZE) {
689 case CS6:
690 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
691 break;
692 case CS7:
693 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
694 break;
695 default:
696 case CS8:
697 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
698 termios->c_cflag &= ~CSIZE;
699 termios->c_cflag |= CS8;
700 break;
701 }
702
703 /* Handling Parity and Stop Bits length */
704 if (termios->c_cflag & CSTOPB)
705 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
706 else
707 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
708
709 if (termios->c_cflag & PARENB) {
710 /* Mark or Space parity */
711 if (termios->c_cflag & CMSPAR) {
712 if (termios->c_cflag & PARODD)
713 cval |= CDNS_UART_MR_PARITY_MARK;
714 else
715 cval |= CDNS_UART_MR_PARITY_SPACE;
716 } else {
717 if (termios->c_cflag & PARODD)
718 cval |= CDNS_UART_MR_PARITY_ODD;
719 else
720 cval |= CDNS_UART_MR_PARITY_EVEN;
721 }
722 } else {
723 cval |= CDNS_UART_MR_PARITY_NONE;
724 }
725 cval |= mode_reg & 1;
726 writel(cval, port->membase + CDNS_UART_MR);
727
728 spin_unlock_irqrestore(&port->lock, flags);
729}
730
731/**
732 * cdns_uart_startup - Called when an application opens a cdns_uart port
733 * @port: Handle to the uart port structure
734 *
735 * Return: 0 on success, negative errno otherwise
736 */
737static int cdns_uart_startup(struct uart_port *port)
738{
739 int ret;
740 unsigned long flags;
741 unsigned int status = 0;
742
743 spin_lock_irqsave(&port->lock, flags);
744
745 /* Disable the TX and RX */
746 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
747 port->membase + CDNS_UART_CR);
748
749 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
750 * no break chars.
751 */
752 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
753 port->membase + CDNS_UART_CR);
754
755 /*
756 * Clear the RX disable bit and then set the RX enable bit to enable
757 * the receiver.
758 */
759 status = readl(port->membase + CDNS_UART_CR);
760 status &= CDNS_UART_CR_RX_DIS;
761 status |= CDNS_UART_CR_RX_EN;
762 writel(status, port->membase + CDNS_UART_CR);
763
764 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
765 * no parity.
766 */
767 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
768 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
769 port->membase + CDNS_UART_MR);
770
771 /*
772 * Set the RX FIFO Trigger level to use most of the FIFO, but it
773 * can be tuned with a module parameter
774 */
775 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
776
777 /*
778 * Receive Timeout register is enabled but it
779 * can be tuned with a module parameter
780 */
781 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
782
783 /* Clear out any pending interrupts before enabling them */
784 writel(readl(port->membase + CDNS_UART_ISR),
785 port->membase + CDNS_UART_ISR);
786
787 spin_unlock_irqrestore(&port->lock, flags);
788
789 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
790 if (ret) {
791 dev_err(port->dev, "request_irq '%d' failed with %d\n",
792 port->irq, ret);
793 return ret;
794 }
795
796 /* Set the Interrupt Registers with desired interrupts */
797 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
798
799 return 0;
800}
801
802/**
803 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
804 * @port: Handle to the uart port structure
805 */
806static void cdns_uart_shutdown(struct uart_port *port)
807{
808 int status;
809 unsigned long flags;
810
811 spin_lock_irqsave(&port->lock, flags);
812
813 /* Disable interrupts */
814 status = readl(port->membase + CDNS_UART_IMR);
815 writel(status, port->membase + CDNS_UART_IDR);
816 writel(0xffffffff, port->membase + CDNS_UART_ISR);
817
818 /* Disable the TX and RX */
819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
820 port->membase + CDNS_UART_CR);
821
822 spin_unlock_irqrestore(&port->lock, flags);
823
824 free_irq(port->irq, port);
825}
826
827/**
828 * cdns_uart_type - Set UART type to cdns_uart port
829 * @port: Handle to the uart port structure
830 *
831 * Return: string on success, NULL otherwise
832 */
833static const char *cdns_uart_type(struct uart_port *port)
834{
835 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
836}
837
838/**
839 * cdns_uart_verify_port - Verify the port params
840 * @port: Handle to the uart port structure
841 * @ser: Handle to the structure whose members are compared
842 *
843 * Return: 0 on success, negative errno otherwise.
844 */
845static int cdns_uart_verify_port(struct uart_port *port,
846 struct serial_struct *ser)
847{
848 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
849 return -EINVAL;
850 if (port->irq != ser->irq)
851 return -EINVAL;
852 if (ser->io_type != UPIO_MEM)
853 return -EINVAL;
854 if (port->iobase != ser->port)
855 return -EINVAL;
856 if (ser->hub6 != 0)
857 return -EINVAL;
858 return 0;
859}
860
861/**
862 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
863 * called when the driver adds a cdns_uart port via
864 * uart_add_one_port()
865 * @port: Handle to the uart port structure
866 *
867 * Return: 0 on success, negative errno otherwise.
868 */
869static int cdns_uart_request_port(struct uart_port *port)
870{
871 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
872 CDNS_UART_NAME)) {
873 return -ENOMEM;
874 }
875
876 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
877 if (!port->membase) {
878 dev_err(port->dev, "Unable to map registers\n");
879 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
880 return -ENOMEM;
881 }
882 return 0;
883}
884
885/**
886 * cdns_uart_release_port - Release UART port
887 * @port: Handle to the uart port structure
888 *
889 * Release the memory region attached to a cdns_uart port. Called when the
890 * driver removes a cdns_uart port via uart_remove_one_port().
891 */
892static void cdns_uart_release_port(struct uart_port *port)
893{
894 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
895 iounmap(port->membase);
896 port->membase = NULL;
897}
898
899/**
900 * cdns_uart_config_port - Configure UART port
901 * @port: Handle to the uart port structure
902 * @flags: If any
903 */
904static void cdns_uart_config_port(struct uart_port *port, int flags)
905{
906 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
907 port->type = PORT_XUARTPS;
908}
909
910/**
911 * cdns_uart_get_mctrl - Get the modem control state
912 * @port: Handle to the uart port structure
913 *
914 * Return: the modem control state
915 */
916static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
917{
918 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
919}
920
921static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
922{
923 u32 val;
924
925 val = readl(port->membase + CDNS_UART_MODEMCR);
926
927 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
928
929 if (mctrl & TIOCM_RTS)
930 val |= CDNS_UART_MODEMCR_RTS;
931 if (mctrl & TIOCM_DTR)
932 val |= CDNS_UART_MODEMCR_DTR;
933
934 writel(val, port->membase + CDNS_UART_MODEMCR);
935}
936
937#ifdef CONFIG_CONSOLE_POLL
938static int cdns_uart_poll_get_char(struct uart_port *port)
939{
940 int c;
941 unsigned long flags;
942
943 spin_lock_irqsave(&port->lock, flags);
944
945 /* Check if FIFO is empty */
946 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
947 c = NO_POLL_CHAR;
948 else /* Read a character */
949 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
950
951 spin_unlock_irqrestore(&port->lock, flags);
952
953 return c;
954}
955
956static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
957{
958 unsigned long flags;
959
960 spin_lock_irqsave(&port->lock, flags);
961
962 /* Wait until FIFO is empty */
963 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
964 cpu_relax();
965
966 /* Write a character */
967 writel(c, port->membase + CDNS_UART_FIFO);
968
969 /* Wait until FIFO is empty */
970 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
971 cpu_relax();
972
973 spin_unlock_irqrestore(&port->lock, flags);
974
975 return;
976}
977#endif
978
979static struct uart_ops cdns_uart_ops = {
980 .set_mctrl = cdns_uart_set_mctrl,
981 .get_mctrl = cdns_uart_get_mctrl,
982 .start_tx = cdns_uart_start_tx,
983 .stop_tx = cdns_uart_stop_tx,
984 .stop_rx = cdns_uart_stop_rx,
985 .tx_empty = cdns_uart_tx_empty,
986 .break_ctl = cdns_uart_break_ctl,
987 .set_termios = cdns_uart_set_termios,
988 .startup = cdns_uart_startup,
989 .shutdown = cdns_uart_shutdown,
990 .type = cdns_uart_type,
991 .verify_port = cdns_uart_verify_port,
992 .request_port = cdns_uart_request_port,
993 .release_port = cdns_uart_release_port,
994 .config_port = cdns_uart_config_port,
995#ifdef CONFIG_CONSOLE_POLL
996 .poll_get_char = cdns_uart_poll_get_char,
997 .poll_put_char = cdns_uart_poll_put_char,
998#endif
999};
1000
1001static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1002
1003/**
1004 * cdns_uart_get_port - Configure the port from platform device resource info
1005 * @id: Port id
1006 *
1007 * Return: a pointer to a uart_port or NULL for failure
1008 */
1009static struct uart_port *cdns_uart_get_port(int id)
1010{
1011 struct uart_port *port;
1012
1013 /* Try the given port id if failed use default method */
1014 if (cdns_uart_port[id].mapbase != 0) {
1015 /* Find the next unused port */
1016 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1017 if (cdns_uart_port[id].mapbase == 0)
1018 break;
1019 }
1020
1021 if (id >= CDNS_UART_NR_PORTS)
1022 return NULL;
1023
1024 port = &cdns_uart_port[id];
1025
1026 /* At this point, we've got an empty uart_port struct, initialize it */
1027 spin_lock_init(&port->lock);
1028 port->membase = NULL;
1029 port->irq = 0;
1030 port->type = PORT_UNKNOWN;
1031 port->iotype = UPIO_MEM32;
1032 port->flags = UPF_BOOT_AUTOCONF;
1033 port->ops = &cdns_uart_ops;
1034 port->fifosize = CDNS_UART_FIFO_SIZE;
1035 port->line = id;
1036 port->dev = NULL;
1037 return port;
1038}
1039
1040#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1041/**
1042 * cdns_uart_console_wait_tx - Wait for the TX to be full
1043 * @port: Handle to the uart port structure
1044 */
1045static void cdns_uart_console_wait_tx(struct uart_port *port)
1046{
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 barrier();
1049}
1050
1051/**
1052 * cdns_uart_console_putchar - write the character to the FIFO buffer
1053 * @port: Handle to the uart port structure
1054 * @ch: Character to be written
1055 */
1056static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1057{
1058 cdns_uart_console_wait_tx(port);
1059 writel(ch, port->membase + CDNS_UART_FIFO);
1060}
1061
1062static void __init cdns_early_write(struct console *con, const char *s,
1063 unsigned n)
1064{
1065 struct earlycon_device *dev = con->data;
1066
1067 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1068}
1069
1070static int __init cdns_early_console_setup(struct earlycon_device *device,
1071 const char *opt)
1072{
1073 if (!device->port.membase)
1074 return -ENODEV;
1075
1076 device->con->write = cdns_early_write;
1077
1078 return 0;
1079}
1080OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1081OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1082OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1083
1084/**
1085 * cdns_uart_console_write - perform write operation
1086 * @co: Console handle
1087 * @s: Pointer to character array
1088 * @count: No of characters
1089 */
1090static void cdns_uart_console_write(struct console *co, const char *s,
1091 unsigned int count)
1092{
1093 struct uart_port *port = &cdns_uart_port[co->index];
1094 unsigned long flags;
1095 unsigned int imr, ctrl;
1096 int locked = 1;
1097
1098 if (port->sysrq)
1099 locked = 0;
1100 else if (oops_in_progress)
1101 locked = spin_trylock_irqsave(&port->lock, flags);
1102 else
1103 spin_lock_irqsave(&port->lock, flags);
1104
1105 /* save and disable interrupt */
1106 imr = readl(port->membase + CDNS_UART_IMR);
1107 writel(imr, port->membase + CDNS_UART_IDR);
1108
1109 /*
1110 * Make sure that the tx part is enabled. Set the TX enable bit and
1111 * clear the TX disable bit to enable the transmitter.
1112 */
1113 ctrl = readl(port->membase + CDNS_UART_CR);
1114 ctrl &= ~CDNS_UART_CR_TX_DIS;
1115 ctrl |= CDNS_UART_CR_TX_EN;
1116 writel(ctrl, port->membase + CDNS_UART_CR);
1117
1118 uart_console_write(port, s, count, cdns_uart_console_putchar);
1119 cdns_uart_console_wait_tx(port);
1120
1121 writel(ctrl, port->membase + CDNS_UART_CR);
1122
1123 /* restore interrupt state */
1124 writel(imr, port->membase + CDNS_UART_IER);
1125
1126 if (locked)
1127 spin_unlock_irqrestore(&port->lock, flags);
1128}
1129
1130/**
1131 * cdns_uart_console_setup - Initialize the uart to default config
1132 * @co: Console handle
1133 * @options: Initial settings of uart
1134 *
1135 * Return: 0 on success, negative errno otherwise.
1136 */
1137static int __init cdns_uart_console_setup(struct console *co, char *options)
1138{
1139 struct uart_port *port = &cdns_uart_port[co->index];
1140 int baud = 9600;
1141 int bits = 8;
1142 int parity = 'n';
1143 int flow = 'n';
1144
1145 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1146 return -EINVAL;
1147
1148 if (!port->membase) {
1149 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1150 co->index);
1151 return -ENODEV;
1152 }
1153
1154 if (options)
1155 uart_parse_options(options, &baud, &parity, &bits, &flow);
1156
1157 return uart_set_options(port, co, baud, parity, bits, flow);
1158}
1159
1160static struct uart_driver cdns_uart_uart_driver;
1161
1162static struct console cdns_uart_console = {
1163 .name = CDNS_UART_TTY_NAME,
1164 .write = cdns_uart_console_write,
1165 .device = uart_console_device,
1166 .setup = cdns_uart_console_setup,
1167 .flags = CON_PRINTBUFFER,
1168 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1169 .data = &cdns_uart_uart_driver,
1170};
1171
1172/**
1173 * cdns_uart_console_init - Initialization call
1174 *
1175 * Return: 0 on success, negative errno otherwise
1176 */
1177static int __init cdns_uart_console_init(void)
1178{
1179 register_console(&cdns_uart_console);
1180 return 0;
1181}
1182
1183console_initcall(cdns_uart_console_init);
1184
1185#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1186
1187static struct uart_driver cdns_uart_uart_driver = {
1188 .owner = THIS_MODULE,
1189 .driver_name = CDNS_UART_NAME,
1190 .dev_name = CDNS_UART_TTY_NAME,
1191 .major = CDNS_UART_MAJOR,
1192 .minor = CDNS_UART_MINOR,
1193 .nr = CDNS_UART_NR_PORTS,
1194#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1195 .cons = &cdns_uart_console,
1196#endif
1197};
1198
1199#ifdef CONFIG_PM_SLEEP
1200/**
1201 * cdns_uart_suspend - suspend event
1202 * @device: Pointer to the device structure
1203 *
1204 * Return: 0
1205 */
1206static int cdns_uart_suspend(struct device *device)
1207{
1208 struct uart_port *port = dev_get_drvdata(device);
1209 struct tty_struct *tty;
1210 struct device *tty_dev;
1211 int may_wake = 0;
1212
1213 /* Get the tty which could be NULL so don't assume it's valid */
1214 tty = tty_port_tty_get(&port->state->port);
1215 if (tty) {
1216 tty_dev = tty->dev;
1217 may_wake = device_may_wakeup(tty_dev);
1218 tty_kref_put(tty);
1219 }
1220
1221 /*
1222 * Call the API provided in serial_core.c file which handles
1223 * the suspend.
1224 */
1225 uart_suspend_port(&cdns_uart_uart_driver, port);
1226 if (console_suspend_enabled && !may_wake) {
1227 struct cdns_uart *cdns_uart = port->private_data;
1228
1229 clk_disable(cdns_uart->uartclk);
1230 clk_disable(cdns_uart->pclk);
1231 } else {
1232 unsigned long flags = 0;
1233
1234 spin_lock_irqsave(&port->lock, flags);
1235 /* Empty the receive FIFO 1st before making changes */
1236 while (!(readl(port->membase + CDNS_UART_SR) &
1237 CDNS_UART_SR_RXEMPTY))
1238 readl(port->membase + CDNS_UART_FIFO);
1239 /* set RX trigger level to 1 */
1240 writel(1, port->membase + CDNS_UART_RXWM);
1241 /* disable RX timeout interrups */
1242 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1243 spin_unlock_irqrestore(&port->lock, flags);
1244 }
1245
1246 return 0;
1247}
1248
1249/**
1250 * cdns_uart_resume - Resume after a previous suspend
1251 * @device: Pointer to the device structure
1252 *
1253 * Return: 0
1254 */
1255static int cdns_uart_resume(struct device *device)
1256{
1257 struct uart_port *port = dev_get_drvdata(device);
1258 unsigned long flags = 0;
1259 u32 ctrl_reg;
1260 struct tty_struct *tty;
1261 struct device *tty_dev;
1262 int may_wake = 0;
1263
1264 /* Get the tty which could be NULL so don't assume it's valid */
1265 tty = tty_port_tty_get(&port->state->port);
1266 if (tty) {
1267 tty_dev = tty->dev;
1268 may_wake = device_may_wakeup(tty_dev);
1269 tty_kref_put(tty);
1270 }
1271
1272 if (console_suspend_enabled && !may_wake) {
1273 struct cdns_uart *cdns_uart = port->private_data;
1274
1275 clk_enable(cdns_uart->pclk);
1276 clk_enable(cdns_uart->uartclk);
1277
1278 spin_lock_irqsave(&port->lock, flags);
1279
1280 /* Set TX/RX Reset */
1281 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1282 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1283 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1284 while (readl(port->membase + CDNS_UART_CR) &
1285 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1286 cpu_relax();
1287
1288 /* restore rx timeout value */
1289 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1290 /* Enable Tx/Rx */
1291 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1292 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1293 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1294 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1295
1296 spin_unlock_irqrestore(&port->lock, flags);
1297 } else {
1298 spin_lock_irqsave(&port->lock, flags);
1299 /* restore original rx trigger level */
1300 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1301 /* enable RX timeout interrupt */
1302 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 }
1305
1306 return uart_resume_port(&cdns_uart_uart_driver, port);
1307}
1308#endif /* ! CONFIG_PM_SLEEP */
1309
1310static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1311 cdns_uart_resume);
1312
1313/**
1314 * cdns_uart_probe - Platform driver probe
1315 * @pdev: Pointer to the platform device structure
1316 *
1317 * Return: 0 on success, negative errno otherwise
1318 */
1319static int cdns_uart_probe(struct platform_device *pdev)
1320{
1321 int rc, id, irq;
1322 struct uart_port *port;
1323 struct resource *res;
1324 struct cdns_uart *cdns_uart_data;
1325
1326 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1327 GFP_KERNEL);
1328 if (!cdns_uart_data)
1329 return -ENOMEM;
1330
1331 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1332 if (IS_ERR(cdns_uart_data->pclk)) {
1333 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1334 if (!IS_ERR(cdns_uart_data->pclk))
1335 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1336 }
1337 if (IS_ERR(cdns_uart_data->pclk)) {
1338 dev_err(&pdev->dev, "pclk clock not found.\n");
1339 return PTR_ERR(cdns_uart_data->pclk);
1340 }
1341
1342 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1343 if (IS_ERR(cdns_uart_data->uartclk)) {
1344 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1345 if (!IS_ERR(cdns_uart_data->uartclk))
1346 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1347 }
1348 if (IS_ERR(cdns_uart_data->uartclk)) {
1349 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1350 return PTR_ERR(cdns_uart_data->uartclk);
1351 }
1352
1353 rc = clk_prepare_enable(cdns_uart_data->pclk);
1354 if (rc) {
1355 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1356 return rc;
1357 }
1358 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1359 if (rc) {
1360 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1361 goto err_out_clk_dis_pclk;
1362 }
1363
1364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1365 if (!res) {
1366 rc = -ENODEV;
1367 goto err_out_clk_disable;
1368 }
1369
1370 irq = platform_get_irq(pdev, 0);
1371 if (irq <= 0) {
1372 rc = -ENXIO;
1373 goto err_out_clk_disable;
1374 }
1375
1376#ifdef CONFIG_COMMON_CLK
1377 cdns_uart_data->clk_rate_change_nb.notifier_call =
1378 cdns_uart_clk_notifier_cb;
1379 if (clk_notifier_register(cdns_uart_data->uartclk,
1380 &cdns_uart_data->clk_rate_change_nb))
1381 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1382#endif
1383 /* Look for a serialN alias */
1384 id = of_alias_get_id(pdev->dev.of_node, "serial");
1385 if (id < 0)
1386 id = 0;
1387
1388 /* Initialize the port structure */
1389 port = cdns_uart_get_port(id);
1390
1391 if (!port) {
1392 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1393 rc = -ENODEV;
1394 goto err_out_notif_unreg;
1395 }
1396
1397 /*
1398 * Register the port.
1399 * This function also registers this device with the tty layer
1400 * and triggers invocation of the config_port() entry point.
1401 */
1402 port->mapbase = res->start;
1403 port->irq = irq;
1404 port->dev = &pdev->dev;
1405 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1406 port->private_data = cdns_uart_data;
1407 cdns_uart_data->port = port;
1408 platform_set_drvdata(pdev, port);
1409
1410 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1411 if (rc) {
1412 dev_err(&pdev->dev,
1413 "uart_add_one_port() failed; err=%i\n", rc);
1414 goto err_out_notif_unreg;
1415 }
1416
1417 return 0;
1418
1419err_out_notif_unreg:
1420#ifdef CONFIG_COMMON_CLK
1421 clk_notifier_unregister(cdns_uart_data->uartclk,
1422 &cdns_uart_data->clk_rate_change_nb);
1423#endif
1424err_out_clk_disable:
1425 clk_disable_unprepare(cdns_uart_data->uartclk);
1426err_out_clk_dis_pclk:
1427 clk_disable_unprepare(cdns_uart_data->pclk);
1428
1429 return rc;
1430}
1431
1432/**
1433 * cdns_uart_remove - called when the platform driver is unregistered
1434 * @pdev: Pointer to the platform device structure
1435 *
1436 * Return: 0 on success, negative errno otherwise
1437 */
1438static int cdns_uart_remove(struct platform_device *pdev)
1439{
1440 struct uart_port *port = platform_get_drvdata(pdev);
1441 struct cdns_uart *cdns_uart_data = port->private_data;
1442 int rc;
1443
1444 /* Remove the cdns_uart port from the serial core */
1445#ifdef CONFIG_COMMON_CLK
1446 clk_notifier_unregister(cdns_uart_data->uartclk,
1447 &cdns_uart_data->clk_rate_change_nb);
1448#endif
1449 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1450 port->mapbase = 0;
1451 clk_disable_unprepare(cdns_uart_data->uartclk);
1452 clk_disable_unprepare(cdns_uart_data->pclk);
1453 return rc;
1454}
1455
1456/* Match table for of_platform binding */
1457static const struct of_device_id cdns_uart_of_match[] = {
1458 { .compatible = "xlnx,xuartps", },
1459 { .compatible = "cdns,uart-r1p8", },
1460 {}
1461};
1462MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1463
1464static struct platform_driver cdns_uart_platform_driver = {
1465 .probe = cdns_uart_probe,
1466 .remove = cdns_uart_remove,
1467 .driver = {
1468 .name = CDNS_UART_NAME,
1469 .of_match_table = cdns_uart_of_match,
1470 .pm = &cdns_uart_dev_pm_ops,
1471 },
1472};
1473
1474static int __init cdns_uart_init(void)
1475{
1476 int retval = 0;
1477
1478 /* Register the cdns_uart driver with the serial core */
1479 retval = uart_register_driver(&cdns_uart_uart_driver);
1480 if (retval)
1481 return retval;
1482
1483 /* Register the platform driver */
1484 retval = platform_driver_register(&cdns_uart_platform_driver);
1485 if (retval)
1486 uart_unregister_driver(&cdns_uart_uart_driver);
1487
1488 return retval;
1489}
1490
1491static void __exit cdns_uart_exit(void)
1492{
1493 /* Unregister the platform driver */
1494 platform_driver_unregister(&cdns_uart_platform_driver);
1495
1496 /* Unregister the cdns_uart driver */
1497 uart_unregister_driver(&cdns_uart_uart_driver);
1498}
1499
1500module_init(cdns_uart_init);
1501module_exit(cdns_uart_exit);
1502
1503MODULE_DESCRIPTION("Driver for Cadence UART");
1504MODULE_AUTHOR("Xilinx Inc.");
1505MODULE_LICENSE("GPL");