1/*
   2 * Freescale QUICC Engine UART device driver
   3 *
   4 * Author: Timur Tabi <timur@freescale.com>
   5 *
   6 * Copyright 2007 Freescale Semiconductor, Inc.  This file is licensed under
   7 * the terms of the GNU General Public License version 2.  This program
   8 * is licensed "as is" without any warranty of any kind, whether express
   9 * or implied.
  10 *
  11 * This driver adds support for UART devices via Freescale's QUICC Engine
  12 * found on some Freescale SOCs.
  13 *
  14 * If Soft-UART support is needed but not already present, then this driver
  15 * will request and upload the "Soft-UART" microcode upon probe.  The
  16 * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X"
  17 * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC,
  18 * (e.g. "11" for 1.1).
  19 */
  20
  21#include <linux/module.h>
  22#include <linux/serial.h>
  23#include <linux/slab.h>
  24#include <linux/serial_core.h>
 
 
 
  25#include <linux/io.h>
 
 
  26#include <linux/of_platform.h>
  27#include <linux/dma-mapping.h>
  28
  29#include <linux/fs_uart_pd.h>
  30#include <asm/ucc_slow.h>
  31
  32#include <linux/firmware.h>
  33#include <asm/reg.h>
  34
  35/*
  36 * The GUMR flag for Soft UART.  This would normally be defined in qe.h,
  37 * but Soft-UART is a hack and we want to keep everything related to it in
  38 * this file.
  39 */
  40#define UCC_SLOW_GUMR_H_SUART   	0x00004000      /* Soft-UART */
  41
  42/*
  43 * soft_uart is 1 if we need to use Soft-UART mode
  44 */
  45static int soft_uart;
  46/*
  47 * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise.
  48 */
  49static int firmware_loaded;
  50
  51/* Enable this macro to configure all serial ports in internal loopback
  52   mode */
  53/* #define LOOPBACK */
  54
  55/* The major and minor device numbers are defined in
  56 * http://www.lanana.org/docs/device-list/devices-2.6+.txt.  For the QE
  57 * UART, we have major number 204 and minor numbers 46 - 49, which are the
  58 * same as for the CPM2.  This decision was made because no Freescale part
  59 * has both a CPM and a QE.
  60 */
  61#define SERIAL_QE_MAJOR 204
  62#define SERIAL_QE_MINOR 46
  63
  64/* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */
  65#define UCC_MAX_UART    4
  66
  67/* The number of buffer descriptors for receiving characters. */
  68#define RX_NUM_FIFO     4
  69
  70/* The number of buffer descriptors for transmitting characters. */
  71#define TX_NUM_FIFO     4
  72
  73/* The maximum size of the character buffer for a single RX BD. */
  74#define RX_BUF_SIZE     32
  75
  76/* The maximum size of the character buffer for a single TX BD. */
  77#define TX_BUF_SIZE     32
  78
  79/*
  80 * The number of jiffies to wait after receiving a close command before the
  81 * device is actually closed.  This allows the last few characters to be
  82 * sent over the wire.
  83 */
  84#define UCC_WAIT_CLOSING 100
  85
  86struct ucc_uart_pram {
  87	struct ucc_slow_pram common;
  88	u8 res1[8];     	/* reserved */
  89	__be16 maxidl;  	/* Maximum idle chars */
  90	__be16 idlc;    	/* temp idle counter */
  91	__be16 brkcr;   	/* Break count register */
  92	__be16 parec;   	/* receive parity error counter */
  93	__be16 frmec;   	/* receive framing error counter */
  94	__be16 nosec;   	/* receive noise counter */
  95	__be16 brkec;   	/* receive break condition counter */
  96	__be16 brkln;   	/* last received break length */
  97	__be16 uaddr[2];	/* UART address character 1 & 2 */
  98	__be16 rtemp;   	/* Temp storage */
  99	__be16 toseq;   	/* Transmit out of sequence char */
 100	__be16 cchars[8];       /* control characters 1-8 */
 101	__be16 rccm;    	/* receive control character mask */
 102	__be16 rccr;    	/* receive control character register */
 103	__be16 rlbc;    	/* receive last break character */
 104	__be16 res2;    	/* reserved */
 105	__be32 res3;    	/* reserved, should be cleared */
 106	u8 res4;		/* reserved, should be cleared */
 107	u8 res5[3];     	/* reserved, should be cleared */
 108	__be32 res6;    	/* reserved, should be cleared */
 109	__be32 res7;    	/* reserved, should be cleared */
 110	__be32 res8;    	/* reserved, should be cleared */
 111	__be32 res9;    	/* reserved, should be cleared */
 112	__be32 res10;   	/* reserved, should be cleared */
 113	__be32 res11;   	/* reserved, should be cleared */
 114	__be32 res12;   	/* reserved, should be cleared */
 115	__be32 res13;   	/* reserved, should be cleared */
 116/* The rest is for Soft-UART only */
 117	__be16 supsmr;  	/* 0x90, Shadow UPSMR */
 118	__be16 res92;   	/* 0x92, reserved, initialize to 0 */
 119	__be32 rx_state;	/* 0x94, RX state, initialize to 0 */
 120	__be32 rx_cnt;  	/* 0x98, RX count, initialize to 0 */
 121	u8 rx_length;   	/* 0x9C, Char length, set to 1+CL+PEN+1+SL */
 122	u8 rx_bitmark;  	/* 0x9D, reserved, initialize to 0 */
 123	u8 rx_temp_dlst_qe;     /* 0x9E, reserved, initialize to 0 */
 124	u8 res14[0xBC - 0x9F];  /* reserved */
 125	__be32 dump_ptr;	/* 0xBC, Dump pointer */
 126	__be32 rx_frame_rem;    /* 0xC0, reserved, initialize to 0 */
 127	u8 rx_frame_rem_size;   /* 0xC4, reserved, initialize to 0 */
 128	u8 tx_mode;     	/* 0xC5, mode, 0=AHDLC, 1=UART */
 129	__be16 tx_state;	/* 0xC6, TX state */
 130	u8 res15[0xD0 - 0xC8];  /* reserved */
 131	__be32 resD0;   	/* 0xD0, reserved, initialize to 0 */
 132	u8 resD4;       	/* 0xD4, reserved, initialize to 0 */
 133	__be16 resD5;   	/* 0xD5, reserved, initialize to 0 */
 134} __attribute__ ((packed));
 135
 136/* SUPSMR definitions, for Soft-UART only */
 137#define UCC_UART_SUPSMR_SL      	0x8000
 138#define UCC_UART_SUPSMR_RPM_MASK	0x6000
 139#define UCC_UART_SUPSMR_RPM_ODD 	0x0000
 140#define UCC_UART_SUPSMR_RPM_LOW 	0x2000
 141#define UCC_UART_SUPSMR_RPM_EVEN	0x4000
 142#define UCC_UART_SUPSMR_RPM_HIGH	0x6000
 143#define UCC_UART_SUPSMR_PEN     	0x1000
 144#define UCC_UART_SUPSMR_TPM_MASK	0x0C00
 145#define UCC_UART_SUPSMR_TPM_ODD 	0x0000
 146#define UCC_UART_SUPSMR_TPM_LOW 	0x0400
 147#define UCC_UART_SUPSMR_TPM_EVEN	0x0800
 148#define UCC_UART_SUPSMR_TPM_HIGH	0x0C00
 149#define UCC_UART_SUPSMR_FRZ     	0x0100
 150#define UCC_UART_SUPSMR_UM_MASK 	0x00c0
 151#define UCC_UART_SUPSMR_UM_NORMAL       0x0000
 152#define UCC_UART_SUPSMR_UM_MAN_MULTI    0x0040
 153#define UCC_UART_SUPSMR_UM_AUTO_MULTI   0x00c0
 154#define UCC_UART_SUPSMR_CL_MASK 	0x0030
 155#define UCC_UART_SUPSMR_CL_8    	0x0030
 156#define UCC_UART_SUPSMR_CL_7    	0x0020
 157#define UCC_UART_SUPSMR_CL_6    	0x0010
 158#define UCC_UART_SUPSMR_CL_5    	0x0000
 159
 160#define UCC_UART_TX_STATE_AHDLC 	0x00
 161#define UCC_UART_TX_STATE_UART  	0x01
 162#define UCC_UART_TX_STATE_X1    	0x00
 163#define UCC_UART_TX_STATE_X16   	0x80
 164
 165#define UCC_UART_PRAM_ALIGNMENT 0x100
 166
 167#define UCC_UART_SIZE_OF_BD     UCC_SLOW_SIZE_OF_BD
 168#define NUM_CONTROL_CHARS       8
 169
 170/* Private per-port data structure */
 171struct uart_qe_port {
 172	struct uart_port port;
 173	struct ucc_slow __iomem *uccp;
 174	struct ucc_uart_pram __iomem *uccup;
 175	struct ucc_slow_info us_info;
 176	struct ucc_slow_private *us_private;
 177	struct device_node *np;
 178	unsigned int ucc_num;   /* First ucc is 0, not 1 */
 179
 180	u16 rx_nrfifos;
 181	u16 rx_fifosize;
 182	u16 tx_nrfifos;
 183	u16 tx_fifosize;
 184	int wait_closing;
 185	u32 flags;
 186	struct qe_bd *rx_bd_base;
 187	struct qe_bd *rx_cur;
 188	struct qe_bd *tx_bd_base;
 189	struct qe_bd *tx_cur;
 190	unsigned char *tx_buf;
 191	unsigned char *rx_buf;
 192	void *bd_virt;  	/* virtual address of the BD buffers */
 193	dma_addr_t bd_dma_addr; /* bus address of the BD buffers */
 194	unsigned int bd_size;   /* size of BD buffer space */
 195};
 196
 197static struct uart_driver ucc_uart_driver = {
 198	.owner  	= THIS_MODULE,
 199	.driver_name    = "ucc_uart",
 200	.dev_name       = "ttyQE",
 201	.major  	= SERIAL_QE_MAJOR,
 202	.minor  	= SERIAL_QE_MINOR,
 203	.nr     	= UCC_MAX_UART,
 204};
 205
 206/*
 207 * Virtual to physical address translation.
 208 *
 209 * Given the virtual address for a character buffer, this function returns
 210 * the physical (DMA) equivalent.
 211 */
 212static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port)
 213{
 214	if (likely((addr >= qe_port->bd_virt)) &&
 215	    (addr < (qe_port->bd_virt + qe_port->bd_size)))
 216		return qe_port->bd_dma_addr + (addr - qe_port->bd_virt);
 217
 218	/* something nasty happened */
 219	printk(KERN_ERR "%s: addr=%p\n", __func__, addr);
 220	BUG();
 221	return 0;
 222}
 223
 224/*
 225 * Physical to virtual address translation.
 226 *
 227 * Given the physical (DMA) address for a character buffer, this function
 228 * returns the virtual equivalent.
 229 */
 230static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port)
 231{
 232	/* sanity check */
 233	if (likely((addr >= qe_port->bd_dma_addr) &&
 234		   (addr < (qe_port->bd_dma_addr + qe_port->bd_size))))
 235		return qe_port->bd_virt + (addr - qe_port->bd_dma_addr);
 236
 237	/* something nasty happened */
 238	printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr);
 239	BUG();
 240	return NULL;
 241}
 242
 243/*
 244 * Return 1 if the QE is done transmitting all buffers for this port
 245 *
 246 * This function scans each BD in sequence.  If we find a BD that is not
 247 * ready (READY=1), then we return 0 indicating that the QE is still sending
 248 * data.  If we reach the last BD (WRAP=1), then we know we've scanned
 249 * the entire list, and all BDs are done.
 250 */
 251static unsigned int qe_uart_tx_empty(struct uart_port *port)
 252{
 253	struct uart_qe_port *qe_port =
 254		container_of(port, struct uart_qe_port, port);
 255	struct qe_bd *bdp = qe_port->tx_bd_base;
 256
 257	while (1) {
 258		if (in_be16(&bdp->status) & BD_SC_READY)
 259			/* This BD is not done, so return "not done" */
 260			return 0;
 261
 262		if (in_be16(&bdp->status) & BD_SC_WRAP)
 263			/*
 264			 * This BD is done and it's the last one, so return
 265			 * "done"
 266			 */
 267			return 1;
 268
 269		bdp++;
 270	};
 271}
 272
 273/*
 274 * Set the modem control lines
 275 *
 276 * Although the QE can control the modem control lines (e.g. CTS), we
 277 * don't need that support. This function must exist, however, otherwise
 278 * the kernel will panic.
 279 */
 280void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
 281{
 282}
 283
 284/*
 285 * Get the current modem control line status
 286 *
 287 * Although the QE can control the modem control lines (e.g. CTS), this
 288 * driver currently doesn't support that, so we always return Carrier
 289 * Detect, Data Set Ready, and Clear To Send.
 290 */
 291static unsigned int qe_uart_get_mctrl(struct uart_port *port)
 292{
 293	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 294}
 295
 296/*
 297 * Disable the transmit interrupt.
 298 *
 299 * Although this function is called "stop_tx", it does not actually stop
 300 * transmission of data.  Instead, it tells the QE to not generate an
 301 * interrupt when the UCC is finished sending characters.
 302 */
 303static void qe_uart_stop_tx(struct uart_port *port)
 304{
 305	struct uart_qe_port *qe_port =
 306		container_of(port, struct uart_qe_port, port);
 307
 308	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
 309}
 310
 311/*
 312 * Transmit as many characters to the HW as possible.
 313 *
 314 * This function will attempt to stuff of all the characters from the
 315 * kernel's transmit buffer into TX BDs.
 316 *
 317 * A return value of non-zero indicates that it successfully stuffed all
 318 * characters from the kernel buffer.
 319 *
 320 * A return value of zero indicates that there are still characters in the
 321 * kernel's buffer that have not been transmitted, but there are no more BDs
 322 * available.  This function should be called again after a BD has been made
 323 * available.
 324 */
 325static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
 326{
 327	struct qe_bd *bdp;
 328	unsigned char *p;
 329	unsigned int count;
 330	struct uart_port *port = &qe_port->port;
 331	struct circ_buf *xmit = &port->state->xmit;
 332
 333	bdp = qe_port->rx_cur;
 334
 335	/* Handle xon/xoff */
 336	if (port->x_char) {
 337		/* Pick next descriptor and fill from buffer */
 338		bdp = qe_port->tx_cur;
 339
 340		p = qe2cpu_addr(bdp->buf, qe_port);
 341
 342		*p++ = port->x_char;
 343		out_be16(&bdp->length, 1);
 344		setbits16(&bdp->status, BD_SC_READY);
 345		/* Get next BD. */
 346		if (in_be16(&bdp->status) & BD_SC_WRAP)
 347			bdp = qe_port->tx_bd_base;
 348		else
 349			bdp++;
 350		qe_port->tx_cur = bdp;
 351
 352		port->icount.tx++;
 353		port->x_char = 0;
 354		return 1;
 355	}
 356
 357	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 358		qe_uart_stop_tx(port);
 359		return 0;
 360	}
 361
 362	/* Pick next descriptor and fill from buffer */
 363	bdp = qe_port->tx_cur;
 364
 365	while (!(in_be16(&bdp->status) & BD_SC_READY) &&
 366	       (xmit->tail != xmit->head)) {
 367		count = 0;
 368		p = qe2cpu_addr(bdp->buf, qe_port);
 369		while (count < qe_port->tx_fifosize) {
 370			*p++ = xmit->buf[xmit->tail];
 371			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 372			port->icount.tx++;
 373			count++;
 374			if (xmit->head == xmit->tail)
 375				break;
 376		}
 377
 378		out_be16(&bdp->length, count);
 379		setbits16(&bdp->status, BD_SC_READY);
 380
 381		/* Get next BD. */
 382		if (in_be16(&bdp->status) & BD_SC_WRAP)
 383			bdp = qe_port->tx_bd_base;
 384		else
 385			bdp++;
 386	}
 387	qe_port->tx_cur = bdp;
 388
 389	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 390		uart_write_wakeup(port);
 391
 392	if (uart_circ_empty(xmit)) {
 393		/* The kernel buffer is empty, so turn off TX interrupts.  We
 394		   don't need to be told when the QE is finished transmitting
 395		   the data. */
 396		qe_uart_stop_tx(port);
 397		return 0;
 398	}
 399
 400	return 1;
 401}
 402
 403/*
 404 * Start transmitting data
 405 *
 406 * This function will start transmitting any available data, if the port
 407 * isn't already transmitting data.
 408 */
 409static void qe_uart_start_tx(struct uart_port *port)
 410{
 411	struct uart_qe_port *qe_port =
 412		container_of(port, struct uart_qe_port, port);
 413
 414	/* If we currently are transmitting, then just return */
 415	if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
 416		return;
 417
 418	/* Otherwise, pump the port and start transmission */
 419	if (qe_uart_tx_pump(qe_port))
 420		setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
 421}
 422
 423/*
 424 * Stop transmitting data
 425 */
 426static void qe_uart_stop_rx(struct uart_port *port)
 427{
 428	struct uart_qe_port *qe_port =
 429		container_of(port, struct uart_qe_port, port);
 430
 431	clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
 432}
 433
 434/*
 435 * Enable status change interrupts
 436 *
 437 * We don't support status change interrupts, but we need to define this
 438 * function otherwise the kernel will panic.
 439 */
 440static void qe_uart_enable_ms(struct uart_port *port)
 441{
 442}
 443
 444/* Start or stop sending  break signal
 445 *
 446 * This function controls the sending of a break signal.  If break_state=1,
 447 * then we start sending a break signal.  If break_state=0, then we stop
 448 * sending the break signal.
 449 */
 450static void qe_uart_break_ctl(struct uart_port *port, int break_state)
 451{
 452	struct uart_qe_port *qe_port =
 453		container_of(port, struct uart_qe_port, port);
 454
 455	if (break_state)
 456		ucc_slow_stop_tx(qe_port->us_private);
 457	else
 458		ucc_slow_restart_tx(qe_port->us_private);
 459}
 460
 461/* ISR helper function for receiving character.
 462 *
 463 * This function is called by the ISR to handling receiving characters
 464 */
 465static void qe_uart_int_rx(struct uart_qe_port *qe_port)
 466{
 467	int i;
 468	unsigned char ch, *cp;
 469	struct uart_port *port = &qe_port->port;
 470	struct tty_struct *tty = port->state->port.tty;
 471	struct qe_bd *bdp;
 472	u16 status;
 473	unsigned int flg;
 474
 475	/* Just loop through the closed BDs and copy the characters into
 476	 * the buffer.
 477	 */
 478	bdp = qe_port->rx_cur;
 479	while (1) {
 480		status = in_be16(&bdp->status);
 481
 482		/* If this one is empty, then we assume we've read them all */
 483		if (status & BD_SC_EMPTY)
 484			break;
 485
 486		/* get number of characters, and check space in RX buffer */
 487		i = in_be16(&bdp->length);
 488
 489		/* If we don't have enough room in RX buffer for the entire BD,
 490		 * then we try later, which will be the next RX interrupt.
 491		 */
 492		if (tty_buffer_request_room(tty, i) < i) {
 493			dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n");
 494			return;
 495		}
 496
 497		/* get pointer */
 498		cp = qe2cpu_addr(bdp->buf, qe_port);
 499
 500		/* loop through the buffer */
 501		while (i-- > 0) {
 502			ch = *cp++;
 503			port->icount.rx++;
 504			flg = TTY_NORMAL;
 505
 506			if (!i && status &
 507			    (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV))
 508				goto handle_error;
 509			if (uart_handle_sysrq_char(port, ch))
 510				continue;
 511
 512error_return:
 513			tty_insert_flip_char(tty, ch, flg);
 514
 515		}
 516
 517		/* This BD is ready to be used again. Clear status. get next */
 518		clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
 519			BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
 520		if (in_be16(&bdp->status) & BD_SC_WRAP)
 521			bdp = qe_port->rx_bd_base;
 522		else
 523			bdp++;
 524
 525	}
 526
 527	/* Write back buffer pointer */
 528	qe_port->rx_cur = bdp;
 529
 530	/* Activate BH processing */
 531	tty_flip_buffer_push(tty);
 532
 533	return;
 534
 535	/* Error processing */
 536
 537handle_error:
 538	/* Statistics */
 539	if (status & BD_SC_BR)
 540		port->icount.brk++;
 541	if (status & BD_SC_PR)
 542		port->icount.parity++;
 543	if (status & BD_SC_FR)
 544		port->icount.frame++;
 545	if (status & BD_SC_OV)
 546		port->icount.overrun++;
 547
 548	/* Mask out ignored conditions */
 549	status &= port->read_status_mask;
 550
 551	/* Handle the remaining ones */
 552	if (status & BD_SC_BR)
 553		flg = TTY_BREAK;
 554	else if (status & BD_SC_PR)
 555		flg = TTY_PARITY;
 556	else if (status & BD_SC_FR)
 557		flg = TTY_FRAME;
 558
 559	/* Overrun does not affect the current character ! */
 560	if (status & BD_SC_OV)
 561		tty_insert_flip_char(tty, 0, TTY_OVERRUN);
 562#ifdef SUPPORT_SYSRQ
 563	port->sysrq = 0;
 564#endif
 565	goto error_return;
 566}
 567
 568/* Interrupt handler
 569 *
 570 * This interrupt handler is called after a BD is processed.
 571 */
 572static irqreturn_t qe_uart_int(int irq, void *data)
 573{
 574	struct uart_qe_port *qe_port = (struct uart_qe_port *) data;
 575	struct ucc_slow __iomem *uccp = qe_port->uccp;
 576	u16 events;
 577
 578	/* Clear the interrupts */
 579	events = in_be16(&uccp->ucce);
 580	out_be16(&uccp->ucce, events);
 581
 582	if (events & UCC_UART_UCCE_BRKE)
 583		uart_handle_break(&qe_port->port);
 584
 585	if (events & UCC_UART_UCCE_RX)
 586		qe_uart_int_rx(qe_port);
 587
 588	if (events & UCC_UART_UCCE_TX)
 589		qe_uart_tx_pump(qe_port);
 590
 591	return events ? IRQ_HANDLED : IRQ_NONE;
 592}
 593
 594/* Initialize buffer descriptors
 595 *
 596 * This function initializes all of the RX and TX buffer descriptors.
 597 */
 598static void qe_uart_initbd(struct uart_qe_port *qe_port)
 599{
 600	int i;
 601	void *bd_virt;
 602	struct qe_bd *bdp;
 603
 604	/* Set the physical address of the host memory buffers in the buffer
 605	 * descriptors, and the virtual address for us to work with.
 606	 */
 607	bd_virt = qe_port->bd_virt;
 608	bdp = qe_port->rx_bd_base;
 609	qe_port->rx_cur = qe_port->rx_bd_base;
 610	for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
 611		out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
 612		out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
 613		out_be16(&bdp->length, 0);
 614		bd_virt += qe_port->rx_fifosize;
 615		bdp++;
 616	}
 617
 618	/* */
 619	out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
 620	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
 621	out_be16(&bdp->length, 0);
 622
 623	/* Set the physical address of the host memory
 624	 * buffers in the buffer descriptors, and the
 625	 * virtual address for us to work with.
 626	 */
 627	bd_virt = qe_port->bd_virt +
 628		L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
 629	qe_port->tx_cur = qe_port->tx_bd_base;
 630	bdp = qe_port->tx_bd_base;
 631	for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
 632		out_be16(&bdp->status, BD_SC_INTRPT);
 633		out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
 634		out_be16(&bdp->length, 0);
 635		bd_virt += qe_port->tx_fifosize;
 636		bdp++;
 637	}
 638
 639	/* Loopback requires the preamble bit to be set on the first TX BD */
 640#ifdef LOOPBACK
 641	setbits16(&qe_port->tx_cur->status, BD_SC_P);
 642#endif
 643
 644	out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
 645	out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
 646	out_be16(&bdp->length, 0);
 647}
 648
 649/*
 650 * Initialize a UCC for UART.
 651 *
 652 * This function configures a given UCC to be used as a UART device. Basic
 653 * UCC initialization is handled in qe_uart_request_port().  This function
 654 * does all the UART-specific stuff.
 655 */
 656static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
 657{
 658	u32 cecr_subblock;
 659	struct ucc_slow __iomem *uccp = qe_port->uccp;
 660	struct ucc_uart_pram *uccup = qe_port->uccup;
 661
 662	unsigned int i;
 663
 664	/* First, disable TX and RX in the UCC */
 665	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 666
 667	/* Program the UCC UART parameter RAM */
 668	out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
 669	out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
 670	out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
 671	out_be16(&uccup->maxidl, 0x10);
 672	out_be16(&uccup->brkcr, 1);
 673	out_be16(&uccup->parec, 0);
 674	out_be16(&uccup->frmec, 0);
 675	out_be16(&uccup->nosec, 0);
 676	out_be16(&uccup->brkec, 0);
 677	out_be16(&uccup->uaddr[0], 0);
 678	out_be16(&uccup->uaddr[1], 0);
 679	out_be16(&uccup->toseq, 0);
 680	for (i = 0; i < 8; i++)
 681		out_be16(&uccup->cchars[i], 0xC000);
 682	out_be16(&uccup->rccm, 0xc0ff);
 683
 684	/* Configure the GUMR registers for UART */
 685	if (soft_uart) {
 686		/* Soft-UART requires a 1X multiplier for TX */
 687		clrsetbits_be32(&uccp->gumr_l,
 688			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
 689			UCC_SLOW_GUMR_L_RDCR_MASK,
 690			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
 691			UCC_SLOW_GUMR_L_RDCR_16);
 692
 693		clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
 694			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
 695	} else {
 696		clrsetbits_be32(&uccp->gumr_l,
 697			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
 698			UCC_SLOW_GUMR_L_RDCR_MASK,
 699			UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
 700			UCC_SLOW_GUMR_L_RDCR_16);
 701
 702		clrsetbits_be32(&uccp->gumr_h,
 703			UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
 704			UCC_SLOW_GUMR_H_RFW);
 705	}
 706
 707#ifdef LOOPBACK
 708	clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
 709		UCC_SLOW_GUMR_L_DIAG_LOOP);
 710	clrsetbits_be32(&uccp->gumr_h,
 711		UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
 712		UCC_SLOW_GUMR_H_CDS);
 713#endif
 714
 715	/* Disable rx interrupts  and clear all pending events.  */
 716	out_be16(&uccp->uccm, 0);
 717	out_be16(&uccp->ucce, 0xffff);
 718	out_be16(&uccp->udsr, 0x7e7e);
 719
 720	/* Initialize UPSMR */
 721	out_be16(&uccp->upsmr, 0);
 722
 723	if (soft_uart) {
 724		out_be16(&uccup->supsmr, 0x30);
 725		out_be16(&uccup->res92, 0);
 726		out_be32(&uccup->rx_state, 0);
 727		out_be32(&uccup->rx_cnt, 0);
 728		out_8(&uccup->rx_bitmark, 0);
 729		out_8(&uccup->rx_length, 10);
 730		out_be32(&uccup->dump_ptr, 0x4000);
 731		out_8(&uccup->rx_temp_dlst_qe, 0);
 732		out_be32(&uccup->rx_frame_rem, 0);
 733		out_8(&uccup->rx_frame_rem_size, 0);
 734		/* Soft-UART requires TX to be 1X */
 735		out_8(&uccup->tx_mode,
 736			UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
 737		out_be16(&uccup->tx_state, 0);
 738		out_8(&uccup->resD4, 0);
 739		out_be16(&uccup->resD5, 0);
 740
 741		/* Set UART mode.
 742		 * Enable receive and transmit.
 743		 */
 744
 745		/* From the microcode errata:
 746		 * 1.GUMR_L register, set mode=0010 (QMC).
 747		 * 2.Set GUMR_H[17] bit. (UART/AHDLC mode).
 748		 * 3.Set GUMR_H[19:20] (Transparent mode)
 749		 * 4.Clear GUMR_H[26] (RFW)
 750		 * ...
 751		 * 6.Receiver must use 16x over sampling
 752		 */
 753		clrsetbits_be32(&uccp->gumr_l,
 754			UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
 755			UCC_SLOW_GUMR_L_RDCR_MASK,
 756			UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
 757			UCC_SLOW_GUMR_L_RDCR_16);
 758
 759		clrsetbits_be32(&uccp->gumr_h,
 760			UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
 761			UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
 762			UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
 763
 764#ifdef LOOPBACK
 765		clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
 766				UCC_SLOW_GUMR_L_DIAG_LOOP);
 767		clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
 768			  UCC_SLOW_GUMR_H_CDS);
 769#endif
 770
 771		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
 772		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 773			QE_CR_PROTOCOL_UNSPECIFIED, 0);
 774	} else {
 775		cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
 776		qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
 777			QE_CR_PROTOCOL_UART, 0);
 778	}
 779}
 780
 781/*
 782 * Initialize the port.
 783 */
 784static int qe_uart_startup(struct uart_port *port)
 785{
 786	struct uart_qe_port *qe_port =
 787		container_of(port, struct uart_qe_port, port);
 788	int ret;
 789
 790	/*
 791	 * If we're using Soft-UART mode, then we need to make sure the
 792	 * firmware has been uploaded first.
 793	 */
 794	if (soft_uart && !firmware_loaded) {
 795		dev_err(port->dev, "Soft-UART firmware not uploaded\n");
 796		return -ENODEV;
 797	}
 798
 799	qe_uart_initbd(qe_port);
 800	qe_uart_init_ucc(qe_port);
 801
 802	/* Install interrupt handler. */
 803	ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart",
 804		qe_port);
 805	if (ret) {
 806		dev_err(port->dev, "could not claim IRQ %u\n", port->irq);
 807		return ret;
 808	}
 809
 810	/* Startup rx-int */
 811	setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
 812	ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 813
 814	return 0;
 815}
 816
 817/*
 818 * Shutdown the port.
 819 */
 820static void qe_uart_shutdown(struct uart_port *port)
 821{
 822	struct uart_qe_port *qe_port =
 823		container_of(port, struct uart_qe_port, port);
 824	struct ucc_slow __iomem *uccp = qe_port->uccp;
 825	unsigned int timeout = 20;
 826
 827	/* Disable RX and TX */
 828
 829	/* Wait for all the BDs marked sent */
 830	while (!qe_uart_tx_empty(port)) {
 831		if (!--timeout) {
 832			dev_warn(port->dev, "shutdown timeout\n");
 833			break;
 834		}
 835		set_current_state(TASK_UNINTERRUPTIBLE);
 836		schedule_timeout(2);
 837	}
 838
 839	if (qe_port->wait_closing) {
 840		/* Wait a bit longer */
 841		set_current_state(TASK_UNINTERRUPTIBLE);
 842		schedule_timeout(qe_port->wait_closing);
 843	}
 844
 845	/* Stop uarts */
 846	ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
 847	clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
 848
 849	/* Shut them really down and reinit buffer descriptors */
 850	ucc_slow_graceful_stop_tx(qe_port->us_private);
 851	qe_uart_initbd(qe_port);
 852
 853	free_irq(port->irq, qe_port);
 854}
 855
 856/*
 857 * Set the serial port parameters.
 858 */
 859static void qe_uart_set_termios(struct uart_port *port,
 860				struct ktermios *termios, struct ktermios *old)
 861{
 862	struct uart_qe_port *qe_port =
 863		container_of(port, struct uart_qe_port, port);
 864	struct ucc_slow __iomem *uccp = qe_port->uccp;
 865	unsigned int baud;
 866	unsigned long flags;
 867	u16 upsmr = in_be16(&uccp->upsmr);
 868	struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
 869	u16 supsmr = in_be16(&uccup->supsmr);
 870	u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
 871
 872	/* Character length programmed into the mode register is the
 873	 * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
 874	 * 1 or 2 stop bits, minus 1.
 875	 * The value 'bits' counts this for us.
 876	 */
 877
 878	/* byte size */
 879	upsmr &= UCC_UART_UPSMR_CL_MASK;
 880	supsmr &= UCC_UART_SUPSMR_CL_MASK;
 881
 882	switch (termios->c_cflag & CSIZE) {
 883	case CS5:
 884		upsmr |= UCC_UART_UPSMR_CL_5;
 885		supsmr |= UCC_UART_SUPSMR_CL_5;
 886		char_length += 5;
 887		break;
 888	case CS6:
 889		upsmr |= UCC_UART_UPSMR_CL_6;
 890		supsmr |= UCC_UART_SUPSMR_CL_6;
 891		char_length += 6;
 892		break;
 893	case CS7:
 894		upsmr |= UCC_UART_UPSMR_CL_7;
 895		supsmr |= UCC_UART_SUPSMR_CL_7;
 896		char_length += 7;
 897		break;
 898	default:	/* case CS8 */
 899		upsmr |= UCC_UART_UPSMR_CL_8;
 900		supsmr |= UCC_UART_SUPSMR_CL_8;
 901		char_length += 8;
 902		break;
 903	}
 904
 905	/* If CSTOPB is set, we want two stop bits */
 906	if (termios->c_cflag & CSTOPB) {
 907		upsmr |= UCC_UART_UPSMR_SL;
 908		supsmr |= UCC_UART_SUPSMR_SL;
 909		char_length++;  /* + SL */
 910	}
 911
 912	if (termios->c_cflag & PARENB) {
 913		upsmr |= UCC_UART_UPSMR_PEN;
 914		supsmr |= UCC_UART_SUPSMR_PEN;
 915		char_length++;  /* + PEN */
 916
 917		if (!(termios->c_cflag & PARODD)) {
 918			upsmr &= ~(UCC_UART_UPSMR_RPM_MASK |
 919				   UCC_UART_UPSMR_TPM_MASK);
 920			upsmr |= UCC_UART_UPSMR_RPM_EVEN |
 921				UCC_UART_UPSMR_TPM_EVEN;
 922			supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK |
 923				    UCC_UART_SUPSMR_TPM_MASK);
 924			supsmr |= UCC_UART_SUPSMR_RPM_EVEN |
 925				UCC_UART_SUPSMR_TPM_EVEN;
 926		}
 927	}
 928
 929	/*
 930	 * Set up parity check flag
 931	 */
 932	port->read_status_mask = BD_SC_EMPTY | BD_SC_OV;
 933	if (termios->c_iflag & INPCK)
 934		port->read_status_mask |= BD_SC_FR | BD_SC_PR;
 935	if (termios->c_iflag & (BRKINT | PARMRK))
 936		port->read_status_mask |= BD_SC_BR;
 937
 938	/*
 939	 * Characters to ignore
 940	 */
 941	port->ignore_status_mask = 0;
 942	if (termios->c_iflag & IGNPAR)
 943		port->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
 944	if (termios->c_iflag & IGNBRK) {
 945		port->ignore_status_mask |= BD_SC_BR;
 946		/*
 947		 * If we're ignore parity and break indicators, ignore
 948		 * overruns too.  (For real raw support).
 949		 */
 950		if (termios->c_iflag & IGNPAR)
 951			port->ignore_status_mask |= BD_SC_OV;
 952	}
 953	/*
 954	 * !!! ignore all characters if CREAD is not set
 955	 */
 956	if ((termios->c_cflag & CREAD) == 0)
 957		port->read_status_mask &= ~BD_SC_EMPTY;
 958
 959	baud = uart_get_baud_rate(port, termios, old, 0, 115200);
 960
 961	/* Do we really need a spinlock here? */
 962	spin_lock_irqsave(&port->lock, flags);
 963
 
 
 
 964	out_be16(&uccp->upsmr, upsmr);
 965	if (soft_uart) {
 966		out_be16(&uccup->supsmr, supsmr);
 967		out_8(&uccup->rx_length, char_length);
 968
 969		/* Soft-UART requires a 1X multiplier for TX */
 970		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
 971		qe_setbrg(qe_port->us_info.tx_clock, baud, 1);
 972	} else {
 973		qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
 974		qe_setbrg(qe_port->us_info.tx_clock, baud, 16);
 975	}
 976
 977	spin_unlock_irqrestore(&port->lock, flags);
 978}
 979
 980/*
 981 * Return a pointer to a string that describes what kind of port this is.
 982 */
 983static const char *qe_uart_type(struct uart_port *port)
 984{
 985	return "QE";
 986}
 987
 988/*
 989 * Allocate any memory and I/O resources required by the port.
 990 */
 991static int qe_uart_request_port(struct uart_port *port)
 992{
 993	int ret;
 994	struct uart_qe_port *qe_port =
 995		container_of(port, struct uart_qe_port, port);
 996	struct ucc_slow_info *us_info = &qe_port->us_info;
 997	struct ucc_slow_private *uccs;
 998	unsigned int rx_size, tx_size;
 999	void *bd_virt;
1000	dma_addr_t bd_dma_addr = 0;
1001
1002	ret = ucc_slow_init(us_info, &uccs);
1003	if (ret) {
1004		dev_err(port->dev, "could not initialize UCC%u\n",
1005		       qe_port->ucc_num);
1006		return ret;
1007	}
1008
1009	qe_port->us_private = uccs;
1010	qe_port->uccp = uccs->us_regs;
1011	qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram;
1012	qe_port->rx_bd_base = uccs->rx_bd;
1013	qe_port->tx_bd_base = uccs->tx_bd;
1014
1015	/*
1016	 * Allocate the transmit and receive data buffers.
1017	 */
1018
1019	rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize);
1020	tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize);
1021
1022	bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr,
1023		GFP_KERNEL);
1024	if (!bd_virt) {
1025		dev_err(port->dev, "could not allocate buffer descriptors\n");
1026		return -ENOMEM;
1027	}
1028
1029	qe_port->bd_virt = bd_virt;
1030	qe_port->bd_dma_addr = bd_dma_addr;
1031	qe_port->bd_size = rx_size + tx_size;
1032
1033	qe_port->rx_buf = bd_virt;
1034	qe_port->tx_buf = qe_port->rx_buf + rx_size;
1035
1036	return 0;
1037}
1038
1039/*
1040 * Configure the port.
1041 *
1042 * We say we're a CPM-type port because that's mostly true.  Once the device
1043 * is configured, this driver operates almost identically to the CPM serial
1044 * driver.
1045 */
1046static void qe_uart_config_port(struct uart_port *port, int flags)
1047{
1048	if (flags & UART_CONFIG_TYPE) {
1049		port->type = PORT_CPM;
1050		qe_uart_request_port(port);
1051	}
1052}
1053
1054/*
1055 * Release any memory and I/O resources that were allocated in
1056 * qe_uart_request_port().
1057 */
1058static void qe_uart_release_port(struct uart_port *port)
1059{
1060	struct uart_qe_port *qe_port =
1061		container_of(port, struct uart_qe_port, port);
1062	struct ucc_slow_private *uccs = qe_port->us_private;
1063
1064	dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt,
1065			  qe_port->bd_dma_addr);
1066
1067	ucc_slow_free(uccs);
1068}
1069
1070/*
1071 * Verify that the data in serial_struct is suitable for this device.
1072 */
1073static int qe_uart_verify_port(struct uart_port *port,
1074			       struct serial_struct *ser)
1075{
1076	if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM)
1077		return -EINVAL;
1078
1079	if (ser->irq < 0 || ser->irq >= nr_irqs)
1080		return -EINVAL;
1081
1082	if (ser->baud_base < 9600)
1083		return -EINVAL;
1084
1085	return 0;
1086}
1087/* UART operations
1088 *
1089 * Details on these functions can be found in Documentation/serial/driver
1090 */
1091static struct uart_ops qe_uart_pops = {
1092	.tx_empty       = qe_uart_tx_empty,
1093	.set_mctrl      = qe_uart_set_mctrl,
1094	.get_mctrl      = qe_uart_get_mctrl,
1095	.stop_tx	= qe_uart_stop_tx,
1096	.start_tx       = qe_uart_start_tx,
1097	.stop_rx	= qe_uart_stop_rx,
1098	.enable_ms      = qe_uart_enable_ms,
1099	.break_ctl      = qe_uart_break_ctl,
1100	.startup	= qe_uart_startup,
1101	.shutdown       = qe_uart_shutdown,
1102	.set_termios    = qe_uart_set_termios,
1103	.type   	= qe_uart_type,
1104	.release_port   = qe_uart_release_port,
1105	.request_port   = qe_uart_request_port,
1106	.config_port    = qe_uart_config_port,
1107	.verify_port    = qe_uart_verify_port,
1108};
1109
1110/*
1111 * Obtain the SOC model number and revision level
1112 *
1113 * This function parses the device tree to obtain the SOC model.  It then
1114 * reads the SVR register to the revision.
1115 *
1116 * The device tree stores the SOC model two different ways.
1117 *
1118 * The new way is:
1119 *
1120 *      	cpu@0 {
1121 *      		compatible = "PowerPC,8323";
1122 *      		device_type = "cpu";
1123 *      		...
1124 *
1125 *
1126 * The old way is:
1127 *      	 PowerPC,8323@0 {
1128 *      		device_type = "cpu";
1129 *      		...
1130 *
1131 * This code first checks the new way, and then the old way.
1132 */
1133static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l)
1134{
1135	struct device_node *np;
1136	const char *soc_string;
1137	unsigned int svr;
1138	unsigned int soc;
1139
1140	/* Find the CPU node */
1141	np = of_find_node_by_type(NULL, "cpu");
1142	if (!np)
1143		return 0;
1144	/* Find the compatible property */
1145	soc_string = of_get_property(np, "compatible", NULL);
1146	if (!soc_string)
1147		/* No compatible property, so try the name. */
1148		soc_string = np->name;
1149
1150	/* Extract the SOC number from the "PowerPC," string */
1151	if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc)
1152		return 0;
1153
1154	/* Get the revision from the SVR */
1155	svr = mfspr(SPRN_SVR);
1156	*rev_h = (svr >> 4) & 0xf;
1157	*rev_l = svr & 0xf;
1158
1159	return soc;
1160}
1161
1162/*
1163 * requst_firmware_nowait() callback function
1164 *
1165 * This function is called by the kernel when a firmware is made available,
1166 * or if it times out waiting for the firmware.
1167 */
1168static void uart_firmware_cont(const struct firmware *fw, void *context)
1169{
1170	struct qe_firmware *firmware;
1171	struct device *dev = context;
1172	int ret;
1173
1174	if (!fw) {
1175		dev_err(dev, "firmware not found\n");
1176		return;
1177	}
1178
1179	firmware = (struct qe_firmware *) fw->data;
1180
1181	if (firmware->header.length != fw->size) {
1182		dev_err(dev, "invalid firmware\n");
1183		goto out;
1184	}
1185
1186	ret = qe_upload_firmware(firmware);
1187	if (ret) {
1188		dev_err(dev, "could not load firmware\n");
1189		goto out;
1190	}
1191
1192	firmware_loaded = 1;
1193 out:
1194	release_firmware(fw);
1195}
1196
1197static int ucc_uart_probe(struct platform_device *ofdev)
1198{
1199	struct device_node *np = ofdev->dev.of_node;
1200	const unsigned int *iprop;      /* Integer OF properties */
1201	const char *sprop;      /* String OF properties */
1202	struct uart_qe_port *qe_port = NULL;
1203	struct resource res;
1204	int ret;
1205
1206	/*
1207	 * Determine if we need Soft-UART mode
1208	 */
1209	if (of_find_property(np, "soft-uart", NULL)) {
1210		dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
1211		soft_uart = 1;
1212	}
1213
1214	/*
1215	 * If we are using Soft-UART, determine if we need to upload the
1216	 * firmware, too.
1217	 */
1218	if (soft_uart) {
1219		struct qe_firmware_info *qe_fw_info;
1220
1221		qe_fw_info = qe_get_firmware_info();
1222
1223		/* Check if the firmware has been uploaded. */
1224		if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
1225			firmware_loaded = 1;
1226		} else {
1227			char filename[32];
1228			unsigned int soc;
1229			unsigned int rev_h;
1230			unsigned int rev_l;
1231
1232			soc = soc_info(&rev_h, &rev_l);
1233			if (!soc) {
1234				dev_err(&ofdev->dev, "unknown CPU model\n");
1235				return -ENXIO;
1236			}
1237			sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
1238				soc, rev_h, rev_l);
1239
1240			dev_info(&ofdev->dev, "waiting for firmware %s\n",
1241				filename);
1242
1243			/*
1244			 * We call request_firmware_nowait instead of
1245			 * request_firmware so that the driver can load and
1246			 * initialize the ports without holding up the rest of
1247			 * the kernel.  If hotplug support is enabled in the
1248			 * kernel, then we use it.
1249			 */
1250			ret = request_firmware_nowait(THIS_MODULE,
1251				FW_ACTION_HOTPLUG, filename, &ofdev->dev,
1252				GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
1253			if (ret) {
1254				dev_err(&ofdev->dev,
1255					"could not load firmware %s\n",
1256					filename);
1257				return ret;
1258			}
1259		}
1260	}
1261
1262	qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
1263	if (!qe_port) {
1264		dev_err(&ofdev->dev, "can't allocate QE port structure\n");
1265		return -ENOMEM;
1266	}
1267
1268	/* Search for IRQ and mapbase */
1269	ret = of_address_to_resource(np, 0, &res);
1270	if (ret) {
1271		dev_err(&ofdev->dev, "missing 'reg' property in device tree\n");
1272		goto out_free;
1273	}
1274	if (!res.start) {
1275		dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n");
1276		ret = -EINVAL;
1277		goto out_free;
1278	}
1279	qe_port->port.mapbase = res.start;
1280
1281	/* Get the UCC number (device ID) */
1282	/* UCCs are numbered 1-7 */
1283	iprop = of_get_property(np, "cell-index", NULL);
1284	if (!iprop) {
1285		iprop = of_get_property(np, "device-id", NULL);
1286		if (!iprop) {
1287			dev_err(&ofdev->dev, "UCC is unspecified in "
1288				"device tree\n");
1289			ret = -EINVAL;
1290			goto out_free;
1291		}
1292	}
1293
1294	if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
1295		dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
1296		ret = -ENODEV;
1297		goto out_free;
1298	}
1299	qe_port->ucc_num = *iprop - 1;
1300
1301	/*
1302	 * In the future, we should not require the BRG to be specified in the
1303	 * device tree.  If no clock-source is specified, then just pick a BRG
1304	 * to use.  This requires a new QE library function that manages BRG
1305	 * assignments.
1306	 */
1307
1308	sprop = of_get_property(np, "rx-clock-name", NULL);
1309	if (!sprop) {
1310		dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n");
1311		ret = -ENODEV;
1312		goto out_free;
1313	}
1314
1315	qe_port->us_info.rx_clock = qe_clock_source(sprop);
1316	if ((qe_port->us_info.rx_clock < QE_BRG1) ||
1317	    (qe_port->us_info.rx_clock > QE_BRG16)) {
1318		dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n");
1319		ret = -ENODEV;
1320		goto out_free;
1321	}
1322
1323#ifdef LOOPBACK
1324	/* In internal loopback mode, TX and RX must use the same clock */
1325	qe_port->us_info.tx_clock = qe_port->us_info.rx_clock;
1326#else
1327	sprop = of_get_property(np, "tx-clock-name", NULL);
1328	if (!sprop) {
1329		dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n");
1330		ret = -ENODEV;
1331		goto out_free;
1332	}
1333	qe_port->us_info.tx_clock = qe_clock_source(sprop);
1334#endif
1335	if ((qe_port->us_info.tx_clock < QE_BRG1) ||
1336	    (qe_port->us_info.tx_clock > QE_BRG16)) {
1337		dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n");
1338		ret = -ENODEV;
1339		goto out_free;
1340	}
1341
1342	/* Get the port number, numbered 0-3 */
1343	iprop = of_get_property(np, "port-number", NULL);
1344	if (!iprop) {
1345		dev_err(&ofdev->dev, "missing port-number in device tree\n");
1346		ret = -EINVAL;
1347		goto out_free;
1348	}
1349	qe_port->port.line = *iprop;
1350	if (qe_port->port.line >= UCC_MAX_UART) {
1351		dev_err(&ofdev->dev, "port-number must be 0-%u\n",
1352			UCC_MAX_UART - 1);
1353		ret = -EINVAL;
1354		goto out_free;
1355	}
1356
1357	qe_port->port.irq = irq_of_parse_and_map(np, 0);
1358	if (qe_port->port.irq == NO_IRQ) {
1359		dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n",
1360		       qe_port->ucc_num + 1);
1361		ret = -EINVAL;
1362		goto out_free;
1363	}
1364
1365	/*
1366	 * Newer device trees have an "fsl,qe" compatible property for the QE
1367	 * node, but we still need to support older device trees.
1368	 */
1369	np = of_find_compatible_node(NULL, NULL, "fsl,qe");
1370	if (!np) {
1371		np = of_find_node_by_type(NULL, "qe");
1372		if (!np) {
1373			dev_err(&ofdev->dev, "could not find 'qe' node\n");
1374			ret = -EINVAL;
1375			goto out_free;
1376		}
1377	}
1378
1379	iprop = of_get_property(np, "brg-frequency", NULL);
1380	if (!iprop) {
1381		dev_err(&ofdev->dev,
1382		       "missing brg-frequency in device tree\n");
1383		ret = -EINVAL;
1384		goto out_np;
1385	}
1386
1387	if (*iprop)
1388		qe_port->port.uartclk = *iprop;
1389	else {
1390		/*
1391		 * Older versions of U-Boot do not initialize the brg-frequency
1392		 * property, so in this case we assume the BRG frequency is
1393		 * half the QE bus frequency.
1394		 */
1395		iprop = of_get_property(np, "bus-frequency", NULL);
1396		if (!iprop) {
1397			dev_err(&ofdev->dev,
1398				"missing QE bus-frequency in device tree\n");
1399			ret = -EINVAL;
1400			goto out_np;
1401		}
1402		if (*iprop)
1403			qe_port->port.uartclk = *iprop / 2;
1404		else {
1405			dev_err(&ofdev->dev,
1406				"invalid QE bus-frequency in device tree\n");
1407			ret = -EINVAL;
1408			goto out_np;
1409		}
1410	}
1411
1412	spin_lock_init(&qe_port->port.lock);
1413	qe_port->np = np;
1414	qe_port->port.dev = &ofdev->dev;
1415	qe_port->port.ops = &qe_uart_pops;
1416	qe_port->port.iotype = UPIO_MEM;
1417
1418	qe_port->tx_nrfifos = TX_NUM_FIFO;
1419	qe_port->tx_fifosize = TX_BUF_SIZE;
1420	qe_port->rx_nrfifos = RX_NUM_FIFO;
1421	qe_port->rx_fifosize = RX_BUF_SIZE;
1422
1423	qe_port->wait_closing = UCC_WAIT_CLOSING;
1424	qe_port->port.fifosize = 512;
1425	qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
1426
1427	qe_port->us_info.ucc_num = qe_port->ucc_num;
1428	qe_port->us_info.regs = (phys_addr_t) res.start;
1429	qe_port->us_info.irq = qe_port->port.irq;
1430
1431	qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos;
1432	qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos;
1433
1434	/* Make sure ucc_slow_init() initializes both TX and RX */
1435	qe_port->us_info.init_tx = 1;
1436	qe_port->us_info.init_rx = 1;
1437
1438	/* Add the port to the uart sub-system.  This will cause
1439	 * qe_uart_config_port() to be called, so the us_info structure must
1440	 * be initialized.
1441	 */
1442	ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port);
1443	if (ret) {
1444		dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n",
1445		       qe_port->port.line);
1446		goto out_np;
1447	}
1448
1449	dev_set_drvdata(&ofdev->dev, qe_port);
1450
1451	dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n",
1452		qe_port->ucc_num + 1, qe_port->port.line);
1453
1454	/* Display the mknod command for this device */
1455	dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n",
1456	       qe_port->port.line, SERIAL_QE_MAJOR,
1457	       SERIAL_QE_MINOR + qe_port->port.line);
1458
1459	return 0;
1460out_np:
1461	of_node_put(np);
1462out_free:
1463	kfree(qe_port);
1464	return ret;
1465}
1466
1467static int ucc_uart_remove(struct platform_device *ofdev)
1468{
1469	struct uart_qe_port *qe_port = dev_get_drvdata(&ofdev->dev);
1470
1471	dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line);
1472
1473	uart_remove_one_port(&ucc_uart_driver, &qe_port->port);
1474
1475	dev_set_drvdata(&ofdev->dev, NULL);
1476	kfree(qe_port);
1477
1478	return 0;
1479}
1480
1481static struct of_device_id ucc_uart_match[] = {
1482	{
1483		.type = "serial",
1484		.compatible = "ucc_uart",
1485	},
1486	{},
1487};
1488MODULE_DEVICE_TABLE(of, ucc_uart_match);
1489
1490static struct platform_driver ucc_uart_of_driver = {
1491	.driver = {
1492		.name = "ucc_uart",
1493		.owner = THIS_MODULE,
1494		.of_match_table    = ucc_uart_match,
1495	},
1496	.probe  	= ucc_uart_probe,
1497	.remove 	= ucc_uart_remove,
1498};
1499
1500static int __init ucc_uart_init(void)
1501{
1502	int ret;
1503
1504	printk(KERN_INFO "Freescale QUICC Engine UART device driver\n");
1505#ifdef LOOPBACK
1506	printk(KERN_INFO "ucc-uart: Using loopback mode\n");
1507#endif
1508
1509	ret = uart_register_driver(&ucc_uart_driver);
1510	if (ret) {
1511		printk(KERN_ERR "ucc-uart: could not register UART driver\n");
1512		return ret;
1513	}
1514
1515	ret = platform_driver_register(&ucc_uart_of_driver);
1516	if (ret)
1517		printk(KERN_ERR
1518		       "ucc-uart: could not register platform driver\n");
 
 
1519
1520	return ret;
1521}
1522
1523static void __exit ucc_uart_exit(void)
1524{
1525	printk(KERN_INFO
1526	       "Freescale QUICC Engine UART device driver unloading\n");
1527
1528	platform_driver_unregister(&ucc_uart_of_driver);
1529	uart_unregister_driver(&ucc_uart_driver);
1530}
1531
1532module_init(ucc_uart_init);
1533module_exit(ucc_uart_exit);
1534
1535MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART");
1536MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1537MODULE_LICENSE("GPL v2");
1538MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR);
1539