1/*
  2 * Driver for the Texas Instruments DP83867 PHY
  3 *
  4 * Copyright (C) 2015 Texas Instruments Inc.
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License as published by
  8 * the Free Software Foundation; either version 2 of the License.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 */
 15
 16#include <linux/ethtool.h>
 17#include <linux/kernel.h>
 18#include <linux/mii.h>
 19#include <linux/module.h>
 20#include <linux/of.h>
 21#include <linux/phy.h>
 22
 23#include <dt-bindings/net/ti-dp83867.h>
 24
 25#define DP83867_PHY_ID		0x2000a231
 26#define DP83867_DEVADDR		0x1f
 27
 28#define MII_DP83867_PHYCTRL	0x10
 29#define MII_DP83867_MICR	0x12
 30#define MII_DP83867_ISR		0x13
 31#define DP83867_CTRL		0x1f
 32
 33/* Extended Registers */
 34#define DP83867_RGMIICTL	0x0032
 35#define DP83867_RGMIIDCTL	0x0086
 36
 37#define DP83867_SW_RESET	BIT(15)
 38#define DP83867_SW_RESTART	BIT(14)
 39
 40/* MICR Interrupt bits */
 41#define MII_DP83867_MICR_AN_ERR_INT_EN		BIT(15)
 42#define MII_DP83867_MICR_SPEED_CHNG_INT_EN	BIT(14)
 43#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN	BIT(13)
 44#define MII_DP83867_MICR_PAGE_RXD_INT_EN	BIT(12)
 45#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN	BIT(11)
 46#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN	BIT(10)
 47#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN	BIT(8)
 48#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN	BIT(4)
 49#define MII_DP83867_MICR_WOL_INT_EN		BIT(3)
 50#define MII_DP83867_MICR_XGMII_ERR_INT_EN	BIT(2)
 51#define MII_DP83867_MICR_POL_CHNG_INT_EN	BIT(1)
 52#define MII_DP83867_MICR_JABBER_INT_EN		BIT(0)
 53
 54/* RGMIICTL bits */
 55#define DP83867_RGMII_TX_CLK_DELAY_EN		BIT(1)
 56#define DP83867_RGMII_RX_CLK_DELAY_EN		BIT(0)
 57
 58/* PHY CTRL bits */
 59#define DP83867_PHYCR_FIFO_DEPTH_SHIFT		14
 60
 61/* RGMIIDCTL bits */
 62#define DP83867_RGMII_TX_CLK_DELAY_SHIFT	4
 63
 64struct dp83867_private {
 65	int rx_id_delay;
 66	int tx_id_delay;
 67	int fifo_depth;
 68};
 69
 70static int dp83867_ack_interrupt(struct phy_device *phydev)
 71{
 72	int err = phy_read(phydev, MII_DP83867_ISR);
 73
 74	if (err < 0)
 75		return err;
 76
 77	return 0;
 78}
 79
 80static int dp83867_config_intr(struct phy_device *phydev)
 81{
 82	int micr_status;
 83
 84	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 85		micr_status = phy_read(phydev, MII_DP83867_MICR);
 86		if (micr_status < 0)
 87			return micr_status;
 88
 89		micr_status |=
 90			(MII_DP83867_MICR_AN_ERR_INT_EN |
 91			MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 92			MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 93			MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 94
 95		return phy_write(phydev, MII_DP83867_MICR, micr_status);
 96	}
 97
 98	micr_status = 0x0;
 99	return phy_write(phydev, MII_DP83867_MICR, micr_status);
100}
101
102#ifdef CONFIG_OF_MDIO
103static int dp83867_of_init(struct phy_device *phydev)
104{
105	struct dp83867_private *dp83867 = phydev->priv;
106	struct device *dev = &phydev->mdio.dev;
107	struct device_node *of_node = dev->of_node;
108	int ret;
109
110	if (!of_node)
111		return -ENODEV;
112
113	ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
114				   &dp83867->rx_id_delay);
115	if (ret)
116		return ret;
117
118	ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
119				   &dp83867->tx_id_delay);
120	if (ret)
121		return ret;
122
123	return of_property_read_u32(of_node, "ti,fifo-depth",
124				   &dp83867->fifo_depth);
125}
126#else
127static int dp83867_of_init(struct phy_device *phydev)
128{
129	return 0;
130}
131#endif /* CONFIG_OF_MDIO */
132
133static int dp83867_config_init(struct phy_device *phydev)
134{
135	struct dp83867_private *dp83867;
136	int ret;
137	u16 val, delay;
138
139	if (!phydev->priv) {
140		dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
141				       GFP_KERNEL);
142		if (!dp83867)
143			return -ENOMEM;
144
145		phydev->priv = dp83867;
146		ret = dp83867_of_init(phydev);
147		if (ret)
148			return ret;
149	} else {
150		dp83867 = (struct dp83867_private *)phydev->priv;
151	}
152
153	if (phy_interface_is_rgmii(phydev)) {
154		ret = phy_write(phydev, MII_DP83867_PHYCTRL,
155			(dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT));
156		if (ret)
157			return ret;
158	}
159
160	if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
161	    (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
162		val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
163					    DP83867_DEVADDR);
164
165		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
166			val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
167
168		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
169			val |= DP83867_RGMII_TX_CLK_DELAY_EN;
170
171		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
172			val |= DP83867_RGMII_RX_CLK_DELAY_EN;
173
174		phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
175				       DP83867_DEVADDR, val);
176
177		delay = (dp83867->rx_id_delay |
178			(dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
179
180		phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
181				       DP83867_DEVADDR, delay);
182	}
183
184	return 0;
185}
186
187static int dp83867_phy_reset(struct phy_device *phydev)
188{
189	int err;
190
191	err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
192	if (err < 0)
193		return err;
194
195	return dp83867_config_init(phydev);
196}
197
198static struct phy_driver dp83867_driver[] = {
199	{
200		.phy_id		= DP83867_PHY_ID,
201		.phy_id_mask	= 0xfffffff0,
202		.name		= "TI DP83867",
203		.features	= PHY_GBIT_FEATURES,
204		.flags		= PHY_HAS_INTERRUPT,
205
206		.config_init	= dp83867_config_init,
207		.soft_reset	= dp83867_phy_reset,
208
209		/* IRQ related */
210		.ack_interrupt	= dp83867_ack_interrupt,
211		.config_intr	= dp83867_config_intr,
212
213		.config_aneg	= genphy_config_aneg,
214		.read_status	= genphy_read_status,
215		.suspend	= genphy_suspend,
216		.resume		= genphy_resume,
217	},
218};
219module_phy_driver(dp83867_driver);
220
221static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
222	{ DP83867_PHY_ID, 0xfffffff0 },
223	{ }
224};
225
226MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
227
228MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
229MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
230MODULE_LICENSE("GPL");