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1/*********************************************************************
2 *
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Status: Experimental.
5 * Author: Daniele Peri (peri@csai.unipa.it)
6 * Created at:
7 * Modified at:
8 * Modified by:
9 *
10 * Copyright (c) 2002 Daniele Peri
11 * All Rights Reserved.
12 * Copyright (c) 2002 Jean Tourrilhes
13 * Copyright (c) 2006 Linus Walleij
14 *
15 *
16 * Based on smc-ircc.c:
17 *
18 * Copyright (c) 2001 Stefani Seibold
19 * Copyright (c) 1999-2001 Dag Brattli
20 * Copyright (c) 1998-1999 Thomas Davis,
21 *
22 * and irport.c:
23 *
24 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
25 *
26 *
27 * This program is free software; you can redistribute it and/or
28 * modify it under the terms of the GNU General Public License as
29 * published by the Free Software Foundation; either version 2 of
30 * the License, or (at your option) any later version.
31 *
32 * This program is distributed in the hope that it will be useful,
33 * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 * GNU General Public License for more details.
36 *
37 * You should have received a copy of the GNU General Public License
38 * along with this program; if not, write to the Free Software
39 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 * MA 02111-1307 USA
41 *
42 ********************************************************************/
43
44#include <linux/module.h>
45#include <linux/kernel.h>
46#include <linux/types.h>
47#include <linux/skbuff.h>
48#include <linux/netdevice.h>
49#include <linux/ioport.h>
50#include <linux/delay.h>
51#include <linux/init.h>
52#include <linux/interrupt.h>
53#include <linux/rtnetlink.h>
54#include <linux/serial_reg.h>
55#include <linux/dma-mapping.h>
56#include <linux/pnp.h>
57#include <linux/platform_device.h>
58#include <linux/gfp.h>
59
60#include <asm/io.h>
61#include <asm/dma.h>
62#include <asm/byteorder.h>
63
64#include <linux/spinlock.h>
65#include <linux/pm.h>
66#ifdef CONFIG_PCI
67#include <linux/pci.h>
68#endif
69
70#include <net/irda/wrapper.h>
71#include <net/irda/irda.h>
72#include <net/irda/irda_device.h>
73
74#include "smsc-ircc2.h"
75#include "smsc-sio.h"
76
77
78MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
79MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
80MODULE_LICENSE("GPL");
81
82static int smsc_nopnp = 1;
83module_param_named(nopnp, smsc_nopnp, bool, 0);
84MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
85
86#define DMA_INVAL 255
87static int ircc_dma = DMA_INVAL;
88module_param(ircc_dma, int, 0);
89MODULE_PARM_DESC(ircc_dma, "DMA channel");
90
91#define IRQ_INVAL 255
92static int ircc_irq = IRQ_INVAL;
93module_param(ircc_irq, int, 0);
94MODULE_PARM_DESC(ircc_irq, "IRQ line");
95
96static int ircc_fir;
97module_param(ircc_fir, int, 0);
98MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
99
100static int ircc_sir;
101module_param(ircc_sir, int, 0);
102MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
103
104static int ircc_cfg;
105module_param(ircc_cfg, int, 0);
106MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
107
108static int ircc_transceiver;
109module_param(ircc_transceiver, int, 0);
110MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
111
112/* Types */
113
114#ifdef CONFIG_PCI
115struct smsc_ircc_subsystem_configuration {
116 unsigned short vendor; /* PCI vendor ID */
117 unsigned short device; /* PCI vendor ID */
118 unsigned short subvendor; /* PCI subsystem vendor ID */
119 unsigned short subdevice; /* PCI subsystem device ID */
120 unsigned short sir_io; /* I/O port for SIR */
121 unsigned short fir_io; /* I/O port for FIR */
122 unsigned char fir_irq; /* FIR IRQ */
123 unsigned char fir_dma; /* FIR DMA */
124 unsigned short cfg_base; /* I/O port for chip configuration */
125 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
126 const char *name; /* name shown as info */
127};
128#endif
129
130struct smsc_transceiver {
131 char *name;
132 void (*set_for_speed)(int fir_base, u32 speed);
133 int (*probe)(int fir_base);
134};
135
136struct smsc_chip {
137 char *name;
138 #if 0
139 u8 type;
140 #endif
141 u16 flags;
142 u8 devid;
143 u8 rev;
144};
145
146struct smsc_chip_address {
147 unsigned int cfg_base;
148 unsigned int type;
149};
150
151/* Private data for each instance */
152struct smsc_ircc_cb {
153 struct net_device *netdev; /* Yes! we are some kind of netdevice */
154 struct irlap_cb *irlap; /* The link layer we are binded to */
155
156 chipio_t io; /* IrDA controller information */
157 iobuff_t tx_buff; /* Transmit buffer */
158 iobuff_t rx_buff; /* Receive buffer */
159 dma_addr_t tx_buff_dma;
160 dma_addr_t rx_buff_dma;
161
162 struct qos_info qos; /* QoS capabilities for this device */
163
164 spinlock_t lock; /* For serializing operations */
165
166 __u32 new_speed;
167 __u32 flags; /* Interface flags */
168
169 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
170 int tx_len; /* Number of frames in tx_buff */
171
172 int transceiver;
173 struct platform_device *pldev;
174};
175
176/* Constants */
177
178#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
179
180#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
181#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
182#define SMSC_IRCC2_C_NET_TIMEOUT 0
183#define SMSC_IRCC2_C_SIR_STOP 0
184
185static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
186
187/* Prototypes */
188
189static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
190static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
191static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
192static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
193static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
194static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
195static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
196static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
197static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
198static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
199 struct net_device *dev);
200static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
201 struct net_device *dev);
202static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
203static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
204static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
205static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
206static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
207static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
208static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
209#if SMSC_IRCC2_C_SIR_STOP
210static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
211#endif
212static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
213static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
214static int smsc_ircc_net_open(struct net_device *dev);
215static int smsc_ircc_net_close(struct net_device *dev);
216static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
217#if SMSC_IRCC2_C_NET_TIMEOUT
218static void smsc_ircc_timeout(struct net_device *dev);
219#endif
220static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
221static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
222static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
223static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
224
225/* Probing */
226static int __init smsc_ircc_look_for_chips(void);
227static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
228static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
229static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
230static int __init smsc_superio_fdc(unsigned short cfg_base);
231static int __init smsc_superio_lpc(unsigned short cfg_base);
232#ifdef CONFIG_PCI
233static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
234static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235static void __init preconfigure_ali_port(struct pci_dev *dev,
236 unsigned short port);
237static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
238static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
239 unsigned short ircc_fir,
240 unsigned short ircc_sir,
241 unsigned char ircc_dma,
242 unsigned char ircc_irq);
243#endif
244
245/* Transceivers specific functions */
246
247static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
248static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
249static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
250static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
251static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
252static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
253
254/* Power Management */
255
256static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
257static int smsc_ircc_resume(struct platform_device *dev);
258
259static struct platform_driver smsc_ircc_driver = {
260 .suspend = smsc_ircc_suspend,
261 .resume = smsc_ircc_resume,
262 .driver = {
263 .name = SMSC_IRCC2_DRIVER_NAME,
264 },
265};
266
267/* Transceivers for SMSC-ircc */
268
269static struct smsc_transceiver smsc_transceivers[] =
270{
271 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
272 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
273 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
274 { NULL, NULL }
275};
276#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
277
278/* SMC SuperIO chipsets definitions */
279
280#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
281#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
282#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
283#define SIR 0 /* SuperIO Chip has only slow IRDA */
284#define FIR 4 /* SuperIO Chip has fast IRDA */
285#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
286
287static struct smsc_chip __initdata fdc_chips_flat[] =
288{
289 /* Base address 0x3f0 or 0x370 */
290 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
291 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
292 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
293 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
294 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
295 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
296 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
297 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
298 { NULL }
299};
300
301static struct smsc_chip __initdata fdc_chips_paged[] =
302{
303 /* Base address 0x3f0 or 0x370 */
304 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
305 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
306 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
307 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
308 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
309 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
310 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
311 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
312 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
313 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
314 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
315 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
316 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
317 { NULL }
318};
319
320static struct smsc_chip __initdata lpc_chips_flat[] =
321{
322 /* Base address 0x2E or 0x4E */
323 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
324 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
325 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
326 { NULL }
327};
328
329static struct smsc_chip __initdata lpc_chips_paged[] =
330{
331 /* Base address 0x2E or 0x4E */
332 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
333 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
334 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
335 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
336 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
337 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
338 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
339 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
340 { NULL }
341};
342
343#define SMSCSIO_TYPE_FDC 1
344#define SMSCSIO_TYPE_LPC 2
345#define SMSCSIO_TYPE_FLAT 4
346#define SMSCSIO_TYPE_PAGED 8
347
348static struct smsc_chip_address __initdata possible_addresses[] =
349{
350 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
353 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
354 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
355 { 0, 0 }
356};
357
358/* Globals */
359
360static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
361static unsigned short dev_count;
362
363static inline void register_bank(int iobase, int bank)
364{
365 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
366 iobase + IRCC_MASTER);
367}
368
369/* PNP hotplug support */
370static const struct pnp_device_id smsc_ircc_pnp_table[] = {
371 { .id = "SMCf010", .driver_data = 0 },
372 /* and presumably others */
373 { }
374};
375MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
376
377static int pnp_driver_registered;
378
379#ifdef CONFIG_PNP
380static int __devinit smsc_ircc_pnp_probe(struct pnp_dev *dev,
381 const struct pnp_device_id *dev_id)
382{
383 unsigned int firbase, sirbase;
384 u8 dma, irq;
385
386 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
387 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
388 return -EINVAL;
389
390 sirbase = pnp_port_start(dev, 0);
391 firbase = pnp_port_start(dev, 1);
392 dma = pnp_dma(dev, 0);
393 irq = pnp_irq(dev, 0);
394
395 if (smsc_ircc_open(firbase, sirbase, dma, irq))
396 return -ENODEV;
397
398 return 0;
399}
400
401static struct pnp_driver smsc_ircc_pnp_driver = {
402 .name = "smsc-ircc2",
403 .id_table = smsc_ircc_pnp_table,
404 .probe = smsc_ircc_pnp_probe,
405};
406#else /* CONFIG_PNP */
407static struct pnp_driver smsc_ircc_pnp_driver;
408#endif
409
410/*******************************************************************************
411 *
412 *
413 * SMSC-ircc stuff
414 *
415 *
416 *******************************************************************************/
417
418static int __init smsc_ircc_legacy_probe(void)
419{
420 int ret = 0;
421
422#ifdef CONFIG_PCI
423 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
424 /* Ignore errors from preconfiguration */
425 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
426 }
427#endif
428
429 if (ircc_fir > 0 && ircc_sir > 0) {
430 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
431 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
432
433 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
434 ret = -ENODEV;
435 } else {
436 ret = -ENODEV;
437
438 /* try user provided configuration register base address */
439 if (ircc_cfg > 0) {
440 IRDA_MESSAGE(" Overriding configuration address "
441 "0x%04x\n", ircc_cfg);
442 if (!smsc_superio_fdc(ircc_cfg))
443 ret = 0;
444 if (!smsc_superio_lpc(ircc_cfg))
445 ret = 0;
446 }
447
448 if (smsc_ircc_look_for_chips() > 0)
449 ret = 0;
450 }
451 return ret;
452}
453
454/*
455 * Function smsc_ircc_init ()
456 *
457 * Initialize chip. Just try to find out how many chips we are dealing with
458 * and where they are
459 */
460static int __init smsc_ircc_init(void)
461{
462 int ret;
463
464 IRDA_DEBUG(1, "%s\n", __func__);
465
466 ret = platform_driver_register(&smsc_ircc_driver);
467 if (ret) {
468 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
469 return ret;
470 }
471
472 dev_count = 0;
473
474 if (smsc_nopnp || !pnp_platform_devices ||
475 ircc_cfg || ircc_fir || ircc_sir ||
476 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
477 ret = smsc_ircc_legacy_probe();
478 } else {
479 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
480 pnp_driver_registered = 1;
481 }
482
483 if (ret) {
484 if (pnp_driver_registered)
485 pnp_unregister_driver(&smsc_ircc_pnp_driver);
486 platform_driver_unregister(&smsc_ircc_driver);
487 }
488
489 return ret;
490}
491
492static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
493 struct net_device *dev)
494{
495 struct smsc_ircc_cb *self = netdev_priv(dev);
496
497 if (self->io.speed > 115200)
498 return smsc_ircc_hard_xmit_fir(skb, dev);
499 else
500 return smsc_ircc_hard_xmit_sir(skb, dev);
501}
502
503static const struct net_device_ops smsc_ircc_netdev_ops = {
504 .ndo_open = smsc_ircc_net_open,
505 .ndo_stop = smsc_ircc_net_close,
506 .ndo_do_ioctl = smsc_ircc_net_ioctl,
507 .ndo_start_xmit = smsc_ircc_net_xmit,
508#if SMSC_IRCC2_C_NET_TIMEOUT
509 .ndo_tx_timeout = smsc_ircc_timeout,
510#endif
511};
512
513/*
514 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
515 *
516 * Try to open driver instance
517 *
518 */
519static int __devinit smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
520{
521 struct smsc_ircc_cb *self;
522 struct net_device *dev;
523 int err;
524
525 IRDA_DEBUG(1, "%s\n", __func__);
526
527 err = smsc_ircc_present(fir_base, sir_base);
528 if (err)
529 goto err_out;
530
531 err = -ENOMEM;
532 if (dev_count >= ARRAY_SIZE(dev_self)) {
533 IRDA_WARNING("%s(), too many devices!\n", __func__);
534 goto err_out1;
535 }
536
537 /*
538 * Allocate new instance of the driver
539 */
540 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
541 if (!dev) {
542 IRDA_WARNING("%s() can't allocate net device\n", __func__);
543 goto err_out1;
544 }
545
546#if SMSC_IRCC2_C_NET_TIMEOUT
547 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
548#endif
549 dev->netdev_ops = &smsc_ircc_netdev_ops;
550
551 self = netdev_priv(dev);
552 self->netdev = dev;
553
554 /* Make ifconfig display some details */
555 dev->base_addr = self->io.fir_base = fir_base;
556 dev->irq = self->io.irq = irq;
557
558 /* Need to store self somewhere */
559 dev_self[dev_count] = self;
560 spin_lock_init(&self->lock);
561
562 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
563 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
564
565 self->rx_buff.head =
566 dma_alloc_coherent(NULL, self->rx_buff.truesize,
567 &self->rx_buff_dma, GFP_KERNEL);
568 if (self->rx_buff.head == NULL) {
569 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
570 driver_name);
571 goto err_out2;
572 }
573
574 self->tx_buff.head =
575 dma_alloc_coherent(NULL, self->tx_buff.truesize,
576 &self->tx_buff_dma, GFP_KERNEL);
577 if (self->tx_buff.head == NULL) {
578 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
579 driver_name);
580 goto err_out3;
581 }
582
583 memset(self->rx_buff.head, 0, self->rx_buff.truesize);
584 memset(self->tx_buff.head, 0, self->tx_buff.truesize);
585
586 self->rx_buff.in_frame = FALSE;
587 self->rx_buff.state = OUTSIDE_FRAME;
588 self->tx_buff.data = self->tx_buff.head;
589 self->rx_buff.data = self->rx_buff.head;
590
591 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
592 smsc_ircc_setup_qos(self);
593 smsc_ircc_init_chip(self);
594
595 if (ircc_transceiver > 0 &&
596 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
597 self->transceiver = ircc_transceiver;
598 else
599 smsc_ircc_probe_transceiver(self);
600
601 err = register_netdev(self->netdev);
602 if (err) {
603 IRDA_ERROR("%s, Network device registration failed!\n",
604 driver_name);
605 goto err_out4;
606 }
607
608 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
609 dev_count, NULL, 0);
610 if (IS_ERR(self->pldev)) {
611 err = PTR_ERR(self->pldev);
612 goto err_out5;
613 }
614 platform_set_drvdata(self->pldev, self);
615
616 IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
617 dev_count++;
618
619 return 0;
620
621 err_out5:
622 unregister_netdev(self->netdev);
623
624 err_out4:
625 dma_free_coherent(NULL, self->tx_buff.truesize,
626 self->tx_buff.head, self->tx_buff_dma);
627 err_out3:
628 dma_free_coherent(NULL, self->rx_buff.truesize,
629 self->rx_buff.head, self->rx_buff_dma);
630 err_out2:
631 free_netdev(self->netdev);
632 dev_self[dev_count] = NULL;
633 err_out1:
634 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
635 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
636 err_out:
637 return err;
638}
639
640/*
641 * Function smsc_ircc_present(fir_base, sir_base)
642 *
643 * Check the smsc-ircc chip presence
644 *
645 */
646static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
647{
648 unsigned char low, high, chip, config, dma, irq, version;
649
650 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
651 driver_name)) {
652 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
653 __func__, fir_base);
654 goto out1;
655 }
656
657 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
658 driver_name)) {
659 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
660 __func__, sir_base);
661 goto out2;
662 }
663
664 register_bank(fir_base, 3);
665
666 high = inb(fir_base + IRCC_ID_HIGH);
667 low = inb(fir_base + IRCC_ID_LOW);
668 chip = inb(fir_base + IRCC_CHIP_ID);
669 version = inb(fir_base + IRCC_VERSION);
670 config = inb(fir_base + IRCC_INTERFACE);
671 dma = config & IRCC_INTERFACE_DMA_MASK;
672 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
673
674 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
675 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
676 __func__, fir_base);
677 goto out3;
678 }
679 IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
680 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
681 chip & 0x0f, version, fir_base, sir_base, dma, irq);
682
683 return 0;
684
685 out3:
686 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
687 out2:
688 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
689 out1:
690 return -ENODEV;
691}
692
693/*
694 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
695 *
696 * Setup I/O
697 *
698 */
699static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
700 unsigned int fir_base, unsigned int sir_base,
701 u8 dma, u8 irq)
702{
703 unsigned char config, chip_dma, chip_irq;
704
705 register_bank(fir_base, 3);
706 config = inb(fir_base + IRCC_INTERFACE);
707 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
708 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
709
710 self->io.fir_base = fir_base;
711 self->io.sir_base = sir_base;
712 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
713 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
714 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
715 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
716
717 if (irq != IRQ_INVAL) {
718 if (irq != chip_irq)
719 IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
720 driver_name, chip_irq, irq);
721 self->io.irq = irq;
722 } else
723 self->io.irq = chip_irq;
724
725 if (dma != DMA_INVAL) {
726 if (dma != chip_dma)
727 IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
728 driver_name, chip_dma, dma);
729 self->io.dma = dma;
730 } else
731 self->io.dma = chip_dma;
732
733}
734
735/*
736 * Function smsc_ircc_setup_qos(self)
737 *
738 * Setup qos
739 *
740 */
741static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
742{
743 /* Initialize QoS for this device */
744 irda_init_max_qos_capabilies(&self->qos);
745
746 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
747 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
748
749 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
750 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
751 irda_qos_bits_to_value(&self->qos);
752}
753
754/*
755 * Function smsc_ircc_init_chip(self)
756 *
757 * Init chip
758 *
759 */
760static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
761{
762 int iobase = self->io.fir_base;
763
764 register_bank(iobase, 0);
765 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
766 outb(0x00, iobase + IRCC_MASTER);
767
768 register_bank(iobase, 1);
769 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
770 iobase + IRCC_SCE_CFGA);
771
772#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
773 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
774 iobase + IRCC_SCE_CFGB);
775#else
776 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
777 iobase + IRCC_SCE_CFGB);
778#endif
779 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
780 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
781
782 register_bank(iobase, 4);
783 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
784
785 register_bank(iobase, 0);
786 outb(0, iobase + IRCC_LCR_A);
787
788 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
789
790 /* Power on device */
791 outb(0x00, iobase + IRCC_MASTER);
792}
793
794/*
795 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
796 *
797 * Process IOCTL commands for this device
798 *
799 */
800static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
801{
802 struct if_irda_req *irq = (struct if_irda_req *) rq;
803 struct smsc_ircc_cb *self;
804 unsigned long flags;
805 int ret = 0;
806
807 IRDA_ASSERT(dev != NULL, return -1;);
808
809 self = netdev_priv(dev);
810
811 IRDA_ASSERT(self != NULL, return -1;);
812
813 IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
814
815 switch (cmd) {
816 case SIOCSBANDWIDTH: /* Set bandwidth */
817 if (!capable(CAP_NET_ADMIN))
818 ret = -EPERM;
819 else {
820 /* Make sure we are the only one touching
821 * self->io.speed and the hardware - Jean II */
822 spin_lock_irqsave(&self->lock, flags);
823 smsc_ircc_change_speed(self, irq->ifr_baudrate);
824 spin_unlock_irqrestore(&self->lock, flags);
825 }
826 break;
827 case SIOCSMEDIABUSY: /* Set media busy */
828 if (!capable(CAP_NET_ADMIN)) {
829 ret = -EPERM;
830 break;
831 }
832
833 irda_device_set_media_busy(self->netdev, TRUE);
834 break;
835 case SIOCGRECEIVING: /* Check if we are receiving right now */
836 irq->ifr_receiving = smsc_ircc_is_receiving(self);
837 break;
838 #if 0
839 case SIOCSDTRRTS:
840 if (!capable(CAP_NET_ADMIN)) {
841 ret = -EPERM;
842 break;
843 }
844 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
845 break;
846 #endif
847 default:
848 ret = -EOPNOTSUPP;
849 }
850
851 return ret;
852}
853
854#if SMSC_IRCC2_C_NET_TIMEOUT
855/*
856 * Function smsc_ircc_timeout (struct net_device *dev)
857 *
858 * The networking timeout management.
859 *
860 */
861
862static void smsc_ircc_timeout(struct net_device *dev)
863{
864 struct smsc_ircc_cb *self = netdev_priv(dev);
865 unsigned long flags;
866
867 IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
868 dev->name, self->io.speed);
869 spin_lock_irqsave(&self->lock, flags);
870 smsc_ircc_sir_start(self);
871 smsc_ircc_change_speed(self, self->io.speed);
872 dev->trans_start = jiffies; /* prevent tx timeout */
873 netif_wake_queue(dev);
874 spin_unlock_irqrestore(&self->lock, flags);
875}
876#endif
877
878/*
879 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
880 *
881 * Transmits the current frame until FIFO is full, then
882 * waits until the next transmit interrupt, and continues until the
883 * frame is transmitted.
884 */
885static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
886 struct net_device *dev)
887{
888 struct smsc_ircc_cb *self;
889 unsigned long flags;
890 s32 speed;
891
892 IRDA_DEBUG(1, "%s\n", __func__);
893
894 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
895
896 self = netdev_priv(dev);
897 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
898
899 netif_stop_queue(dev);
900
901 /* Make sure test of self->io.speed & speed change are atomic */
902 spin_lock_irqsave(&self->lock, flags);
903
904 /* Check if we need to change the speed */
905 speed = irda_get_next_speed(skb);
906 if (speed != self->io.speed && speed != -1) {
907 /* Check for empty frame */
908 if (!skb->len) {
909 /*
910 * We send frames one by one in SIR mode (no
911 * pipelining), so at this point, if we were sending
912 * a previous frame, we just received the interrupt
913 * telling us it is finished (UART_IIR_THRI).
914 * Therefore, waiting for the transmitter to really
915 * finish draining the fifo won't take too long.
916 * And the interrupt handler is not expected to run.
917 * - Jean II */
918 smsc_ircc_sir_wait_hw_transmitter_finish(self);
919 smsc_ircc_change_speed(self, speed);
920 spin_unlock_irqrestore(&self->lock, flags);
921 dev_kfree_skb(skb);
922 return NETDEV_TX_OK;
923 }
924 self->new_speed = speed;
925 }
926
927 /* Init tx buffer */
928 self->tx_buff.data = self->tx_buff.head;
929
930 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
931 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
932 self->tx_buff.truesize);
933
934 dev->stats.tx_bytes += self->tx_buff.len;
935
936 /* Turn on transmit finished interrupt. Will fire immediately! */
937 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
938
939 spin_unlock_irqrestore(&self->lock, flags);
940
941 dev_kfree_skb(skb);
942
943 return NETDEV_TX_OK;
944}
945
946/*
947 * Function smsc_ircc_set_fir_speed (self, baud)
948 *
949 * Change the speed of the device
950 *
951 */
952static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
953{
954 int fir_base, ir_mode, ctrl, fast;
955
956 IRDA_ASSERT(self != NULL, return;);
957 fir_base = self->io.fir_base;
958
959 self->io.speed = speed;
960
961 switch (speed) {
962 default:
963 case 576000:
964 ir_mode = IRCC_CFGA_IRDA_HDLC;
965 ctrl = IRCC_CRC;
966 fast = 0;
967 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
968 break;
969 case 1152000:
970 ir_mode = IRCC_CFGA_IRDA_HDLC;
971 ctrl = IRCC_1152 | IRCC_CRC;
972 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
973 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
974 __func__);
975 break;
976 case 4000000:
977 ir_mode = IRCC_CFGA_IRDA_4PPM;
978 ctrl = IRCC_CRC;
979 fast = IRCC_LCR_A_FAST;
980 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
981 __func__);
982 break;
983 }
984 #if 0
985 Now in tranceiver!
986 /* This causes an interrupt */
987 register_bank(fir_base, 0);
988 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
989 #endif
990
991 register_bank(fir_base, 1);
992 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
993
994 register_bank(fir_base, 4);
995 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
996}
997
998/*
999 * Function smsc_ircc_fir_start(self)
1000 *
1001 * Change the speed of the device
1002 *
1003 */
1004static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1005{
1006 struct net_device *dev;
1007 int fir_base;
1008
1009 IRDA_DEBUG(1, "%s\n", __func__);
1010
1011 IRDA_ASSERT(self != NULL, return;);
1012 dev = self->netdev;
1013 IRDA_ASSERT(dev != NULL, return;);
1014
1015 fir_base = self->io.fir_base;
1016
1017 /* Reset everything */
1018
1019 /* Clear FIFO */
1020 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1021
1022 /* Enable interrupt */
1023 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1024
1025 register_bank(fir_base, 1);
1026
1027 /* Select the TX/RX interface */
1028#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1029 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1030 fir_base + IRCC_SCE_CFGB);
1031#else
1032 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1033 fir_base + IRCC_SCE_CFGB);
1034#endif
1035 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1036
1037 /* Enable SCE interrupts */
1038 outb(0, fir_base + IRCC_MASTER);
1039 register_bank(fir_base, 0);
1040 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1041 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1042}
1043
1044/*
1045 * Function smsc_ircc_fir_stop(self, baud)
1046 *
1047 * Change the speed of the device
1048 *
1049 */
1050static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1051{
1052 int fir_base;
1053
1054 IRDA_DEBUG(1, "%s\n", __func__);
1055
1056 IRDA_ASSERT(self != NULL, return;);
1057
1058 fir_base = self->io.fir_base;
1059 register_bank(fir_base, 0);
1060 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1061 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1062}
1063
1064
1065/*
1066 * Function smsc_ircc_change_speed(self, baud)
1067 *
1068 * Change the speed of the device
1069 *
1070 * This function *must* be called with spinlock held, because it may
1071 * be called from the irq handler. - Jean II
1072 */
1073static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1074{
1075 struct net_device *dev;
1076 int last_speed_was_sir;
1077
1078 IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1079
1080 IRDA_ASSERT(self != NULL, return;);
1081 dev = self->netdev;
1082
1083 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1084
1085 #if 0
1086 /* Temp Hack */
1087 speed= 1152000;
1088 self->io.speed = speed;
1089 last_speed_was_sir = 0;
1090 smsc_ircc_fir_start(self);
1091 #endif
1092
1093 if (self->io.speed == 0)
1094 smsc_ircc_sir_start(self);
1095
1096 #if 0
1097 if (!last_speed_was_sir) speed = self->io.speed;
1098 #endif
1099
1100 if (self->io.speed != speed)
1101 smsc_ircc_set_transceiver_for_speed(self, speed);
1102
1103 self->io.speed = speed;
1104
1105 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1106 if (!last_speed_was_sir) {
1107 smsc_ircc_fir_stop(self);
1108 smsc_ircc_sir_start(self);
1109 }
1110 smsc_ircc_set_sir_speed(self, speed);
1111 } else {
1112 if (last_speed_was_sir) {
1113 #if SMSC_IRCC2_C_SIR_STOP
1114 smsc_ircc_sir_stop(self);
1115 #endif
1116 smsc_ircc_fir_start(self);
1117 }
1118 smsc_ircc_set_fir_speed(self, speed);
1119
1120 #if 0
1121 self->tx_buff.len = 10;
1122 self->tx_buff.data = self->tx_buff.head;
1123
1124 smsc_ircc_dma_xmit(self, 4000);
1125 #endif
1126 /* Be ready for incoming frames */
1127 smsc_ircc_dma_receive(self);
1128 }
1129
1130 netif_wake_queue(dev);
1131}
1132
1133/*
1134 * Function smsc_ircc_set_sir_speed (self, speed)
1135 *
1136 * Set speed of IrDA port to specified baudrate
1137 *
1138 */
1139static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1140{
1141 int iobase;
1142 int fcr; /* FIFO control reg */
1143 int lcr; /* Line control reg */
1144 int divisor;
1145
1146 IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1147
1148 IRDA_ASSERT(self != NULL, return;);
1149 iobase = self->io.sir_base;
1150
1151 /* Update accounting for new speed */
1152 self->io.speed = speed;
1153
1154 /* Turn off interrupts */
1155 outb(0, iobase + UART_IER);
1156
1157 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1158
1159 fcr = UART_FCR_ENABLE_FIFO;
1160
1161 /*
1162 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1163 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1164 * about this timeout since it will always be fast enough.
1165 */
1166 fcr |= self->io.speed < 38400 ?
1167 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1168
1169 /* IrDA ports use 8N1 */
1170 lcr = UART_LCR_WLEN8;
1171
1172 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1173 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1174 outb(divisor >> 8, iobase + UART_DLM);
1175 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1176 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1177
1178 /* Turn on interrups */
1179 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1180
1181 IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1182}
1183
1184
1185/*
1186 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1187 *
1188 * Transmit the frame!
1189 *
1190 */
1191static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1192 struct net_device *dev)
1193{
1194 struct smsc_ircc_cb *self;
1195 unsigned long flags;
1196 s32 speed;
1197 int mtt;
1198
1199 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1200 self = netdev_priv(dev);
1201 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1202
1203 netif_stop_queue(dev);
1204
1205 /* Make sure test of self->io.speed & speed change are atomic */
1206 spin_lock_irqsave(&self->lock, flags);
1207
1208 /* Check if we need to change the speed after this frame */
1209 speed = irda_get_next_speed(skb);
1210 if (speed != self->io.speed && speed != -1) {
1211 /* Check for empty frame */
1212 if (!skb->len) {
1213 /* Note : you should make sure that speed changes
1214 * are not going to corrupt any outgoing frame.
1215 * Look at nsc-ircc for the gory details - Jean II */
1216 smsc_ircc_change_speed(self, speed);
1217 spin_unlock_irqrestore(&self->lock, flags);
1218 dev_kfree_skb(skb);
1219 return NETDEV_TX_OK;
1220 }
1221
1222 self->new_speed = speed;
1223 }
1224
1225 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1226
1227 self->tx_buff.len = skb->len;
1228 self->tx_buff.data = self->tx_buff.head;
1229
1230 mtt = irda_get_mtt(skb);
1231 if (mtt) {
1232 int bofs;
1233
1234 /*
1235 * Compute how many BOFs (STA or PA's) we need to waste the
1236 * min turn time given the speed of the link.
1237 */
1238 bofs = mtt * (self->io.speed / 1000) / 8000;
1239 if (bofs > 4095)
1240 bofs = 4095;
1241
1242 smsc_ircc_dma_xmit(self, bofs);
1243 } else {
1244 /* Transmit frame */
1245 smsc_ircc_dma_xmit(self, 0);
1246 }
1247
1248 spin_unlock_irqrestore(&self->lock, flags);
1249 dev_kfree_skb(skb);
1250
1251 return NETDEV_TX_OK;
1252}
1253
1254/*
1255 * Function smsc_ircc_dma_xmit (self, bofs)
1256 *
1257 * Transmit data using DMA
1258 *
1259 */
1260static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1261{
1262 int iobase = self->io.fir_base;
1263 u8 ctrl;
1264
1265 IRDA_DEBUG(3, "%s\n", __func__);
1266#if 1
1267 /* Disable Rx */
1268 register_bank(iobase, 0);
1269 outb(0x00, iobase + IRCC_LCR_B);
1270#endif
1271 register_bank(iobase, 1);
1272 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1273 iobase + IRCC_SCE_CFGB);
1274
1275 self->io.direction = IO_XMIT;
1276
1277 /* Set BOF additional count for generating the min turn time */
1278 register_bank(iobase, 4);
1279 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1280 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1281 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1282
1283 /* Set max Tx frame size */
1284 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1285 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1286
1287 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1288
1289 /* Enable burst mode chip Tx DMA */
1290 register_bank(iobase, 1);
1291 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1292 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1293
1294 /* Setup DMA controller (must be done after enabling chip DMA) */
1295 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1296 DMA_TX_MODE);
1297
1298 /* Enable interrupt */
1299
1300 register_bank(iobase, 0);
1301 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1302 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1303
1304 /* Enable transmit */
1305 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1306}
1307
1308/*
1309 * Function smsc_ircc_dma_xmit_complete (self)
1310 *
1311 * The transfer of a frame in finished. This function will only be called
1312 * by the interrupt handler
1313 *
1314 */
1315static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1316{
1317 int iobase = self->io.fir_base;
1318
1319 IRDA_DEBUG(3, "%s\n", __func__);
1320#if 0
1321 /* Disable Tx */
1322 register_bank(iobase, 0);
1323 outb(0x00, iobase + IRCC_LCR_B);
1324#endif
1325 register_bank(iobase, 1);
1326 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1327 iobase + IRCC_SCE_CFGB);
1328
1329 /* Check for underrun! */
1330 register_bank(iobase, 0);
1331 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1332 self->netdev->stats.tx_errors++;
1333 self->netdev->stats.tx_fifo_errors++;
1334
1335 /* Reset error condition */
1336 register_bank(iobase, 0);
1337 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1338 outb(0x00, iobase + IRCC_MASTER);
1339 } else {
1340 self->netdev->stats.tx_packets++;
1341 self->netdev->stats.tx_bytes += self->tx_buff.len;
1342 }
1343
1344 /* Check if it's time to change the speed */
1345 if (self->new_speed) {
1346 smsc_ircc_change_speed(self, self->new_speed);
1347 self->new_speed = 0;
1348 }
1349
1350 netif_wake_queue(self->netdev);
1351}
1352
1353/*
1354 * Function smsc_ircc_dma_receive(self)
1355 *
1356 * Get ready for receiving a frame. The device will initiate a DMA
1357 * if it starts to receive a frame.
1358 *
1359 */
1360static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1361{
1362 int iobase = self->io.fir_base;
1363#if 0
1364 /* Turn off chip DMA */
1365 register_bank(iobase, 1);
1366 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1367 iobase + IRCC_SCE_CFGB);
1368#endif
1369
1370 /* Disable Tx */
1371 register_bank(iobase, 0);
1372 outb(0x00, iobase + IRCC_LCR_B);
1373
1374 /* Turn off chip DMA */
1375 register_bank(iobase, 1);
1376 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1377 iobase + IRCC_SCE_CFGB);
1378
1379 self->io.direction = IO_RECV;
1380 self->rx_buff.data = self->rx_buff.head;
1381
1382 /* Set max Rx frame size */
1383 register_bank(iobase, 4);
1384 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1385 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1386
1387 /* Setup DMA controller */
1388 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1389 DMA_RX_MODE);
1390
1391 /* Enable burst mode chip Rx DMA */
1392 register_bank(iobase, 1);
1393 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1394 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1395
1396 /* Enable interrupt */
1397 register_bank(iobase, 0);
1398 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1399 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1400
1401 /* Enable receiver */
1402 register_bank(iobase, 0);
1403 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1404 iobase + IRCC_LCR_B);
1405
1406 return 0;
1407}
1408
1409/*
1410 * Function smsc_ircc_dma_receive_complete(self)
1411 *
1412 * Finished with receiving frames
1413 *
1414 */
1415static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1416{
1417 struct sk_buff *skb;
1418 int len, msgcnt, lsr;
1419 int iobase = self->io.fir_base;
1420
1421 register_bank(iobase, 0);
1422
1423 IRDA_DEBUG(3, "%s\n", __func__);
1424#if 0
1425 /* Disable Rx */
1426 register_bank(iobase, 0);
1427 outb(0x00, iobase + IRCC_LCR_B);
1428#endif
1429 register_bank(iobase, 0);
1430 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1431 lsr= inb(iobase + IRCC_LSR);
1432 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1433
1434 IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1435 get_dma_residue(self->io.dma));
1436
1437 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1438
1439 /* Look for errors */
1440 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1441 self->netdev->stats.rx_errors++;
1442 if (lsr & IRCC_LSR_FRAME_ERROR)
1443 self->netdev->stats.rx_frame_errors++;
1444 if (lsr & IRCC_LSR_CRC_ERROR)
1445 self->netdev->stats.rx_crc_errors++;
1446 if (lsr & IRCC_LSR_SIZE_ERROR)
1447 self->netdev->stats.rx_length_errors++;
1448 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1449 self->netdev->stats.rx_length_errors++;
1450 return;
1451 }
1452
1453 /* Remove CRC */
1454 len -= self->io.speed < 4000000 ? 2 : 4;
1455
1456 if (len < 2 || len > 2050) {
1457 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1458 return;
1459 }
1460 IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1461
1462 skb = dev_alloc_skb(len + 1);
1463 if (!skb) {
1464 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1465 __func__);
1466 return;
1467 }
1468 /* Make sure IP header gets aligned */
1469 skb_reserve(skb, 1);
1470
1471 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1472 self->netdev->stats.rx_packets++;
1473 self->netdev->stats.rx_bytes += len;
1474
1475 skb->dev = self->netdev;
1476 skb_reset_mac_header(skb);
1477 skb->protocol = htons(ETH_P_IRDA);
1478 netif_rx(skb);
1479}
1480
1481/*
1482 * Function smsc_ircc_sir_receive (self)
1483 *
1484 * Receive one frame from the infrared port
1485 *
1486 */
1487static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1488{
1489 int boguscount = 0;
1490 int iobase;
1491
1492 IRDA_ASSERT(self != NULL, return;);
1493
1494 iobase = self->io.sir_base;
1495
1496 /*
1497 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1498 * async_unwrap_char will deliver all found frames
1499 */
1500 do {
1501 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1502 inb(iobase + UART_RX));
1503
1504 /* Make sure we don't stay here to long */
1505 if (boguscount++ > 32) {
1506 IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1507 break;
1508 }
1509 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1510}
1511
1512
1513/*
1514 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1515 *
1516 * An interrupt from the chip has arrived. Time to do some work
1517 *
1518 */
1519static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1520{
1521 struct net_device *dev = dev_id;
1522 struct smsc_ircc_cb *self = netdev_priv(dev);
1523 int iobase, iir, lcra, lsr;
1524 irqreturn_t ret = IRQ_NONE;
1525
1526 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1527 spin_lock(&self->lock);
1528
1529 /* Check if we should use the SIR interrupt handler */
1530 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1531 ret = smsc_ircc_interrupt_sir(dev);
1532 goto irq_ret_unlock;
1533 }
1534
1535 iobase = self->io.fir_base;
1536
1537 register_bank(iobase, 0);
1538 iir = inb(iobase + IRCC_IIR);
1539 if (iir == 0)
1540 goto irq_ret_unlock;
1541 ret = IRQ_HANDLED;
1542
1543 /* Disable interrupts */
1544 outb(0, iobase + IRCC_IER);
1545 lcra = inb(iobase + IRCC_LCR_A);
1546 lsr = inb(iobase + IRCC_LSR);
1547
1548 IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1549
1550 if (iir & IRCC_IIR_EOM) {
1551 if (self->io.direction == IO_RECV)
1552 smsc_ircc_dma_receive_complete(self);
1553 else
1554 smsc_ircc_dma_xmit_complete(self);
1555
1556 smsc_ircc_dma_receive(self);
1557 }
1558
1559 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1560 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1561 }
1562
1563 /* Enable interrupts again */
1564
1565 register_bank(iobase, 0);
1566 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1567
1568 irq_ret_unlock:
1569 spin_unlock(&self->lock);
1570
1571 return ret;
1572}
1573
1574/*
1575 * Function irport_interrupt_sir (irq, dev_id)
1576 *
1577 * Interrupt handler for SIR modes
1578 */
1579static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1580{
1581 struct smsc_ircc_cb *self = netdev_priv(dev);
1582 int boguscount = 0;
1583 int iobase;
1584 int iir, lsr;
1585
1586 /* Already locked coming here in smsc_ircc_interrupt() */
1587 /*spin_lock(&self->lock);*/
1588
1589 iobase = self->io.sir_base;
1590
1591 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1592 if (iir == 0)
1593 return IRQ_NONE;
1594 while (iir) {
1595 /* Clear interrupt */
1596 lsr = inb(iobase + UART_LSR);
1597
1598 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1599 __func__, iir, lsr, iobase);
1600
1601 switch (iir) {
1602 case UART_IIR_RLSI:
1603 IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1604 break;
1605 case UART_IIR_RDI:
1606 /* Receive interrupt */
1607 smsc_ircc_sir_receive(self);
1608 break;
1609 case UART_IIR_THRI:
1610 if (lsr & UART_LSR_THRE)
1611 /* Transmitter ready for data */
1612 smsc_ircc_sir_write_wakeup(self);
1613 break;
1614 default:
1615 IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1616 __func__, iir);
1617 break;
1618 }
1619
1620 /* Make sure we don't stay here to long */
1621 if (boguscount++ > 100)
1622 break;
1623
1624 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1625 }
1626 /*spin_unlock(&self->lock);*/
1627 return IRQ_HANDLED;
1628}
1629
1630
1631#if 0 /* unused */
1632/*
1633 * Function ircc_is_receiving (self)
1634 *
1635 * Return TRUE is we are currently receiving a frame
1636 *
1637 */
1638static int ircc_is_receiving(struct smsc_ircc_cb *self)
1639{
1640 int status = FALSE;
1641 /* int iobase; */
1642
1643 IRDA_DEBUG(1, "%s\n", __func__);
1644
1645 IRDA_ASSERT(self != NULL, return FALSE;);
1646
1647 IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1648 get_dma_residue(self->io.dma));
1649
1650 status = (self->rx_buff.state != OUTSIDE_FRAME);
1651
1652 return status;
1653}
1654#endif /* unused */
1655
1656static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1657{
1658 int error;
1659
1660 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1661 self->netdev->name, self->netdev);
1662 if (error)
1663 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1664 __func__, self->io.irq, error);
1665
1666 return error;
1667}
1668
1669static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1670{
1671 unsigned long flags;
1672
1673 spin_lock_irqsave(&self->lock, flags);
1674
1675 self->io.speed = 0;
1676 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1677
1678 spin_unlock_irqrestore(&self->lock, flags);
1679}
1680
1681static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1682{
1683 int iobase = self->io.fir_base;
1684 unsigned long flags;
1685
1686 spin_lock_irqsave(&self->lock, flags);
1687
1688 register_bank(iobase, 0);
1689 outb(0, iobase + IRCC_IER);
1690 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1691 outb(0x00, iobase + IRCC_MASTER);
1692
1693 spin_unlock_irqrestore(&self->lock, flags);
1694}
1695
1696
1697/*
1698 * Function smsc_ircc_net_open (dev)
1699 *
1700 * Start the device
1701 *
1702 */
1703static int smsc_ircc_net_open(struct net_device *dev)
1704{
1705 struct smsc_ircc_cb *self;
1706 char hwname[16];
1707
1708 IRDA_DEBUG(1, "%s\n", __func__);
1709
1710 IRDA_ASSERT(dev != NULL, return -1;);
1711 self = netdev_priv(dev);
1712 IRDA_ASSERT(self != NULL, return 0;);
1713
1714 if (self->io.suspended) {
1715 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1716 return -EAGAIN;
1717 }
1718
1719 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1720 (void *) dev)) {
1721 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1722 __func__, self->io.irq);
1723 return -EAGAIN;
1724 }
1725
1726 smsc_ircc_start_interrupts(self);
1727
1728 /* Give self a hardware name */
1729 /* It would be cool to offer the chip revision here - Jean II */
1730 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1731
1732 /*
1733 * Open new IrLAP layer instance, now that everything should be
1734 * initialized properly
1735 */
1736 self->irlap = irlap_open(dev, &self->qos, hwname);
1737
1738 /*
1739 * Always allocate the DMA channel after the IRQ,
1740 * and clean up on failure.
1741 */
1742 if (request_dma(self->io.dma, dev->name)) {
1743 smsc_ircc_net_close(dev);
1744
1745 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1746 __func__, self->io.dma);
1747 return -EAGAIN;
1748 }
1749
1750 netif_start_queue(dev);
1751
1752 return 0;
1753}
1754
1755/*
1756 * Function smsc_ircc_net_close (dev)
1757 *
1758 * Stop the device
1759 *
1760 */
1761static int smsc_ircc_net_close(struct net_device *dev)
1762{
1763 struct smsc_ircc_cb *self;
1764
1765 IRDA_DEBUG(1, "%s\n", __func__);
1766
1767 IRDA_ASSERT(dev != NULL, return -1;);
1768 self = netdev_priv(dev);
1769 IRDA_ASSERT(self != NULL, return 0;);
1770
1771 /* Stop device */
1772 netif_stop_queue(dev);
1773
1774 /* Stop and remove instance of IrLAP */
1775 if (self->irlap)
1776 irlap_close(self->irlap);
1777 self->irlap = NULL;
1778
1779 smsc_ircc_stop_interrupts(self);
1780
1781 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1782 if (!self->io.suspended)
1783 free_irq(self->io.irq, dev);
1784
1785 disable_dma(self->io.dma);
1786 free_dma(self->io.dma);
1787
1788 return 0;
1789}
1790
1791static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1792{
1793 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1794
1795 if (!self->io.suspended) {
1796 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1797
1798 rtnl_lock();
1799 if (netif_running(self->netdev)) {
1800 netif_device_detach(self->netdev);
1801 smsc_ircc_stop_interrupts(self);
1802 free_irq(self->io.irq, self->netdev);
1803 disable_dma(self->io.dma);
1804 }
1805 self->io.suspended = 1;
1806 rtnl_unlock();
1807 }
1808
1809 return 0;
1810}
1811
1812static int smsc_ircc_resume(struct platform_device *dev)
1813{
1814 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1815
1816 if (self->io.suspended) {
1817 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1818
1819 rtnl_lock();
1820 smsc_ircc_init_chip(self);
1821 if (netif_running(self->netdev)) {
1822 if (smsc_ircc_request_irq(self)) {
1823 /*
1824 * Don't fail resume process, just kill this
1825 * network interface
1826 */
1827 unregister_netdevice(self->netdev);
1828 } else {
1829 enable_dma(self->io.dma);
1830 smsc_ircc_start_interrupts(self);
1831 netif_device_attach(self->netdev);
1832 }
1833 }
1834 self->io.suspended = 0;
1835 rtnl_unlock();
1836 }
1837 return 0;
1838}
1839
1840/*
1841 * Function smsc_ircc_close (self)
1842 *
1843 * Close driver instance
1844 *
1845 */
1846static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1847{
1848 IRDA_DEBUG(1, "%s\n", __func__);
1849
1850 IRDA_ASSERT(self != NULL, return -1;);
1851
1852 platform_device_unregister(self->pldev);
1853
1854 /* Remove netdevice */
1855 unregister_netdev(self->netdev);
1856
1857 smsc_ircc_stop_interrupts(self);
1858
1859 /* Release the PORTS that this driver is using */
1860 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1861 self->io.fir_base);
1862
1863 release_region(self->io.fir_base, self->io.fir_ext);
1864
1865 IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1866 self->io.sir_base);
1867
1868 release_region(self->io.sir_base, self->io.sir_ext);
1869
1870 if (self->tx_buff.head)
1871 dma_free_coherent(NULL, self->tx_buff.truesize,
1872 self->tx_buff.head, self->tx_buff_dma);
1873
1874 if (self->rx_buff.head)
1875 dma_free_coherent(NULL, self->rx_buff.truesize,
1876 self->rx_buff.head, self->rx_buff_dma);
1877
1878 free_netdev(self->netdev);
1879
1880 return 0;
1881}
1882
1883static void __exit smsc_ircc_cleanup(void)
1884{
1885 int i;
1886
1887 IRDA_DEBUG(1, "%s\n", __func__);
1888
1889 for (i = 0; i < 2; i++) {
1890 if (dev_self[i])
1891 smsc_ircc_close(dev_self[i]);
1892 }
1893
1894 if (pnp_driver_registered)
1895 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1896
1897 platform_driver_unregister(&smsc_ircc_driver);
1898}
1899
1900/*
1901 * Start SIR operations
1902 *
1903 * This function *must* be called with spinlock held, because it may
1904 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1905 */
1906static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1907{
1908 struct net_device *dev;
1909 int fir_base, sir_base;
1910
1911 IRDA_DEBUG(3, "%s\n", __func__);
1912
1913 IRDA_ASSERT(self != NULL, return;);
1914 dev = self->netdev;
1915 IRDA_ASSERT(dev != NULL, return;);
1916
1917 fir_base = self->io.fir_base;
1918 sir_base = self->io.sir_base;
1919
1920 /* Reset everything */
1921 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1922
1923 #if SMSC_IRCC2_C_SIR_STOP
1924 /*smsc_ircc_sir_stop(self);*/
1925 #endif
1926
1927 register_bank(fir_base, 1);
1928 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1929
1930 /* Initialize UART */
1931 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1932 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1933
1934 /* Turn on interrups */
1935 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1936
1937 IRDA_DEBUG(3, "%s() - exit\n", __func__);
1938
1939 outb(0x00, fir_base + IRCC_MASTER);
1940}
1941
1942#if SMSC_IRCC2_C_SIR_STOP
1943void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1944{
1945 int iobase;
1946
1947 IRDA_DEBUG(3, "%s\n", __func__);
1948 iobase = self->io.sir_base;
1949
1950 /* Reset UART */
1951 outb(0, iobase + UART_MCR);
1952
1953 /* Turn off interrupts */
1954 outb(0, iobase + UART_IER);
1955}
1956#endif
1957
1958/*
1959 * Function smsc_sir_write_wakeup (self)
1960 *
1961 * Called by the SIR interrupt handler when there's room for more data.
1962 * If we have more packets to send, we send them here.
1963 *
1964 */
1965static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1966{
1967 int actual = 0;
1968 int iobase;
1969 int fcr;
1970
1971 IRDA_ASSERT(self != NULL, return;);
1972
1973 IRDA_DEBUG(4, "%s\n", __func__);
1974
1975 iobase = self->io.sir_base;
1976
1977 /* Finished with frame? */
1978 if (self->tx_buff.len > 0) {
1979 /* Write data left in transmit buffer */
1980 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1981 self->tx_buff.data, self->tx_buff.len);
1982 self->tx_buff.data += actual;
1983 self->tx_buff.len -= actual;
1984 } else {
1985
1986 /*if (self->tx_buff.len ==0) {*/
1987
1988 /*
1989 * Now serial buffer is almost free & we can start
1990 * transmission of another packet. But first we must check
1991 * if we need to change the speed of the hardware
1992 */
1993 if (self->new_speed) {
1994 IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1995 __func__, self->new_speed);
1996 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1997 smsc_ircc_change_speed(self, self->new_speed);
1998 self->new_speed = 0;
1999 } else {
2000 /* Tell network layer that we want more frames */
2001 netif_wake_queue(self->netdev);
2002 }
2003 self->netdev->stats.tx_packets++;
2004
2005 if (self->io.speed <= 115200) {
2006 /*
2007 * Reset Rx FIFO to make sure that all reflected transmit data
2008 * is discarded. This is needed for half duplex operation
2009 */
2010 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2011 fcr |= self->io.speed < 38400 ?
2012 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2013
2014 outb(fcr, iobase + UART_FCR);
2015
2016 /* Turn on receive interrupts */
2017 outb(UART_IER_RDI, iobase + UART_IER);
2018 }
2019 }
2020}
2021
2022/*
2023 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2024 *
2025 * Fill Tx FIFO with transmit data
2026 *
2027 */
2028static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2029{
2030 int actual = 0;
2031
2032 /* Tx FIFO should be empty! */
2033 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2034 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2035 return 0;
2036 }
2037
2038 /* Fill FIFO with current frame */
2039 while (fifo_size-- > 0 && actual < len) {
2040 /* Transmit next byte */
2041 outb(buf[actual], iobase + UART_TX);
2042 actual++;
2043 }
2044 return actual;
2045}
2046
2047/*
2048 * Function smsc_ircc_is_receiving (self)
2049 *
2050 * Returns true is we are currently receiving data
2051 *
2052 */
2053static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2054{
2055 return self->rx_buff.state != OUTSIDE_FRAME;
2056}
2057
2058
2059/*
2060 * Function smsc_ircc_probe_transceiver(self)
2061 *
2062 * Tries to find the used Transceiver
2063 *
2064 */
2065static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2066{
2067 unsigned int i;
2068
2069 IRDA_ASSERT(self != NULL, return;);
2070
2071 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2072 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2073 IRDA_MESSAGE(" %s transceiver found\n",
2074 smsc_transceivers[i].name);
2075 self->transceiver= i + 1;
2076 return;
2077 }
2078
2079 IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2080 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2081
2082 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2083}
2084
2085
2086/*
2087 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2088 *
2089 * Set the transceiver according to the speed
2090 *
2091 */
2092static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2093{
2094 unsigned int trx;
2095
2096 trx = self->transceiver;
2097 if (trx > 0)
2098 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2099}
2100
2101/*
2102 * Function smsc_ircc_wait_hw_transmitter_finish ()
2103 *
2104 * Wait for the real end of HW transmission
2105 *
2106 * The UART is a strict FIFO, and we get called only when we have finished
2107 * pushing data to the FIFO, so the maximum amount of time we must wait
2108 * is only for the FIFO to drain out.
2109 *
2110 * We use a simple calibrated loop. We may need to adjust the loop
2111 * delay (udelay) to balance I/O traffic and latency. And we also need to
2112 * adjust the maximum timeout.
2113 * It would probably be better to wait for the proper interrupt,
2114 * but it doesn't seem to be available.
2115 *
2116 * We can't use jiffies or kernel timers because :
2117 * 1) We are called from the interrupt handler, which disable softirqs,
2118 * so jiffies won't be increased
2119 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2120 * want to wait that long to detect stuck hardware.
2121 * Jean II
2122 */
2123
2124static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2125{
2126 int iobase = self->io.sir_base;
2127 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2128
2129 /* Calibrated busy loop */
2130 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2131 udelay(1);
2132
2133 if (count < 0)
2134 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2135}
2136
2137
2138/* PROBING
2139 *
2140 * REVISIT we can be told about the device by PNP, and should use that info
2141 * instead of probing hardware and creating a platform_device ...
2142 */
2143
2144static int __init smsc_ircc_look_for_chips(void)
2145{
2146 struct smsc_chip_address *address;
2147 char *type;
2148 unsigned int cfg_base, found;
2149
2150 found = 0;
2151 address = possible_addresses;
2152
2153 while (address->cfg_base) {
2154 cfg_base = address->cfg_base;
2155
2156 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2157
2158 if (address->type & SMSCSIO_TYPE_FDC) {
2159 type = "FDC";
2160 if (address->type & SMSCSIO_TYPE_FLAT)
2161 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2162 found++;
2163
2164 if (address->type & SMSCSIO_TYPE_PAGED)
2165 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2166 found++;
2167 }
2168 if (address->type & SMSCSIO_TYPE_LPC) {
2169 type = "LPC";
2170 if (address->type & SMSCSIO_TYPE_FLAT)
2171 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2172 found++;
2173
2174 if (address->type & SMSCSIO_TYPE_PAGED)
2175 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2176 found++;
2177 }
2178 address++;
2179 }
2180 return found;
2181}
2182
2183/*
2184 * Function smsc_superio_flat (chip, base, type)
2185 *
2186 * Try to get configuration of a smc SuperIO chip with flat register model
2187 *
2188 */
2189static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2190{
2191 unsigned short firbase, sirbase;
2192 u8 mode, dma, irq;
2193 int ret = -ENODEV;
2194
2195 IRDA_DEBUG(1, "%s\n", __func__);
2196
2197 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2198 return ret;
2199
2200 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2201 mode = inb(cfgbase + 1);
2202
2203 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2204
2205 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2206 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2207
2208 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2209 sirbase = inb(cfgbase + 1) << 2;
2210
2211 /* FIR iobase */
2212 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2213 firbase = inb(cfgbase + 1) << 3;
2214
2215 /* DMA */
2216 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2217 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2218
2219 /* IRQ */
2220 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2221 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2222
2223 IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2224
2225 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2226 ret = 0;
2227
2228 /* Exit configuration */
2229 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2230
2231 return ret;
2232}
2233
2234/*
2235 * Function smsc_superio_paged (chip, base, type)
2236 *
2237 * Try to get configuration of a smc SuperIO chip with paged register model
2238 *
2239 */
2240static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2241{
2242 unsigned short fir_io, sir_io;
2243 int ret = -ENODEV;
2244
2245 IRDA_DEBUG(1, "%s\n", __func__);
2246
2247 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2248 return ret;
2249
2250 /* Select logical device (UART2) */
2251 outb(0x07, cfg_base);
2252 outb(0x05, cfg_base + 1);
2253
2254 /* SIR iobase */
2255 outb(0x60, cfg_base);
2256 sir_io = inb(cfg_base + 1) << 8;
2257 outb(0x61, cfg_base);
2258 sir_io |= inb(cfg_base + 1);
2259
2260 /* Read FIR base */
2261 outb(0x62, cfg_base);
2262 fir_io = inb(cfg_base + 1) << 8;
2263 outb(0x63, cfg_base);
2264 fir_io |= inb(cfg_base + 1);
2265 outb(0x2b, cfg_base); /* ??? */
2266
2267 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2268 ret = 0;
2269
2270 /* Exit configuration */
2271 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2272
2273 return ret;
2274}
2275
2276
2277static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2278{
2279 IRDA_DEBUG(1, "%s\n", __func__);
2280
2281 outb(reg, cfg_base);
2282 return inb(cfg_base) != reg ? -1 : 0;
2283}
2284
2285static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2286{
2287 u8 devid, xdevid, rev;
2288
2289 IRDA_DEBUG(1, "%s\n", __func__);
2290
2291 /* Leave configuration */
2292
2293 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2294
2295 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2296 return NULL;
2297
2298 outb(reg, cfg_base);
2299
2300 xdevid = inb(cfg_base + 1);
2301
2302 /* Enter configuration */
2303
2304 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2305
2306 #if 0
2307 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2308 return NULL;
2309 #endif
2310
2311 /* probe device ID */
2312
2313 if (smsc_access(cfg_base, reg))
2314 return NULL;
2315
2316 devid = inb(cfg_base + 1);
2317
2318 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2319 return NULL;
2320
2321 /* probe revision ID */
2322
2323 if (smsc_access(cfg_base, reg + 1))
2324 return NULL;
2325
2326 rev = inb(cfg_base + 1);
2327
2328 if (rev >= 128) /* i think this will make no sense */
2329 return NULL;
2330
2331 if (devid == xdevid) /* protection against false positives */
2332 return NULL;
2333
2334 /* Check for expected device ID; are there others? */
2335
2336 while (chip->devid != devid) {
2337
2338 chip++;
2339
2340 if (chip->name == NULL)
2341 return NULL;
2342 }
2343
2344 IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2345 devid, rev, cfg_base, type, chip->name);
2346
2347 if (chip->rev > rev) {
2348 IRDA_MESSAGE("Revision higher than expected\n");
2349 return NULL;
2350 }
2351
2352 if (chip->flags & NoIRDA)
2353 IRDA_MESSAGE("chipset does not support IRDA\n");
2354
2355 return chip;
2356}
2357
2358static int __init smsc_superio_fdc(unsigned short cfg_base)
2359{
2360 int ret = -1;
2361
2362 if (!request_region(cfg_base, 2, driver_name)) {
2363 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2364 __func__, cfg_base);
2365 } else {
2366 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2367 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2368 ret = 0;
2369
2370 release_region(cfg_base, 2);
2371 }
2372
2373 return ret;
2374}
2375
2376static int __init smsc_superio_lpc(unsigned short cfg_base)
2377{
2378 int ret = -1;
2379
2380 if (!request_region(cfg_base, 2, driver_name)) {
2381 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2382 __func__, cfg_base);
2383 } else {
2384 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2385 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2386 ret = 0;
2387
2388 release_region(cfg_base, 2);
2389 }
2390 return ret;
2391}
2392
2393/*
2394 * Look for some specific subsystem setups that need
2395 * pre-configuration not properly done by the BIOS (especially laptops)
2396 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2397 * and tosh2450-smcinit.c. The table lists the device entries
2398 * for ISA bridges with an LPC (Low Pin Count) controller which
2399 * handles the communication with the SMSC device. After the LPC
2400 * controller is initialized through PCI, the SMSC device is initialized
2401 * through a dedicated port in the ISA port-mapped I/O area, this latter
2402 * area is used to configure the SMSC device with default
2403 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2404 * used different sets of parameters and different control port
2405 * addresses making a subsystem device table necessary.
2406 */
2407#ifdef CONFIG_PCI
2408static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2409 /*
2410 * Subsystems needing entries:
2411 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2412 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2413 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2414 */
2415 {
2416 /* Guessed entry */
2417 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2418 .device = 0x24cc,
2419 .subvendor = 0x103c,
2420 .subdevice = 0x08bc,
2421 .sir_io = 0x02f8,
2422 .fir_io = 0x0130,
2423 .fir_irq = 0x05,
2424 .fir_dma = 0x03,
2425 .cfg_base = 0x004e,
2426 .preconfigure = preconfigure_through_82801,
2427 .name = "HP nx5000 family",
2428 },
2429 {
2430 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2431 .device = 0x24cc,
2432 .subvendor = 0x103c,
2433 .subdevice = 0x088c,
2434 /* Quite certain these are the same for nc8000 as for nc6000 */
2435 .sir_io = 0x02f8,
2436 .fir_io = 0x0130,
2437 .fir_irq = 0x05,
2438 .fir_dma = 0x03,
2439 .cfg_base = 0x004e,
2440 .preconfigure = preconfigure_through_82801,
2441 .name = "HP nc8000 family",
2442 },
2443 {
2444 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2445 .device = 0x24cc,
2446 .subvendor = 0x103c,
2447 .subdevice = 0x0890,
2448 .sir_io = 0x02f8,
2449 .fir_io = 0x0130,
2450 .fir_irq = 0x05,
2451 .fir_dma = 0x03,
2452 .cfg_base = 0x004e,
2453 .preconfigure = preconfigure_through_82801,
2454 .name = "HP nc6000 family",
2455 },
2456 {
2457 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2458 .device = 0x24cc,
2459 .subvendor = 0x0e11,
2460 .subdevice = 0x0860,
2461 /* I assume these are the same for x1000 as for the others */
2462 .sir_io = 0x02e8,
2463 .fir_io = 0x02f8,
2464 .fir_irq = 0x07,
2465 .fir_dma = 0x03,
2466 .cfg_base = 0x002e,
2467 .preconfigure = preconfigure_through_82801,
2468 .name = "Compaq x1000 family",
2469 },
2470 {
2471 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2472 .vendor = PCI_VENDOR_ID_INTEL,
2473 .device = 0x24c0,
2474 .subvendor = 0x1179,
2475 .subdevice = 0xffff, /* 0xffff is "any" */
2476 .sir_io = 0x03f8,
2477 .fir_io = 0x0130,
2478 .fir_irq = 0x07,
2479 .fir_dma = 0x01,
2480 .cfg_base = 0x002e,
2481 .preconfigure = preconfigure_through_82801,
2482 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2483 },
2484 {
2485 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
2486 .device = 0x248c,
2487 .subvendor = 0x1179,
2488 .subdevice = 0xffff, /* 0xffff is "any" */
2489 .sir_io = 0x03f8,
2490 .fir_io = 0x0130,
2491 .fir_irq = 0x03,
2492 .fir_dma = 0x03,
2493 .cfg_base = 0x002e,
2494 .preconfigure = preconfigure_through_82801,
2495 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2496 },
2497 {
2498 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2499 .vendor = PCI_VENDOR_ID_INTEL,
2500 .device = 0x24cc,
2501 .subvendor = 0x1179,
2502 .subdevice = 0xffff, /* 0xffff is "any" */
2503 .sir_io = 0x03f8,
2504 .fir_io = 0x0130,
2505 .fir_irq = 0x03,
2506 .fir_dma = 0x03,
2507 .cfg_base = 0x002e,
2508 .preconfigure = preconfigure_through_82801,
2509 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2510 },
2511 {
2512 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2513 .vendor = PCI_VENDOR_ID_AL,
2514 .device = 0x1533,
2515 .subvendor = 0x1179,
2516 .subdevice = 0xffff, /* 0xffff is "any" */
2517 .sir_io = 0x02e8,
2518 .fir_io = 0x02f8,
2519 .fir_irq = 0x07,
2520 .fir_dma = 0x03,
2521 .cfg_base = 0x002e,
2522 .preconfigure = preconfigure_through_ali,
2523 .name = "Toshiba laptop with ALi ISA bridge",
2524 },
2525 { } // Terminator
2526};
2527
2528
2529/*
2530 * This sets up the basic SMSC parameters
2531 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2532 * through the chip configuration port.
2533 */
2534static int __init preconfigure_smsc_chip(struct
2535 smsc_ircc_subsystem_configuration
2536 *conf)
2537{
2538 unsigned short iobase = conf->cfg_base;
2539 unsigned char tmpbyte;
2540
2541 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2542 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2543 tmpbyte = inb(iobase +1); // Read device ID
2544 IRDA_DEBUG(0,
2545 "Detected Chip id: 0x%02x, setting up registers...\n",
2546 tmpbyte);
2547
2548 /* Disable UART1 and set up SIR I/O port */
2549 outb(0x24, iobase); // select CR24 - UART1 base addr
2550 outb(0x00, iobase + 1); // disable UART1
2551 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2552 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2553 tmpbyte = inb(iobase + 1);
2554 if (tmpbyte != (conf->sir_io >> 2) ) {
2555 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2556 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2557 return -ENXIO;
2558 }
2559
2560 /* Set up FIR IRQ channel for UART2 */
2561 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2562 tmpbyte = inb(iobase + 1);
2563 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2564 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2565 outb(tmpbyte, iobase + 1);
2566 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2567 if (tmpbyte != conf->fir_irq) {
2568 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2569 return -ENXIO;
2570 }
2571
2572 /* Set up FIR I/O port */
2573 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2574 outb((conf->fir_io >> 3), iobase + 1);
2575 tmpbyte = inb(iobase + 1);
2576 if (tmpbyte != (conf->fir_io >> 3) ) {
2577 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2578 return -ENXIO;
2579 }
2580
2581 /* Set up FIR DMA channel */
2582 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2583 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2584 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2585 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2586 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2587 return -ENXIO;
2588 }
2589
2590 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2591 tmpbyte = inb(iobase + 1);
2592 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2593 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2594 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2595
2596 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2597 tmpbyte = inb(iobase + 1);
2598 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2599
2600 /* This one was not part of tosh1800 */
2601 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2602 tmpbyte = inb(iobase + 1);
2603 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2604
2605 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2606 tmpbyte = inb(iobase + 1);
2607 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2608
2609 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2610 tmpbyte = inb(iobase + 1);
2611 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2612
2613 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2614
2615 return 0;
2616}
2617
2618/* 82801CAM generic registers */
2619#define VID 0x00
2620#define DID 0x02
2621#define PIRQ_A_D_ROUT 0x60
2622#define SIRQ_CNTL 0x64
2623#define PIRQ_E_H_ROUT 0x68
2624#define PCI_DMA_C 0x90
2625/* LPC-specific registers */
2626#define COM_DEC 0xe0
2627#define GEN1_DEC 0xe4
2628#define LPC_EN 0xe6
2629#define GEN2_DEC 0xec
2630/*
2631 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2632 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2633 * They all work the same way!
2634 */
2635static int __init preconfigure_through_82801(struct pci_dev *dev,
2636 struct
2637 smsc_ircc_subsystem_configuration
2638 *conf)
2639{
2640 unsigned short tmpword;
2641 unsigned char tmpbyte;
2642
2643 IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2644 /*
2645 * Select the range for the COMA COM port (SIR)
2646 * Register COM_DEC:
2647 * Bit 7: reserved
2648 * Bit 6-4, COMB decode range
2649 * Bit 3: reserved
2650 * Bit 2-0, COMA decode range
2651 *
2652 * Decode ranges:
2653 * 000 = 0x3f8-0x3ff (COM1)
2654 * 001 = 0x2f8-0x2ff (COM2)
2655 * 010 = 0x220-0x227
2656 * 011 = 0x228-0x22f
2657 * 100 = 0x238-0x23f
2658 * 101 = 0x2e8-0x2ef (COM4)
2659 * 110 = 0x338-0x33f
2660 * 111 = 0x3e8-0x3ef (COM3)
2661 */
2662 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2663 tmpbyte &= 0xf8; /* mask COMA bits */
2664 switch(conf->sir_io) {
2665 case 0x3f8:
2666 tmpbyte |= 0x00;
2667 break;
2668 case 0x2f8:
2669 tmpbyte |= 0x01;
2670 break;
2671 case 0x220:
2672 tmpbyte |= 0x02;
2673 break;
2674 case 0x228:
2675 tmpbyte |= 0x03;
2676 break;
2677 case 0x238:
2678 tmpbyte |= 0x04;
2679 break;
2680 case 0x2e8:
2681 tmpbyte |= 0x05;
2682 break;
2683 case 0x338:
2684 tmpbyte |= 0x06;
2685 break;
2686 case 0x3e8:
2687 tmpbyte |= 0x07;
2688 break;
2689 default:
2690 tmpbyte |= 0x01; /* COM2 default */
2691 }
2692 IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2693 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2694
2695 /* Enable Low Pin Count interface */
2696 pci_read_config_word(dev, LPC_EN, &tmpword);
2697 /* These seem to be set up at all times,
2698 * just make sure it is properly set.
2699 */
2700 switch(conf->cfg_base) {
2701 case 0x04e:
2702 tmpword |= 0x2000;
2703 break;
2704 case 0x02e:
2705 tmpword |= 0x1000;
2706 break;
2707 case 0x062:
2708 tmpword |= 0x0800;
2709 break;
2710 case 0x060:
2711 tmpword |= 0x0400;
2712 break;
2713 default:
2714 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2715 conf->cfg_base);
2716 break;
2717 }
2718 tmpword &= 0xfffd; /* disable LPC COMB */
2719 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2720 IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2721 pci_write_config_word(dev, LPC_EN, tmpword);
2722
2723 /*
2724 * Configure LPC DMA channel
2725 * PCI_DMA_C bits:
2726 * Bit 15-14: DMA channel 7 select
2727 * Bit 13-12: DMA channel 6 select
2728 * Bit 11-10: DMA channel 5 select
2729 * Bit 9-8: Reserved
2730 * Bit 7-6: DMA channel 3 select
2731 * Bit 5-4: DMA channel 2 select
2732 * Bit 3-2: DMA channel 1 select
2733 * Bit 1-0: DMA channel 0 select
2734 * 00 = Reserved value
2735 * 01 = PC/PCI DMA
2736 * 10 = Reserved value
2737 * 11 = LPC I/F DMA
2738 */
2739 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2740 switch(conf->fir_dma) {
2741 case 0x07:
2742 tmpword |= 0xc000;
2743 break;
2744 case 0x06:
2745 tmpword |= 0x3000;
2746 break;
2747 case 0x05:
2748 tmpword |= 0x0c00;
2749 break;
2750 case 0x03:
2751 tmpword |= 0x00c0;
2752 break;
2753 case 0x02:
2754 tmpword |= 0x0030;
2755 break;
2756 case 0x01:
2757 tmpword |= 0x000c;
2758 break;
2759 case 0x00:
2760 tmpword |= 0x0003;
2761 break;
2762 default:
2763 break; /* do not change settings */
2764 }
2765 IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2766 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2767
2768 /*
2769 * GEN2_DEC bits:
2770 * Bit 15-4: Generic I/O range
2771 * Bit 3-1: reserved (read as 0)
2772 * Bit 0: enable GEN2 range on LPC I/F
2773 */
2774 tmpword = conf->fir_io & 0xfff8;
2775 tmpword |= 0x0001;
2776 IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2777 pci_write_config_word(dev, GEN2_DEC, tmpword);
2778
2779 /* Pre-configure chip */
2780 return preconfigure_smsc_chip(conf);
2781}
2782
2783/*
2784 * Pre-configure a certain port on the ALi 1533 bridge.
2785 * This is based on reverse-engineering since ALi does not
2786 * provide any data sheet for the 1533 chip.
2787 */
2788static void __init preconfigure_ali_port(struct pci_dev *dev,
2789 unsigned short port)
2790{
2791 unsigned char reg;
2792 /* These bits obviously control the different ports */
2793 unsigned char mask;
2794 unsigned char tmpbyte;
2795
2796 switch(port) {
2797 case 0x0130:
2798 case 0x0178:
2799 reg = 0xb0;
2800 mask = 0x80;
2801 break;
2802 case 0x03f8:
2803 reg = 0xb4;
2804 mask = 0x80;
2805 break;
2806 case 0x02f8:
2807 reg = 0xb4;
2808 mask = 0x30;
2809 break;
2810 case 0x02e8:
2811 reg = 0xb4;
2812 mask = 0x08;
2813 break;
2814 default:
2815 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2816 return;
2817 }
2818
2819 pci_read_config_byte(dev, reg, &tmpbyte);
2820 /* Turn on the right bits */
2821 tmpbyte |= mask;
2822 pci_write_config_byte(dev, reg, tmpbyte);
2823 IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2824}
2825
2826static int __init preconfigure_through_ali(struct pci_dev *dev,
2827 struct
2828 smsc_ircc_subsystem_configuration
2829 *conf)
2830{
2831 /* Configure the two ports on the ALi 1533 */
2832 preconfigure_ali_port(dev, conf->sir_io);
2833 preconfigure_ali_port(dev, conf->fir_io);
2834
2835 /* Pre-configure chip */
2836 return preconfigure_smsc_chip(conf);
2837}
2838
2839static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2840 unsigned short ircc_fir,
2841 unsigned short ircc_sir,
2842 unsigned char ircc_dma,
2843 unsigned char ircc_irq)
2844{
2845 struct pci_dev *dev = NULL;
2846 unsigned short ss_vendor = 0x0000;
2847 unsigned short ss_device = 0x0000;
2848 int ret = 0;
2849
2850 for_each_pci_dev(dev) {
2851 struct smsc_ircc_subsystem_configuration *conf;
2852
2853 /*
2854 * Cache the subsystem vendor/device:
2855 * some manufacturers fail to set this for all components,
2856 * so we save it in case there is just 0x0000 0x0000 on the
2857 * device we want to check.
2858 */
2859 if (dev->subsystem_vendor != 0x0000U) {
2860 ss_vendor = dev->subsystem_vendor;
2861 ss_device = dev->subsystem_device;
2862 }
2863 conf = subsystem_configurations;
2864 for( ; conf->subvendor; conf++) {
2865 if(conf->vendor == dev->vendor &&
2866 conf->device == dev->device &&
2867 conf->subvendor == ss_vendor &&
2868 /* Sometimes these are cached values */
2869 (conf->subdevice == ss_device ||
2870 conf->subdevice == 0xffff)) {
2871 struct smsc_ircc_subsystem_configuration
2872 tmpconf;
2873
2874 memcpy(&tmpconf, conf,
2875 sizeof(struct smsc_ircc_subsystem_configuration));
2876
2877 /*
2878 * Override the default values with anything
2879 * passed in as parameter
2880 */
2881 if (ircc_cfg != 0)
2882 tmpconf.cfg_base = ircc_cfg;
2883 if (ircc_fir != 0)
2884 tmpconf.fir_io = ircc_fir;
2885 if (ircc_sir != 0)
2886 tmpconf.sir_io = ircc_sir;
2887 if (ircc_dma != DMA_INVAL)
2888 tmpconf.fir_dma = ircc_dma;
2889 if (ircc_irq != IRQ_INVAL)
2890 tmpconf.fir_irq = ircc_irq;
2891
2892 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2893 if (conf->preconfigure)
2894 ret = conf->preconfigure(dev, &tmpconf);
2895 else
2896 ret = -ENODEV;
2897 }
2898 }
2899 }
2900
2901 return ret;
2902}
2903#endif // CONFIG_PCI
2904
2905/************************************************
2906 *
2907 * Transceivers specific functions
2908 *
2909 ************************************************/
2910
2911
2912/*
2913 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2914 *
2915 * Program transceiver through smsc-ircc ATC circuitry
2916 *
2917 */
2918
2919static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2920{
2921 unsigned long jiffies_now, jiffies_timeout;
2922 u8 val;
2923
2924 jiffies_now = jiffies;
2925 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2926
2927 /* ATC */
2928 register_bank(fir_base, 4);
2929 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2930 fir_base + IRCC_ATC);
2931
2932 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2933 !time_after(jiffies, jiffies_timeout))
2934 /* empty */;
2935
2936 if (val)
2937 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2938 inb(fir_base + IRCC_ATC));
2939}
2940
2941/*
2942 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2943 *
2944 * Probe transceiver smsc-ircc ATC circuitry
2945 *
2946 */
2947
2948static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2949{
2950 return 0;
2951}
2952
2953/*
2954 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2955 *
2956 * Set transceiver
2957 *
2958 */
2959
2960static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2961{
2962 u8 fast_mode;
2963
2964 switch (speed) {
2965 default:
2966 case 576000 :
2967 fast_mode = 0;
2968 break;
2969 case 1152000 :
2970 case 4000000 :
2971 fast_mode = IRCC_LCR_A_FAST;
2972 break;
2973 }
2974 register_bank(fir_base, 0);
2975 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2976}
2977
2978/*
2979 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2980 *
2981 * Probe transceiver
2982 *
2983 */
2984
2985static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2986{
2987 return 0;
2988}
2989
2990/*
2991 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2992 *
2993 * Set transceiver
2994 *
2995 */
2996
2997static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2998{
2999 u8 fast_mode;
3000
3001 switch (speed) {
3002 default:
3003 case 576000 :
3004 fast_mode = 0;
3005 break;
3006 case 1152000 :
3007 case 4000000 :
3008 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3009 break;
3010
3011 }
3012 /* This causes an interrupt */
3013 register_bank(fir_base, 0);
3014 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3015}
3016
3017/*
3018 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3019 *
3020 * Probe transceiver
3021 *
3022 */
3023
3024static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3025{
3026 return 0;
3027}
3028
3029
3030module_init(smsc_ircc_init);
3031module_exit(smsc_ircc_cleanup);
1/*********************************************************************
2 *
3 * Description: Driver for the SMC Infrared Communications Controller
4 * Author: Daniele Peri (peri@csai.unipa.it)
5 * Created at:
6 * Modified at:
7 * Modified by:
8 *
9 * Copyright (c) 2002 Daniele Peri
10 * All Rights Reserved.
11 * Copyright (c) 2002 Jean Tourrilhes
12 * Copyright (c) 2006 Linus Walleij
13 *
14 *
15 * Based on smc-ircc.c:
16 *
17 * Copyright (c) 2001 Stefani Seibold
18 * Copyright (c) 1999-2001 Dag Brattli
19 * Copyright (c) 1998-1999 Thomas Davis,
20 *
21 * and irport.c:
22 *
23 * Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
24 *
25 *
26 * This program is free software; you can redistribute it and/or
27 * modify it under the terms of the GNU General Public License as
28 * published by the Free Software Foundation; either version 2 of
29 * the License, or (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, see <http://www.gnu.org/licenses/>.
38 *
39 ********************************************************************/
40
41#include <linux/module.h>
42#include <linux/kernel.h>
43#include <linux/types.h>
44#include <linux/skbuff.h>
45#include <linux/netdevice.h>
46#include <linux/ioport.h>
47#include <linux/delay.h>
48#include <linux/init.h>
49#include <linux/interrupt.h>
50#include <linux/rtnetlink.h>
51#include <linux/serial_reg.h>
52#include <linux/dma-mapping.h>
53#include <linux/pnp.h>
54#include <linux/platform_device.h>
55#include <linux/gfp.h>
56
57#include <asm/io.h>
58#include <asm/dma.h>
59#include <asm/byteorder.h>
60
61#include <linux/spinlock.h>
62#include <linux/pm.h>
63#ifdef CONFIG_PCI
64#include <linux/pci.h>
65#endif
66
67#include <net/irda/wrapper.h>
68#include <net/irda/irda.h>
69#include <net/irda/irda_device.h>
70
71#include "smsc-ircc2.h"
72#include "smsc-sio.h"
73
74
75MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
76MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
77MODULE_LICENSE("GPL");
78
79static bool smsc_nopnp = true;
80module_param_named(nopnp, smsc_nopnp, bool, 0);
81MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
82
83#define DMA_INVAL 255
84static int ircc_dma = DMA_INVAL;
85module_param(ircc_dma, int, 0);
86MODULE_PARM_DESC(ircc_dma, "DMA channel");
87
88#define IRQ_INVAL 255
89static int ircc_irq = IRQ_INVAL;
90module_param(ircc_irq, int, 0);
91MODULE_PARM_DESC(ircc_irq, "IRQ line");
92
93static int ircc_fir;
94module_param(ircc_fir, int, 0);
95MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
96
97static int ircc_sir;
98module_param(ircc_sir, int, 0);
99MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
100
101static int ircc_cfg;
102module_param(ircc_cfg, int, 0);
103MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
104
105static int ircc_transceiver;
106module_param(ircc_transceiver, int, 0);
107MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
108
109/* Types */
110
111#ifdef CONFIG_PCI
112struct smsc_ircc_subsystem_configuration {
113 unsigned short vendor; /* PCI vendor ID */
114 unsigned short device; /* PCI vendor ID */
115 unsigned short subvendor; /* PCI subsystem vendor ID */
116 unsigned short subdevice; /* PCI subsystem device ID */
117 unsigned short sir_io; /* I/O port for SIR */
118 unsigned short fir_io; /* I/O port for FIR */
119 unsigned char fir_irq; /* FIR IRQ */
120 unsigned char fir_dma; /* FIR DMA */
121 unsigned short cfg_base; /* I/O port for chip configuration */
122 int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
123 const char *name; /* name shown as info */
124};
125#endif
126
127struct smsc_transceiver {
128 char *name;
129 void (*set_for_speed)(int fir_base, u32 speed);
130 int (*probe)(int fir_base);
131};
132
133struct smsc_chip {
134 char *name;
135 #if 0
136 u8 type;
137 #endif
138 u16 flags;
139 u8 devid;
140 u8 rev;
141};
142
143struct smsc_chip_address {
144 unsigned int cfg_base;
145 unsigned int type;
146};
147
148/* Private data for each instance */
149struct smsc_ircc_cb {
150 struct net_device *netdev; /* Yes! we are some kind of netdevice */
151 struct irlap_cb *irlap; /* The link layer we are binded to */
152
153 chipio_t io; /* IrDA controller information */
154 iobuff_t tx_buff; /* Transmit buffer */
155 iobuff_t rx_buff; /* Receive buffer */
156 dma_addr_t tx_buff_dma;
157 dma_addr_t rx_buff_dma;
158
159 struct qos_info qos; /* QoS capabilities for this device */
160
161 spinlock_t lock; /* For serializing operations */
162
163 __u32 new_speed;
164 __u32 flags; /* Interface flags */
165
166 int tx_buff_offsets[10]; /* Offsets between frames in tx_buff */
167 int tx_len; /* Number of frames in tx_buff */
168
169 int transceiver;
170 struct platform_device *pldev;
171};
172
173/* Constants */
174
175#define SMSC_IRCC2_DRIVER_NAME "smsc-ircc2"
176
177#define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED 9600
178#define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER 1
179#define SMSC_IRCC2_C_NET_TIMEOUT 0
180#define SMSC_IRCC2_C_SIR_STOP 0
181
182static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
183
184/* Prototypes */
185
186static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
187static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
188static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
189static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
190static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
191static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
192static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
193static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
194static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
195static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
196 struct net_device *dev);
197static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
198 struct net_device *dev);
199static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
200static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
201static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
202static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
203static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
204static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
205static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
206#if SMSC_IRCC2_C_SIR_STOP
207static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
208#endif
209static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
210static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
211static int smsc_ircc_net_open(struct net_device *dev);
212static int smsc_ircc_net_close(struct net_device *dev);
213static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
214#if SMSC_IRCC2_C_NET_TIMEOUT
215static void smsc_ircc_timeout(struct net_device *dev);
216#endif
217static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
218static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
219static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
220static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
221
222/* Probing */
223static int __init smsc_ircc_look_for_chips(void);
224static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
225static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
226static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
227static int __init smsc_superio_fdc(unsigned short cfg_base);
228static int __init smsc_superio_lpc(unsigned short cfg_base);
229#ifdef CONFIG_PCI
230static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
231static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
232static void __init preconfigure_ali_port(struct pci_dev *dev,
233 unsigned short port);
234static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
235static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
236 unsigned short ircc_fir,
237 unsigned short ircc_sir,
238 unsigned char ircc_dma,
239 unsigned char ircc_irq);
240#endif
241
242/* Transceivers specific functions */
243
244static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
245static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
246static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
247static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
248static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
249static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
250
251/* Power Management */
252
253static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
254static int smsc_ircc_resume(struct platform_device *dev);
255
256static struct platform_driver smsc_ircc_driver = {
257 .suspend = smsc_ircc_suspend,
258 .resume = smsc_ircc_resume,
259 .driver = {
260 .name = SMSC_IRCC2_DRIVER_NAME,
261 },
262};
263
264/* Transceivers for SMSC-ircc */
265
266static struct smsc_transceiver smsc_transceivers[] =
267{
268 { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
269 { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
270 { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
271 { NULL, NULL }
272};
273#define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
274
275/* SMC SuperIO chipsets definitions */
276
277#define KEY55_1 0 /* SuperIO Configuration mode with Key <0x55> */
278#define KEY55_2 1 /* SuperIO Configuration mode with Key <0x55,0x55> */
279#define NoIRDA 2 /* SuperIO Chip has no IRDA Port */
280#define SIR 0 /* SuperIO Chip has only slow IRDA */
281#define FIR 4 /* SuperIO Chip has fast IRDA */
282#define SERx4 8 /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
283
284static struct smsc_chip __initdata fdc_chips_flat[] =
285{
286 /* Base address 0x3f0 or 0x370 */
287 { "37C44", KEY55_1|NoIRDA, 0x00, 0x00 }, /* This chip cannot be detected */
288 { "37C665GT", KEY55_2|NoIRDA, 0x65, 0x01 },
289 { "37C665GT", KEY55_2|NoIRDA, 0x66, 0x01 },
290 { "37C669", KEY55_2|SIR|SERx4, 0x03, 0x02 },
291 { "37C669", KEY55_2|SIR|SERx4, 0x04, 0x02 }, /* ID? */
292 { "37C78", KEY55_2|NoIRDA, 0x78, 0x00 },
293 { "37N769", KEY55_1|FIR|SERx4, 0x28, 0x00 },
294 { "37N869", KEY55_1|FIR|SERx4, 0x29, 0x00 },
295 { NULL }
296};
297
298static struct smsc_chip __initdata fdc_chips_paged[] =
299{
300 /* Base address 0x3f0 or 0x370 */
301 { "37B72X", KEY55_1|SIR|SERx4, 0x4c, 0x00 },
302 { "37B77X", KEY55_1|SIR|SERx4, 0x43, 0x00 },
303 { "37B78X", KEY55_1|SIR|SERx4, 0x44, 0x00 },
304 { "37B80X", KEY55_1|SIR|SERx4, 0x42, 0x00 },
305 { "37C67X", KEY55_1|FIR|SERx4, 0x40, 0x00 },
306 { "37C93X", KEY55_2|SIR|SERx4, 0x02, 0x01 },
307 { "37C93XAPM", KEY55_1|SIR|SERx4, 0x30, 0x01 },
308 { "37C93XFR", KEY55_2|FIR|SERx4, 0x03, 0x01 },
309 { "37M707", KEY55_1|SIR|SERx4, 0x42, 0x00 },
310 { "37M81X", KEY55_1|SIR|SERx4, 0x4d, 0x00 },
311 { "37N958FR", KEY55_1|FIR|SERx4, 0x09, 0x04 },
312 { "37N971", KEY55_1|FIR|SERx4, 0x0a, 0x00 },
313 { "37N972", KEY55_1|FIR|SERx4, 0x0b, 0x00 },
314 { NULL }
315};
316
317static struct smsc_chip __initdata lpc_chips_flat[] =
318{
319 /* Base address 0x2E or 0x4E */
320 { "47N227", KEY55_1|FIR|SERx4, 0x5a, 0x00 },
321 { "47N227", KEY55_1|FIR|SERx4, 0x7a, 0x00 },
322 { "47N267", KEY55_1|FIR|SERx4, 0x5e, 0x00 },
323 { NULL }
324};
325
326static struct smsc_chip __initdata lpc_chips_paged[] =
327{
328 /* Base address 0x2E or 0x4E */
329 { "47B27X", KEY55_1|SIR|SERx4, 0x51, 0x00 },
330 { "47B37X", KEY55_1|SIR|SERx4, 0x52, 0x00 },
331 { "47M10X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
332 { "47M120", KEY55_1|NoIRDA|SERx4, 0x5c, 0x00 },
333 { "47M13X", KEY55_1|SIR|SERx4, 0x59, 0x00 },
334 { "47M14X", KEY55_1|SIR|SERx4, 0x5f, 0x00 },
335 { "47N252", KEY55_1|FIR|SERx4, 0x0e, 0x00 },
336 { "47S42X", KEY55_1|SIR|SERx4, 0x57, 0x00 },
337 { NULL }
338};
339
340#define SMSCSIO_TYPE_FDC 1
341#define SMSCSIO_TYPE_LPC 2
342#define SMSCSIO_TYPE_FLAT 4
343#define SMSCSIO_TYPE_PAGED 8
344
345static struct smsc_chip_address __initdata possible_addresses[] =
346{
347 { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
348 { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
349 { 0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
350 { 0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
351 { 0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
352 { 0, 0 }
353};
354
355/* Globals */
356
357static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
358static unsigned short dev_count;
359
360static inline void register_bank(int iobase, int bank)
361{
362 outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
363 iobase + IRCC_MASTER);
364}
365
366/* PNP hotplug support */
367static const struct pnp_device_id smsc_ircc_pnp_table[] = {
368 { .id = "SMCf010", .driver_data = 0 },
369 /* and presumably others */
370 { }
371};
372MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
373
374static int pnp_driver_registered;
375
376#ifdef CONFIG_PNP
377static int smsc_ircc_pnp_probe(struct pnp_dev *dev,
378 const struct pnp_device_id *dev_id)
379{
380 unsigned int firbase, sirbase;
381 u8 dma, irq;
382
383 if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
384 pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
385 return -EINVAL;
386
387 sirbase = pnp_port_start(dev, 0);
388 firbase = pnp_port_start(dev, 1);
389 dma = pnp_dma(dev, 0);
390 irq = pnp_irq(dev, 0);
391
392 if (smsc_ircc_open(firbase, sirbase, dma, irq))
393 return -ENODEV;
394
395 return 0;
396}
397
398static struct pnp_driver smsc_ircc_pnp_driver = {
399 .name = "smsc-ircc2",
400 .id_table = smsc_ircc_pnp_table,
401 .probe = smsc_ircc_pnp_probe,
402};
403#else /* CONFIG_PNP */
404static struct pnp_driver smsc_ircc_pnp_driver;
405#endif
406
407/*******************************************************************************
408 *
409 *
410 * SMSC-ircc stuff
411 *
412 *
413 *******************************************************************************/
414
415static int __init smsc_ircc_legacy_probe(void)
416{
417 int ret = 0;
418
419#ifdef CONFIG_PCI
420 if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
421 /* Ignore errors from preconfiguration */
422 net_err_ratelimited("%s, Preconfiguration failed !\n",
423 driver_name);
424 }
425#endif
426
427 if (ircc_fir > 0 && ircc_sir > 0) {
428 net_info_ratelimited(" Overriding FIR address 0x%04x\n",
429 ircc_fir);
430 net_info_ratelimited(" Overriding SIR address 0x%04x\n",
431 ircc_sir);
432
433 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
434 ret = -ENODEV;
435 } else {
436 ret = -ENODEV;
437
438 /* try user provided configuration register base address */
439 if (ircc_cfg > 0) {
440 net_info_ratelimited(" Overriding configuration address 0x%04x\n",
441 ircc_cfg);
442 if (!smsc_superio_fdc(ircc_cfg))
443 ret = 0;
444 if (!smsc_superio_lpc(ircc_cfg))
445 ret = 0;
446 }
447
448 if (smsc_ircc_look_for_chips() > 0)
449 ret = 0;
450 }
451 return ret;
452}
453
454/*
455 * Function smsc_ircc_init ()
456 *
457 * Initialize chip. Just try to find out how many chips we are dealing with
458 * and where they are
459 */
460static int __init smsc_ircc_init(void)
461{
462 int ret;
463
464 pr_debug("%s\n", __func__);
465
466 ret = platform_driver_register(&smsc_ircc_driver);
467 if (ret) {
468 net_err_ratelimited("%s, Can't register driver!\n",
469 driver_name);
470 return ret;
471 }
472
473 dev_count = 0;
474
475 if (smsc_nopnp || !pnp_platform_devices ||
476 ircc_cfg || ircc_fir || ircc_sir ||
477 ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
478 ret = smsc_ircc_legacy_probe();
479 } else {
480 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
481 pnp_driver_registered = 1;
482 }
483
484 if (ret) {
485 if (pnp_driver_registered)
486 pnp_unregister_driver(&smsc_ircc_pnp_driver);
487 platform_driver_unregister(&smsc_ircc_driver);
488 }
489
490 return ret;
491}
492
493static netdev_tx_t smsc_ircc_net_xmit(struct sk_buff *skb,
494 struct net_device *dev)
495{
496 struct smsc_ircc_cb *self = netdev_priv(dev);
497
498 if (self->io.speed > 115200)
499 return smsc_ircc_hard_xmit_fir(skb, dev);
500 else
501 return smsc_ircc_hard_xmit_sir(skb, dev);
502}
503
504static const struct net_device_ops smsc_ircc_netdev_ops = {
505 .ndo_open = smsc_ircc_net_open,
506 .ndo_stop = smsc_ircc_net_close,
507 .ndo_do_ioctl = smsc_ircc_net_ioctl,
508 .ndo_start_xmit = smsc_ircc_net_xmit,
509#if SMSC_IRCC2_C_NET_TIMEOUT
510 .ndo_tx_timeout = smsc_ircc_timeout,
511#endif
512};
513
514/*
515 * Function smsc_ircc_open (firbase, sirbase, dma, irq)
516 *
517 * Try to open driver instance
518 *
519 */
520static int smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
521{
522 struct smsc_ircc_cb *self;
523 struct net_device *dev;
524 int err;
525
526 pr_debug("%s\n", __func__);
527
528 err = smsc_ircc_present(fir_base, sir_base);
529 if (err)
530 goto err_out;
531
532 err = -ENOMEM;
533 if (dev_count >= ARRAY_SIZE(dev_self)) {
534 net_warn_ratelimited("%s(), too many devices!\n", __func__);
535 goto err_out1;
536 }
537
538 /*
539 * Allocate new instance of the driver
540 */
541 dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
542 if (!dev) {
543 net_warn_ratelimited("%s() can't allocate net device\n",
544 __func__);
545 goto err_out1;
546 }
547
548#if SMSC_IRCC2_C_NET_TIMEOUT
549 dev->watchdog_timeo = HZ * 2; /* Allow enough time for speed change */
550#endif
551 dev->netdev_ops = &smsc_ircc_netdev_ops;
552
553 self = netdev_priv(dev);
554 self->netdev = dev;
555
556 /* Make ifconfig display some details */
557 dev->base_addr = self->io.fir_base = fir_base;
558 dev->irq = self->io.irq = irq;
559
560 /* Need to store self somewhere */
561 dev_self[dev_count] = self;
562 spin_lock_init(&self->lock);
563
564 self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
565 self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
566
567 self->rx_buff.head =
568 dma_zalloc_coherent(NULL, self->rx_buff.truesize,
569 &self->rx_buff_dma, GFP_KERNEL);
570 if (self->rx_buff.head == NULL)
571 goto err_out2;
572
573 self->tx_buff.head =
574 dma_zalloc_coherent(NULL, self->tx_buff.truesize,
575 &self->tx_buff_dma, GFP_KERNEL);
576 if (self->tx_buff.head == NULL)
577 goto err_out3;
578
579 self->rx_buff.in_frame = FALSE;
580 self->rx_buff.state = OUTSIDE_FRAME;
581 self->tx_buff.data = self->tx_buff.head;
582 self->rx_buff.data = self->rx_buff.head;
583
584 smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
585 smsc_ircc_setup_qos(self);
586 smsc_ircc_init_chip(self);
587
588 if (ircc_transceiver > 0 &&
589 ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
590 self->transceiver = ircc_transceiver;
591 else
592 smsc_ircc_probe_transceiver(self);
593
594 err = register_netdev(self->netdev);
595 if (err) {
596 net_err_ratelimited("%s, Network device registration failed!\n",
597 driver_name);
598 goto err_out4;
599 }
600
601 self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
602 dev_count, NULL, 0);
603 if (IS_ERR(self->pldev)) {
604 err = PTR_ERR(self->pldev);
605 goto err_out5;
606 }
607 platform_set_drvdata(self->pldev, self);
608
609 net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
610 dev_count++;
611
612 return 0;
613
614 err_out5:
615 unregister_netdev(self->netdev);
616
617 err_out4:
618 dma_free_coherent(NULL, self->tx_buff.truesize,
619 self->tx_buff.head, self->tx_buff_dma);
620 err_out3:
621 dma_free_coherent(NULL, self->rx_buff.truesize,
622 self->rx_buff.head, self->rx_buff_dma);
623 err_out2:
624 free_netdev(self->netdev);
625 dev_self[dev_count] = NULL;
626 err_out1:
627 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
628 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
629 err_out:
630 return err;
631}
632
633/*
634 * Function smsc_ircc_present(fir_base, sir_base)
635 *
636 * Check the smsc-ircc chip presence
637 *
638 */
639static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
640{
641 unsigned char low, high, chip, config, dma, irq, version;
642
643 if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
644 driver_name)) {
645 net_warn_ratelimited("%s: can't get fir_base of 0x%03x\n",
646 __func__, fir_base);
647 goto out1;
648 }
649
650 if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
651 driver_name)) {
652 net_warn_ratelimited("%s: can't get sir_base of 0x%03x\n",
653 __func__, sir_base);
654 goto out2;
655 }
656
657 register_bank(fir_base, 3);
658
659 high = inb(fir_base + IRCC_ID_HIGH);
660 low = inb(fir_base + IRCC_ID_LOW);
661 chip = inb(fir_base + IRCC_CHIP_ID);
662 version = inb(fir_base + IRCC_VERSION);
663 config = inb(fir_base + IRCC_INTERFACE);
664 dma = config & IRCC_INTERFACE_DMA_MASK;
665 irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
666
667 if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
668 net_warn_ratelimited("%s(), addr 0x%04x - no device found!\n",
669 __func__, fir_base);
670 goto out3;
671 }
672 net_info_ratelimited("SMsC IrDA Controller found\n IrCC version %d.%d, firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
673 chip & 0x0f, version,
674 fir_base, sir_base, dma, irq);
675
676 return 0;
677
678 out3:
679 release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
680 out2:
681 release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
682 out1:
683 return -ENODEV;
684}
685
686/*
687 * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
688 *
689 * Setup I/O
690 *
691 */
692static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
693 unsigned int fir_base, unsigned int sir_base,
694 u8 dma, u8 irq)
695{
696 unsigned char config, chip_dma, chip_irq;
697
698 register_bank(fir_base, 3);
699 config = inb(fir_base + IRCC_INTERFACE);
700 chip_dma = config & IRCC_INTERFACE_DMA_MASK;
701 chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
702
703 self->io.fir_base = fir_base;
704 self->io.sir_base = sir_base;
705 self->io.fir_ext = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
706 self->io.sir_ext = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
707 self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
708 self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
709
710 if (irq != IRQ_INVAL) {
711 if (irq != chip_irq)
712 net_info_ratelimited("%s, Overriding IRQ - chip says %d, using %d\n",
713 driver_name, chip_irq, irq);
714 self->io.irq = irq;
715 } else
716 self->io.irq = chip_irq;
717
718 if (dma != DMA_INVAL) {
719 if (dma != chip_dma)
720 net_info_ratelimited("%s, Overriding DMA - chip says %d, using %d\n",
721 driver_name, chip_dma, dma);
722 self->io.dma = dma;
723 } else
724 self->io.dma = chip_dma;
725
726}
727
728/*
729 * Function smsc_ircc_setup_qos(self)
730 *
731 * Setup qos
732 *
733 */
734static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
735{
736 /* Initialize QoS for this device */
737 irda_init_max_qos_capabilies(&self->qos);
738
739 self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
740 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
741
742 self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
743 self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
744 irda_qos_bits_to_value(&self->qos);
745}
746
747/*
748 * Function smsc_ircc_init_chip(self)
749 *
750 * Init chip
751 *
752 */
753static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
754{
755 int iobase = self->io.fir_base;
756
757 register_bank(iobase, 0);
758 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
759 outb(0x00, iobase + IRCC_MASTER);
760
761 register_bank(iobase, 1);
762 outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
763 iobase + IRCC_SCE_CFGA);
764
765#ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
766 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
767 iobase + IRCC_SCE_CFGB);
768#else
769 outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
770 iobase + IRCC_SCE_CFGB);
771#endif
772 (void) inb(iobase + IRCC_FIFO_THRESHOLD);
773 outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
774
775 register_bank(iobase, 4);
776 outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
777
778 register_bank(iobase, 0);
779 outb(0, iobase + IRCC_LCR_A);
780
781 smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
782
783 /* Power on device */
784 outb(0x00, iobase + IRCC_MASTER);
785}
786
787/*
788 * Function smsc_ircc_net_ioctl (dev, rq, cmd)
789 *
790 * Process IOCTL commands for this device
791 *
792 */
793static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
794{
795 struct if_irda_req *irq = (struct if_irda_req *) rq;
796 struct smsc_ircc_cb *self;
797 unsigned long flags;
798 int ret = 0;
799
800 IRDA_ASSERT(dev != NULL, return -1;);
801
802 self = netdev_priv(dev);
803
804 IRDA_ASSERT(self != NULL, return -1;);
805
806 pr_debug("%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
807
808 switch (cmd) {
809 case SIOCSBANDWIDTH: /* Set bandwidth */
810 if (!capable(CAP_NET_ADMIN))
811 ret = -EPERM;
812 else {
813 /* Make sure we are the only one touching
814 * self->io.speed and the hardware - Jean II */
815 spin_lock_irqsave(&self->lock, flags);
816 smsc_ircc_change_speed(self, irq->ifr_baudrate);
817 spin_unlock_irqrestore(&self->lock, flags);
818 }
819 break;
820 case SIOCSMEDIABUSY: /* Set media busy */
821 if (!capable(CAP_NET_ADMIN)) {
822 ret = -EPERM;
823 break;
824 }
825
826 irda_device_set_media_busy(self->netdev, TRUE);
827 break;
828 case SIOCGRECEIVING: /* Check if we are receiving right now */
829 irq->ifr_receiving = smsc_ircc_is_receiving(self);
830 break;
831 #if 0
832 case SIOCSDTRRTS:
833 if (!capable(CAP_NET_ADMIN)) {
834 ret = -EPERM;
835 break;
836 }
837 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
838 break;
839 #endif
840 default:
841 ret = -EOPNOTSUPP;
842 }
843
844 return ret;
845}
846
847#if SMSC_IRCC2_C_NET_TIMEOUT
848/*
849 * Function smsc_ircc_timeout (struct net_device *dev)
850 *
851 * The networking timeout management.
852 *
853 */
854
855static void smsc_ircc_timeout(struct net_device *dev)
856{
857 struct smsc_ircc_cb *self = netdev_priv(dev);
858 unsigned long flags;
859
860 net_warn_ratelimited("%s: transmit timed out, changing speed to: %d\n",
861 dev->name, self->io.speed);
862 spin_lock_irqsave(&self->lock, flags);
863 smsc_ircc_sir_start(self);
864 smsc_ircc_change_speed(self, self->io.speed);
865 dev->trans_start = jiffies; /* prevent tx timeout */
866 netif_wake_queue(dev);
867 spin_unlock_irqrestore(&self->lock, flags);
868}
869#endif
870
871/*
872 * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
873 *
874 * Transmits the current frame until FIFO is full, then
875 * waits until the next transmit interrupt, and continues until the
876 * frame is transmitted.
877 */
878static netdev_tx_t smsc_ircc_hard_xmit_sir(struct sk_buff *skb,
879 struct net_device *dev)
880{
881 struct smsc_ircc_cb *self;
882 unsigned long flags;
883 s32 speed;
884
885 pr_debug("%s\n", __func__);
886
887 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
888
889 self = netdev_priv(dev);
890 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
891
892 netif_stop_queue(dev);
893
894 /* Make sure test of self->io.speed & speed change are atomic */
895 spin_lock_irqsave(&self->lock, flags);
896
897 /* Check if we need to change the speed */
898 speed = irda_get_next_speed(skb);
899 if (speed != self->io.speed && speed != -1) {
900 /* Check for empty frame */
901 if (!skb->len) {
902 /*
903 * We send frames one by one in SIR mode (no
904 * pipelining), so at this point, if we were sending
905 * a previous frame, we just received the interrupt
906 * telling us it is finished (UART_IIR_THRI).
907 * Therefore, waiting for the transmitter to really
908 * finish draining the fifo won't take too long.
909 * And the interrupt handler is not expected to run.
910 * - Jean II */
911 smsc_ircc_sir_wait_hw_transmitter_finish(self);
912 smsc_ircc_change_speed(self, speed);
913 spin_unlock_irqrestore(&self->lock, flags);
914 dev_kfree_skb(skb);
915 return NETDEV_TX_OK;
916 }
917 self->new_speed = speed;
918 }
919
920 /* Init tx buffer */
921 self->tx_buff.data = self->tx_buff.head;
922
923 /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
924 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
925 self->tx_buff.truesize);
926
927 dev->stats.tx_bytes += self->tx_buff.len;
928
929 /* Turn on transmit finished interrupt. Will fire immediately! */
930 outb(UART_IER_THRI, self->io.sir_base + UART_IER);
931
932 spin_unlock_irqrestore(&self->lock, flags);
933
934 dev_kfree_skb(skb);
935
936 return NETDEV_TX_OK;
937}
938
939/*
940 * Function smsc_ircc_set_fir_speed (self, baud)
941 *
942 * Change the speed of the device
943 *
944 */
945static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
946{
947 int fir_base, ir_mode, ctrl, fast;
948
949 IRDA_ASSERT(self != NULL, return;);
950 fir_base = self->io.fir_base;
951
952 self->io.speed = speed;
953
954 switch (speed) {
955 default:
956 case 576000:
957 ir_mode = IRCC_CFGA_IRDA_HDLC;
958 ctrl = IRCC_CRC;
959 fast = 0;
960 pr_debug("%s(), handling baud of 576000\n", __func__);
961 break;
962 case 1152000:
963 ir_mode = IRCC_CFGA_IRDA_HDLC;
964 ctrl = IRCC_1152 | IRCC_CRC;
965 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
966 pr_debug("%s(), handling baud of 1152000\n",
967 __func__);
968 break;
969 case 4000000:
970 ir_mode = IRCC_CFGA_IRDA_4PPM;
971 ctrl = IRCC_CRC;
972 fast = IRCC_LCR_A_FAST;
973 pr_debug("%s(), handling baud of 4000000\n",
974 __func__);
975 break;
976 }
977 #if 0
978 Now in tranceiver!
979 /* This causes an interrupt */
980 register_bank(fir_base, 0);
981 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast, fir_base + IRCC_LCR_A);
982 #endif
983
984 register_bank(fir_base, 1);
985 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
986
987 register_bank(fir_base, 4);
988 outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
989}
990
991/*
992 * Function smsc_ircc_fir_start(self)
993 *
994 * Change the speed of the device
995 *
996 */
997static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
998{
999 struct net_device *dev;
1000 int fir_base;
1001
1002 pr_debug("%s\n", __func__);
1003
1004 IRDA_ASSERT(self != NULL, return;);
1005 dev = self->netdev;
1006 IRDA_ASSERT(dev != NULL, return;);
1007
1008 fir_base = self->io.fir_base;
1009
1010 /* Reset everything */
1011
1012 /* Clear FIFO */
1013 outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1014
1015 /* Enable interrupt */
1016 /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1017
1018 register_bank(fir_base, 1);
1019
1020 /* Select the TX/RX interface */
1021#ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1022 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1023 fir_base + IRCC_SCE_CFGB);
1024#else
1025 outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1026 fir_base + IRCC_SCE_CFGB);
1027#endif
1028 (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1029
1030 /* Enable SCE interrupts */
1031 outb(0, fir_base + IRCC_MASTER);
1032 register_bank(fir_base, 0);
1033 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1034 outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1035}
1036
1037/*
1038 * Function smsc_ircc_fir_stop(self, baud)
1039 *
1040 * Change the speed of the device
1041 *
1042 */
1043static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1044{
1045 int fir_base;
1046
1047 pr_debug("%s\n", __func__);
1048
1049 IRDA_ASSERT(self != NULL, return;);
1050
1051 fir_base = self->io.fir_base;
1052 register_bank(fir_base, 0);
1053 /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1054 outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1055}
1056
1057
1058/*
1059 * Function smsc_ircc_change_speed(self, baud)
1060 *
1061 * Change the speed of the device
1062 *
1063 * This function *must* be called with spinlock held, because it may
1064 * be called from the irq handler. - Jean II
1065 */
1066static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1067{
1068 struct net_device *dev;
1069 int last_speed_was_sir;
1070
1071 pr_debug("%s() changing speed to: %d\n", __func__, speed);
1072
1073 IRDA_ASSERT(self != NULL, return;);
1074 dev = self->netdev;
1075
1076 last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1077
1078 #if 0
1079 /* Temp Hack */
1080 speed= 1152000;
1081 self->io.speed = speed;
1082 last_speed_was_sir = 0;
1083 smsc_ircc_fir_start(self);
1084 #endif
1085
1086 if (self->io.speed == 0)
1087 smsc_ircc_sir_start(self);
1088
1089 #if 0
1090 if (!last_speed_was_sir) speed = self->io.speed;
1091 #endif
1092
1093 if (self->io.speed != speed)
1094 smsc_ircc_set_transceiver_for_speed(self, speed);
1095
1096 self->io.speed = speed;
1097
1098 if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1099 if (!last_speed_was_sir) {
1100 smsc_ircc_fir_stop(self);
1101 smsc_ircc_sir_start(self);
1102 }
1103 smsc_ircc_set_sir_speed(self, speed);
1104 } else {
1105 if (last_speed_was_sir) {
1106 #if SMSC_IRCC2_C_SIR_STOP
1107 smsc_ircc_sir_stop(self);
1108 #endif
1109 smsc_ircc_fir_start(self);
1110 }
1111 smsc_ircc_set_fir_speed(self, speed);
1112
1113 #if 0
1114 self->tx_buff.len = 10;
1115 self->tx_buff.data = self->tx_buff.head;
1116
1117 smsc_ircc_dma_xmit(self, 4000);
1118 #endif
1119 /* Be ready for incoming frames */
1120 smsc_ircc_dma_receive(self);
1121 }
1122
1123 netif_wake_queue(dev);
1124}
1125
1126/*
1127 * Function smsc_ircc_set_sir_speed (self, speed)
1128 *
1129 * Set speed of IrDA port to specified baudrate
1130 *
1131 */
1132static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1133{
1134 int iobase;
1135 int fcr; /* FIFO control reg */
1136 int lcr; /* Line control reg */
1137 int divisor;
1138
1139 pr_debug("%s(), Setting speed to: %d\n", __func__, speed);
1140
1141 IRDA_ASSERT(self != NULL, return;);
1142 iobase = self->io.sir_base;
1143
1144 /* Update accounting for new speed */
1145 self->io.speed = speed;
1146
1147 /* Turn off interrupts */
1148 outb(0, iobase + UART_IER);
1149
1150 divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1151
1152 fcr = UART_FCR_ENABLE_FIFO;
1153
1154 /*
1155 * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1156 * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1157 * about this timeout since it will always be fast enough.
1158 */
1159 fcr |= self->io.speed < 38400 ?
1160 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1161
1162 /* IrDA ports use 8N1 */
1163 lcr = UART_LCR_WLEN8;
1164
1165 outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1166 outb(divisor & 0xff, iobase + UART_DLL); /* Set speed */
1167 outb(divisor >> 8, iobase + UART_DLM);
1168 outb(lcr, iobase + UART_LCR); /* Set 8N1 */
1169 outb(fcr, iobase + UART_FCR); /* Enable FIFO's */
1170
1171 /* Turn on interrups */
1172 outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1173
1174 pr_debug("%s() speed changed to: %d\n", __func__, speed);
1175}
1176
1177
1178/*
1179 * Function smsc_ircc_hard_xmit_fir (skb, dev)
1180 *
1181 * Transmit the frame!
1182 *
1183 */
1184static netdev_tx_t smsc_ircc_hard_xmit_fir(struct sk_buff *skb,
1185 struct net_device *dev)
1186{
1187 struct smsc_ircc_cb *self;
1188 unsigned long flags;
1189 s32 speed;
1190 int mtt;
1191
1192 IRDA_ASSERT(dev != NULL, return NETDEV_TX_OK;);
1193 self = netdev_priv(dev);
1194 IRDA_ASSERT(self != NULL, return NETDEV_TX_OK;);
1195
1196 netif_stop_queue(dev);
1197
1198 /* Make sure test of self->io.speed & speed change are atomic */
1199 spin_lock_irqsave(&self->lock, flags);
1200
1201 /* Check if we need to change the speed after this frame */
1202 speed = irda_get_next_speed(skb);
1203 if (speed != self->io.speed && speed != -1) {
1204 /* Check for empty frame */
1205 if (!skb->len) {
1206 /* Note : you should make sure that speed changes
1207 * are not going to corrupt any outgoing frame.
1208 * Look at nsc-ircc for the gory details - Jean II */
1209 smsc_ircc_change_speed(self, speed);
1210 spin_unlock_irqrestore(&self->lock, flags);
1211 dev_kfree_skb(skb);
1212 return NETDEV_TX_OK;
1213 }
1214
1215 self->new_speed = speed;
1216 }
1217
1218 skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1219
1220 self->tx_buff.len = skb->len;
1221 self->tx_buff.data = self->tx_buff.head;
1222
1223 mtt = irda_get_mtt(skb);
1224 if (mtt) {
1225 int bofs;
1226
1227 /*
1228 * Compute how many BOFs (STA or PA's) we need to waste the
1229 * min turn time given the speed of the link.
1230 */
1231 bofs = mtt * (self->io.speed / 1000) / 8000;
1232 if (bofs > 4095)
1233 bofs = 4095;
1234
1235 smsc_ircc_dma_xmit(self, bofs);
1236 } else {
1237 /* Transmit frame */
1238 smsc_ircc_dma_xmit(self, 0);
1239 }
1240
1241 spin_unlock_irqrestore(&self->lock, flags);
1242 dev_kfree_skb(skb);
1243
1244 return NETDEV_TX_OK;
1245}
1246
1247/*
1248 * Function smsc_ircc_dma_xmit (self, bofs)
1249 *
1250 * Transmit data using DMA
1251 *
1252 */
1253static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1254{
1255 int iobase = self->io.fir_base;
1256 u8 ctrl;
1257
1258 pr_debug("%s\n", __func__);
1259#if 1
1260 /* Disable Rx */
1261 register_bank(iobase, 0);
1262 outb(0x00, iobase + IRCC_LCR_B);
1263#endif
1264 register_bank(iobase, 1);
1265 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1266 iobase + IRCC_SCE_CFGB);
1267
1268 self->io.direction = IO_XMIT;
1269
1270 /* Set BOF additional count for generating the min turn time */
1271 register_bank(iobase, 4);
1272 outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1273 ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1274 outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1275
1276 /* Set max Tx frame size */
1277 outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1278 outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1279
1280 /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1281
1282 /* Enable burst mode chip Tx DMA */
1283 register_bank(iobase, 1);
1284 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1285 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1286
1287 /* Setup DMA controller (must be done after enabling chip DMA) */
1288 irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1289 DMA_TX_MODE);
1290
1291 /* Enable interrupt */
1292
1293 register_bank(iobase, 0);
1294 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1295 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1296
1297 /* Enable transmit */
1298 outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1299}
1300
1301/*
1302 * Function smsc_ircc_dma_xmit_complete (self)
1303 *
1304 * The transfer of a frame in finished. This function will only be called
1305 * by the interrupt handler
1306 *
1307 */
1308static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1309{
1310 int iobase = self->io.fir_base;
1311
1312 pr_debug("%s\n", __func__);
1313#if 0
1314 /* Disable Tx */
1315 register_bank(iobase, 0);
1316 outb(0x00, iobase + IRCC_LCR_B);
1317#endif
1318 register_bank(iobase, 1);
1319 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1320 iobase + IRCC_SCE_CFGB);
1321
1322 /* Check for underrun! */
1323 register_bank(iobase, 0);
1324 if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1325 self->netdev->stats.tx_errors++;
1326 self->netdev->stats.tx_fifo_errors++;
1327
1328 /* Reset error condition */
1329 register_bank(iobase, 0);
1330 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1331 outb(0x00, iobase + IRCC_MASTER);
1332 } else {
1333 self->netdev->stats.tx_packets++;
1334 self->netdev->stats.tx_bytes += self->tx_buff.len;
1335 }
1336
1337 /* Check if it's time to change the speed */
1338 if (self->new_speed) {
1339 smsc_ircc_change_speed(self, self->new_speed);
1340 self->new_speed = 0;
1341 }
1342
1343 netif_wake_queue(self->netdev);
1344}
1345
1346/*
1347 * Function smsc_ircc_dma_receive(self)
1348 *
1349 * Get ready for receiving a frame. The device will initiate a DMA
1350 * if it starts to receive a frame.
1351 *
1352 */
1353static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1354{
1355 int iobase = self->io.fir_base;
1356#if 0
1357 /* Turn off chip DMA */
1358 register_bank(iobase, 1);
1359 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1360 iobase + IRCC_SCE_CFGB);
1361#endif
1362
1363 /* Disable Tx */
1364 register_bank(iobase, 0);
1365 outb(0x00, iobase + IRCC_LCR_B);
1366
1367 /* Turn off chip DMA */
1368 register_bank(iobase, 1);
1369 outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1370 iobase + IRCC_SCE_CFGB);
1371
1372 self->io.direction = IO_RECV;
1373 self->rx_buff.data = self->rx_buff.head;
1374
1375 /* Set max Rx frame size */
1376 register_bank(iobase, 4);
1377 outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1378 outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1379
1380 /* Setup DMA controller */
1381 irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1382 DMA_RX_MODE);
1383
1384 /* Enable burst mode chip Rx DMA */
1385 register_bank(iobase, 1);
1386 outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1387 IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1388
1389 /* Enable interrupt */
1390 register_bank(iobase, 0);
1391 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1392 outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1393
1394 /* Enable receiver */
1395 register_bank(iobase, 0);
1396 outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1397 iobase + IRCC_LCR_B);
1398
1399 return 0;
1400}
1401
1402/*
1403 * Function smsc_ircc_dma_receive_complete(self)
1404 *
1405 * Finished with receiving frames
1406 *
1407 */
1408static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1409{
1410 struct sk_buff *skb;
1411 int len, msgcnt, lsr;
1412 int iobase = self->io.fir_base;
1413
1414 register_bank(iobase, 0);
1415
1416 pr_debug("%s\n", __func__);
1417#if 0
1418 /* Disable Rx */
1419 register_bank(iobase, 0);
1420 outb(0x00, iobase + IRCC_LCR_B);
1421#endif
1422 register_bank(iobase, 0);
1423 outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1424 lsr= inb(iobase + IRCC_LSR);
1425 msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1426
1427 pr_debug("%s: dma count = %d\n", __func__,
1428 get_dma_residue(self->io.dma));
1429
1430 len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1431
1432 /* Look for errors */
1433 if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1434 self->netdev->stats.rx_errors++;
1435 if (lsr & IRCC_LSR_FRAME_ERROR)
1436 self->netdev->stats.rx_frame_errors++;
1437 if (lsr & IRCC_LSR_CRC_ERROR)
1438 self->netdev->stats.rx_crc_errors++;
1439 if (lsr & IRCC_LSR_SIZE_ERROR)
1440 self->netdev->stats.rx_length_errors++;
1441 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1442 self->netdev->stats.rx_length_errors++;
1443 return;
1444 }
1445
1446 /* Remove CRC */
1447 len -= self->io.speed < 4000000 ? 2 : 4;
1448
1449 if (len < 2 || len > 2050) {
1450 net_warn_ratelimited("%s(), bogus len=%d\n", __func__, len);
1451 return;
1452 }
1453 pr_debug("%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1454
1455 skb = dev_alloc_skb(len + 1);
1456 if (!skb)
1457 return;
1458
1459 /* Make sure IP header gets aligned */
1460 skb_reserve(skb, 1);
1461
1462 memcpy(skb_put(skb, len), self->rx_buff.data, len);
1463 self->netdev->stats.rx_packets++;
1464 self->netdev->stats.rx_bytes += len;
1465
1466 skb->dev = self->netdev;
1467 skb_reset_mac_header(skb);
1468 skb->protocol = htons(ETH_P_IRDA);
1469 netif_rx(skb);
1470}
1471
1472/*
1473 * Function smsc_ircc_sir_receive (self)
1474 *
1475 * Receive one frame from the infrared port
1476 *
1477 */
1478static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1479{
1480 int boguscount = 0;
1481 int iobase;
1482
1483 IRDA_ASSERT(self != NULL, return;);
1484
1485 iobase = self->io.sir_base;
1486
1487 /*
1488 * Receive all characters in Rx FIFO, unwrap and unstuff them.
1489 * async_unwrap_char will deliver all found frames
1490 */
1491 do {
1492 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1493 inb(iobase + UART_RX));
1494
1495 /* Make sure we don't stay here to long */
1496 if (boguscount++ > 32) {
1497 pr_debug("%s(), breaking!\n", __func__);
1498 break;
1499 }
1500 } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1501}
1502
1503
1504/*
1505 * Function smsc_ircc_interrupt (irq, dev_id, regs)
1506 *
1507 * An interrupt from the chip has arrived. Time to do some work
1508 *
1509 */
1510static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1511{
1512 struct net_device *dev = dev_id;
1513 struct smsc_ircc_cb *self = netdev_priv(dev);
1514 int iobase, iir, lcra, lsr;
1515 irqreturn_t ret = IRQ_NONE;
1516
1517 /* Serialise the interrupt handler in various CPUs, stop Tx path */
1518 spin_lock(&self->lock);
1519
1520 /* Check if we should use the SIR interrupt handler */
1521 if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1522 ret = smsc_ircc_interrupt_sir(dev);
1523 goto irq_ret_unlock;
1524 }
1525
1526 iobase = self->io.fir_base;
1527
1528 register_bank(iobase, 0);
1529 iir = inb(iobase + IRCC_IIR);
1530 if (iir == 0)
1531 goto irq_ret_unlock;
1532 ret = IRQ_HANDLED;
1533
1534 /* Disable interrupts */
1535 outb(0, iobase + IRCC_IER);
1536 lcra = inb(iobase + IRCC_LCR_A);
1537 lsr = inb(iobase + IRCC_LSR);
1538
1539 pr_debug("%s(), iir = 0x%02x\n", __func__, iir);
1540
1541 if (iir & IRCC_IIR_EOM) {
1542 if (self->io.direction == IO_RECV)
1543 smsc_ircc_dma_receive_complete(self);
1544 else
1545 smsc_ircc_dma_xmit_complete(self);
1546
1547 smsc_ircc_dma_receive(self);
1548 }
1549
1550 if (iir & IRCC_IIR_ACTIVE_FRAME) {
1551 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1552 }
1553
1554 /* Enable interrupts again */
1555
1556 register_bank(iobase, 0);
1557 outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1558
1559 irq_ret_unlock:
1560 spin_unlock(&self->lock);
1561
1562 return ret;
1563}
1564
1565/*
1566 * Function irport_interrupt_sir (irq, dev_id)
1567 *
1568 * Interrupt handler for SIR modes
1569 */
1570static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1571{
1572 struct smsc_ircc_cb *self = netdev_priv(dev);
1573 int boguscount = 0;
1574 int iobase;
1575 int iir, lsr;
1576
1577 /* Already locked coming here in smsc_ircc_interrupt() */
1578 /*spin_lock(&self->lock);*/
1579
1580 iobase = self->io.sir_base;
1581
1582 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1583 if (iir == 0)
1584 return IRQ_NONE;
1585 while (iir) {
1586 /* Clear interrupt */
1587 lsr = inb(iobase + UART_LSR);
1588
1589 pr_debug("%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1590 __func__, iir, lsr, iobase);
1591
1592 switch (iir) {
1593 case UART_IIR_RLSI:
1594 pr_debug("%s(), RLSI\n", __func__);
1595 break;
1596 case UART_IIR_RDI:
1597 /* Receive interrupt */
1598 smsc_ircc_sir_receive(self);
1599 break;
1600 case UART_IIR_THRI:
1601 if (lsr & UART_LSR_THRE)
1602 /* Transmitter ready for data */
1603 smsc_ircc_sir_write_wakeup(self);
1604 break;
1605 default:
1606 pr_debug("%s(), unhandled IIR=%#x\n",
1607 __func__, iir);
1608 break;
1609 }
1610
1611 /* Make sure we don't stay here to long */
1612 if (boguscount++ > 100)
1613 break;
1614
1615 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1616 }
1617 /*spin_unlock(&self->lock);*/
1618 return IRQ_HANDLED;
1619}
1620
1621
1622#if 0 /* unused */
1623/*
1624 * Function ircc_is_receiving (self)
1625 *
1626 * Return TRUE is we are currently receiving a frame
1627 *
1628 */
1629static int ircc_is_receiving(struct smsc_ircc_cb *self)
1630{
1631 int status = FALSE;
1632 /* int iobase; */
1633
1634 pr_debug("%s\n", __func__);
1635
1636 IRDA_ASSERT(self != NULL, return FALSE;);
1637
1638 pr_debug("%s: dma count = %d\n", __func__,
1639 get_dma_residue(self->io.dma));
1640
1641 status = (self->rx_buff.state != OUTSIDE_FRAME);
1642
1643 return status;
1644}
1645#endif /* unused */
1646
1647static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1648{
1649 int error;
1650
1651 error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1652 self->netdev->name, self->netdev);
1653 if (error)
1654 pr_debug("%s(), unable to allocate irq=%d, err=%d\n",
1655 __func__, self->io.irq, error);
1656
1657 return error;
1658}
1659
1660static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1661{
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&self->lock, flags);
1665
1666 self->io.speed = 0;
1667 smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1668
1669 spin_unlock_irqrestore(&self->lock, flags);
1670}
1671
1672static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1673{
1674 int iobase = self->io.fir_base;
1675 unsigned long flags;
1676
1677 spin_lock_irqsave(&self->lock, flags);
1678
1679 register_bank(iobase, 0);
1680 outb(0, iobase + IRCC_IER);
1681 outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1682 outb(0x00, iobase + IRCC_MASTER);
1683
1684 spin_unlock_irqrestore(&self->lock, flags);
1685}
1686
1687
1688/*
1689 * Function smsc_ircc_net_open (dev)
1690 *
1691 * Start the device
1692 *
1693 */
1694static int smsc_ircc_net_open(struct net_device *dev)
1695{
1696 struct smsc_ircc_cb *self;
1697 char hwname[16];
1698
1699 pr_debug("%s\n", __func__);
1700
1701 IRDA_ASSERT(dev != NULL, return -1;);
1702 self = netdev_priv(dev);
1703 IRDA_ASSERT(self != NULL, return 0;);
1704
1705 if (self->io.suspended) {
1706 pr_debug("%s(), device is suspended\n", __func__);
1707 return -EAGAIN;
1708 }
1709
1710 if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1711 (void *) dev)) {
1712 pr_debug("%s(), unable to allocate irq=%d\n",
1713 __func__, self->io.irq);
1714 return -EAGAIN;
1715 }
1716
1717 smsc_ircc_start_interrupts(self);
1718
1719 /* Give self a hardware name */
1720 /* It would be cool to offer the chip revision here - Jean II */
1721 sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1722
1723 /*
1724 * Open new IrLAP layer instance, now that everything should be
1725 * initialized properly
1726 */
1727 self->irlap = irlap_open(dev, &self->qos, hwname);
1728
1729 /*
1730 * Always allocate the DMA channel after the IRQ,
1731 * and clean up on failure.
1732 */
1733 if (request_dma(self->io.dma, dev->name)) {
1734 smsc_ircc_net_close(dev);
1735
1736 net_warn_ratelimited("%s(), unable to allocate DMA=%d\n",
1737 __func__, self->io.dma);
1738 return -EAGAIN;
1739 }
1740
1741 netif_start_queue(dev);
1742
1743 return 0;
1744}
1745
1746/*
1747 * Function smsc_ircc_net_close (dev)
1748 *
1749 * Stop the device
1750 *
1751 */
1752static int smsc_ircc_net_close(struct net_device *dev)
1753{
1754 struct smsc_ircc_cb *self;
1755
1756 pr_debug("%s\n", __func__);
1757
1758 IRDA_ASSERT(dev != NULL, return -1;);
1759 self = netdev_priv(dev);
1760 IRDA_ASSERT(self != NULL, return 0;);
1761
1762 /* Stop device */
1763 netif_stop_queue(dev);
1764
1765 /* Stop and remove instance of IrLAP */
1766 if (self->irlap)
1767 irlap_close(self->irlap);
1768 self->irlap = NULL;
1769
1770 smsc_ircc_stop_interrupts(self);
1771
1772 /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1773 if (!self->io.suspended)
1774 free_irq(self->io.irq, dev);
1775
1776 disable_dma(self->io.dma);
1777 free_dma(self->io.dma);
1778
1779 return 0;
1780}
1781
1782static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1783{
1784 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1785
1786 if (!self->io.suspended) {
1787 pr_debug("%s, Suspending\n", driver_name);
1788
1789 rtnl_lock();
1790 if (netif_running(self->netdev)) {
1791 netif_device_detach(self->netdev);
1792 smsc_ircc_stop_interrupts(self);
1793 free_irq(self->io.irq, self->netdev);
1794 disable_dma(self->io.dma);
1795 }
1796 self->io.suspended = 1;
1797 rtnl_unlock();
1798 }
1799
1800 return 0;
1801}
1802
1803static int smsc_ircc_resume(struct platform_device *dev)
1804{
1805 struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1806
1807 if (self->io.suspended) {
1808 pr_debug("%s, Waking up\n", driver_name);
1809
1810 rtnl_lock();
1811 smsc_ircc_init_chip(self);
1812 if (netif_running(self->netdev)) {
1813 if (smsc_ircc_request_irq(self)) {
1814 /*
1815 * Don't fail resume process, just kill this
1816 * network interface
1817 */
1818 unregister_netdevice(self->netdev);
1819 } else {
1820 enable_dma(self->io.dma);
1821 smsc_ircc_start_interrupts(self);
1822 netif_device_attach(self->netdev);
1823 }
1824 }
1825 self->io.suspended = 0;
1826 rtnl_unlock();
1827 }
1828 return 0;
1829}
1830
1831/*
1832 * Function smsc_ircc_close (self)
1833 *
1834 * Close driver instance
1835 *
1836 */
1837static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1838{
1839 pr_debug("%s\n", __func__);
1840
1841 IRDA_ASSERT(self != NULL, return -1;);
1842
1843 platform_device_unregister(self->pldev);
1844
1845 /* Remove netdevice */
1846 unregister_netdev(self->netdev);
1847
1848 smsc_ircc_stop_interrupts(self);
1849
1850 /* Release the PORTS that this driver is using */
1851 pr_debug("%s(), releasing 0x%03x\n", __func__,
1852 self->io.fir_base);
1853
1854 release_region(self->io.fir_base, self->io.fir_ext);
1855
1856 pr_debug("%s(), releasing 0x%03x\n", __func__,
1857 self->io.sir_base);
1858
1859 release_region(self->io.sir_base, self->io.sir_ext);
1860
1861 if (self->tx_buff.head)
1862 dma_free_coherent(NULL, self->tx_buff.truesize,
1863 self->tx_buff.head, self->tx_buff_dma);
1864
1865 if (self->rx_buff.head)
1866 dma_free_coherent(NULL, self->rx_buff.truesize,
1867 self->rx_buff.head, self->rx_buff_dma);
1868
1869 free_netdev(self->netdev);
1870
1871 return 0;
1872}
1873
1874static void __exit smsc_ircc_cleanup(void)
1875{
1876 int i;
1877
1878 pr_debug("%s\n", __func__);
1879
1880 for (i = 0; i < 2; i++) {
1881 if (dev_self[i])
1882 smsc_ircc_close(dev_self[i]);
1883 }
1884
1885 if (pnp_driver_registered)
1886 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1887
1888 platform_driver_unregister(&smsc_ircc_driver);
1889}
1890
1891/*
1892 * Start SIR operations
1893 *
1894 * This function *must* be called with spinlock held, because it may
1895 * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1896 */
1897static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1898{
1899 struct net_device *dev;
1900 int fir_base, sir_base;
1901
1902 pr_debug("%s\n", __func__);
1903
1904 IRDA_ASSERT(self != NULL, return;);
1905 dev = self->netdev;
1906 IRDA_ASSERT(dev != NULL, return;);
1907
1908 fir_base = self->io.fir_base;
1909 sir_base = self->io.sir_base;
1910
1911 /* Reset everything */
1912 outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1913
1914 #if SMSC_IRCC2_C_SIR_STOP
1915 /*smsc_ircc_sir_stop(self);*/
1916 #endif
1917
1918 register_bank(fir_base, 1);
1919 outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1920
1921 /* Initialize UART */
1922 outb(UART_LCR_WLEN8, sir_base + UART_LCR); /* Reset DLAB */
1923 outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1924
1925 /* Turn on interrups */
1926 outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1927
1928 pr_debug("%s() - exit\n", __func__);
1929
1930 outb(0x00, fir_base + IRCC_MASTER);
1931}
1932
1933#if SMSC_IRCC2_C_SIR_STOP
1934void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1935{
1936 int iobase;
1937
1938 pr_debug("%s\n", __func__);
1939 iobase = self->io.sir_base;
1940
1941 /* Reset UART */
1942 outb(0, iobase + UART_MCR);
1943
1944 /* Turn off interrupts */
1945 outb(0, iobase + UART_IER);
1946}
1947#endif
1948
1949/*
1950 * Function smsc_sir_write_wakeup (self)
1951 *
1952 * Called by the SIR interrupt handler when there's room for more data.
1953 * If we have more packets to send, we send them here.
1954 *
1955 */
1956static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1957{
1958 int actual = 0;
1959 int iobase;
1960 int fcr;
1961
1962 IRDA_ASSERT(self != NULL, return;);
1963
1964 pr_debug("%s\n", __func__);
1965
1966 iobase = self->io.sir_base;
1967
1968 /* Finished with frame? */
1969 if (self->tx_buff.len > 0) {
1970 /* Write data left in transmit buffer */
1971 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1972 self->tx_buff.data, self->tx_buff.len);
1973 self->tx_buff.data += actual;
1974 self->tx_buff.len -= actual;
1975 } else {
1976
1977 /*if (self->tx_buff.len ==0) {*/
1978
1979 /*
1980 * Now serial buffer is almost free & we can start
1981 * transmission of another packet. But first we must check
1982 * if we need to change the speed of the hardware
1983 */
1984 if (self->new_speed) {
1985 pr_debug("%s(), Changing speed to %d.\n",
1986 __func__, self->new_speed);
1987 smsc_ircc_sir_wait_hw_transmitter_finish(self);
1988 smsc_ircc_change_speed(self, self->new_speed);
1989 self->new_speed = 0;
1990 } else {
1991 /* Tell network layer that we want more frames */
1992 netif_wake_queue(self->netdev);
1993 }
1994 self->netdev->stats.tx_packets++;
1995
1996 if (self->io.speed <= 115200) {
1997 /*
1998 * Reset Rx FIFO to make sure that all reflected transmit data
1999 * is discarded. This is needed for half duplex operation
2000 */
2001 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2002 fcr |= self->io.speed < 38400 ?
2003 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2004
2005 outb(fcr, iobase + UART_FCR);
2006
2007 /* Turn on receive interrupts */
2008 outb(UART_IER_RDI, iobase + UART_IER);
2009 }
2010 }
2011}
2012
2013/*
2014 * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2015 *
2016 * Fill Tx FIFO with transmit data
2017 *
2018 */
2019static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2020{
2021 int actual = 0;
2022
2023 /* Tx FIFO should be empty! */
2024 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2025 net_warn_ratelimited("%s(), failed, fifo not empty!\n",
2026 __func__);
2027 return 0;
2028 }
2029
2030 /* Fill FIFO with current frame */
2031 while (fifo_size-- > 0 && actual < len) {
2032 /* Transmit next byte */
2033 outb(buf[actual], iobase + UART_TX);
2034 actual++;
2035 }
2036 return actual;
2037}
2038
2039/*
2040 * Function smsc_ircc_is_receiving (self)
2041 *
2042 * Returns true is we are currently receiving data
2043 *
2044 */
2045static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2046{
2047 return self->rx_buff.state != OUTSIDE_FRAME;
2048}
2049
2050
2051/*
2052 * Function smsc_ircc_probe_transceiver(self)
2053 *
2054 * Tries to find the used Transceiver
2055 *
2056 */
2057static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2058{
2059 unsigned int i;
2060
2061 IRDA_ASSERT(self != NULL, return;);
2062
2063 for (i = 0; smsc_transceivers[i].name != NULL; i++)
2064 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2065 net_info_ratelimited(" %s transceiver found\n",
2066 smsc_transceivers[i].name);
2067 self->transceiver= i + 1;
2068 return;
2069 }
2070
2071 net_info_ratelimited("No transceiver found. Defaulting to %s\n",
2072 smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2073
2074 self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2075}
2076
2077
2078/*
2079 * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2080 *
2081 * Set the transceiver according to the speed
2082 *
2083 */
2084static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2085{
2086 unsigned int trx;
2087
2088 trx = self->transceiver;
2089 if (trx > 0)
2090 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2091}
2092
2093/*
2094 * Function smsc_ircc_wait_hw_transmitter_finish ()
2095 *
2096 * Wait for the real end of HW transmission
2097 *
2098 * The UART is a strict FIFO, and we get called only when we have finished
2099 * pushing data to the FIFO, so the maximum amount of time we must wait
2100 * is only for the FIFO to drain out.
2101 *
2102 * We use a simple calibrated loop. We may need to adjust the loop
2103 * delay (udelay) to balance I/O traffic and latency. And we also need to
2104 * adjust the maximum timeout.
2105 * It would probably be better to wait for the proper interrupt,
2106 * but it doesn't seem to be available.
2107 *
2108 * We can't use jiffies or kernel timers because :
2109 * 1) We are called from the interrupt handler, which disable softirqs,
2110 * so jiffies won't be increased
2111 * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2112 * want to wait that long to detect stuck hardware.
2113 * Jean II
2114 */
2115
2116static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2117{
2118 int iobase = self->io.sir_base;
2119 int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2120
2121 /* Calibrated busy loop */
2122 while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2123 udelay(1);
2124
2125 if (count < 0)
2126 pr_debug("%s(): stuck transmitter\n", __func__);
2127}
2128
2129
2130/* PROBING
2131 *
2132 * REVISIT we can be told about the device by PNP, and should use that info
2133 * instead of probing hardware and creating a platform_device ...
2134 */
2135
2136static int __init smsc_ircc_look_for_chips(void)
2137{
2138 struct smsc_chip_address *address;
2139 char *type;
2140 unsigned int cfg_base, found;
2141
2142 found = 0;
2143 address = possible_addresses;
2144
2145 while (address->cfg_base) {
2146 cfg_base = address->cfg_base;
2147
2148 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2149
2150 if (address->type & SMSCSIO_TYPE_FDC) {
2151 type = "FDC";
2152 if (address->type & SMSCSIO_TYPE_FLAT)
2153 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2154 found++;
2155
2156 if (address->type & SMSCSIO_TYPE_PAGED)
2157 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2158 found++;
2159 }
2160 if (address->type & SMSCSIO_TYPE_LPC) {
2161 type = "LPC";
2162 if (address->type & SMSCSIO_TYPE_FLAT)
2163 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2164 found++;
2165
2166 if (address->type & SMSCSIO_TYPE_PAGED)
2167 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2168 found++;
2169 }
2170 address++;
2171 }
2172 return found;
2173}
2174
2175/*
2176 * Function smsc_superio_flat (chip, base, type)
2177 *
2178 * Try to get configuration of a smc SuperIO chip with flat register model
2179 *
2180 */
2181static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2182{
2183 unsigned short firbase, sirbase;
2184 u8 mode, dma, irq;
2185 int ret = -ENODEV;
2186
2187 pr_debug("%s\n", __func__);
2188
2189 if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2190 return ret;
2191
2192 outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2193 mode = inb(cfgbase + 1);
2194
2195 /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2196
2197 if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2198 net_warn_ratelimited("%s(): IrDA not enabled\n", __func__);
2199
2200 outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2201 sirbase = inb(cfgbase + 1) << 2;
2202
2203 /* FIR iobase */
2204 outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2205 firbase = inb(cfgbase + 1) << 3;
2206
2207 /* DMA */
2208 outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2209 dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2210
2211 /* IRQ */
2212 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2213 irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2214
2215 net_info_ratelimited("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n",
2216 __func__, firbase, sirbase, dma, irq, mode);
2217
2218 if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2219 ret = 0;
2220
2221 /* Exit configuration */
2222 outb(SMSCSIO_CFGEXITKEY, cfgbase);
2223
2224 return ret;
2225}
2226
2227/*
2228 * Function smsc_superio_paged (chip, base, type)
2229 *
2230 * Try to get configuration of a smc SuperIO chip with paged register model
2231 *
2232 */
2233static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2234{
2235 unsigned short fir_io, sir_io;
2236 int ret = -ENODEV;
2237
2238 pr_debug("%s\n", __func__);
2239
2240 if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2241 return ret;
2242
2243 /* Select logical device (UART2) */
2244 outb(0x07, cfg_base);
2245 outb(0x05, cfg_base + 1);
2246
2247 /* SIR iobase */
2248 outb(0x60, cfg_base);
2249 sir_io = inb(cfg_base + 1) << 8;
2250 outb(0x61, cfg_base);
2251 sir_io |= inb(cfg_base + 1);
2252
2253 /* Read FIR base */
2254 outb(0x62, cfg_base);
2255 fir_io = inb(cfg_base + 1) << 8;
2256 outb(0x63, cfg_base);
2257 fir_io |= inb(cfg_base + 1);
2258 outb(0x2b, cfg_base); /* ??? */
2259
2260 if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2261 ret = 0;
2262
2263 /* Exit configuration */
2264 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2265
2266 return ret;
2267}
2268
2269
2270static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2271{
2272 pr_debug("%s\n", __func__);
2273
2274 outb(reg, cfg_base);
2275 return inb(cfg_base) != reg ? -1 : 0;
2276}
2277
2278static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2279{
2280 u8 devid, xdevid, rev;
2281
2282 pr_debug("%s\n", __func__);
2283
2284 /* Leave configuration */
2285
2286 outb(SMSCSIO_CFGEXITKEY, cfg_base);
2287
2288 if (inb(cfg_base) == SMSCSIO_CFGEXITKEY) /* not a smc superio chip */
2289 return NULL;
2290
2291 outb(reg, cfg_base);
2292
2293 xdevid = inb(cfg_base + 1);
2294
2295 /* Enter configuration */
2296
2297 outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2298
2299 #if 0
2300 if (smsc_access(cfg_base,0x55)) /* send second key and check */
2301 return NULL;
2302 #endif
2303
2304 /* probe device ID */
2305
2306 if (smsc_access(cfg_base, reg))
2307 return NULL;
2308
2309 devid = inb(cfg_base + 1);
2310
2311 if (devid == 0 || devid == 0xff) /* typical values for unused port */
2312 return NULL;
2313
2314 /* probe revision ID */
2315
2316 if (smsc_access(cfg_base, reg + 1))
2317 return NULL;
2318
2319 rev = inb(cfg_base + 1);
2320
2321 if (rev >= 128) /* i think this will make no sense */
2322 return NULL;
2323
2324 if (devid == xdevid) /* protection against false positives */
2325 return NULL;
2326
2327 /* Check for expected device ID; are there others? */
2328
2329 while (chip->devid != devid) {
2330
2331 chip++;
2332
2333 if (chip->name == NULL)
2334 return NULL;
2335 }
2336
2337 net_info_ratelimited("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2338 devid, rev, cfg_base, type, chip->name);
2339
2340 if (chip->rev > rev) {
2341 net_info_ratelimited("Revision higher than expected\n");
2342 return NULL;
2343 }
2344
2345 if (chip->flags & NoIRDA)
2346 net_info_ratelimited("chipset does not support IRDA\n");
2347
2348 return chip;
2349}
2350
2351static int __init smsc_superio_fdc(unsigned short cfg_base)
2352{
2353 int ret = -1;
2354
2355 if (!request_region(cfg_base, 2, driver_name)) {
2356 net_warn_ratelimited("%s: can't get cfg_base of 0x%03x\n",
2357 __func__, cfg_base);
2358 } else {
2359 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2360 !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2361 ret = 0;
2362
2363 release_region(cfg_base, 2);
2364 }
2365
2366 return ret;
2367}
2368
2369static int __init smsc_superio_lpc(unsigned short cfg_base)
2370{
2371 int ret = -1;
2372
2373 if (!request_region(cfg_base, 2, driver_name)) {
2374 net_warn_ratelimited("%s: can't get cfg_base of 0x%03x\n",
2375 __func__, cfg_base);
2376 } else {
2377 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2378 !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2379 ret = 0;
2380
2381 release_region(cfg_base, 2);
2382 }
2383 return ret;
2384}
2385
2386/*
2387 * Look for some specific subsystem setups that need
2388 * pre-configuration not properly done by the BIOS (especially laptops)
2389 * This code is based in part on smcinit.c, tosh1800-smcinit.c
2390 * and tosh2450-smcinit.c. The table lists the device entries
2391 * for ISA bridges with an LPC (Low Pin Count) controller which
2392 * handles the communication with the SMSC device. After the LPC
2393 * controller is initialized through PCI, the SMSC device is initialized
2394 * through a dedicated port in the ISA port-mapped I/O area, this latter
2395 * area is used to configure the SMSC device with default
2396 * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2397 * used different sets of parameters and different control port
2398 * addresses making a subsystem device table necessary.
2399 */
2400#ifdef CONFIG_PCI
2401static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2402 /*
2403 * Subsystems needing entries:
2404 * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2405 * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2406 * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2407 */
2408 {
2409 /* Guessed entry */
2410 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2411 .device = 0x24cc,
2412 .subvendor = 0x103c,
2413 .subdevice = 0x08bc,
2414 .sir_io = 0x02f8,
2415 .fir_io = 0x0130,
2416 .fir_irq = 0x05,
2417 .fir_dma = 0x03,
2418 .cfg_base = 0x004e,
2419 .preconfigure = preconfigure_through_82801,
2420 .name = "HP nx5000 family",
2421 },
2422 {
2423 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2424 .device = 0x24cc,
2425 .subvendor = 0x103c,
2426 .subdevice = 0x088c,
2427 /* Quite certain these are the same for nc8000 as for nc6000 */
2428 .sir_io = 0x02f8,
2429 .fir_io = 0x0130,
2430 .fir_irq = 0x05,
2431 .fir_dma = 0x03,
2432 .cfg_base = 0x004e,
2433 .preconfigure = preconfigure_through_82801,
2434 .name = "HP nc8000 family",
2435 },
2436 {
2437 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2438 .device = 0x24cc,
2439 .subvendor = 0x103c,
2440 .subdevice = 0x0890,
2441 .sir_io = 0x02f8,
2442 .fir_io = 0x0130,
2443 .fir_irq = 0x05,
2444 .fir_dma = 0x03,
2445 .cfg_base = 0x004e,
2446 .preconfigure = preconfigure_through_82801,
2447 .name = "HP nc6000 family",
2448 },
2449 {
2450 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801DBM LPC bridge */
2451 .device = 0x24cc,
2452 .subvendor = 0x0e11,
2453 .subdevice = 0x0860,
2454 /* I assume these are the same for x1000 as for the others */
2455 .sir_io = 0x02e8,
2456 .fir_io = 0x02f8,
2457 .fir_irq = 0x07,
2458 .fir_dma = 0x03,
2459 .cfg_base = 0x002e,
2460 .preconfigure = preconfigure_through_82801,
2461 .name = "Compaq x1000 family",
2462 },
2463 {
2464 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2465 .vendor = PCI_VENDOR_ID_INTEL,
2466 .device = 0x24c0,
2467 .subvendor = 0x1179,
2468 .subdevice = 0xffff, /* 0xffff is "any" */
2469 .sir_io = 0x03f8,
2470 .fir_io = 0x0130,
2471 .fir_irq = 0x07,
2472 .fir_dma = 0x01,
2473 .cfg_base = 0x002e,
2474 .preconfigure = preconfigure_through_82801,
2475 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2476 },
2477 {
2478 .vendor = PCI_VENDOR_ID_INTEL, /* Intel 82801CAM ISA bridge */
2479 .device = 0x248c,
2480 .subvendor = 0x1179,
2481 .subdevice = 0xffff, /* 0xffff is "any" */
2482 .sir_io = 0x03f8,
2483 .fir_io = 0x0130,
2484 .fir_irq = 0x03,
2485 .fir_dma = 0x03,
2486 .cfg_base = 0x002e,
2487 .preconfigure = preconfigure_through_82801,
2488 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2489 },
2490 {
2491 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2492 .vendor = PCI_VENDOR_ID_INTEL,
2493 .device = 0x24cc,
2494 .subvendor = 0x1179,
2495 .subdevice = 0xffff, /* 0xffff is "any" */
2496 .sir_io = 0x03f8,
2497 .fir_io = 0x0130,
2498 .fir_irq = 0x03,
2499 .fir_dma = 0x03,
2500 .cfg_base = 0x002e,
2501 .preconfigure = preconfigure_through_82801,
2502 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2503 },
2504 {
2505 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2506 .vendor = PCI_VENDOR_ID_AL,
2507 .device = 0x1533,
2508 .subvendor = 0x1179,
2509 .subdevice = 0xffff, /* 0xffff is "any" */
2510 .sir_io = 0x02e8,
2511 .fir_io = 0x02f8,
2512 .fir_irq = 0x07,
2513 .fir_dma = 0x03,
2514 .cfg_base = 0x002e,
2515 .preconfigure = preconfigure_through_ali,
2516 .name = "Toshiba laptop with ALi ISA bridge",
2517 },
2518 { } // Terminator
2519};
2520
2521
2522/*
2523 * This sets up the basic SMSC parameters
2524 * (FIR port, SIR port, FIR DMA, FIR IRQ)
2525 * through the chip configuration port.
2526 */
2527static int __init preconfigure_smsc_chip(struct
2528 smsc_ircc_subsystem_configuration
2529 *conf)
2530{
2531 unsigned short iobase = conf->cfg_base;
2532 unsigned char tmpbyte;
2533
2534 outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2535 outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2536 tmpbyte = inb(iobase +1); // Read device ID
2537 pr_debug("Detected Chip id: 0x%02x, setting up registers...\n",
2538 tmpbyte);
2539
2540 /* Disable UART1 and set up SIR I/O port */
2541 outb(0x24, iobase); // select CR24 - UART1 base addr
2542 outb(0x00, iobase + 1); // disable UART1
2543 outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase); // select CR25 - UART2 base addr
2544 outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2545 tmpbyte = inb(iobase + 1);
2546 if (tmpbyte != (conf->sir_io >> 2) ) {
2547 net_warn_ratelimited("ERROR: could not configure SIR ioport\n");
2548 net_warn_ratelimited("Try to supply ircc_cfg argument\n");
2549 return -ENXIO;
2550 }
2551
2552 /* Set up FIR IRQ channel for UART2 */
2553 outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2554 tmpbyte = inb(iobase + 1);
2555 tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2556 tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2557 outb(tmpbyte, iobase + 1);
2558 tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2559 if (tmpbyte != conf->fir_irq) {
2560 net_warn_ratelimited("ERROR: could not configure FIR IRQ channel\n");
2561 return -ENXIO;
2562 }
2563
2564 /* Set up FIR I/O port */
2565 outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase); // CR2B - SCE (FIR) base addr
2566 outb((conf->fir_io >> 3), iobase + 1);
2567 tmpbyte = inb(iobase + 1);
2568 if (tmpbyte != (conf->fir_io >> 3) ) {
2569 net_warn_ratelimited("ERROR: could not configure FIR I/O port\n");
2570 return -ENXIO;
2571 }
2572
2573 /* Set up FIR DMA channel */
2574 outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase); // CR2C - SCE (FIR) DMA select
2575 outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2576 tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2577 if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2578 net_warn_ratelimited("ERROR: could not configure FIR DMA channel\n");
2579 return -ENXIO;
2580 }
2581
2582 outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase); // CR0C - UART mode
2583 tmpbyte = inb(iobase + 1);
2584 tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2585 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2586 outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2587
2588 outb(LPC47N227_APMBOOTDRIVE_REG, iobase); // CR07 - Auto Pwr Mgt/boot drive sel
2589 tmpbyte = inb(iobase + 1);
2590 outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2591
2592 /* This one was not part of tosh1800 */
2593 outb(0x0a, iobase); // CR0a - ecp fifo / ir mux
2594 tmpbyte = inb(iobase + 1);
2595 outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2596
2597 outb(LPC47N227_UART12POWER_REG, iobase); // CR02 - UART 1,2 power
2598 tmpbyte = inb(iobase + 1);
2599 outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2600
2601 outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase); // CR00 - FDC Power/valid config cycle
2602 tmpbyte = inb(iobase + 1);
2603 outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2604
2605 outb(LPC47N227_CFGEXITKEY, iobase); // Exit configuration
2606
2607 return 0;
2608}
2609
2610/* 82801CAM generic registers */
2611#define VID 0x00
2612#define DID 0x02
2613#define PIRQ_A_D_ROUT 0x60
2614#define SIRQ_CNTL 0x64
2615#define PIRQ_E_H_ROUT 0x68
2616#define PCI_DMA_C 0x90
2617/* LPC-specific registers */
2618#define COM_DEC 0xe0
2619#define GEN1_DEC 0xe4
2620#define LPC_EN 0xe6
2621#define GEN2_DEC 0xec
2622/*
2623 * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2624 * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2625 * They all work the same way!
2626 */
2627static int __init preconfigure_through_82801(struct pci_dev *dev,
2628 struct
2629 smsc_ircc_subsystem_configuration
2630 *conf)
2631{
2632 unsigned short tmpword;
2633 unsigned char tmpbyte;
2634
2635 net_info_ratelimited("Setting up Intel 82801 controller and SMSC device\n");
2636 /*
2637 * Select the range for the COMA COM port (SIR)
2638 * Register COM_DEC:
2639 * Bit 7: reserved
2640 * Bit 6-4, COMB decode range
2641 * Bit 3: reserved
2642 * Bit 2-0, COMA decode range
2643 *
2644 * Decode ranges:
2645 * 000 = 0x3f8-0x3ff (COM1)
2646 * 001 = 0x2f8-0x2ff (COM2)
2647 * 010 = 0x220-0x227
2648 * 011 = 0x228-0x22f
2649 * 100 = 0x238-0x23f
2650 * 101 = 0x2e8-0x2ef (COM4)
2651 * 110 = 0x338-0x33f
2652 * 111 = 0x3e8-0x3ef (COM3)
2653 */
2654 pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2655 tmpbyte &= 0xf8; /* mask COMA bits */
2656 switch(conf->sir_io) {
2657 case 0x3f8:
2658 tmpbyte |= 0x00;
2659 break;
2660 case 0x2f8:
2661 tmpbyte |= 0x01;
2662 break;
2663 case 0x220:
2664 tmpbyte |= 0x02;
2665 break;
2666 case 0x228:
2667 tmpbyte |= 0x03;
2668 break;
2669 case 0x238:
2670 tmpbyte |= 0x04;
2671 break;
2672 case 0x2e8:
2673 tmpbyte |= 0x05;
2674 break;
2675 case 0x338:
2676 tmpbyte |= 0x06;
2677 break;
2678 case 0x3e8:
2679 tmpbyte |= 0x07;
2680 break;
2681 default:
2682 tmpbyte |= 0x01; /* COM2 default */
2683 }
2684 pr_debug("COM_DEC (write): 0x%02x\n", tmpbyte);
2685 pci_write_config_byte(dev, COM_DEC, tmpbyte);
2686
2687 /* Enable Low Pin Count interface */
2688 pci_read_config_word(dev, LPC_EN, &tmpword);
2689 /* These seem to be set up at all times,
2690 * just make sure it is properly set.
2691 */
2692 switch(conf->cfg_base) {
2693 case 0x04e:
2694 tmpword |= 0x2000;
2695 break;
2696 case 0x02e:
2697 tmpword |= 0x1000;
2698 break;
2699 case 0x062:
2700 tmpword |= 0x0800;
2701 break;
2702 case 0x060:
2703 tmpword |= 0x0400;
2704 break;
2705 default:
2706 net_warn_ratelimited("Uncommon I/O base address: 0x%04x\n",
2707 conf->cfg_base);
2708 break;
2709 }
2710 tmpword &= 0xfffd; /* disable LPC COMB */
2711 tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2712 pr_debug("LPC_EN (write): 0x%04x\n", tmpword);
2713 pci_write_config_word(dev, LPC_EN, tmpword);
2714
2715 /*
2716 * Configure LPC DMA channel
2717 * PCI_DMA_C bits:
2718 * Bit 15-14: DMA channel 7 select
2719 * Bit 13-12: DMA channel 6 select
2720 * Bit 11-10: DMA channel 5 select
2721 * Bit 9-8: Reserved
2722 * Bit 7-6: DMA channel 3 select
2723 * Bit 5-4: DMA channel 2 select
2724 * Bit 3-2: DMA channel 1 select
2725 * Bit 1-0: DMA channel 0 select
2726 * 00 = Reserved value
2727 * 01 = PC/PCI DMA
2728 * 10 = Reserved value
2729 * 11 = LPC I/F DMA
2730 */
2731 pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2732 switch(conf->fir_dma) {
2733 case 0x07:
2734 tmpword |= 0xc000;
2735 break;
2736 case 0x06:
2737 tmpword |= 0x3000;
2738 break;
2739 case 0x05:
2740 tmpword |= 0x0c00;
2741 break;
2742 case 0x03:
2743 tmpword |= 0x00c0;
2744 break;
2745 case 0x02:
2746 tmpword |= 0x0030;
2747 break;
2748 case 0x01:
2749 tmpword |= 0x000c;
2750 break;
2751 case 0x00:
2752 tmpword |= 0x0003;
2753 break;
2754 default:
2755 break; /* do not change settings */
2756 }
2757 pr_debug("PCI_DMA_C (write): 0x%04x\n", tmpword);
2758 pci_write_config_word(dev, PCI_DMA_C, tmpword);
2759
2760 /*
2761 * GEN2_DEC bits:
2762 * Bit 15-4: Generic I/O range
2763 * Bit 3-1: reserved (read as 0)
2764 * Bit 0: enable GEN2 range on LPC I/F
2765 */
2766 tmpword = conf->fir_io & 0xfff8;
2767 tmpword |= 0x0001;
2768 pr_debug("GEN2_DEC (write): 0x%04x\n", tmpword);
2769 pci_write_config_word(dev, GEN2_DEC, tmpword);
2770
2771 /* Pre-configure chip */
2772 return preconfigure_smsc_chip(conf);
2773}
2774
2775/*
2776 * Pre-configure a certain port on the ALi 1533 bridge.
2777 * This is based on reverse-engineering since ALi does not
2778 * provide any data sheet for the 1533 chip.
2779 */
2780static void __init preconfigure_ali_port(struct pci_dev *dev,
2781 unsigned short port)
2782{
2783 unsigned char reg;
2784 /* These bits obviously control the different ports */
2785 unsigned char mask;
2786 unsigned char tmpbyte;
2787
2788 switch(port) {
2789 case 0x0130:
2790 case 0x0178:
2791 reg = 0xb0;
2792 mask = 0x80;
2793 break;
2794 case 0x03f8:
2795 reg = 0xb4;
2796 mask = 0x80;
2797 break;
2798 case 0x02f8:
2799 reg = 0xb4;
2800 mask = 0x30;
2801 break;
2802 case 0x02e8:
2803 reg = 0xb4;
2804 mask = 0x08;
2805 break;
2806 default:
2807 net_err_ratelimited("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n",
2808 port);
2809 return;
2810 }
2811
2812 pci_read_config_byte(dev, reg, &tmpbyte);
2813 /* Turn on the right bits */
2814 tmpbyte |= mask;
2815 pci_write_config_byte(dev, reg, tmpbyte);
2816 net_info_ratelimited("Activated ALi 1533 ISA bridge port 0x%04x\n",
2817 port);
2818}
2819
2820static int __init preconfigure_through_ali(struct pci_dev *dev,
2821 struct
2822 smsc_ircc_subsystem_configuration
2823 *conf)
2824{
2825 /* Configure the two ports on the ALi 1533 */
2826 preconfigure_ali_port(dev, conf->sir_io);
2827 preconfigure_ali_port(dev, conf->fir_io);
2828
2829 /* Pre-configure chip */
2830 return preconfigure_smsc_chip(conf);
2831}
2832
2833static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2834 unsigned short ircc_fir,
2835 unsigned short ircc_sir,
2836 unsigned char ircc_dma,
2837 unsigned char ircc_irq)
2838{
2839 struct pci_dev *dev = NULL;
2840 unsigned short ss_vendor = 0x0000;
2841 unsigned short ss_device = 0x0000;
2842 int ret = 0;
2843
2844 for_each_pci_dev(dev) {
2845 struct smsc_ircc_subsystem_configuration *conf;
2846
2847 /*
2848 * Cache the subsystem vendor/device:
2849 * some manufacturers fail to set this for all components,
2850 * so we save it in case there is just 0x0000 0x0000 on the
2851 * device we want to check.
2852 */
2853 if (dev->subsystem_vendor != 0x0000U) {
2854 ss_vendor = dev->subsystem_vendor;
2855 ss_device = dev->subsystem_device;
2856 }
2857 conf = subsystem_configurations;
2858 for( ; conf->subvendor; conf++) {
2859 if(conf->vendor == dev->vendor &&
2860 conf->device == dev->device &&
2861 conf->subvendor == ss_vendor &&
2862 /* Sometimes these are cached values */
2863 (conf->subdevice == ss_device ||
2864 conf->subdevice == 0xffff)) {
2865 struct smsc_ircc_subsystem_configuration
2866 tmpconf;
2867
2868 memcpy(&tmpconf, conf,
2869 sizeof(struct smsc_ircc_subsystem_configuration));
2870
2871 /*
2872 * Override the default values with anything
2873 * passed in as parameter
2874 */
2875 if (ircc_cfg != 0)
2876 tmpconf.cfg_base = ircc_cfg;
2877 if (ircc_fir != 0)
2878 tmpconf.fir_io = ircc_fir;
2879 if (ircc_sir != 0)
2880 tmpconf.sir_io = ircc_sir;
2881 if (ircc_dma != DMA_INVAL)
2882 tmpconf.fir_dma = ircc_dma;
2883 if (ircc_irq != IRQ_INVAL)
2884 tmpconf.fir_irq = ircc_irq;
2885
2886 net_info_ratelimited("Detected unconfigured %s SMSC IrDA chip, pre-configuring device\n",
2887 conf->name);
2888 if (conf->preconfigure)
2889 ret = conf->preconfigure(dev, &tmpconf);
2890 else
2891 ret = -ENODEV;
2892 }
2893 }
2894 }
2895
2896 return ret;
2897}
2898#endif // CONFIG_PCI
2899
2900/************************************************
2901 *
2902 * Transceivers specific functions
2903 *
2904 ************************************************/
2905
2906
2907/*
2908 * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2909 *
2910 * Program transceiver through smsc-ircc ATC circuitry
2911 *
2912 */
2913
2914static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2915{
2916 unsigned long jiffies_now, jiffies_timeout;
2917 u8 val;
2918
2919 jiffies_now = jiffies;
2920 jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2921
2922 /* ATC */
2923 register_bank(fir_base, 4);
2924 outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2925 fir_base + IRCC_ATC);
2926
2927 while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2928 !time_after(jiffies, jiffies_timeout))
2929 /* empty */;
2930
2931 if (val)
2932 net_warn_ratelimited("%s(): ATC: 0x%02x\n",
2933 __func__, inb(fir_base + IRCC_ATC));
2934}
2935
2936/*
2937 * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2938 *
2939 * Probe transceiver smsc-ircc ATC circuitry
2940 *
2941 */
2942
2943static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2944{
2945 return 0;
2946}
2947
2948/*
2949 * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2950 *
2951 * Set transceiver
2952 *
2953 */
2954
2955static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2956{
2957 u8 fast_mode;
2958
2959 switch (speed) {
2960 default:
2961 case 576000 :
2962 fast_mode = 0;
2963 break;
2964 case 1152000 :
2965 case 4000000 :
2966 fast_mode = IRCC_LCR_A_FAST;
2967 break;
2968 }
2969 register_bank(fir_base, 0);
2970 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2971}
2972
2973/*
2974 * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2975 *
2976 * Probe transceiver
2977 *
2978 */
2979
2980static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2981{
2982 return 0;
2983}
2984
2985/*
2986 * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2987 *
2988 * Set transceiver
2989 *
2990 */
2991
2992static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2993{
2994 u8 fast_mode;
2995
2996 switch (speed) {
2997 default:
2998 case 576000 :
2999 fast_mode = 0;
3000 break;
3001 case 1152000 :
3002 case 4000000 :
3003 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3004 break;
3005
3006 }
3007 /* This causes an interrupt */
3008 register_bank(fir_base, 0);
3009 outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3010}
3011
3012/*
3013 * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3014 *
3015 * Probe transceiver
3016 *
3017 */
3018
3019static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3020{
3021 return 0;
3022}
3023
3024
3025module_init(smsc_ircc_init);
3026module_exit(smsc_ircc_cleanup);