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1/* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
2/*
3 Written 1996-1999 by Donald Becker.
4
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
7
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
11
12 Problem reports and questions should be directed to
13 vortex@scyld.com
14
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
18 Annapolis MD 21403
19
20*/
21
22/*
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
25 *
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
29 */
30
31
32#define DRV_NAME "3c59x"
33
34
35
36/* A few values that may be tweaked. */
37/* Keep the ring sizes a power of two for efficiency. */
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
41
42/* "Knobs" that adjust features and parameters. */
43/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48/* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50static int rx_copybreak = 1513;
51#endif
52/* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53static const int mtu = 1500;
54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55static int max_interrupt_work = 32;
56/* Tx timeout interval (millisecs) */
57static int watchdog = 5000;
58
59/* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
62 */
63#define tx_interrupt_mitigation 1
64
65/* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
91#include <linux/jiffies.h>
92#include <linux/gfp.h>
93#include <asm/irq.h> /* For nr_irqs only. */
94#include <asm/io.h>
95#include <asm/uaccess.h>
96
97/* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110MODULE_LICENSE("GPL");
111
112
113/* Operational parameter that usually are not changed. */
114
115/* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
122/* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
128
129
130
131/*
132 Theory of Operation
133
134I. Board Compatibility
135
136This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
140
141The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
144
145II. Board-specific settings
146
147PCI bus devices are configured by the system at boot time, so no jumpers
148need to be set on the board. The system BIOS should be set to assign the
149PCI INTA signal to an otherwise unused system IRQ line.
150
151The EEPROM settings for media type and forced-full-duplex are observed.
152The EEPROM media type should be left at the default "autoselect" unless using
15310base2 or AUI connections which cannot be reliably detected.
154
155III. Driver operation
156
157The 3c59x series use an interface that's very similar to the previous 3c5x9
158series. The primary interface is two programmed-I/O FIFOs, with an
159alternate single-contiguous-region bus-master transfer (see next).
160
161The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164programmed-I/O interface that has been removed in 'B' and subsequent board
165revisions.
166
167One extension that is advertised in a very large font is that the adapters
168are capable of being bus masters. On the Vortex chip this capability was
169only for a single contiguous region making it far less useful than the full
170bus master capability. There is a significant performance impact of taking
171an extra interrupt or polling for the completion of each transfer, as well
172as difficulty sharing the single transfer engine between the transmit and
173receive threads. Using DMA transfers is a win only with large blocks or
174with the flawed versions of the Intel Orion motherboard PCI controller.
175
176The Boomerang chip's full-bus-master interface is useful, and has the
177currently-unused advantages over other similar chips that queued transmit
178packets may be reordered and receive buffer groups are associated with a
179single frame.
180
181With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182Rather than a fixed intermediate receive buffer, this scheme allocates
183full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184the copying breakpoint: it is chosen to trade-off the memory wasted by
185passing the full-sized skbuff to the queue layer for all frames vs. the
186copying cost of copying a frame to a correctly-sized skbuff.
187
188IIIC. Synchronization
189The driver runs as two independent, single-threaded flows of control. One
190is the send-packet routine, which enforces single-threaded use by the
191dev->tbusy flag. The other thread is the interrupt handler, which is single
192threaded by the hardware and other software.
193
194IV. Notes
195
196Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
1973c590, 3c595, and 3c900 boards.
198The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199the EISA version is called "Demon". According to Terry these names come
200from rides at the local amusement park.
201
202The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203This driver only supports ethernet packets because of the skbuff allocation
204limit of 4K.
205*/
206
207/* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
209*/
210enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271/* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
273 * table below
274 */
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,}, /* NULL terminated list. */
375};
376
377
378static const struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,} /* 0 terminated list. */
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
431/* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
434
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
437 */
438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441/* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459/* The SetRxFilter command accepts the following classes: */
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463/* Bits in the general status register. */
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
471};
472
473/* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
479};
480enum Window0 {
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
489};
490/* EEPROM locations. */
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 { /* Window 2. */
498 Wn2_ResetOptions=12,
499};
500enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532/* Boomerang bus master control registers. */
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538/* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541#define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
545 __le32 status;
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
548};
549/* Values for the Rx status entry. */
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
566#if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571#else
572 __le32 addr;
573 __le32 length;
574#endif
575};
576
577/* Values for the Tx status entry. */
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
582};
583
584/* Chip features we care about in vp->capabilities, read from the EEPROM. */
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593};
594
595struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
609
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
614
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
630 has_nway:1,
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
633 open:1,
634 medialock:1,
635 large_frames:1, /* accept large frames */
636 handling_irq:1; /* private in_irq indicator */
637 /* {get|set}_wol operations are already serialized by rtnl.
638 * no additional locking is required for the enable_wol and acpi_set_WOL()
639 */
640 int drv_flags;
641 u16 status_enable;
642 u16 intr_enable;
643 u16 available_media; /* From Wn3_Options. */
644 u16 capabilities, info1, info2; /* Various, from EEPROM. */
645 u16 advertising; /* NWay media advertisement */
646 unsigned char phys[2]; /* MII device addresses. */
647 u16 deferred; /* Resend these interrupts when we
648 * bale from the ISR */
649 u16 io_size; /* Size of PCI region (for release_region) */
650
651 /* Serialises access to hardware other than MII and variables below.
652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
653 spinlock_t lock;
654
655 spinlock_t mii_lock; /* Serialises access to MII */
656 struct mii_if_info mii; /* MII lib hooks/info */
657 spinlock_t window_lock; /* Serialises access to windowed regs */
658 int window; /* Register window */
659};
660
661static void window_set(struct vortex_private *vp, int window)
662{
663 if (window != vp->window) {
664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
665 vp->window = window;
666 }
667}
668
669#define DEFINE_WINDOW_IO(size) \
670static u ## size \
671window_read ## size(struct vortex_private *vp, int window, int addr) \
672{ \
673 unsigned long flags; \
674 u ## size ret; \
675 spin_lock_irqsave(&vp->window_lock, flags); \
676 window_set(vp, window); \
677 ret = ioread ## size(vp->ioaddr + addr); \
678 spin_unlock_irqrestore(&vp->window_lock, flags); \
679 return ret; \
680} \
681static void \
682window_write ## size(struct vortex_private *vp, u ## size value, \
683 int window, int addr) \
684{ \
685 unsigned long flags; \
686 spin_lock_irqsave(&vp->window_lock, flags); \
687 window_set(vp, window); \
688 iowrite ## size(value, vp->ioaddr + addr); \
689 spin_unlock_irqrestore(&vp->window_lock, flags); \
690}
691DEFINE_WINDOW_IO(8)
692DEFINE_WINDOW_IO(16)
693DEFINE_WINDOW_IO(32)
694
695#ifdef CONFIG_PCI
696#define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
697#else
698#define DEVICE_PCI(dev) NULL
699#endif
700
701#define VORTEX_PCI(vp) \
702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
703
704#ifdef CONFIG_EISA
705#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
706#else
707#define DEVICE_EISA(dev) NULL
708#endif
709
710#define VORTEX_EISA(vp) \
711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
712
713/* The action to take with a media selection timer tick.
714 Note that we deviate from the 3Com order by checking 10base2 before AUI.
715 */
716enum xcvr_types {
717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
719};
720
721static const struct media_table {
722 char *name;
723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
724 mask:8, /* The transceiver-present bit in Wn3_Config.*/
725 next:8; /* The media type to try next. */
726 int wait; /* Time before we check media status. */
727} media_tbl[] = {
728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
730 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
735 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
738 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
739};
740
741static struct {
742 const char str[ETH_GSTRING_LEN];
743} ethtool_stats_keys[] = {
744 { "tx_deferred" },
745 { "tx_max_collisions" },
746 { "tx_multiple_collisions" },
747 { "tx_single_collisions" },
748 { "rx_bad_ssd" },
749};
750
751/* number of ETHTOOL_GSTATS u64's */
752#define VORTEX_NUM_STATS 5
753
754static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
755 int chip_idx, int card_idx);
756static int vortex_up(struct net_device *dev);
757static void vortex_down(struct net_device *dev, int final);
758static int vortex_open(struct net_device *dev);
759static void mdio_sync(struct vortex_private *vp, int bits);
760static int mdio_read(struct net_device *dev, int phy_id, int location);
761static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
762static void vortex_timer(unsigned long arg);
763static void rx_oom_timer(unsigned long arg);
764static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
767 struct net_device *dev);
768static int vortex_rx(struct net_device *dev);
769static int boomerang_rx(struct net_device *dev);
770static irqreturn_t vortex_interrupt(int irq, void *dev_id);
771static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
772static int vortex_close(struct net_device *dev);
773static void dump_tx_ring(struct net_device *dev);
774static void update_stats(void __iomem *ioaddr, struct net_device *dev);
775static struct net_device_stats *vortex_get_stats(struct net_device *dev);
776static void set_rx_mode(struct net_device *dev);
777#ifdef CONFIG_PCI
778static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
779#endif
780static void vortex_tx_timeout(struct net_device *dev);
781static void acpi_set_WOL(struct net_device *dev);
782static const struct ethtool_ops vortex_ethtool_ops;
783static void set_8021q_mode(struct net_device *dev, int enable);
784
785/* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
786/* Option count limit only -- unlimited interfaces are supported. */
787#define MAX_UNITS 8
788static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
789static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
793static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
794static int global_options = -1;
795static int global_full_duplex = -1;
796static int global_enable_wol = -1;
797static int global_use_mmio = -1;
798
799/* Variables to work-around the Compaq PCI BIOS32 problem. */
800static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
801static struct net_device *compaq_net_device;
802
803static int vortex_cards_found;
804
805module_param(debug, int, 0);
806module_param(global_options, int, 0);
807module_param_array(options, int, NULL, 0);
808module_param(global_full_duplex, int, 0);
809module_param_array(full_duplex, int, NULL, 0);
810module_param_array(hw_checksums, int, NULL, 0);
811module_param_array(flow_ctrl, int, NULL, 0);
812module_param(global_enable_wol, int, 0);
813module_param_array(enable_wol, int, NULL, 0);
814module_param(rx_copybreak, int, 0);
815module_param(max_interrupt_work, int, 0);
816module_param(compaq_ioaddr, int, 0);
817module_param(compaq_irq, int, 0);
818module_param(compaq_device_id, int, 0);
819module_param(watchdog, int, 0);
820module_param(global_use_mmio, int, 0);
821module_param_array(use_mmio, int, NULL, 0);
822MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
823MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
824MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
825MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
826MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
827MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
828MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
829MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
830MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
831MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
832MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
833MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
834MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
835MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
836MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
837MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
838MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
839
840#ifdef CONFIG_NET_POLL_CONTROLLER
841static void poll_vortex(struct net_device *dev)
842{
843 struct vortex_private *vp = netdev_priv(dev);
844 unsigned long flags;
845 local_irq_save(flags);
846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
847 local_irq_restore(flags);
848}
849#endif
850
851#ifdef CONFIG_PM
852
853static int vortex_suspend(struct device *dev)
854{
855 struct pci_dev *pdev = to_pci_dev(dev);
856 struct net_device *ndev = pci_get_drvdata(pdev);
857
858 if (!ndev || !netif_running(ndev))
859 return 0;
860
861 netif_device_detach(ndev);
862 vortex_down(ndev, 1);
863
864 return 0;
865}
866
867static int vortex_resume(struct device *dev)
868{
869 struct pci_dev *pdev = to_pci_dev(dev);
870 struct net_device *ndev = pci_get_drvdata(pdev);
871 int err;
872
873 if (!ndev || !netif_running(ndev))
874 return 0;
875
876 err = vortex_up(ndev);
877 if (err)
878 return err;
879
880 netif_device_attach(ndev);
881
882 return 0;
883}
884
885static const struct dev_pm_ops vortex_pm_ops = {
886 .suspend = vortex_suspend,
887 .resume = vortex_resume,
888 .freeze = vortex_suspend,
889 .thaw = vortex_resume,
890 .poweroff = vortex_suspend,
891 .restore = vortex_resume,
892};
893
894#define VORTEX_PM_OPS (&vortex_pm_ops)
895
896#else /* !CONFIG_PM */
897
898#define VORTEX_PM_OPS NULL
899
900#endif /* !CONFIG_PM */
901
902#ifdef CONFIG_EISA
903static struct eisa_device_id vortex_eisa_ids[] = {
904 { "TCM5920", CH_3C592 },
905 { "TCM5970", CH_3C597 },
906 { "" }
907};
908MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
909
910static int vortex_eisa_probe(struct device *device)
911{
912 void __iomem *ioaddr;
913 struct eisa_device *edev;
914
915 edev = to_eisa_device(device);
916
917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
918 return -EBUSY;
919
920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
921
922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
923 edev->id.driver_data, vortex_cards_found)) {
924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
925 return -ENODEV;
926 }
927
928 vortex_cards_found++;
929
930 return 0;
931}
932
933static int vortex_eisa_remove(struct device *device)
934{
935 struct eisa_device *edev;
936 struct net_device *dev;
937 struct vortex_private *vp;
938 void __iomem *ioaddr;
939
940 edev = to_eisa_device(device);
941 dev = eisa_get_drvdata(edev);
942
943 if (!dev) {
944 pr_err("vortex_eisa_remove called for Compaq device!\n");
945 BUG();
946 }
947
948 vp = netdev_priv(dev);
949 ioaddr = vp->ioaddr;
950
951 unregister_netdev(dev);
952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
954
955 free_netdev(dev);
956 return 0;
957}
958
959static struct eisa_driver vortex_eisa_driver = {
960 .id_table = vortex_eisa_ids,
961 .driver = {
962 .name = "3c59x",
963 .probe = vortex_eisa_probe,
964 .remove = vortex_eisa_remove
965 }
966};
967
968#endif /* CONFIG_EISA */
969
970/* returns count found (>= 0), or negative on error */
971static int __init vortex_eisa_init(void)
972{
973 int eisa_found = 0;
974 int orig_cards_found = vortex_cards_found;
975
976#ifdef CONFIG_EISA
977 int err;
978
979 err = eisa_driver_register (&vortex_eisa_driver);
980 if (!err) {
981 /*
982 * Because of the way EISA bus is probed, we cannot assume
983 * any device have been found when we exit from
984 * eisa_driver_register (the bus root driver may not be
985 * initialized yet). So we blindly assume something was
986 * found, and let the sysfs magic happened...
987 */
988 eisa_found = 1;
989 }
990#endif
991
992 /* Special code to work-around the Compaq PCI BIOS32 problem. */
993 if (compaq_ioaddr) {
994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
995 compaq_irq, compaq_device_id, vortex_cards_found++);
996 }
997
998 return vortex_cards_found - orig_cards_found + eisa_found;
999}
1000
1001/* returns count (>= 0), or negative on error */
1002static int vortex_init_one(struct pci_dev *pdev,
1003 const struct pci_device_id *ent)
1004{
1005 int rc, unit, pci_bar;
1006 struct vortex_chip_info *vci;
1007 void __iomem *ioaddr;
1008
1009 /* wake up and enable device */
1010 rc = pci_enable_device(pdev);
1011 if (rc < 0)
1012 goto out;
1013
1014 rc = pci_request_regions(pdev, DRV_NAME);
1015 if (rc < 0)
1016 goto out_disable;
1017
1018 unit = vortex_cards_found;
1019
1020 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1021 /* Determine the default if the user didn't override us */
1022 vci = &vortex_info_tbl[ent->driver_data];
1023 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1024 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1025 pci_bar = use_mmio[unit] ? 1 : 0;
1026 else
1027 pci_bar = global_use_mmio ? 1 : 0;
1028
1029 ioaddr = pci_iomap(pdev, pci_bar, 0);
1030 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1031 ioaddr = pci_iomap(pdev, 0, 0);
1032 if (!ioaddr) {
1033 rc = -ENOMEM;
1034 goto out_release;
1035 }
1036
1037 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1038 ent->driver_data, unit);
1039 if (rc < 0)
1040 goto out_iounmap;
1041
1042 vortex_cards_found++;
1043 goto out;
1044
1045out_iounmap:
1046 pci_iounmap(pdev, ioaddr);
1047out_release:
1048 pci_release_regions(pdev);
1049out_disable:
1050 pci_disable_device(pdev);
1051out:
1052 return rc;
1053}
1054
1055static const struct net_device_ops boomrang_netdev_ops = {
1056 .ndo_open = vortex_open,
1057 .ndo_stop = vortex_close,
1058 .ndo_start_xmit = boomerang_start_xmit,
1059 .ndo_tx_timeout = vortex_tx_timeout,
1060 .ndo_get_stats = vortex_get_stats,
1061#ifdef CONFIG_PCI
1062 .ndo_do_ioctl = vortex_ioctl,
1063#endif
1064 .ndo_set_rx_mode = set_rx_mode,
1065 .ndo_change_mtu = eth_change_mtu,
1066 .ndo_set_mac_address = eth_mac_addr,
1067 .ndo_validate_addr = eth_validate_addr,
1068#ifdef CONFIG_NET_POLL_CONTROLLER
1069 .ndo_poll_controller = poll_vortex,
1070#endif
1071};
1072
1073static const struct net_device_ops vortex_netdev_ops = {
1074 .ndo_open = vortex_open,
1075 .ndo_stop = vortex_close,
1076 .ndo_start_xmit = vortex_start_xmit,
1077 .ndo_tx_timeout = vortex_tx_timeout,
1078 .ndo_get_stats = vortex_get_stats,
1079#ifdef CONFIG_PCI
1080 .ndo_do_ioctl = vortex_ioctl,
1081#endif
1082 .ndo_set_rx_mode = set_rx_mode,
1083 .ndo_change_mtu = eth_change_mtu,
1084 .ndo_set_mac_address = eth_mac_addr,
1085 .ndo_validate_addr = eth_validate_addr,
1086#ifdef CONFIG_NET_POLL_CONTROLLER
1087 .ndo_poll_controller = poll_vortex,
1088#endif
1089};
1090
1091/*
1092 * Start up the PCI/EISA device which is described by *gendev.
1093 * Return 0 on success.
1094 *
1095 * NOTE: pdev can be NULL, for the case of a Compaq device
1096 */
1097static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1098 int chip_idx, int card_idx)
1099{
1100 struct vortex_private *vp;
1101 int option;
1102 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1103 int i, step;
1104 struct net_device *dev;
1105 static int printed_version;
1106 int retval, print_info;
1107 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1108 const char *print_name = "3c59x";
1109 struct pci_dev *pdev = NULL;
1110 struct eisa_device *edev = NULL;
1111
1112 if (!printed_version) {
1113 pr_info("%s", version);
1114 printed_version = 1;
1115 }
1116
1117 if (gendev) {
1118 if ((pdev = DEVICE_PCI(gendev))) {
1119 print_name = pci_name(pdev);
1120 }
1121
1122 if ((edev = DEVICE_EISA(gendev))) {
1123 print_name = dev_name(&edev->dev);
1124 }
1125 }
1126
1127 dev = alloc_etherdev(sizeof(*vp));
1128 retval = -ENOMEM;
1129 if (!dev)
1130 goto out;
1131
1132 SET_NETDEV_DEV(dev, gendev);
1133 vp = netdev_priv(dev);
1134
1135 option = global_options;
1136
1137 /* The lower four bits are the media type. */
1138 if (dev->mem_start) {
1139 /*
1140 * The 'options' param is passed in as the third arg to the
1141 * LILO 'ether=' argument for non-modular use
1142 */
1143 option = dev->mem_start;
1144 }
1145 else if (card_idx < MAX_UNITS) {
1146 if (options[card_idx] >= 0)
1147 option = options[card_idx];
1148 }
1149
1150 if (option > 0) {
1151 if (option & 0x8000)
1152 vortex_debug = 7;
1153 if (option & 0x4000)
1154 vortex_debug = 2;
1155 if (option & 0x0400)
1156 vp->enable_wol = 1;
1157 }
1158
1159 print_info = (vortex_debug > 1);
1160 if (print_info)
1161 pr_info("See Documentation/networking/vortex.txt\n");
1162
1163 pr_info("%s: 3Com %s %s at %p.\n",
1164 print_name,
1165 pdev ? "PCI" : "EISA",
1166 vci->name,
1167 ioaddr);
1168
1169 dev->base_addr = (unsigned long)ioaddr;
1170 dev->irq = irq;
1171 dev->mtu = mtu;
1172 vp->ioaddr = ioaddr;
1173 vp->large_frames = mtu > 1500;
1174 vp->drv_flags = vci->drv_flags;
1175 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1176 vp->io_size = vci->io_size;
1177 vp->card_idx = card_idx;
1178 vp->window = -1;
1179
1180 /* module list only for Compaq device */
1181 if (gendev == NULL) {
1182 compaq_net_device = dev;
1183 }
1184
1185 /* PCI-only startup logic */
1186 if (pdev) {
1187 /* enable bus-mastering if necessary */
1188 if (vci->flags & PCI_USES_MASTER)
1189 pci_set_master(pdev);
1190
1191 if (vci->drv_flags & IS_VORTEX) {
1192 u8 pci_latency;
1193 u8 new_latency = 248;
1194
1195 /* Check the PCI latency value. On the 3c590 series the latency timer
1196 must be set to the maximum value to avoid data corruption that occurs
1197 when the timer expires during a transfer. This bug exists the Vortex
1198 chip only. */
1199 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1200 if (pci_latency < new_latency) {
1201 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1202 print_name, pci_latency, new_latency);
1203 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1204 }
1205 }
1206 }
1207
1208 spin_lock_init(&vp->lock);
1209 spin_lock_init(&vp->mii_lock);
1210 spin_lock_init(&vp->window_lock);
1211 vp->gendev = gendev;
1212 vp->mii.dev = dev;
1213 vp->mii.mdio_read = mdio_read;
1214 vp->mii.mdio_write = mdio_write;
1215 vp->mii.phy_id_mask = 0x1f;
1216 vp->mii.reg_num_mask = 0x1f;
1217
1218 /* Makes sure rings are at least 16 byte aligned. */
1219 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1220 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1221 &vp->rx_ring_dma);
1222 retval = -ENOMEM;
1223 if (!vp->rx_ring)
1224 goto free_device;
1225
1226 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1227 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1228
1229 /* if we are a PCI driver, we store info in pdev->driver_data
1230 * instead of a module list */
1231 if (pdev)
1232 pci_set_drvdata(pdev, dev);
1233 if (edev)
1234 eisa_set_drvdata(edev, dev);
1235
1236 vp->media_override = 7;
1237 if (option >= 0) {
1238 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1239 if (vp->media_override != 7)
1240 vp->medialock = 1;
1241 vp->full_duplex = (option & 0x200) ? 1 : 0;
1242 vp->bus_master = (option & 16) ? 1 : 0;
1243 }
1244
1245 if (global_full_duplex > 0)
1246 vp->full_duplex = 1;
1247 if (global_enable_wol > 0)
1248 vp->enable_wol = 1;
1249
1250 if (card_idx < MAX_UNITS) {
1251 if (full_duplex[card_idx] > 0)
1252 vp->full_duplex = 1;
1253 if (flow_ctrl[card_idx] > 0)
1254 vp->flow_ctrl = 1;
1255 if (enable_wol[card_idx] > 0)
1256 vp->enable_wol = 1;
1257 }
1258
1259 vp->mii.force_media = vp->full_duplex;
1260 vp->options = option;
1261 /* Read the station address from the EEPROM. */
1262 {
1263 int base;
1264
1265 if (vci->drv_flags & EEPROM_8BIT)
1266 base = 0x230;
1267 else if (vci->drv_flags & EEPROM_OFFSET)
1268 base = EEPROM_Read + 0x30;
1269 else
1270 base = EEPROM_Read;
1271
1272 for (i = 0; i < 0x40; i++) {
1273 int timer;
1274 window_write16(vp, base + i, 0, Wn0EepromCmd);
1275 /* Pause for at least 162 us. for the read to take place. */
1276 for (timer = 10; timer >= 0; timer--) {
1277 udelay(162);
1278 if ((window_read16(vp, 0, Wn0EepromCmd) &
1279 0x8000) == 0)
1280 break;
1281 }
1282 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1283 }
1284 }
1285 for (i = 0; i < 0x18; i++)
1286 checksum ^= eeprom[i];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1288 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1289 while (i < 0x21)
1290 checksum ^= eeprom[i++];
1291 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1292 }
1293 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1294 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1295 for (i = 0; i < 3; i++)
1296 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1297 if (print_info)
1298 pr_cont(" %pM", dev->dev_addr);
1299 /* Unfortunately an all zero eeprom passes the checksum and this
1300 gets found in the wild in failure cases. Crypto is hard 8) */
1301 if (!is_valid_ether_addr(dev->dev_addr)) {
1302 retval = -EINVAL;
1303 pr_err("*** EEPROM MAC address is invalid.\n");
1304 goto free_ring; /* With every pack */
1305 }
1306 for (i = 0; i < 6; i++)
1307 window_write8(vp, dev->dev_addr[i], 2, i);
1308
1309 if (print_info)
1310 pr_cont(", IRQ %d\n", dev->irq);
1311 /* Tell them about an invalid IRQ. */
1312 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1313 pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1314 dev->irq);
1315
1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1317 if (print_info) {
1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1321 }
1322
1323
1324 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1325 unsigned short n;
1326
1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1328 if (!vp->cb_fn_base) {
1329 retval = -ENOMEM;
1330 goto free_ring;
1331 }
1332
1333 if (print_info) {
1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1335 print_name,
1336 (unsigned long long)pci_resource_start(pdev, 2),
1337 vp->cb_fn_base);
1338 }
1339
1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1341 if (vp->drv_flags & INVERT_LED_PWR)
1342 n |= 0x10;
1343 if (vp->drv_flags & INVERT_MII_PWR)
1344 n |= 0x4000;
1345 window_write16(vp, n, 2, Wn2_ResetOptions);
1346 if (vp->drv_flags & WNO_XCVR_PWR) {
1347 window_write16(vp, 0x0800, 0, 0);
1348 }
1349 }
1350
1351 /* Extract our information from the EEPROM data. */
1352 vp->info1 = eeprom[13];
1353 vp->info2 = eeprom[15];
1354 vp->capabilities = eeprom[16];
1355
1356 if (vp->info1 & 0x8000) {
1357 vp->full_duplex = 1;
1358 if (print_info)
1359 pr_info("Full duplex capable\n");
1360 }
1361
1362 {
1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1364 unsigned int config;
1365 vp->available_media = window_read16(vp, 3, Wn3_Options);
1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1367 vp->available_media = 0x40;
1368 config = window_read32(vp, 3, Wn3_Config);
1369 if (print_info) {
1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1371 config, window_read16(vp, 3, Wn3_Options));
1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1373 8 << RAM_SIZE(config),
1374 RAM_WIDTH(config) ? "word" : "byte",
1375 ram_split[RAM_SPLIT(config)],
1376 AUTOSELECT(config) ? "autoselect/" : "",
1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1378 media_tbl[XCVR(config)].name);
1379 }
1380 vp->default_media = XCVR(config);
1381 if (vp->default_media == XCVR_NWAY)
1382 vp->has_nway = 1;
1383 vp->autoselect = AUTOSELECT(config);
1384 }
1385
1386 if (vp->media_override != 7) {
1387 pr_info("%s: Media override to transceiver type %d (%s).\n",
1388 print_name, vp->media_override,
1389 media_tbl[vp->media_override].name);
1390 dev->if_port = vp->media_override;
1391 } else
1392 dev->if_port = vp->default_media;
1393
1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1396 int phy, phy_idx = 0;
1397 mii_preamble_required++;
1398 if (vp->drv_flags & EXTRA_PREAMBLE)
1399 mii_preamble_required++;
1400 mdio_sync(vp, 32);
1401 mdio_read(dev, 24, MII_BMSR);
1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1403 int mii_status, phyx;
1404
1405 /*
1406 * For the 3c905CX we look at index 24 first, because it bogusly
1407 * reports an external PHY at all indices
1408 */
1409 if (phy == 0)
1410 phyx = 24;
1411 else if (phy <= 24)
1412 phyx = phy - 1;
1413 else
1414 phyx = phy;
1415 mii_status = mdio_read(dev, phyx, MII_BMSR);
1416 if (mii_status && mii_status != 0xffff) {
1417 vp->phys[phy_idx++] = phyx;
1418 if (print_info) {
1419 pr_info(" MII transceiver found at address %d, status %4x.\n",
1420 phyx, mii_status);
1421 }
1422 if ((mii_status & 0x0040) == 0)
1423 mii_preamble_required++;
1424 }
1425 }
1426 mii_preamble_required--;
1427 if (phy_idx == 0) {
1428 pr_warn(" ***WARNING*** No MII transceivers found!\n");
1429 vp->phys[0] = 24;
1430 } else {
1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1432 if (vp->full_duplex) {
1433 /* Only advertise the FD media types. */
1434 vp->advertising &= ~0x02A0;
1435 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1436 }
1437 }
1438 vp->mii.phy_id = vp->phys[0];
1439 }
1440
1441 if (vp->capabilities & CapBusMaster) {
1442 vp->full_bus_master_tx = 1;
1443 if (print_info) {
1444 pr_info(" Enabling bus-master transmits and %s receives.\n",
1445 (vp->info2 & 1) ? "early" : "whole-frame" );
1446 }
1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1448 vp->bus_master = 0; /* AKPM: vortex only */
1449 }
1450
1451 /* The 3c59x-specific entries in the device structure. */
1452 if (vp->full_bus_master_tx) {
1453 dev->netdev_ops = &boomrang_netdev_ops;
1454 /* Actually, it still should work with iommu. */
1455 if (card_idx < MAX_UNITS &&
1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1457 hw_checksums[card_idx] == 1)) {
1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1459 }
1460 } else
1461 dev->netdev_ops = &vortex_netdev_ops;
1462
1463 if (print_info) {
1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1465 print_name,
1466 (dev->features & NETIF_F_SG) ? "en":"dis",
1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1468 }
1469
1470 dev->ethtool_ops = &vortex_ethtool_ops;
1471 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1472
1473 if (pdev) {
1474 vp->pm_state_valid = 1;
1475 pci_save_state(pdev);
1476 acpi_set_WOL(dev);
1477 }
1478 retval = register_netdev(dev);
1479 if (retval == 0)
1480 return 0;
1481
1482free_ring:
1483 pci_free_consistent(pdev,
1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1486 vp->rx_ring,
1487 vp->rx_ring_dma);
1488free_device:
1489 free_netdev(dev);
1490 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1491out:
1492 return retval;
1493}
1494
1495static void
1496issue_and_wait(struct net_device *dev, int cmd)
1497{
1498 struct vortex_private *vp = netdev_priv(dev);
1499 void __iomem *ioaddr = vp->ioaddr;
1500 int i;
1501
1502 iowrite16(cmd, ioaddr + EL3_CMD);
1503 for (i = 0; i < 2000; i++) {
1504 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1505 return;
1506 }
1507
1508 /* OK, that didn't work. Do it the slow way. One second */
1509 for (i = 0; i < 100000; i++) {
1510 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1511 if (vortex_debug > 1)
1512 pr_info("%s: command 0x%04x took %d usecs\n",
1513 dev->name, cmd, i * 10);
1514 return;
1515 }
1516 udelay(10);
1517 }
1518 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1519 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1520}
1521
1522static void
1523vortex_set_duplex(struct net_device *dev)
1524{
1525 struct vortex_private *vp = netdev_priv(dev);
1526
1527 pr_info("%s: setting %s-duplex.\n",
1528 dev->name, (vp->full_duplex) ? "full" : "half");
1529
1530 /* Set the full-duplex bit. */
1531 window_write16(vp,
1532 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1533 (vp->large_frames ? 0x40 : 0) |
1534 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1535 0x100 : 0),
1536 3, Wn3_MAC_Ctrl);
1537}
1538
1539static void vortex_check_media(struct net_device *dev, unsigned int init)
1540{
1541 struct vortex_private *vp = netdev_priv(dev);
1542 unsigned int ok_to_print = 0;
1543
1544 if (vortex_debug > 3)
1545 ok_to_print = 1;
1546
1547 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1548 vp->full_duplex = vp->mii.full_duplex;
1549 vortex_set_duplex(dev);
1550 } else if (init) {
1551 vortex_set_duplex(dev);
1552 }
1553}
1554
1555static int
1556vortex_up(struct net_device *dev)
1557{
1558 struct vortex_private *vp = netdev_priv(dev);
1559 void __iomem *ioaddr = vp->ioaddr;
1560 unsigned int config;
1561 int i, mii_reg1, mii_reg5, err = 0;
1562
1563 if (VORTEX_PCI(vp)) {
1564 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1565 if (vp->pm_state_valid)
1566 pci_restore_state(VORTEX_PCI(vp));
1567 err = pci_enable_device(VORTEX_PCI(vp));
1568 if (err) {
1569 pr_warn("%s: Could not enable device\n", dev->name);
1570 goto err_out;
1571 }
1572 }
1573
1574 /* Before initializing select the active media port. */
1575 config = window_read32(vp, 3, Wn3_Config);
1576
1577 if (vp->media_override != 7) {
1578 pr_info("%s: Media override to transceiver %d (%s).\n",
1579 dev->name, vp->media_override,
1580 media_tbl[vp->media_override].name);
1581 dev->if_port = vp->media_override;
1582 } else if (vp->autoselect) {
1583 if (vp->has_nway) {
1584 if (vortex_debug > 1)
1585 pr_info("%s: using NWAY device table, not %d\n",
1586 dev->name, dev->if_port);
1587 dev->if_port = XCVR_NWAY;
1588 } else {
1589 /* Find first available media type, starting with 100baseTx. */
1590 dev->if_port = XCVR_100baseTx;
1591 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1592 dev->if_port = media_tbl[dev->if_port].next;
1593 if (vortex_debug > 1)
1594 pr_info("%s: first available media type: %s\n",
1595 dev->name, media_tbl[dev->if_port].name);
1596 }
1597 } else {
1598 dev->if_port = vp->default_media;
1599 if (vortex_debug > 1)
1600 pr_info("%s: using default media %s\n",
1601 dev->name, media_tbl[dev->if_port].name);
1602 }
1603
1604 setup_timer(&vp->timer, vortex_timer, (unsigned long)dev);
1605 mod_timer(&vp->timer, RUN_AT(media_tbl[dev->if_port].wait));
1606 setup_timer(&vp->rx_oom_timer, rx_oom_timer, (unsigned long)dev);
1607
1608 if (vortex_debug > 1)
1609 pr_debug("%s: Initial media type %s.\n",
1610 dev->name, media_tbl[dev->if_port].name);
1611
1612 vp->full_duplex = vp->mii.force_media;
1613 config = BFINS(config, dev->if_port, 20, 4);
1614 if (vortex_debug > 6)
1615 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1616 window_write32(vp, config, 3, Wn3_Config);
1617
1618 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1619 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1620 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1621 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1622 vp->mii.full_duplex = vp->full_duplex;
1623
1624 vortex_check_media(dev, 1);
1625 }
1626 else
1627 vortex_set_duplex(dev);
1628
1629 issue_and_wait(dev, TxReset);
1630 /*
1631 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1632 */
1633 issue_and_wait(dev, RxReset|0x04);
1634
1635
1636 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1637
1638 if (vortex_debug > 1) {
1639 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1640 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1641 }
1642
1643 /* Set the station address and mask in window 2 each time opened. */
1644 for (i = 0; i < 6; i++)
1645 window_write8(vp, dev->dev_addr[i], 2, i);
1646 for (; i < 12; i+=2)
1647 window_write16(vp, 0, 2, i);
1648
1649 if (vp->cb_fn_base) {
1650 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1651 if (vp->drv_flags & INVERT_LED_PWR)
1652 n |= 0x10;
1653 if (vp->drv_flags & INVERT_MII_PWR)
1654 n |= 0x4000;
1655 window_write16(vp, n, 2, Wn2_ResetOptions);
1656 }
1657
1658 if (dev->if_port == XCVR_10base2)
1659 /* Start the thinnet transceiver. We should really wait 50ms...*/
1660 iowrite16(StartCoax, ioaddr + EL3_CMD);
1661 if (dev->if_port != XCVR_NWAY) {
1662 window_write16(vp,
1663 (window_read16(vp, 4, Wn4_Media) &
1664 ~(Media_10TP|Media_SQE)) |
1665 media_tbl[dev->if_port].media_bits,
1666 4, Wn4_Media);
1667 }
1668
1669 /* Switch to the stats window, and clear all stats by reading. */
1670 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1671 for (i = 0; i < 10; i++)
1672 window_read8(vp, 6, i);
1673 window_read16(vp, 6, 10);
1674 window_read16(vp, 6, 12);
1675 /* New: On the Vortex we must also clear the BadSSD counter. */
1676 window_read8(vp, 4, 12);
1677 /* ..and on the Boomerang we enable the extra statistics bits. */
1678 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1679
1680 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1681 vp->cur_rx = vp->dirty_rx = 0;
1682 /* Initialize the RxEarly register as recommended. */
1683 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1684 iowrite32(0x0020, ioaddr + PktStatus);
1685 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1686 }
1687 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1688 vp->cur_tx = vp->dirty_tx = 0;
1689 if (vp->drv_flags & IS_BOOMERANG)
1690 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1691 /* Clear the Rx, Tx rings. */
1692 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1693 vp->rx_ring[i].status = 0;
1694 for (i = 0; i < TX_RING_SIZE; i++)
1695 vp->tx_skbuff[i] = NULL;
1696 iowrite32(0, ioaddr + DownListPtr);
1697 }
1698 /* Set receiver mode: presumably accept b-case and phys addr only. */
1699 set_rx_mode(dev);
1700 /* enable 802.1q tagged frames */
1701 set_8021q_mode(dev, 1);
1702 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1703
1704 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1705 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1706 /* Allow status bits to be seen. */
1707 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1708 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1709 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1710 (vp->bus_master ? DMADone : 0);
1711 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1712 (vp->full_bus_master_rx ? 0 : RxComplete) |
1713 StatsFull | HostError | TxComplete | IntReq
1714 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1715 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1716 /* Ack all pending events, and set active indicator mask. */
1717 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1718 ioaddr + EL3_CMD);
1719 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1720 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1721 iowrite32(0x8000, vp->cb_fn_base + 4);
1722 netif_start_queue (dev);
1723 netdev_reset_queue(dev);
1724err_out:
1725 return err;
1726}
1727
1728static int
1729vortex_open(struct net_device *dev)
1730{
1731 struct vortex_private *vp = netdev_priv(dev);
1732 int i;
1733 int retval;
1734
1735 /* Use the now-standard shared IRQ implementation. */
1736 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1737 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1738 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1739 goto err;
1740 }
1741
1742 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1743 if (vortex_debug > 2)
1744 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1745 for (i = 0; i < RX_RING_SIZE; i++) {
1746 struct sk_buff *skb;
1747 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1748 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1749 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1750
1751 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1752 GFP_KERNEL);
1753 vp->rx_skbuff[i] = skb;
1754 if (skb == NULL)
1755 break; /* Bad news! */
1756
1757 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1758 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1759 }
1760 if (i != RX_RING_SIZE) {
1761 pr_emerg("%s: no memory for rx ring\n", dev->name);
1762 retval = -ENOMEM;
1763 goto err_free_skb;
1764 }
1765 /* Wrap the ring. */
1766 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1767 }
1768
1769 retval = vortex_up(dev);
1770 if (!retval)
1771 goto out;
1772
1773err_free_skb:
1774 for (i = 0; i < RX_RING_SIZE; i++) {
1775 if (vp->rx_skbuff[i]) {
1776 dev_kfree_skb(vp->rx_skbuff[i]);
1777 vp->rx_skbuff[i] = NULL;
1778 }
1779 }
1780 free_irq(dev->irq, dev);
1781err:
1782 if (vortex_debug > 1)
1783 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1784out:
1785 return retval;
1786}
1787
1788static void
1789vortex_timer(unsigned long data)
1790{
1791 struct net_device *dev = (struct net_device *)data;
1792 struct vortex_private *vp = netdev_priv(dev);
1793 void __iomem *ioaddr = vp->ioaddr;
1794 int next_tick = 60*HZ;
1795 int ok = 0;
1796 int media_status;
1797
1798 if (vortex_debug > 2) {
1799 pr_debug("%s: Media selection timer tick happened, %s.\n",
1800 dev->name, media_tbl[dev->if_port].name);
1801 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1802 }
1803
1804 media_status = window_read16(vp, 4, Wn4_Media);
1805 switch (dev->if_port) {
1806 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1807 if (media_status & Media_LnkBeat) {
1808 netif_carrier_on(dev);
1809 ok = 1;
1810 if (vortex_debug > 1)
1811 pr_debug("%s: Media %s has link beat, %x.\n",
1812 dev->name, media_tbl[dev->if_port].name, media_status);
1813 } else {
1814 netif_carrier_off(dev);
1815 if (vortex_debug > 1) {
1816 pr_debug("%s: Media %s has no link beat, %x.\n",
1817 dev->name, media_tbl[dev->if_port].name, media_status);
1818 }
1819 }
1820 break;
1821 case XCVR_MII: case XCVR_NWAY:
1822 {
1823 ok = 1;
1824 vortex_check_media(dev, 0);
1825 }
1826 break;
1827 default: /* Other media types handled by Tx timeouts. */
1828 if (vortex_debug > 1)
1829 pr_debug("%s: Media %s has no indication, %x.\n",
1830 dev->name, media_tbl[dev->if_port].name, media_status);
1831 ok = 1;
1832 }
1833
1834 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1835 next_tick = 5*HZ;
1836
1837 if (vp->medialock)
1838 goto leave_media_alone;
1839
1840 if (!ok) {
1841 unsigned int config;
1842
1843 spin_lock_irq(&vp->lock);
1844
1845 do {
1846 dev->if_port = media_tbl[dev->if_port].next;
1847 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1848 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1849 dev->if_port = vp->default_media;
1850 if (vortex_debug > 1)
1851 pr_debug("%s: Media selection failing, using default %s port.\n",
1852 dev->name, media_tbl[dev->if_port].name);
1853 } else {
1854 if (vortex_debug > 1)
1855 pr_debug("%s: Media selection failed, now trying %s port.\n",
1856 dev->name, media_tbl[dev->if_port].name);
1857 next_tick = media_tbl[dev->if_port].wait;
1858 }
1859 window_write16(vp,
1860 (media_status & ~(Media_10TP|Media_SQE)) |
1861 media_tbl[dev->if_port].media_bits,
1862 4, Wn4_Media);
1863
1864 config = window_read32(vp, 3, Wn3_Config);
1865 config = BFINS(config, dev->if_port, 20, 4);
1866 window_write32(vp, config, 3, Wn3_Config);
1867
1868 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1869 ioaddr + EL3_CMD);
1870 if (vortex_debug > 1)
1871 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1872 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1873
1874 spin_unlock_irq(&vp->lock);
1875 }
1876
1877leave_media_alone:
1878 if (vortex_debug > 2)
1879 pr_debug("%s: Media selection timer finished, %s.\n",
1880 dev->name, media_tbl[dev->if_port].name);
1881
1882 mod_timer(&vp->timer, RUN_AT(next_tick));
1883 if (vp->deferred)
1884 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1885}
1886
1887static void vortex_tx_timeout(struct net_device *dev)
1888{
1889 struct vortex_private *vp = netdev_priv(dev);
1890 void __iomem *ioaddr = vp->ioaddr;
1891
1892 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1893 dev->name, ioread8(ioaddr + TxStatus),
1894 ioread16(ioaddr + EL3_STATUS));
1895 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1896 window_read16(vp, 4, Wn4_NetDiag),
1897 window_read16(vp, 4, Wn4_Media),
1898 ioread32(ioaddr + PktStatus),
1899 window_read16(vp, 4, Wn4_FIFODiag));
1900 /* Slight code bloat to be user friendly. */
1901 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1902 pr_err("%s: Transmitter encountered 16 collisions --"
1903 " network cable problem?\n", dev->name);
1904 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1905 pr_err("%s: Interrupt posted but not delivered --"
1906 " IRQ blocked by another device?\n", dev->name);
1907 /* Bad idea here.. but we might as well handle a few events. */
1908 {
1909 /*
1910 * Block interrupts because vortex_interrupt does a bare spin_lock()
1911 */
1912 unsigned long flags;
1913 local_irq_save(flags);
1914 if (vp->full_bus_master_tx)
1915 boomerang_interrupt(dev->irq, dev);
1916 else
1917 vortex_interrupt(dev->irq, dev);
1918 local_irq_restore(flags);
1919 }
1920 }
1921
1922 if (vortex_debug > 0)
1923 dump_tx_ring(dev);
1924
1925 issue_and_wait(dev, TxReset);
1926
1927 dev->stats.tx_errors++;
1928 if (vp->full_bus_master_tx) {
1929 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1930 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1931 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1932 ioaddr + DownListPtr);
1933 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
1934 netif_wake_queue (dev);
1935 netdev_reset_queue (dev);
1936 }
1937 if (vp->drv_flags & IS_BOOMERANG)
1938 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1939 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1940 } else {
1941 dev->stats.tx_dropped++;
1942 netif_wake_queue(dev);
1943 netdev_reset_queue(dev);
1944 }
1945 /* Issue Tx Enable */
1946 iowrite16(TxEnable, ioaddr + EL3_CMD);
1947 dev->trans_start = jiffies; /* prevent tx timeout */
1948}
1949
1950/*
1951 * Handle uncommon interrupt sources. This is a separate routine to minimize
1952 * the cache impact.
1953 */
1954static void
1955vortex_error(struct net_device *dev, int status)
1956{
1957 struct vortex_private *vp = netdev_priv(dev);
1958 void __iomem *ioaddr = vp->ioaddr;
1959 int do_tx_reset = 0, reset_mask = 0;
1960 unsigned char tx_status = 0;
1961
1962 if (vortex_debug > 2) {
1963 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1964 }
1965
1966 if (status & TxComplete) { /* Really "TxError" for us. */
1967 tx_status = ioread8(ioaddr + TxStatus);
1968 /* Presumably a tx-timeout. We must merely re-enable. */
1969 if (vortex_debug > 2 ||
1970 (tx_status != 0x88 && vortex_debug > 0)) {
1971 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1972 dev->name, tx_status);
1973 if (tx_status == 0x82) {
1974 pr_err("Probably a duplex mismatch. See "
1975 "Documentation/networking/vortex.txt\n");
1976 }
1977 dump_tx_ring(dev);
1978 }
1979 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1980 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1981 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1982 iowrite8(0, ioaddr + TxStatus);
1983 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1984 do_tx_reset = 1;
1985 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1986 do_tx_reset = 1;
1987 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1988 } else { /* Merely re-enable the transmitter. */
1989 iowrite16(TxEnable, ioaddr + EL3_CMD);
1990 }
1991 }
1992
1993 if (status & RxEarly) /* Rx early is unused. */
1994 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1995
1996 if (status & StatsFull) { /* Empty statistics. */
1997 static int DoneDidThat;
1998 if (vortex_debug > 4)
1999 pr_debug("%s: Updating stats.\n", dev->name);
2000 update_stats(ioaddr, dev);
2001 /* HACK: Disable statistics as an interrupt source. */
2002 /* This occurs when we have the wrong media type! */
2003 if (DoneDidThat == 0 &&
2004 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2005 pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
2006 dev->name);
2007 iowrite16(SetIntrEnb |
2008 (window_read16(vp, 5, 10) & ~StatsFull),
2009 ioaddr + EL3_CMD);
2010 vp->intr_enable &= ~StatsFull;
2011 DoneDidThat++;
2012 }
2013 }
2014 if (status & IntReq) { /* Restore all interrupt sources. */
2015 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2016 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2017 }
2018 if (status & HostError) {
2019 u16 fifo_diag;
2020 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2021 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2022 dev->name, fifo_diag);
2023 /* Adapter failure requires Tx/Rx reset and reinit. */
2024 if (vp->full_bus_master_tx) {
2025 int bus_status = ioread32(ioaddr + PktStatus);
2026 /* 0x80000000 PCI master abort. */
2027 /* 0x40000000 PCI target abort. */
2028 if (vortex_debug)
2029 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2030
2031 /* In this case, blow the card away */
2032 /* Must not enter D3 or we can't legally issue the reset! */
2033 vortex_down(dev, 0);
2034 issue_and_wait(dev, TotalReset | 0xff);
2035 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2036 } else if (fifo_diag & 0x0400)
2037 do_tx_reset = 1;
2038 if (fifo_diag & 0x3000) {
2039 /* Reset Rx fifo and upload logic */
2040 issue_and_wait(dev, RxReset|0x07);
2041 /* Set the Rx filter to the current state. */
2042 set_rx_mode(dev);
2043 /* enable 802.1q VLAN tagged frames */
2044 set_8021q_mode(dev, 1);
2045 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2046 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2047 }
2048 }
2049
2050 if (do_tx_reset) {
2051 issue_and_wait(dev, TxReset|reset_mask);
2052 iowrite16(TxEnable, ioaddr + EL3_CMD);
2053 if (!vp->full_bus_master_tx)
2054 netif_wake_queue(dev);
2055 }
2056}
2057
2058static netdev_tx_t
2059vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2060{
2061 struct vortex_private *vp = netdev_priv(dev);
2062 void __iomem *ioaddr = vp->ioaddr;
2063 int skblen = skb->len;
2064
2065 /* Put out the doubleword header... */
2066 iowrite32(skb->len, ioaddr + TX_FIFO);
2067 if (vp->bus_master) {
2068 /* Set the bus-master controller to transfer the packet. */
2069 int len = (skb->len + 3) & ~3;
2070 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2071 PCI_DMA_TODEVICE);
2072 spin_lock_irq(&vp->window_lock);
2073 window_set(vp, 7);
2074 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2075 iowrite16(len, ioaddr + Wn7_MasterLen);
2076 spin_unlock_irq(&vp->window_lock);
2077 vp->tx_skb = skb;
2078 skb_tx_timestamp(skb);
2079 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2080 /* netif_wake_queue() will be called at the DMADone interrupt. */
2081 } else {
2082 /* ... and the packet rounded to a doubleword. */
2083 skb_tx_timestamp(skb);
2084 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2085 dev_consume_skb_any (skb);
2086 if (ioread16(ioaddr + TxFree) > 1536) {
2087 netif_start_queue (dev); /* AKPM: redundant? */
2088 } else {
2089 /* Interrupt us when the FIFO has room for max-sized packet. */
2090 netif_stop_queue(dev);
2091 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2092 }
2093 }
2094
2095 netdev_sent_queue(dev, skblen);
2096
2097 /* Clear the Tx status stack. */
2098 {
2099 int tx_status;
2100 int i = 32;
2101
2102 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2103 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2104 if (vortex_debug > 2)
2105 pr_debug("%s: Tx error, status %2.2x.\n",
2106 dev->name, tx_status);
2107 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2108 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2109 if (tx_status & 0x30) {
2110 issue_and_wait(dev, TxReset);
2111 }
2112 iowrite16(TxEnable, ioaddr + EL3_CMD);
2113 }
2114 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2115 }
2116 }
2117 return NETDEV_TX_OK;
2118}
2119
2120static netdev_tx_t
2121boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2122{
2123 struct vortex_private *vp = netdev_priv(dev);
2124 void __iomem *ioaddr = vp->ioaddr;
2125 /* Calculate the next Tx descriptor entry. */
2126 int entry = vp->cur_tx % TX_RING_SIZE;
2127 int skblen = skb->len;
2128 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2129 unsigned long flags;
2130 dma_addr_t dma_addr;
2131
2132 if (vortex_debug > 6) {
2133 pr_debug("boomerang_start_xmit()\n");
2134 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2135 dev->name, vp->cur_tx);
2136 }
2137
2138 /*
2139 * We can't allow a recursion from our interrupt handler back into the
2140 * tx routine, as they take the same spin lock, and that causes
2141 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2142 * a bit
2143 */
2144 if (vp->handling_irq)
2145 return NETDEV_TX_BUSY;
2146
2147 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2148 if (vortex_debug > 0)
2149 pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2150 dev->name);
2151 netif_stop_queue(dev);
2152 return NETDEV_TX_BUSY;
2153 }
2154
2155 vp->tx_skbuff[entry] = skb;
2156
2157 vp->tx_ring[entry].next = 0;
2158#if DO_ZEROCOPY
2159 if (skb->ip_summed != CHECKSUM_PARTIAL)
2160 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2161 else
2162 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2163
2164 if (!skb_shinfo(skb)->nr_frags) {
2165 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len,
2166 PCI_DMA_TODEVICE);
2167 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2168 goto out_dma_err;
2169
2170 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2171 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2172 } else {
2173 int i;
2174
2175 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data,
2176 skb_headlen(skb), PCI_DMA_TODEVICE);
2177 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2178 goto out_dma_err;
2179
2180 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2181 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2182
2183 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2184 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2185
2186 dma_addr = skb_frag_dma_map(&VORTEX_PCI(vp)->dev, frag,
2187 0,
2188 frag->size,
2189 DMA_TO_DEVICE);
2190 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr)) {
2191 for(i = i-1; i >= 0; i--)
2192 dma_unmap_page(&VORTEX_PCI(vp)->dev,
2193 le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2194 le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2195 DMA_TO_DEVICE);
2196
2197 pci_unmap_single(VORTEX_PCI(vp),
2198 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2199 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2200 PCI_DMA_TODEVICE);
2201
2202 goto out_dma_err;
2203 }
2204
2205 vp->tx_ring[entry].frag[i+1].addr =
2206 cpu_to_le32(dma_addr);
2207
2208 if (i == skb_shinfo(skb)->nr_frags-1)
2209 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2210 else
2211 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2212 }
2213 }
2214#else
2215 dma_addr = pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE);
2216 if (dma_mapping_error(&VORTEX_PCI(vp)->dev, dma_addr))
2217 goto out_dma_err;
2218 vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2219 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2220 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2221#endif
2222
2223 spin_lock_irqsave(&vp->lock, flags);
2224 /* Wait for the stall to complete. */
2225 issue_and_wait(dev, DownStall);
2226 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2227 if (ioread32(ioaddr + DownListPtr) == 0) {
2228 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2229 vp->queued_packet++;
2230 }
2231
2232 vp->cur_tx++;
2233 netdev_sent_queue(dev, skblen);
2234
2235 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2236 netif_stop_queue (dev);
2237 } else { /* Clear previous interrupt enable. */
2238#if defined(tx_interrupt_mitigation)
2239 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2240 * were selected, this would corrupt DN_COMPLETE. No?
2241 */
2242 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2243#endif
2244 }
2245 skb_tx_timestamp(skb);
2246 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2247 spin_unlock_irqrestore(&vp->lock, flags);
2248out:
2249 return NETDEV_TX_OK;
2250out_dma_err:
2251 dev_err(&VORTEX_PCI(vp)->dev, "Error mapping dma buffer\n");
2252 goto out;
2253}
2254
2255/* The interrupt handler does all of the Rx thread work and cleans up
2256 after the Tx thread. */
2257
2258/*
2259 * This is the ISR for the vortex series chips.
2260 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2261 */
2262
2263static irqreturn_t
2264vortex_interrupt(int irq, void *dev_id)
2265{
2266 struct net_device *dev = dev_id;
2267 struct vortex_private *vp = netdev_priv(dev);
2268 void __iomem *ioaddr;
2269 int status;
2270 int work_done = max_interrupt_work;
2271 int handled = 0;
2272 unsigned int bytes_compl = 0, pkts_compl = 0;
2273
2274 ioaddr = vp->ioaddr;
2275 spin_lock(&vp->lock);
2276
2277 status = ioread16(ioaddr + EL3_STATUS);
2278
2279 if (vortex_debug > 6)
2280 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2281
2282 if ((status & IntLatch) == 0)
2283 goto handler_exit; /* No interrupt: shared IRQs cause this */
2284 handled = 1;
2285
2286 if (status & IntReq) {
2287 status |= vp->deferred;
2288 vp->deferred = 0;
2289 }
2290
2291 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2292 goto handler_exit;
2293
2294 if (vortex_debug > 4)
2295 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2296 dev->name, status, ioread8(ioaddr + Timer));
2297
2298 spin_lock(&vp->window_lock);
2299 window_set(vp, 7);
2300
2301 do {
2302 if (vortex_debug > 5)
2303 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2304 dev->name, status);
2305 if (status & RxComplete)
2306 vortex_rx(dev);
2307
2308 if (status & TxAvailable) {
2309 if (vortex_debug > 5)
2310 pr_debug(" TX room bit was handled.\n");
2311 /* There's room in the FIFO for a full-sized packet. */
2312 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2313 netif_wake_queue (dev);
2314 }
2315
2316 if (status & DMADone) {
2317 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2318 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2319 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2320 pkts_compl++;
2321 bytes_compl += vp->tx_skb->len;
2322 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2323 if (ioread16(ioaddr + TxFree) > 1536) {
2324 /*
2325 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2326 * insufficient FIFO room, the TxAvailable test will succeed and call
2327 * netif_wake_queue()
2328 */
2329 netif_wake_queue(dev);
2330 } else { /* Interrupt when FIFO has room for max-sized packet. */
2331 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2332 netif_stop_queue(dev);
2333 }
2334 }
2335 }
2336 /* Check for all uncommon interrupts at once. */
2337 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2338 if (status == 0xffff)
2339 break;
2340 if (status & RxEarly)
2341 vortex_rx(dev);
2342 spin_unlock(&vp->window_lock);
2343 vortex_error(dev, status);
2344 spin_lock(&vp->window_lock);
2345 window_set(vp, 7);
2346 }
2347
2348 if (--work_done < 0) {
2349 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2350 dev->name, status);
2351 /* Disable all pending interrupts. */
2352 do {
2353 vp->deferred |= status;
2354 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2355 ioaddr + EL3_CMD);
2356 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2357 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2358 /* The timer will reenable interrupts. */
2359 mod_timer(&vp->timer, jiffies + 1*HZ);
2360 break;
2361 }
2362 /* Acknowledge the IRQ. */
2363 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2364 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2365
2366 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2367 spin_unlock(&vp->window_lock);
2368
2369 if (vortex_debug > 4)
2370 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2371 dev->name, status);
2372handler_exit:
2373 spin_unlock(&vp->lock);
2374 return IRQ_RETVAL(handled);
2375}
2376
2377/*
2378 * This is the ISR for the boomerang series chips.
2379 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2380 */
2381
2382static irqreturn_t
2383boomerang_interrupt(int irq, void *dev_id)
2384{
2385 struct net_device *dev = dev_id;
2386 struct vortex_private *vp = netdev_priv(dev);
2387 void __iomem *ioaddr;
2388 int status;
2389 int work_done = max_interrupt_work;
2390 int handled = 0;
2391 unsigned int bytes_compl = 0, pkts_compl = 0;
2392
2393 ioaddr = vp->ioaddr;
2394
2395
2396 /*
2397 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2398 * and boomerang_start_xmit
2399 */
2400 spin_lock(&vp->lock);
2401 vp->handling_irq = 1;
2402
2403 status = ioread16(ioaddr + EL3_STATUS);
2404
2405 if (vortex_debug > 6)
2406 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2407
2408 if ((status & IntLatch) == 0)
2409 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2410 handled = 1;
2411
2412 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2413 if (vortex_debug > 1)
2414 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2415 goto handler_exit;
2416 }
2417
2418 if (status & IntReq) {
2419 status |= vp->deferred;
2420 vp->deferred = 0;
2421 }
2422
2423 if (vortex_debug > 4)
2424 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2425 dev->name, status, ioread8(ioaddr + Timer));
2426 do {
2427 if (vortex_debug > 5)
2428 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2429 dev->name, status);
2430 if (status & UpComplete) {
2431 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2432 if (vortex_debug > 5)
2433 pr_debug("boomerang_interrupt->boomerang_rx\n");
2434 boomerang_rx(dev);
2435 }
2436
2437 if (status & DownComplete) {
2438 unsigned int dirty_tx = vp->dirty_tx;
2439
2440 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2441 while (vp->cur_tx - dirty_tx > 0) {
2442 int entry = dirty_tx % TX_RING_SIZE;
2443#if 1 /* AKPM: the latter is faster, but cyclone-only */
2444 if (ioread32(ioaddr + DownListPtr) ==
2445 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2446 break; /* It still hasn't been processed. */
2447#else
2448 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2449 break; /* It still hasn't been processed. */
2450#endif
2451
2452 if (vp->tx_skbuff[entry]) {
2453 struct sk_buff *skb = vp->tx_skbuff[entry];
2454#if DO_ZEROCOPY
2455 int i;
2456 pci_unmap_single(VORTEX_PCI(vp),
2457 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2458 le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF,
2459 PCI_DMA_TODEVICE);
2460
2461 for (i=1; i<=skb_shinfo(skb)->nr_frags; i++)
2462 pci_unmap_page(VORTEX_PCI(vp),
2463 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2464 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2465 PCI_DMA_TODEVICE);
2466#else
2467 pci_unmap_single(VORTEX_PCI(vp),
2468 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2469#endif
2470 pkts_compl++;
2471 bytes_compl += skb->len;
2472 dev_kfree_skb_irq(skb);
2473 vp->tx_skbuff[entry] = NULL;
2474 } else {
2475 pr_debug("boomerang_interrupt: no skb!\n");
2476 }
2477 /* dev->stats.tx_packets++; Counted below. */
2478 dirty_tx++;
2479 }
2480 vp->dirty_tx = dirty_tx;
2481 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2482 if (vortex_debug > 6)
2483 pr_debug("boomerang_interrupt: wake queue\n");
2484 netif_wake_queue (dev);
2485 }
2486 }
2487
2488 /* Check for all uncommon interrupts at once. */
2489 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2490 vortex_error(dev, status);
2491
2492 if (--work_done < 0) {
2493 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2494 dev->name, status);
2495 /* Disable all pending interrupts. */
2496 do {
2497 vp->deferred |= status;
2498 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2499 ioaddr + EL3_CMD);
2500 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2501 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2502 /* The timer will reenable interrupts. */
2503 mod_timer(&vp->timer, jiffies + 1*HZ);
2504 break;
2505 }
2506 /* Acknowledge the IRQ. */
2507 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2508 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2509 iowrite32(0x8000, vp->cb_fn_base + 4);
2510
2511 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2512 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2513
2514 if (vortex_debug > 4)
2515 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2516 dev->name, status);
2517handler_exit:
2518 vp->handling_irq = 0;
2519 spin_unlock(&vp->lock);
2520 return IRQ_RETVAL(handled);
2521}
2522
2523static int vortex_rx(struct net_device *dev)
2524{
2525 struct vortex_private *vp = netdev_priv(dev);
2526 void __iomem *ioaddr = vp->ioaddr;
2527 int i;
2528 short rx_status;
2529
2530 if (vortex_debug > 5)
2531 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2532 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2533 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2534 if (rx_status & 0x4000) { /* Error, update stats. */
2535 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2536 if (vortex_debug > 2)
2537 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2538 dev->stats.rx_errors++;
2539 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2540 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2541 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2542 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2543 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2544 } else {
2545 /* The packet length: up to 4.5K!. */
2546 int pkt_len = rx_status & 0x1fff;
2547 struct sk_buff *skb;
2548
2549 skb = netdev_alloc_skb(dev, pkt_len + 5);
2550 if (vortex_debug > 4)
2551 pr_debug("Receiving packet size %d status %4.4x.\n",
2552 pkt_len, rx_status);
2553 if (skb != NULL) {
2554 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2555 /* 'skb_put()' points to the start of sk_buff data area. */
2556 if (vp->bus_master &&
2557 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2558 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2559 pkt_len, PCI_DMA_FROMDEVICE);
2560 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2561 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2562 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2563 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2564 ;
2565 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2566 } else {
2567 ioread32_rep(ioaddr + RX_FIFO,
2568 skb_put(skb, pkt_len),
2569 (pkt_len + 3) >> 2);
2570 }
2571 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2572 skb->protocol = eth_type_trans(skb, dev);
2573 netif_rx(skb);
2574 dev->stats.rx_packets++;
2575 /* Wait a limited time to go to next packet. */
2576 for (i = 200; i >= 0; i--)
2577 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2578 break;
2579 continue;
2580 } else if (vortex_debug > 0)
2581 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2582 dev->name, pkt_len);
2583 dev->stats.rx_dropped++;
2584 }
2585 issue_and_wait(dev, RxDiscard);
2586 }
2587
2588 return 0;
2589}
2590
2591static int
2592boomerang_rx(struct net_device *dev)
2593{
2594 struct vortex_private *vp = netdev_priv(dev);
2595 int entry = vp->cur_rx % RX_RING_SIZE;
2596 void __iomem *ioaddr = vp->ioaddr;
2597 int rx_status;
2598 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2599
2600 if (vortex_debug > 5)
2601 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2602
2603 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2604 if (--rx_work_limit < 0)
2605 break;
2606 if (rx_status & RxDError) { /* Error, update stats. */
2607 unsigned char rx_error = rx_status >> 16;
2608 if (vortex_debug > 2)
2609 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2610 dev->stats.rx_errors++;
2611 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2612 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2613 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2614 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2615 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2616 } else {
2617 /* The packet length: up to 4.5K!. */
2618 int pkt_len = rx_status & 0x1fff;
2619 struct sk_buff *skb;
2620 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2621
2622 if (vortex_debug > 4)
2623 pr_debug("Receiving packet size %d status %4.4x.\n",
2624 pkt_len, rx_status);
2625
2626 /* Check if the packet is long enough to just accept without
2627 copying to a properly sized skbuff. */
2628 if (pkt_len < rx_copybreak &&
2629 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2630 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2631 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2632 /* 'skb_put()' points to the start of sk_buff data area. */
2633 memcpy(skb_put(skb, pkt_len),
2634 vp->rx_skbuff[entry]->data,
2635 pkt_len);
2636 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2637 vp->rx_copy++;
2638 } else {
2639 /* Pass up the skbuff already on the Rx ring. */
2640 skb = vp->rx_skbuff[entry];
2641 vp->rx_skbuff[entry] = NULL;
2642 skb_put(skb, pkt_len);
2643 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2644 vp->rx_nocopy++;
2645 }
2646 skb->protocol = eth_type_trans(skb, dev);
2647 { /* Use hardware checksum info. */
2648 int csum_bits = rx_status & 0xee000000;
2649 if (csum_bits &&
2650 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2651 csum_bits == (IPChksumValid | UDPChksumValid))) {
2652 skb->ip_summed = CHECKSUM_UNNECESSARY;
2653 vp->rx_csumhits++;
2654 }
2655 }
2656 netif_rx(skb);
2657 dev->stats.rx_packets++;
2658 }
2659 entry = (++vp->cur_rx) % RX_RING_SIZE;
2660 }
2661 /* Refill the Rx ring buffers. */
2662 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2663 struct sk_buff *skb;
2664 entry = vp->dirty_rx % RX_RING_SIZE;
2665 if (vp->rx_skbuff[entry] == NULL) {
2666 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2667 if (skb == NULL) {
2668 static unsigned long last_jif;
2669 if (time_after(jiffies, last_jif + 10 * HZ)) {
2670 pr_warn("%s: memory shortage\n",
2671 dev->name);
2672 last_jif = jiffies;
2673 }
2674 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2675 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2676 break; /* Bad news! */
2677 }
2678
2679 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2680 vp->rx_skbuff[entry] = skb;
2681 }
2682 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2683 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2684 }
2685 return 0;
2686}
2687
2688/*
2689 * If we've hit a total OOM refilling the Rx ring we poll once a second
2690 * for some memory. Otherwise there is no way to restart the rx process.
2691 */
2692static void
2693rx_oom_timer(unsigned long arg)
2694{
2695 struct net_device *dev = (struct net_device *)arg;
2696 struct vortex_private *vp = netdev_priv(dev);
2697
2698 spin_lock_irq(&vp->lock);
2699 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2700 boomerang_rx(dev);
2701 if (vortex_debug > 1) {
2702 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2703 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2704 }
2705 spin_unlock_irq(&vp->lock);
2706}
2707
2708static void
2709vortex_down(struct net_device *dev, int final_down)
2710{
2711 struct vortex_private *vp = netdev_priv(dev);
2712 void __iomem *ioaddr = vp->ioaddr;
2713
2714 netdev_reset_queue(dev);
2715 netif_stop_queue(dev);
2716
2717 del_timer_sync(&vp->rx_oom_timer);
2718 del_timer_sync(&vp->timer);
2719
2720 /* Turn off statistics ASAP. We update dev->stats below. */
2721 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2722
2723 /* Disable the receiver and transmitter. */
2724 iowrite16(RxDisable, ioaddr + EL3_CMD);
2725 iowrite16(TxDisable, ioaddr + EL3_CMD);
2726
2727 /* Disable receiving 802.1q tagged frames */
2728 set_8021q_mode(dev, 0);
2729
2730 if (dev->if_port == XCVR_10base2)
2731 /* Turn off thinnet power. Green! */
2732 iowrite16(StopCoax, ioaddr + EL3_CMD);
2733
2734 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2735
2736 update_stats(ioaddr, dev);
2737 if (vp->full_bus_master_rx)
2738 iowrite32(0, ioaddr + UpListPtr);
2739 if (vp->full_bus_master_tx)
2740 iowrite32(0, ioaddr + DownListPtr);
2741
2742 if (final_down && VORTEX_PCI(vp)) {
2743 vp->pm_state_valid = 1;
2744 pci_save_state(VORTEX_PCI(vp));
2745 acpi_set_WOL(dev);
2746 }
2747}
2748
2749static int
2750vortex_close(struct net_device *dev)
2751{
2752 struct vortex_private *vp = netdev_priv(dev);
2753 void __iomem *ioaddr = vp->ioaddr;
2754 int i;
2755
2756 if (netif_device_present(dev))
2757 vortex_down(dev, 1);
2758
2759 if (vortex_debug > 1) {
2760 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2761 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2762 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2763 " tx_queued %d Rx pre-checksummed %d.\n",
2764 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2765 }
2766
2767#if DO_ZEROCOPY
2768 if (vp->rx_csumhits &&
2769 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2770 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2771 pr_warn("%s supports hardware checksums, and we're not using them!\n",
2772 dev->name);
2773 }
2774#endif
2775
2776 free_irq(dev->irq, dev);
2777
2778 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2779 for (i = 0; i < RX_RING_SIZE; i++)
2780 if (vp->rx_skbuff[i]) {
2781 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2782 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2783 dev_kfree_skb(vp->rx_skbuff[i]);
2784 vp->rx_skbuff[i] = NULL;
2785 }
2786 }
2787 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2788 for (i = 0; i < TX_RING_SIZE; i++) {
2789 if (vp->tx_skbuff[i]) {
2790 struct sk_buff *skb = vp->tx_skbuff[i];
2791#if DO_ZEROCOPY
2792 int k;
2793
2794 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2795 pci_unmap_single(VORTEX_PCI(vp),
2796 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2797 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2798 PCI_DMA_TODEVICE);
2799#else
2800 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2801#endif
2802 dev_kfree_skb(skb);
2803 vp->tx_skbuff[i] = NULL;
2804 }
2805 }
2806 }
2807
2808 return 0;
2809}
2810
2811static void
2812dump_tx_ring(struct net_device *dev)
2813{
2814 if (vortex_debug > 0) {
2815 struct vortex_private *vp = netdev_priv(dev);
2816 void __iomem *ioaddr = vp->ioaddr;
2817
2818 if (vp->full_bus_master_tx) {
2819 int i;
2820 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2821
2822 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2823 vp->full_bus_master_tx,
2824 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2825 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2826 pr_err(" Transmit list %8.8x vs. %p.\n",
2827 ioread32(ioaddr + DownListPtr),
2828 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2829 issue_and_wait(dev, DownStall);
2830 for (i = 0; i < TX_RING_SIZE; i++) {
2831 unsigned int length;
2832
2833#if DO_ZEROCOPY
2834 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2835#else
2836 length = le32_to_cpu(vp->tx_ring[i].length);
2837#endif
2838 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2839 i, &vp->tx_ring[i], length,
2840 le32_to_cpu(vp->tx_ring[i].status));
2841 }
2842 if (!stalled)
2843 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2844 }
2845 }
2846}
2847
2848static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2849{
2850 struct vortex_private *vp = netdev_priv(dev);
2851 void __iomem *ioaddr = vp->ioaddr;
2852 unsigned long flags;
2853
2854 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2855 spin_lock_irqsave (&vp->lock, flags);
2856 update_stats(ioaddr, dev);
2857 spin_unlock_irqrestore (&vp->lock, flags);
2858 }
2859 return &dev->stats;
2860}
2861
2862/* Update statistics.
2863 Unlike with the EL3 we need not worry about interrupts changing
2864 the window setting from underneath us, but we must still guard
2865 against a race condition with a StatsUpdate interrupt updating the
2866 table. This is done by checking that the ASM (!) code generated uses
2867 atomic updates with '+='.
2868 */
2869static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2870{
2871 struct vortex_private *vp = netdev_priv(dev);
2872
2873 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2874 /* Switch to the stats window, and read everything. */
2875 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2876 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2877 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2878 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2879 dev->stats.tx_packets += window_read8(vp, 6, 6);
2880 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2881 0x30) << 4;
2882 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2883 /* Don't bother with register 9, an extension of registers 6&7.
2884 If we do use the 6&7 values the atomic update assumption above
2885 is invalid. */
2886 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2887 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2888 /* Extra stats for get_ethtool_stats() */
2889 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2890 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2891 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2892 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2893
2894 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2895 + vp->xstats.tx_single_collisions
2896 + vp->xstats.tx_max_collisions;
2897
2898 {
2899 u8 up = window_read8(vp, 4, 13);
2900 dev->stats.rx_bytes += (up & 0x0f) << 16;
2901 dev->stats.tx_bytes += (up & 0xf0) << 12;
2902 }
2903}
2904
2905static int vortex_nway_reset(struct net_device *dev)
2906{
2907 struct vortex_private *vp = netdev_priv(dev);
2908
2909 return mii_nway_restart(&vp->mii);
2910}
2911
2912static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2913{
2914 struct vortex_private *vp = netdev_priv(dev);
2915
2916 return mii_ethtool_gset(&vp->mii, cmd);
2917}
2918
2919static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2920{
2921 struct vortex_private *vp = netdev_priv(dev);
2922
2923 return mii_ethtool_sset(&vp->mii, cmd);
2924}
2925
2926static u32 vortex_get_msglevel(struct net_device *dev)
2927{
2928 return vortex_debug;
2929}
2930
2931static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2932{
2933 vortex_debug = dbg;
2934}
2935
2936static int vortex_get_sset_count(struct net_device *dev, int sset)
2937{
2938 switch (sset) {
2939 case ETH_SS_STATS:
2940 return VORTEX_NUM_STATS;
2941 default:
2942 return -EOPNOTSUPP;
2943 }
2944}
2945
2946static void vortex_get_ethtool_stats(struct net_device *dev,
2947 struct ethtool_stats *stats, u64 *data)
2948{
2949 struct vortex_private *vp = netdev_priv(dev);
2950 void __iomem *ioaddr = vp->ioaddr;
2951 unsigned long flags;
2952
2953 spin_lock_irqsave(&vp->lock, flags);
2954 update_stats(ioaddr, dev);
2955 spin_unlock_irqrestore(&vp->lock, flags);
2956
2957 data[0] = vp->xstats.tx_deferred;
2958 data[1] = vp->xstats.tx_max_collisions;
2959 data[2] = vp->xstats.tx_multiple_collisions;
2960 data[3] = vp->xstats.tx_single_collisions;
2961 data[4] = vp->xstats.rx_bad_ssd;
2962}
2963
2964
2965static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2966{
2967 switch (stringset) {
2968 case ETH_SS_STATS:
2969 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2970 break;
2971 default:
2972 WARN_ON(1);
2973 break;
2974 }
2975}
2976
2977static void vortex_get_drvinfo(struct net_device *dev,
2978 struct ethtool_drvinfo *info)
2979{
2980 struct vortex_private *vp = netdev_priv(dev);
2981
2982 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2983 if (VORTEX_PCI(vp)) {
2984 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2985 sizeof(info->bus_info));
2986 } else {
2987 if (VORTEX_EISA(vp))
2988 strlcpy(info->bus_info, dev_name(vp->gendev),
2989 sizeof(info->bus_info));
2990 else
2991 snprintf(info->bus_info, sizeof(info->bus_info),
2992 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2993 }
2994}
2995
2996static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2997{
2998 struct vortex_private *vp = netdev_priv(dev);
2999
3000 if (!VORTEX_PCI(vp))
3001 return;
3002
3003 wol->supported = WAKE_MAGIC;
3004
3005 wol->wolopts = 0;
3006 if (vp->enable_wol)
3007 wol->wolopts |= WAKE_MAGIC;
3008}
3009
3010static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3011{
3012 struct vortex_private *vp = netdev_priv(dev);
3013
3014 if (!VORTEX_PCI(vp))
3015 return -EOPNOTSUPP;
3016
3017 if (wol->wolopts & ~WAKE_MAGIC)
3018 return -EINVAL;
3019
3020 if (wol->wolopts & WAKE_MAGIC)
3021 vp->enable_wol = 1;
3022 else
3023 vp->enable_wol = 0;
3024 acpi_set_WOL(dev);
3025
3026 return 0;
3027}
3028
3029static const struct ethtool_ops vortex_ethtool_ops = {
3030 .get_drvinfo = vortex_get_drvinfo,
3031 .get_strings = vortex_get_strings,
3032 .get_msglevel = vortex_get_msglevel,
3033 .set_msglevel = vortex_set_msglevel,
3034 .get_ethtool_stats = vortex_get_ethtool_stats,
3035 .get_sset_count = vortex_get_sset_count,
3036 .get_settings = vortex_get_settings,
3037 .set_settings = vortex_set_settings,
3038 .get_link = ethtool_op_get_link,
3039 .nway_reset = vortex_nway_reset,
3040 .get_wol = vortex_get_wol,
3041 .set_wol = vortex_set_wol,
3042 .get_ts_info = ethtool_op_get_ts_info,
3043};
3044
3045#ifdef CONFIG_PCI
3046/*
3047 * Must power the device up to do MDIO operations
3048 */
3049static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3050{
3051 int err;
3052 struct vortex_private *vp = netdev_priv(dev);
3053 pci_power_t state = 0;
3054
3055 if(VORTEX_PCI(vp))
3056 state = VORTEX_PCI(vp)->current_state;
3057
3058 /* The kernel core really should have pci_get_power_state() */
3059
3060 if(state != 0)
3061 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3062 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3063 if(state != 0)
3064 pci_set_power_state(VORTEX_PCI(vp), state);
3065
3066 return err;
3067}
3068#endif
3069
3070
3071/* Pre-Cyclone chips have no documented multicast filter, so the only
3072 multicast setting is to receive all multicast frames. At least
3073 the chip has a very clean way to set the mode, unlike many others. */
3074static void set_rx_mode(struct net_device *dev)
3075{
3076 struct vortex_private *vp = netdev_priv(dev);
3077 void __iomem *ioaddr = vp->ioaddr;
3078 int new_mode;
3079
3080 if (dev->flags & IFF_PROMISC) {
3081 if (vortex_debug > 3)
3082 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3083 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3084 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3085 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3086 } else
3087 new_mode = SetRxFilter | RxStation | RxBroadcast;
3088
3089 iowrite16(new_mode, ioaddr + EL3_CMD);
3090}
3091
3092#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3093/* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3094 Note that this must be done after each RxReset due to some backwards
3095 compatibility logic in the Cyclone and Tornado ASICs */
3096
3097/* The Ethernet Type used for 802.1q tagged frames */
3098#define VLAN_ETHER_TYPE 0x8100
3099
3100static void set_8021q_mode(struct net_device *dev, int enable)
3101{
3102 struct vortex_private *vp = netdev_priv(dev);
3103 int mac_ctrl;
3104
3105 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3106 /* cyclone and tornado chipsets can recognize 802.1q
3107 * tagged frames and treat them correctly */
3108
3109 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3110 if (enable)
3111 max_pkt_size += 4; /* 802.1Q VLAN tag */
3112
3113 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3114
3115 /* set VlanEtherType to let the hardware checksumming
3116 treat tagged frames correctly */
3117 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3118 } else {
3119 /* on older cards we have to enable large frames */
3120
3121 vp->large_frames = dev->mtu > 1500 || enable;
3122
3123 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3124 if (vp->large_frames)
3125 mac_ctrl |= 0x40;
3126 else
3127 mac_ctrl &= ~0x40;
3128 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3129 }
3130}
3131#else
3132
3133static void set_8021q_mode(struct net_device *dev, int enable)
3134{
3135}
3136
3137
3138#endif
3139
3140/* MII transceiver control section.
3141 Read and write the MII registers using software-generated serial
3142 MDIO protocol. See the MII specifications or DP83840A data sheet
3143 for details. */
3144
3145/* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3146 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3147 "overclocking" issues. */
3148static void mdio_delay(struct vortex_private *vp)
3149{
3150 window_read32(vp, 4, Wn4_PhysicalMgmt);
3151}
3152
3153#define MDIO_SHIFT_CLK 0x01
3154#define MDIO_DIR_WRITE 0x04
3155#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3156#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3157#define MDIO_DATA_READ 0x02
3158#define MDIO_ENB_IN 0x00
3159
3160/* Generate the preamble required for initial synchronization and
3161 a few older transceivers. */
3162static void mdio_sync(struct vortex_private *vp, int bits)
3163{
3164 /* Establish sync by sending at least 32 logic ones. */
3165 while (-- bits >= 0) {
3166 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3167 mdio_delay(vp);
3168 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3169 4, Wn4_PhysicalMgmt);
3170 mdio_delay(vp);
3171 }
3172}
3173
3174static int mdio_read(struct net_device *dev, int phy_id, int location)
3175{
3176 int i;
3177 struct vortex_private *vp = netdev_priv(dev);
3178 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3179 unsigned int retval = 0;
3180
3181 spin_lock_bh(&vp->mii_lock);
3182
3183 if (mii_preamble_required)
3184 mdio_sync(vp, 32);
3185
3186 /* Shift the read command bits out. */
3187 for (i = 14; i >= 0; i--) {
3188 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3189 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3190 mdio_delay(vp);
3191 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3192 4, Wn4_PhysicalMgmt);
3193 mdio_delay(vp);
3194 }
3195 /* Read the two transition, 16 data, and wire-idle bits. */
3196 for (i = 19; i > 0; i--) {
3197 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3198 mdio_delay(vp);
3199 retval = (retval << 1) |
3200 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3201 MDIO_DATA_READ) ? 1 : 0);
3202 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3203 4, Wn4_PhysicalMgmt);
3204 mdio_delay(vp);
3205 }
3206
3207 spin_unlock_bh(&vp->mii_lock);
3208
3209 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3210}
3211
3212static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3213{
3214 struct vortex_private *vp = netdev_priv(dev);
3215 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3216 int i;
3217
3218 spin_lock_bh(&vp->mii_lock);
3219
3220 if (mii_preamble_required)
3221 mdio_sync(vp, 32);
3222
3223 /* Shift the command bits out. */
3224 for (i = 31; i >= 0; i--) {
3225 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3226 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3227 mdio_delay(vp);
3228 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3229 4, Wn4_PhysicalMgmt);
3230 mdio_delay(vp);
3231 }
3232 /* Leave the interface idle. */
3233 for (i = 1; i >= 0; i--) {
3234 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3235 mdio_delay(vp);
3236 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3237 4, Wn4_PhysicalMgmt);
3238 mdio_delay(vp);
3239 }
3240
3241 spin_unlock_bh(&vp->mii_lock);
3242}
3243
3244/* ACPI: Advanced Configuration and Power Interface. */
3245/* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3246static void acpi_set_WOL(struct net_device *dev)
3247{
3248 struct vortex_private *vp = netdev_priv(dev);
3249 void __iomem *ioaddr = vp->ioaddr;
3250
3251 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3252
3253 if (vp->enable_wol) {
3254 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3255 window_write16(vp, 2, 7, 0x0c);
3256 /* The RxFilter must accept the WOL frames. */
3257 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3258 iowrite16(RxEnable, ioaddr + EL3_CMD);
3259
3260 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3261 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3262
3263 vp->enable_wol = 0;
3264 return;
3265 }
3266
3267 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3268 return;
3269
3270 /* Change the power state to D3; RxEnable doesn't take effect. */
3271 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3272 }
3273}
3274
3275
3276static void vortex_remove_one(struct pci_dev *pdev)
3277{
3278 struct net_device *dev = pci_get_drvdata(pdev);
3279 struct vortex_private *vp;
3280
3281 if (!dev) {
3282 pr_err("vortex_remove_one called for Compaq device!\n");
3283 BUG();
3284 }
3285
3286 vp = netdev_priv(dev);
3287
3288 if (vp->cb_fn_base)
3289 pci_iounmap(pdev, vp->cb_fn_base);
3290
3291 unregister_netdev(dev);
3292
3293 pci_set_power_state(pdev, PCI_D0); /* Go active */
3294 if (vp->pm_state_valid)
3295 pci_restore_state(pdev);
3296 pci_disable_device(pdev);
3297
3298 /* Should really use issue_and_wait() here */
3299 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3300 vp->ioaddr + EL3_CMD);
3301
3302 pci_iounmap(pdev, vp->ioaddr);
3303
3304 pci_free_consistent(pdev,
3305 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3306 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3307 vp->rx_ring,
3308 vp->rx_ring_dma);
3309
3310 pci_release_regions(pdev);
3311
3312 free_netdev(dev);
3313}
3314
3315
3316static struct pci_driver vortex_driver = {
3317 .name = "3c59x",
3318 .probe = vortex_init_one,
3319 .remove = vortex_remove_one,
3320 .id_table = vortex_pci_tbl,
3321 .driver.pm = VORTEX_PM_OPS,
3322};
3323
3324
3325static int vortex_have_pci;
3326static int vortex_have_eisa;
3327
3328
3329static int __init vortex_init(void)
3330{
3331 int pci_rc, eisa_rc;
3332
3333 pci_rc = pci_register_driver(&vortex_driver);
3334 eisa_rc = vortex_eisa_init();
3335
3336 if (pci_rc == 0)
3337 vortex_have_pci = 1;
3338 if (eisa_rc > 0)
3339 vortex_have_eisa = 1;
3340
3341 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3342}
3343
3344
3345static void __exit vortex_eisa_cleanup(void)
3346{
3347 void __iomem *ioaddr;
3348
3349#ifdef CONFIG_EISA
3350 /* Take care of the EISA devices */
3351 eisa_driver_unregister(&vortex_eisa_driver);
3352#endif
3353
3354 if (compaq_net_device) {
3355 ioaddr = ioport_map(compaq_net_device->base_addr,
3356 VORTEX_TOTAL_SIZE);
3357
3358 unregister_netdev(compaq_net_device);
3359 iowrite16(TotalReset, ioaddr + EL3_CMD);
3360 release_region(compaq_net_device->base_addr,
3361 VORTEX_TOTAL_SIZE);
3362
3363 free_netdev(compaq_net_device);
3364 }
3365}
3366
3367
3368static void __exit vortex_cleanup(void)
3369{
3370 if (vortex_have_pci)
3371 pci_unregister_driver(&vortex_driver);
3372 if (vortex_have_eisa)
3373 vortex_eisa_cleanup();
3374}
3375
3376
3377module_init(vortex_init);
3378module_exit(vortex_cleanup);