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1/*
2 * Header file for Samsung DP (Display Port) interface driver.
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef _EXYNOS_DP_CORE_H
14#define _EXYNOS_DP_CORE_H
15
16#include <drm/drm_crtc.h>
17#include <drm/drm_dp_helper.h>
18#include <drm/exynos_drm.h>
19#include <video/videomode.h>
20
21#include "exynos_drm_drv.h"
22
23#define DP_TIMEOUT_LOOP_COUNT 100
24#define MAX_CR_LOOP 5
25#define MAX_EQ_LOOP 5
26
27enum link_rate_type {
28 LINK_RATE_1_62GBPS = 0x06,
29 LINK_RATE_2_70GBPS = 0x0a
30};
31
32enum link_lane_count_type {
33 LANE_COUNT1 = 1,
34 LANE_COUNT2 = 2,
35 LANE_COUNT4 = 4
36};
37
38enum link_training_state {
39 START,
40 CLOCK_RECOVERY,
41 EQUALIZER_TRAINING,
42 FINISHED,
43 FAILED
44};
45
46enum voltage_swing_level {
47 VOLTAGE_LEVEL_0,
48 VOLTAGE_LEVEL_1,
49 VOLTAGE_LEVEL_2,
50 VOLTAGE_LEVEL_3,
51};
52
53enum pre_emphasis_level {
54 PRE_EMPHASIS_LEVEL_0,
55 PRE_EMPHASIS_LEVEL_1,
56 PRE_EMPHASIS_LEVEL_2,
57 PRE_EMPHASIS_LEVEL_3,
58};
59
60enum pattern_set {
61 PRBS7,
62 D10_2,
63 TRAINING_PTN1,
64 TRAINING_PTN2,
65 DP_NONE
66};
67
68enum color_space {
69 COLOR_RGB,
70 COLOR_YCBCR422,
71 COLOR_YCBCR444
72};
73
74enum color_depth {
75 COLOR_6,
76 COLOR_8,
77 COLOR_10,
78 COLOR_12
79};
80
81enum color_coefficient {
82 COLOR_YCBCR601,
83 COLOR_YCBCR709
84};
85
86enum dynamic_range {
87 VESA,
88 CEA
89};
90
91enum pll_status {
92 PLL_UNLOCKED,
93 PLL_LOCKED
94};
95
96enum clock_recovery_m_value_type {
97 CALCULATED_M,
98 REGISTER_M
99};
100
101enum video_timing_recognition_type {
102 VIDEO_TIMING_FROM_CAPTURE,
103 VIDEO_TIMING_FROM_REGISTER
104};
105
106enum analog_power_block {
107 AUX_BLOCK,
108 CH0_BLOCK,
109 CH1_BLOCK,
110 CH2_BLOCK,
111 CH3_BLOCK,
112 ANALOG_TOTAL,
113 POWER_ALL
114};
115
116enum dp_irq_type {
117 DP_IRQ_TYPE_HP_CABLE_IN,
118 DP_IRQ_TYPE_HP_CABLE_OUT,
119 DP_IRQ_TYPE_HP_CHANGE,
120 DP_IRQ_TYPE_UNKNOWN,
121};
122
123struct video_info {
124 char *name;
125
126 bool h_sync_polarity;
127 bool v_sync_polarity;
128 bool interlaced;
129
130 enum color_space color_space;
131 enum dynamic_range dynamic_range;
132 enum color_coefficient ycbcr_coeff;
133 enum color_depth color_depth;
134
135 enum link_rate_type link_rate;
136 enum link_lane_count_type lane_count;
137};
138
139struct link_train {
140 int eq_loop;
141 int cr_loop[4];
142
143 u8 link_rate;
144 u8 lane_count;
145 u8 training_lane[4];
146
147 enum link_training_state lt_state;
148};
149
150struct exynos_dp_device {
151 struct drm_encoder encoder;
152 struct device *dev;
153 struct drm_device *drm_dev;
154 struct drm_connector connector;
155 struct drm_panel *panel;
156 struct drm_bridge *bridge;
157 struct drm_bridge *ptn_bridge;
158 struct clk *clock;
159 unsigned int irq;
160 void __iomem *reg_base;
161
162 struct video_info *video_info;
163 struct link_train link_train;
164 struct work_struct hotplug_work;
165 struct phy *phy;
166 int dpms_mode;
167 int hpd_gpio;
168 struct videomode vm;
169};
170
171/* exynos_dp_reg.c */
172void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
173void exynos_dp_stop_video(struct exynos_dp_device *dp);
174void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
175void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
176void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
177void exynos_dp_reset(struct exynos_dp_device *dp);
178void exynos_dp_swreset(struct exynos_dp_device *dp);
179void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
180enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
181void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
182void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
183 enum analog_power_block block,
184 bool enable);
185void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
186void exynos_dp_init_hpd(struct exynos_dp_device *dp);
187enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
188void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
189void exynos_dp_reset_aux(struct exynos_dp_device *dp);
190void exynos_dp_init_aux(struct exynos_dp_device *dp);
191int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
192void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
193int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
194int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
195 unsigned int reg_addr,
196 unsigned char data);
197int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
198 unsigned int reg_addr,
199 unsigned char *data);
200int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
201 unsigned int reg_addr,
202 unsigned int count,
203 unsigned char data[]);
204int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
205 unsigned int reg_addr,
206 unsigned int count,
207 unsigned char data[]);
208int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
209 unsigned int device_addr,
210 unsigned int reg_addr);
211int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
212 unsigned int device_addr,
213 unsigned int reg_addr,
214 unsigned int *data);
215int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
216 unsigned int device_addr,
217 unsigned int reg_addr,
218 unsigned int count,
219 unsigned char edid[]);
220void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
221void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
222void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
223void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
224void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
225void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
226 enum pattern_set pattern);
227void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
228void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
229void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
230void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
231void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
232 u32 training_lane);
233void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
234 u32 training_lane);
235void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
236 u32 training_lane);
237void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
238 u32 training_lane);
239u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
240u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
241u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
242u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
243void exynos_dp_reset_macro(struct exynos_dp_device *dp);
244void exynos_dp_init_video(struct exynos_dp_device *dp);
245
246void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
247int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
248void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
249 enum clock_recovery_m_value_type type,
250 u32 m_value,
251 u32 n_value);
252void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
253void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
254void exynos_dp_start_video(struct exynos_dp_device *dp);
255int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
256void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
257void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
258void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
259
260/* I2C EDID Chip ID, Slave Address */
261#define I2C_EDID_DEVICE_ADDR 0x50
262#define I2C_E_EDID_DEVICE_ADDR 0x30
263
264#define EDID_BLOCK_LENGTH 0x80
265#define EDID_HEADER_PATTERN 0x00
266#define EDID_EXTENSION_FLAG 0x7e
267#define EDID_CHECKSUM 0x7f
268
269/* DP_MAX_LANE_COUNT */
270#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
271#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
272
273/* DP_LANE_COUNT_SET */
274#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
275
276/* DP_TRAINING_LANE0_SET */
277#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
278#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
279#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
280#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
281
282#endif /* _EXYNOS_DP_CORE_H */