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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/console.h>
29#include <linux/slab.h>
30#include <linux/debugfs.h>
31#include <drm/drmP.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/amdgpu_drm.h>
34#include <linux/vgaarb.h>
35#include <linux/vga_switcheroo.h>
36#include <linux/efi.h>
37#include "amdgpu.h"
38#include "amdgpu_i2c.h"
39#include "atom.h"
40#include "amdgpu_atombios.h"
41#include "amd_pcie.h"
42#ifdef CONFIG_DRM_AMDGPU_CIK
43#include "cik.h"
44#endif
45#include "vi.h"
46#include "bif/bif_4_1_d.h"
47
48static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
49static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
50
51static const char *amdgpu_asic_name[] = {
52 "BONAIRE",
53 "KAVERI",
54 "KABINI",
55 "HAWAII",
56 "MULLINS",
57 "TOPAZ",
58 "TONGA",
59 "FIJI",
60 "CARRIZO",
61 "STONEY",
62 "LAST",
63};
64
65bool amdgpu_device_is_px(struct drm_device *dev)
66{
67 struct amdgpu_device *adev = dev->dev_private;
68
69 if (adev->flags & AMD_IS_PX)
70 return true;
71 return false;
72}
73
74/*
75 * MMIO register access helper functions.
76 */
77uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
78 bool always_indirect)
79{
80 if ((reg * 4) < adev->rmmio_size && !always_indirect)
81 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
82 else {
83 unsigned long flags;
84 uint32_t ret;
85
86 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
87 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
88 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
89 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
90
91 return ret;
92 }
93}
94
95void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
96 bool always_indirect)
97{
98 if ((reg * 4) < adev->rmmio_size && !always_indirect)
99 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
100 else {
101 unsigned long flags;
102
103 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
104 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
105 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
106 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
107 }
108}
109
110u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
111{
112 if ((reg * 4) < adev->rio_mem_size)
113 return ioread32(adev->rio_mem + (reg * 4));
114 else {
115 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
116 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
117 }
118}
119
120void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
121{
122
123 if ((reg * 4) < adev->rio_mem_size)
124 iowrite32(v, adev->rio_mem + (reg * 4));
125 else {
126 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
127 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
128 }
129}
130
131/**
132 * amdgpu_mm_rdoorbell - read a doorbell dword
133 *
134 * @adev: amdgpu_device pointer
135 * @index: doorbell index
136 *
137 * Returns the value in the doorbell aperture at the
138 * requested doorbell index (CIK).
139 */
140u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
141{
142 if (index < adev->doorbell.num_doorbells) {
143 return readl(adev->doorbell.ptr + index);
144 } else {
145 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
146 return 0;
147 }
148}
149
150/**
151 * amdgpu_mm_wdoorbell - write a doorbell dword
152 *
153 * @adev: amdgpu_device pointer
154 * @index: doorbell index
155 * @v: value to write
156 *
157 * Writes @v to the doorbell aperture at the
158 * requested doorbell index (CIK).
159 */
160void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
161{
162 if (index < adev->doorbell.num_doorbells) {
163 writel(v, adev->doorbell.ptr + index);
164 } else {
165 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
166 }
167}
168
169/**
170 * amdgpu_invalid_rreg - dummy reg read function
171 *
172 * @adev: amdgpu device pointer
173 * @reg: offset of register
174 *
175 * Dummy register read function. Used for register blocks
176 * that certain asics don't have (all asics).
177 * Returns the value in the register.
178 */
179static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
180{
181 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
182 BUG();
183 return 0;
184}
185
186/**
187 * amdgpu_invalid_wreg - dummy reg write function
188 *
189 * @adev: amdgpu device pointer
190 * @reg: offset of register
191 * @v: value to write to the register
192 *
193 * Dummy register read function. Used for register blocks
194 * that certain asics don't have (all asics).
195 */
196static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
197{
198 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
199 reg, v);
200 BUG();
201}
202
203/**
204 * amdgpu_block_invalid_rreg - dummy reg read function
205 *
206 * @adev: amdgpu device pointer
207 * @block: offset of instance
208 * @reg: offset of register
209 *
210 * Dummy register read function. Used for register blocks
211 * that certain asics don't have (all asics).
212 * Returns the value in the register.
213 */
214static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
215 uint32_t block, uint32_t reg)
216{
217 DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
218 reg, block);
219 BUG();
220 return 0;
221}
222
223/**
224 * amdgpu_block_invalid_wreg - dummy reg write function
225 *
226 * @adev: amdgpu device pointer
227 * @block: offset of instance
228 * @reg: offset of register
229 * @v: value to write to the register
230 *
231 * Dummy register read function. Used for register blocks
232 * that certain asics don't have (all asics).
233 */
234static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
235 uint32_t block,
236 uint32_t reg, uint32_t v)
237{
238 DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
239 reg, block, v);
240 BUG();
241}
242
243static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
244{
245 int r;
246
247 if (adev->vram_scratch.robj == NULL) {
248 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
249 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
250 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
251 NULL, NULL, &adev->vram_scratch.robj);
252 if (r) {
253 return r;
254 }
255 }
256
257 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
258 if (unlikely(r != 0))
259 return r;
260 r = amdgpu_bo_pin(adev->vram_scratch.robj,
261 AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
262 if (r) {
263 amdgpu_bo_unreserve(adev->vram_scratch.robj);
264 return r;
265 }
266 r = amdgpu_bo_kmap(adev->vram_scratch.robj,
267 (void **)&adev->vram_scratch.ptr);
268 if (r)
269 amdgpu_bo_unpin(adev->vram_scratch.robj);
270 amdgpu_bo_unreserve(adev->vram_scratch.robj);
271
272 return r;
273}
274
275static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
276{
277 int r;
278
279 if (adev->vram_scratch.robj == NULL) {
280 return;
281 }
282 r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
283 if (likely(r == 0)) {
284 amdgpu_bo_kunmap(adev->vram_scratch.robj);
285 amdgpu_bo_unpin(adev->vram_scratch.robj);
286 amdgpu_bo_unreserve(adev->vram_scratch.robj);
287 }
288 amdgpu_bo_unref(&adev->vram_scratch.robj);
289}
290
291/**
292 * amdgpu_program_register_sequence - program an array of registers.
293 *
294 * @adev: amdgpu_device pointer
295 * @registers: pointer to the register array
296 * @array_size: size of the register array
297 *
298 * Programs an array or registers with and and or masks.
299 * This is a helper for setting golden registers.
300 */
301void amdgpu_program_register_sequence(struct amdgpu_device *adev,
302 const u32 *registers,
303 const u32 array_size)
304{
305 u32 tmp, reg, and_mask, or_mask;
306 int i;
307
308 if (array_size % 3)
309 return;
310
311 for (i = 0; i < array_size; i +=3) {
312 reg = registers[i + 0];
313 and_mask = registers[i + 1];
314 or_mask = registers[i + 2];
315
316 if (and_mask == 0xffffffff) {
317 tmp = or_mask;
318 } else {
319 tmp = RREG32(reg);
320 tmp &= ~and_mask;
321 tmp |= or_mask;
322 }
323 WREG32(reg, tmp);
324 }
325}
326
327void amdgpu_pci_config_reset(struct amdgpu_device *adev)
328{
329 pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
330}
331
332/*
333 * GPU doorbell aperture helpers function.
334 */
335/**
336 * amdgpu_doorbell_init - Init doorbell driver information.
337 *
338 * @adev: amdgpu_device pointer
339 *
340 * Init doorbell driver information (CIK)
341 * Returns 0 on success, error on failure.
342 */
343static int amdgpu_doorbell_init(struct amdgpu_device *adev)
344{
345 /* doorbell bar mapping */
346 adev->doorbell.base = pci_resource_start(adev->pdev, 2);
347 adev->doorbell.size = pci_resource_len(adev->pdev, 2);
348
349 adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
350 AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
351 if (adev->doorbell.num_doorbells == 0)
352 return -EINVAL;
353
354 adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
355 if (adev->doorbell.ptr == NULL) {
356 return -ENOMEM;
357 }
358 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
359 DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
360
361 return 0;
362}
363
364/**
365 * amdgpu_doorbell_fini - Tear down doorbell driver information.
366 *
367 * @adev: amdgpu_device pointer
368 *
369 * Tear down doorbell driver information (CIK)
370 */
371static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
372{
373 iounmap(adev->doorbell.ptr);
374 adev->doorbell.ptr = NULL;
375}
376
377/**
378 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
379 * setup amdkfd
380 *
381 * @adev: amdgpu_device pointer
382 * @aperture_base: output returning doorbell aperture base physical address
383 * @aperture_size: output returning doorbell aperture size in bytes
384 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
385 *
386 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
387 * takes doorbells required for its own rings and reports the setup to amdkfd.
388 * amdgpu reserved doorbells are at the start of the doorbell aperture.
389 */
390void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
391 phys_addr_t *aperture_base,
392 size_t *aperture_size,
393 size_t *start_offset)
394{
395 /*
396 * The first num_doorbells are used by amdgpu.
397 * amdkfd takes whatever's left in the aperture.
398 */
399 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
400 *aperture_base = adev->doorbell.base;
401 *aperture_size = adev->doorbell.size;
402 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
403 } else {
404 *aperture_base = 0;
405 *aperture_size = 0;
406 *start_offset = 0;
407 }
408}
409
410/*
411 * amdgpu_wb_*()
412 * Writeback is the the method by which the the GPU updates special pages
413 * in memory with the status of certain GPU events (fences, ring pointers,
414 * etc.).
415 */
416
417/**
418 * amdgpu_wb_fini - Disable Writeback and free memory
419 *
420 * @adev: amdgpu_device pointer
421 *
422 * Disables Writeback and frees the Writeback memory (all asics).
423 * Used at driver shutdown.
424 */
425static void amdgpu_wb_fini(struct amdgpu_device *adev)
426{
427 if (adev->wb.wb_obj) {
428 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
429 amdgpu_bo_kunmap(adev->wb.wb_obj);
430 amdgpu_bo_unpin(adev->wb.wb_obj);
431 amdgpu_bo_unreserve(adev->wb.wb_obj);
432 }
433 amdgpu_bo_unref(&adev->wb.wb_obj);
434 adev->wb.wb = NULL;
435 adev->wb.wb_obj = NULL;
436 }
437}
438
439/**
440 * amdgpu_wb_init- Init Writeback driver info and allocate memory
441 *
442 * @adev: amdgpu_device pointer
443 *
444 * Disables Writeback and frees the Writeback memory (all asics).
445 * Used at driver startup.
446 * Returns 0 on success or an -error on failure.
447 */
448static int amdgpu_wb_init(struct amdgpu_device *adev)
449{
450 int r;
451
452 if (adev->wb.wb_obj == NULL) {
453 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
454 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
455 &adev->wb.wb_obj);
456 if (r) {
457 dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
458 return r;
459 }
460 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
461 if (unlikely(r != 0)) {
462 amdgpu_wb_fini(adev);
463 return r;
464 }
465 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
466 &adev->wb.gpu_addr);
467 if (r) {
468 amdgpu_bo_unreserve(adev->wb.wb_obj);
469 dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
470 amdgpu_wb_fini(adev);
471 return r;
472 }
473 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
474 amdgpu_bo_unreserve(adev->wb.wb_obj);
475 if (r) {
476 dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
477 amdgpu_wb_fini(adev);
478 return r;
479 }
480
481 adev->wb.num_wb = AMDGPU_MAX_WB;
482 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
483
484 /* clear wb memory */
485 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
486 }
487
488 return 0;
489}
490
491/**
492 * amdgpu_wb_get - Allocate a wb entry
493 *
494 * @adev: amdgpu_device pointer
495 * @wb: wb index
496 *
497 * Allocate a wb slot for use by the driver (all asics).
498 * Returns 0 on success or -EINVAL on failure.
499 */
500int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
501{
502 unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
503 if (offset < adev->wb.num_wb) {
504 __set_bit(offset, adev->wb.used);
505 *wb = offset;
506 return 0;
507 } else {
508 return -EINVAL;
509 }
510}
511
512/**
513 * amdgpu_wb_free - Free a wb entry
514 *
515 * @adev: amdgpu_device pointer
516 * @wb: wb index
517 *
518 * Free a wb slot allocated for use by the driver (all asics)
519 */
520void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
521{
522 if (wb < adev->wb.num_wb)
523 __clear_bit(wb, adev->wb.used);
524}
525
526/**
527 * amdgpu_vram_location - try to find VRAM location
528 * @adev: amdgpu device structure holding all necessary informations
529 * @mc: memory controller structure holding memory informations
530 * @base: base address at which to put VRAM
531 *
532 * Function will place try to place VRAM at base address provided
533 * as parameter (which is so far either PCI aperture address or
534 * for IGP TOM base address).
535 *
536 * If there is not enough space to fit the unvisible VRAM in the 32bits
537 * address space then we limit the VRAM size to the aperture.
538 *
539 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
540 * this shouldn't be a problem as we are using the PCI aperture as a reference.
541 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
542 * not IGP.
543 *
544 * Note: we use mc_vram_size as on some board we need to program the mc to
545 * cover the whole aperture even if VRAM size is inferior to aperture size
546 * Novell bug 204882 + along with lots of ubuntu ones
547 *
548 * Note: when limiting vram it's safe to overwritte real_vram_size because
549 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
550 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
551 * ones)
552 *
553 * Note: IGP TOM addr should be the same as the aperture addr, we don't
554 * explicitly check for that thought.
555 *
556 * FIXME: when reducing VRAM size align new size on power of 2.
557 */
558void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
559{
560 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
561
562 mc->vram_start = base;
563 if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
564 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
565 mc->real_vram_size = mc->aper_size;
566 mc->mc_vram_size = mc->aper_size;
567 }
568 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
569 if (limit && limit < mc->real_vram_size)
570 mc->real_vram_size = limit;
571 dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
572 mc->mc_vram_size >> 20, mc->vram_start,
573 mc->vram_end, mc->real_vram_size >> 20);
574}
575
576/**
577 * amdgpu_gtt_location - try to find GTT location
578 * @adev: amdgpu device structure holding all necessary informations
579 * @mc: memory controller structure holding memory informations
580 *
581 * Function will place try to place GTT before or after VRAM.
582 *
583 * If GTT size is bigger than space left then we ajust GTT size.
584 * Thus function will never fails.
585 *
586 * FIXME: when reducing GTT size align new size on power of 2.
587 */
588void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
589{
590 u64 size_af, size_bf;
591
592 size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
593 size_bf = mc->vram_start & ~mc->gtt_base_align;
594 if (size_bf > size_af) {
595 if (mc->gtt_size > size_bf) {
596 dev_warn(adev->dev, "limiting GTT\n");
597 mc->gtt_size = size_bf;
598 }
599 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
600 } else {
601 if (mc->gtt_size > size_af) {
602 dev_warn(adev->dev, "limiting GTT\n");
603 mc->gtt_size = size_af;
604 }
605 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
606 }
607 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
608 dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
609 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
610}
611
612/*
613 * GPU helpers function.
614 */
615/**
616 * amdgpu_card_posted - check if the hw has already been initialized
617 *
618 * @adev: amdgpu_device pointer
619 *
620 * Check if the asic has been initialized (all asics).
621 * Used at driver startup.
622 * Returns true if initialized or false if not.
623 */
624bool amdgpu_card_posted(struct amdgpu_device *adev)
625{
626 uint32_t reg;
627
628 /* then check MEM_SIZE, in case the crtcs are off */
629 reg = RREG32(mmCONFIG_MEMSIZE);
630
631 if (reg)
632 return true;
633
634 return false;
635
636}
637
638/**
639 * amdgpu_dummy_page_init - init dummy page used by the driver
640 *
641 * @adev: amdgpu_device pointer
642 *
643 * Allocate the dummy page used by the driver (all asics).
644 * This dummy page is used by the driver as a filler for gart entries
645 * when pages are taken out of the GART
646 * Returns 0 on sucess, -ENOMEM on failure.
647 */
648int amdgpu_dummy_page_init(struct amdgpu_device *adev)
649{
650 if (adev->dummy_page.page)
651 return 0;
652 adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
653 if (adev->dummy_page.page == NULL)
654 return -ENOMEM;
655 adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
656 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
657 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
658 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
659 __free_page(adev->dummy_page.page);
660 adev->dummy_page.page = NULL;
661 return -ENOMEM;
662 }
663 return 0;
664}
665
666/**
667 * amdgpu_dummy_page_fini - free dummy page used by the driver
668 *
669 * @adev: amdgpu_device pointer
670 *
671 * Frees the dummy page used by the driver (all asics).
672 */
673void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
674{
675 if (adev->dummy_page.page == NULL)
676 return;
677 pci_unmap_page(adev->pdev, adev->dummy_page.addr,
678 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
679 __free_page(adev->dummy_page.page);
680 adev->dummy_page.page = NULL;
681}
682
683
684/* ATOM accessor methods */
685/*
686 * ATOM is an interpreted byte code stored in tables in the vbios. The
687 * driver registers callbacks to access registers and the interpreter
688 * in the driver parses the tables and executes then to program specific
689 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
690 * atombios.h, and atom.c
691 */
692
693/**
694 * cail_pll_read - read PLL register
695 *
696 * @info: atom card_info pointer
697 * @reg: PLL register offset
698 *
699 * Provides a PLL register accessor for the atom interpreter (r4xx+).
700 * Returns the value of the PLL register.
701 */
702static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
703{
704 return 0;
705}
706
707/**
708 * cail_pll_write - write PLL register
709 *
710 * @info: atom card_info pointer
711 * @reg: PLL register offset
712 * @val: value to write to the pll register
713 *
714 * Provides a PLL register accessor for the atom interpreter (r4xx+).
715 */
716static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
717{
718
719}
720
721/**
722 * cail_mc_read - read MC (Memory Controller) register
723 *
724 * @info: atom card_info pointer
725 * @reg: MC register offset
726 *
727 * Provides an MC register accessor for the atom interpreter (r4xx+).
728 * Returns the value of the MC register.
729 */
730static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
731{
732 return 0;
733}
734
735/**
736 * cail_mc_write - write MC (Memory Controller) register
737 *
738 * @info: atom card_info pointer
739 * @reg: MC register offset
740 * @val: value to write to the pll register
741 *
742 * Provides a MC register accessor for the atom interpreter (r4xx+).
743 */
744static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
745{
746
747}
748
749/**
750 * cail_reg_write - write MMIO register
751 *
752 * @info: atom card_info pointer
753 * @reg: MMIO register offset
754 * @val: value to write to the pll register
755 *
756 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
757 */
758static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
759{
760 struct amdgpu_device *adev = info->dev->dev_private;
761
762 WREG32(reg, val);
763}
764
765/**
766 * cail_reg_read - read MMIO register
767 *
768 * @info: atom card_info pointer
769 * @reg: MMIO register offset
770 *
771 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
772 * Returns the value of the MMIO register.
773 */
774static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
775{
776 struct amdgpu_device *adev = info->dev->dev_private;
777 uint32_t r;
778
779 r = RREG32(reg);
780 return r;
781}
782
783/**
784 * cail_ioreg_write - write IO register
785 *
786 * @info: atom card_info pointer
787 * @reg: IO register offset
788 * @val: value to write to the pll register
789 *
790 * Provides a IO register accessor for the atom interpreter (r4xx+).
791 */
792static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
793{
794 struct amdgpu_device *adev = info->dev->dev_private;
795
796 WREG32_IO(reg, val);
797}
798
799/**
800 * cail_ioreg_read - read IO register
801 *
802 * @info: atom card_info pointer
803 * @reg: IO register offset
804 *
805 * Provides an IO register accessor for the atom interpreter (r4xx+).
806 * Returns the value of the IO register.
807 */
808static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
809{
810 struct amdgpu_device *adev = info->dev->dev_private;
811 uint32_t r;
812
813 r = RREG32_IO(reg);
814 return r;
815}
816
817/**
818 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
819 *
820 * @adev: amdgpu_device pointer
821 *
822 * Frees the driver info and register access callbacks for the ATOM
823 * interpreter (r4xx+).
824 * Called at driver shutdown.
825 */
826static void amdgpu_atombios_fini(struct amdgpu_device *adev)
827{
828 if (adev->mode_info.atom_context)
829 kfree(adev->mode_info.atom_context->scratch);
830 kfree(adev->mode_info.atom_context);
831 adev->mode_info.atom_context = NULL;
832 kfree(adev->mode_info.atom_card_info);
833 adev->mode_info.atom_card_info = NULL;
834}
835
836/**
837 * amdgpu_atombios_init - init the driver info and callbacks for atombios
838 *
839 * @adev: amdgpu_device pointer
840 *
841 * Initializes the driver info and register access callbacks for the
842 * ATOM interpreter (r4xx+).
843 * Returns 0 on sucess, -ENOMEM on failure.
844 * Called at driver startup.
845 */
846static int amdgpu_atombios_init(struct amdgpu_device *adev)
847{
848 struct card_info *atom_card_info =
849 kzalloc(sizeof(struct card_info), GFP_KERNEL);
850
851 if (!atom_card_info)
852 return -ENOMEM;
853
854 adev->mode_info.atom_card_info = atom_card_info;
855 atom_card_info->dev = adev->ddev;
856 atom_card_info->reg_read = cail_reg_read;
857 atom_card_info->reg_write = cail_reg_write;
858 /* needed for iio ops */
859 if (adev->rio_mem) {
860 atom_card_info->ioreg_read = cail_ioreg_read;
861 atom_card_info->ioreg_write = cail_ioreg_write;
862 } else {
863 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
864 atom_card_info->ioreg_read = cail_reg_read;
865 atom_card_info->ioreg_write = cail_reg_write;
866 }
867 atom_card_info->mc_read = cail_mc_read;
868 atom_card_info->mc_write = cail_mc_write;
869 atom_card_info->pll_read = cail_pll_read;
870 atom_card_info->pll_write = cail_pll_write;
871
872 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
873 if (!adev->mode_info.atom_context) {
874 amdgpu_atombios_fini(adev);
875 return -ENOMEM;
876 }
877
878 mutex_init(&adev->mode_info.atom_context->mutex);
879 amdgpu_atombios_scratch_regs_init(adev);
880 amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
881 return 0;
882}
883
884/* if we get transitioned to only one device, take VGA back */
885/**
886 * amdgpu_vga_set_decode - enable/disable vga decode
887 *
888 * @cookie: amdgpu_device pointer
889 * @state: enable/disable vga decode
890 *
891 * Enable/disable vga decode (all asics).
892 * Returns VGA resource flags.
893 */
894static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
895{
896 struct amdgpu_device *adev = cookie;
897 amdgpu_asic_set_vga_state(adev, state);
898 if (state)
899 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
900 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
901 else
902 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
903}
904
905/**
906 * amdgpu_check_pot_argument - check that argument is a power of two
907 *
908 * @arg: value to check
909 *
910 * Validates that a certain argument is a power of two (all asics).
911 * Returns true if argument is valid.
912 */
913static bool amdgpu_check_pot_argument(int arg)
914{
915 return (arg & (arg - 1)) == 0;
916}
917
918/**
919 * amdgpu_check_arguments - validate module params
920 *
921 * @adev: amdgpu_device pointer
922 *
923 * Validates certain module parameters and updates
924 * the associated values used by the driver (all asics).
925 */
926static void amdgpu_check_arguments(struct amdgpu_device *adev)
927{
928 if (amdgpu_sched_jobs < 4) {
929 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
930 amdgpu_sched_jobs);
931 amdgpu_sched_jobs = 4;
932 } else if (!amdgpu_check_pot_argument(amdgpu_sched_jobs)){
933 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
934 amdgpu_sched_jobs);
935 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
936 }
937
938 if (amdgpu_gart_size != -1) {
939 /* gtt size must be power of two and greater or equal to 32M */
940 if (amdgpu_gart_size < 32) {
941 dev_warn(adev->dev, "gart size (%d) too small\n",
942 amdgpu_gart_size);
943 amdgpu_gart_size = -1;
944 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
945 dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
946 amdgpu_gart_size);
947 amdgpu_gart_size = -1;
948 }
949 }
950
951 if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
952 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
953 amdgpu_vm_size);
954 amdgpu_vm_size = 8;
955 }
956
957 if (amdgpu_vm_size < 1) {
958 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
959 amdgpu_vm_size);
960 amdgpu_vm_size = 8;
961 }
962
963 /*
964 * Max GPUVM size for Cayman, SI and CI are 40 bits.
965 */
966 if (amdgpu_vm_size > 1024) {
967 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
968 amdgpu_vm_size);
969 amdgpu_vm_size = 8;
970 }
971
972 /* defines number of bits in page table versus page directory,
973 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
974 * page table and the remaining bits are in the page directory */
975 if (amdgpu_vm_block_size == -1) {
976
977 /* Total bits covered by PD + PTs */
978 unsigned bits = ilog2(amdgpu_vm_size) + 18;
979
980 /* Make sure the PD is 4K in size up to 8GB address space.
981 Above that split equal between PD and PTs */
982 if (amdgpu_vm_size <= 8)
983 amdgpu_vm_block_size = bits - 9;
984 else
985 amdgpu_vm_block_size = (bits + 3) / 2;
986
987 } else if (amdgpu_vm_block_size < 9) {
988 dev_warn(adev->dev, "VM page table size (%d) too small\n",
989 amdgpu_vm_block_size);
990 amdgpu_vm_block_size = 9;
991 }
992
993 if (amdgpu_vm_block_size > 24 ||
994 (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
995 dev_warn(adev->dev, "VM page table size (%d) too large\n",
996 amdgpu_vm_block_size);
997 amdgpu_vm_block_size = 9;
998 }
999}
1000
1001/**
1002 * amdgpu_switcheroo_set_state - set switcheroo state
1003 *
1004 * @pdev: pci dev pointer
1005 * @state: vga_switcheroo state
1006 *
1007 * Callback for the switcheroo driver. Suspends or resumes the
1008 * the asics before or after it is powered up using ACPI methods.
1009 */
1010static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1011{
1012 struct drm_device *dev = pci_get_drvdata(pdev);
1013
1014 if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1015 return;
1016
1017 if (state == VGA_SWITCHEROO_ON) {
1018 unsigned d3_delay = dev->pdev->d3_delay;
1019
1020 printk(KERN_INFO "amdgpu: switched on\n");
1021 /* don't suspend or resume card normally */
1022 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1023
1024 amdgpu_resume_kms(dev, true, true);
1025
1026 dev->pdev->d3_delay = d3_delay;
1027
1028 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1029 drm_kms_helper_poll_enable(dev);
1030 } else {
1031 printk(KERN_INFO "amdgpu: switched off\n");
1032 drm_kms_helper_poll_disable(dev);
1033 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1034 amdgpu_suspend_kms(dev, true, true);
1035 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1036 }
1037}
1038
1039/**
1040 * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1041 *
1042 * @pdev: pci dev pointer
1043 *
1044 * Callback for the switcheroo driver. Check of the switcheroo
1045 * state can be changed.
1046 * Returns true if the state can be changed, false if not.
1047 */
1048static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1049{
1050 struct drm_device *dev = pci_get_drvdata(pdev);
1051
1052 /*
1053 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1054 * locking inversion with the driver load path. And the access here is
1055 * completely racy anyway. So don't bother with locking for now.
1056 */
1057 return dev->open_count == 0;
1058}
1059
1060static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1061 .set_gpu_state = amdgpu_switcheroo_set_state,
1062 .reprobe = NULL,
1063 .can_switch = amdgpu_switcheroo_can_switch,
1064};
1065
1066int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1067 enum amd_ip_block_type block_type,
1068 enum amd_clockgating_state state)
1069{
1070 int i, r = 0;
1071
1072 for (i = 0; i < adev->num_ip_blocks; i++) {
1073 if (adev->ip_blocks[i].type == block_type) {
1074 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1075 state);
1076 if (r)
1077 return r;
1078 }
1079 }
1080 return r;
1081}
1082
1083int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1084 enum amd_ip_block_type block_type,
1085 enum amd_powergating_state state)
1086{
1087 int i, r = 0;
1088
1089 for (i = 0; i < adev->num_ip_blocks; i++) {
1090 if (adev->ip_blocks[i].type == block_type) {
1091 r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1092 state);
1093 if (r)
1094 return r;
1095 }
1096 }
1097 return r;
1098}
1099
1100const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1101 struct amdgpu_device *adev,
1102 enum amd_ip_block_type type)
1103{
1104 int i;
1105
1106 for (i = 0; i < adev->num_ip_blocks; i++)
1107 if (adev->ip_blocks[i].type == type)
1108 return &adev->ip_blocks[i];
1109
1110 return NULL;
1111}
1112
1113/**
1114 * amdgpu_ip_block_version_cmp
1115 *
1116 * @adev: amdgpu_device pointer
1117 * @type: enum amd_ip_block_type
1118 * @major: major version
1119 * @minor: minor version
1120 *
1121 * return 0 if equal or greater
1122 * return 1 if smaller or the ip_block doesn't exist
1123 */
1124int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1125 enum amd_ip_block_type type,
1126 u32 major, u32 minor)
1127{
1128 const struct amdgpu_ip_block_version *ip_block;
1129 ip_block = amdgpu_get_ip_block(adev, type);
1130
1131 if (ip_block && ((ip_block->major > major) ||
1132 ((ip_block->major == major) &&
1133 (ip_block->minor >= minor))))
1134 return 0;
1135
1136 return 1;
1137}
1138
1139static int amdgpu_early_init(struct amdgpu_device *adev)
1140{
1141 int i, r;
1142
1143 switch (adev->asic_type) {
1144 case CHIP_TOPAZ:
1145 case CHIP_TONGA:
1146 case CHIP_FIJI:
1147 case CHIP_CARRIZO:
1148 case CHIP_STONEY:
1149 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1150 adev->family = AMDGPU_FAMILY_CZ;
1151 else
1152 adev->family = AMDGPU_FAMILY_VI;
1153
1154 r = vi_set_ip_blocks(adev);
1155 if (r)
1156 return r;
1157 break;
1158#ifdef CONFIG_DRM_AMDGPU_CIK
1159 case CHIP_BONAIRE:
1160 case CHIP_HAWAII:
1161 case CHIP_KAVERI:
1162 case CHIP_KABINI:
1163 case CHIP_MULLINS:
1164 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1165 adev->family = AMDGPU_FAMILY_CI;
1166 else
1167 adev->family = AMDGPU_FAMILY_KV;
1168
1169 r = cik_set_ip_blocks(adev);
1170 if (r)
1171 return r;
1172 break;
1173#endif
1174 default:
1175 /* FIXME: not supported yet */
1176 return -EINVAL;
1177 }
1178
1179 adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1180 sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1181 if (adev->ip_block_status == NULL)
1182 return -ENOMEM;
1183
1184 if (adev->ip_blocks == NULL) {
1185 DRM_ERROR("No IP blocks found!\n");
1186 return r;
1187 }
1188
1189 for (i = 0; i < adev->num_ip_blocks; i++) {
1190 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1191 DRM_ERROR("disabled ip block: %d\n", i);
1192 adev->ip_block_status[i].valid = false;
1193 } else {
1194 if (adev->ip_blocks[i].funcs->early_init) {
1195 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1196 if (r == -ENOENT) {
1197 adev->ip_block_status[i].valid = false;
1198 } else if (r) {
1199 DRM_ERROR("early_init %d failed %d\n", i, r);
1200 return r;
1201 } else {
1202 adev->ip_block_status[i].valid = true;
1203 }
1204 } else {
1205 adev->ip_block_status[i].valid = true;
1206 }
1207 }
1208 }
1209
1210 return 0;
1211}
1212
1213static int amdgpu_init(struct amdgpu_device *adev)
1214{
1215 int i, r;
1216
1217 for (i = 0; i < adev->num_ip_blocks; i++) {
1218 if (!adev->ip_block_status[i].valid)
1219 continue;
1220 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1221 if (r) {
1222 DRM_ERROR("sw_init %d failed %d\n", i, r);
1223 return r;
1224 }
1225 adev->ip_block_status[i].sw = true;
1226 /* need to do gmc hw init early so we can allocate gpu mem */
1227 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1228 r = amdgpu_vram_scratch_init(adev);
1229 if (r) {
1230 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1231 return r;
1232 }
1233 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1234 if (r) {
1235 DRM_ERROR("hw_init %d failed %d\n", i, r);
1236 return r;
1237 }
1238 r = amdgpu_wb_init(adev);
1239 if (r) {
1240 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1241 return r;
1242 }
1243 adev->ip_block_status[i].hw = true;
1244 }
1245 }
1246
1247 for (i = 0; i < adev->num_ip_blocks; i++) {
1248 if (!adev->ip_block_status[i].sw)
1249 continue;
1250 /* gmc hw init is done early */
1251 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1252 continue;
1253 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1254 if (r) {
1255 DRM_ERROR("hw_init %d failed %d\n", i, r);
1256 return r;
1257 }
1258 adev->ip_block_status[i].hw = true;
1259 }
1260
1261 return 0;
1262}
1263
1264static int amdgpu_late_init(struct amdgpu_device *adev)
1265{
1266 int i = 0, r;
1267
1268 for (i = 0; i < adev->num_ip_blocks; i++) {
1269 if (!adev->ip_block_status[i].valid)
1270 continue;
1271 /* enable clockgating to save power */
1272 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1273 AMD_CG_STATE_GATE);
1274 if (r) {
1275 DRM_ERROR("set_clockgating_state(gate) %d failed %d\n", i, r);
1276 return r;
1277 }
1278 if (adev->ip_blocks[i].funcs->late_init) {
1279 r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1280 if (r) {
1281 DRM_ERROR("late_init %d failed %d\n", i, r);
1282 return r;
1283 }
1284 }
1285 }
1286
1287 return 0;
1288}
1289
1290static int amdgpu_fini(struct amdgpu_device *adev)
1291{
1292 int i, r;
1293
1294 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1295 if (!adev->ip_block_status[i].hw)
1296 continue;
1297 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1298 amdgpu_wb_fini(adev);
1299 amdgpu_vram_scratch_fini(adev);
1300 }
1301 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1302 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1303 AMD_CG_STATE_UNGATE);
1304 if (r) {
1305 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1306 return r;
1307 }
1308 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1309 /* XXX handle errors */
1310 if (r) {
1311 DRM_DEBUG("hw_fini %d failed %d\n", i, r);
1312 }
1313 adev->ip_block_status[i].hw = false;
1314 }
1315
1316 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1317 if (!adev->ip_block_status[i].sw)
1318 continue;
1319 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1320 /* XXX handle errors */
1321 if (r) {
1322 DRM_DEBUG("sw_fini %d failed %d\n", i, r);
1323 }
1324 adev->ip_block_status[i].sw = false;
1325 adev->ip_block_status[i].valid = false;
1326 }
1327
1328 return 0;
1329}
1330
1331static int amdgpu_suspend(struct amdgpu_device *adev)
1332{
1333 int i, r;
1334
1335 for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1336 if (!adev->ip_block_status[i].valid)
1337 continue;
1338 /* ungate blocks so that suspend can properly shut them down */
1339 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1340 AMD_CG_STATE_UNGATE);
1341 if (r) {
1342 DRM_ERROR("set_clockgating_state(ungate) %d failed %d\n", i, r);
1343 }
1344 /* XXX handle errors */
1345 r = adev->ip_blocks[i].funcs->suspend(adev);
1346 /* XXX handle errors */
1347 if (r) {
1348 DRM_ERROR("suspend %d failed %d\n", i, r);
1349 }
1350 }
1351
1352 return 0;
1353}
1354
1355static int amdgpu_resume(struct amdgpu_device *adev)
1356{
1357 int i, r;
1358
1359 for (i = 0; i < adev->num_ip_blocks; i++) {
1360 if (!adev->ip_block_status[i].valid)
1361 continue;
1362 r = adev->ip_blocks[i].funcs->resume(adev);
1363 if (r) {
1364 DRM_ERROR("resume %d failed %d\n", i, r);
1365 return r;
1366 }
1367 }
1368
1369 return 0;
1370}
1371
1372/**
1373 * amdgpu_device_init - initialize the driver
1374 *
1375 * @adev: amdgpu_device pointer
1376 * @pdev: drm dev pointer
1377 * @pdev: pci dev pointer
1378 * @flags: driver flags
1379 *
1380 * Initializes the driver info and hw (all asics).
1381 * Returns 0 for success or an error on failure.
1382 * Called at driver startup.
1383 */
1384int amdgpu_device_init(struct amdgpu_device *adev,
1385 struct drm_device *ddev,
1386 struct pci_dev *pdev,
1387 uint32_t flags)
1388{
1389 int r, i;
1390 bool runtime = false;
1391
1392 adev->shutdown = false;
1393 adev->dev = &pdev->dev;
1394 adev->ddev = ddev;
1395 adev->pdev = pdev;
1396 adev->flags = flags;
1397 adev->asic_type = flags & AMD_ASIC_MASK;
1398 adev->is_atom_bios = false;
1399 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1400 adev->mc.gtt_size = 512 * 1024 * 1024;
1401 adev->accel_working = false;
1402 adev->num_rings = 0;
1403 adev->mman.buffer_funcs = NULL;
1404 adev->mman.buffer_funcs_ring = NULL;
1405 adev->vm_manager.vm_pte_funcs = NULL;
1406 adev->vm_manager.vm_pte_num_rings = 0;
1407 adev->gart.gart_funcs = NULL;
1408 adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1409
1410 adev->smc_rreg = &amdgpu_invalid_rreg;
1411 adev->smc_wreg = &amdgpu_invalid_wreg;
1412 adev->pcie_rreg = &amdgpu_invalid_rreg;
1413 adev->pcie_wreg = &amdgpu_invalid_wreg;
1414 adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1415 adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1416 adev->didt_rreg = &amdgpu_invalid_rreg;
1417 adev->didt_wreg = &amdgpu_invalid_wreg;
1418 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1419 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1420
1421 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1422 amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1423 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1424
1425 /* mutex initialization are all done here so we
1426 * can recall function without having locking issues */
1427 mutex_init(&adev->vm_manager.lock);
1428 atomic_set(&adev->irq.ih.lock, 0);
1429 mutex_init(&adev->pm.mutex);
1430 mutex_init(&adev->gfx.gpu_clock_mutex);
1431 mutex_init(&adev->srbm_mutex);
1432 mutex_init(&adev->grbm_idx_mutex);
1433 mutex_init(&adev->mn_lock);
1434 hash_init(adev->mn_hash);
1435
1436 amdgpu_check_arguments(adev);
1437
1438 /* Registers mapping */
1439 /* TODO: block userspace mapping of io register */
1440 spin_lock_init(&adev->mmio_idx_lock);
1441 spin_lock_init(&adev->smc_idx_lock);
1442 spin_lock_init(&adev->pcie_idx_lock);
1443 spin_lock_init(&adev->uvd_ctx_idx_lock);
1444 spin_lock_init(&adev->didt_idx_lock);
1445 spin_lock_init(&adev->audio_endpt_idx_lock);
1446
1447 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1448 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1449 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1450 if (adev->rmmio == NULL) {
1451 return -ENOMEM;
1452 }
1453 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1454 DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1455
1456 /* doorbell bar mapping */
1457 amdgpu_doorbell_init(adev);
1458
1459 /* io port mapping */
1460 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1461 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1462 adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1463 adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1464 break;
1465 }
1466 }
1467 if (adev->rio_mem == NULL)
1468 DRM_ERROR("Unable to find PCI I/O BAR\n");
1469
1470 /* early init functions */
1471 r = amdgpu_early_init(adev);
1472 if (r)
1473 return r;
1474
1475 /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1476 /* this will fail for cards that aren't VGA class devices, just
1477 * ignore it */
1478 vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1479
1480 if (amdgpu_runtime_pm == 1)
1481 runtime = true;
1482 if (amdgpu_device_is_px(ddev))
1483 runtime = true;
1484 vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1485 if (runtime)
1486 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1487
1488 /* Read BIOS */
1489 if (!amdgpu_get_bios(adev))
1490 return -EINVAL;
1491 /* Must be an ATOMBIOS */
1492 if (!adev->is_atom_bios) {
1493 dev_err(adev->dev, "Expecting atombios for GPU\n");
1494 return -EINVAL;
1495 }
1496 r = amdgpu_atombios_init(adev);
1497 if (r) {
1498 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
1499 return r;
1500 }
1501
1502 /* See if the asic supports SR-IOV */
1503 adev->virtualization.supports_sr_iov =
1504 amdgpu_atombios_has_gpu_virtualization_table(adev);
1505
1506 /* Post card if necessary */
1507 if (!amdgpu_card_posted(adev) ||
1508 adev->virtualization.supports_sr_iov) {
1509 if (!adev->bios) {
1510 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1511 return -EINVAL;
1512 }
1513 DRM_INFO("GPU not posted. posting now...\n");
1514 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1515 }
1516
1517 /* Initialize clocks */
1518 r = amdgpu_atombios_get_clock_info(adev);
1519 if (r) {
1520 dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
1521 return r;
1522 }
1523 /* init i2c buses */
1524 amdgpu_atombios_i2c_init(adev);
1525
1526 /* Fence driver */
1527 r = amdgpu_fence_driver_init(adev);
1528 if (r) {
1529 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
1530 return r;
1531 }
1532
1533 /* init the mode config */
1534 drm_mode_config_init(adev->ddev);
1535
1536 r = amdgpu_init(adev);
1537 if (r) {
1538 dev_err(adev->dev, "amdgpu_init failed\n");
1539 amdgpu_fini(adev);
1540 return r;
1541 }
1542
1543 adev->accel_working = true;
1544
1545 amdgpu_fbdev_init(adev);
1546
1547 r = amdgpu_ib_pool_init(adev);
1548 if (r) {
1549 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1550 return r;
1551 }
1552
1553 r = amdgpu_ib_ring_tests(adev);
1554 if (r)
1555 DRM_ERROR("ib ring test failed (%d).\n", r);
1556
1557 r = amdgpu_gem_debugfs_init(adev);
1558 if (r) {
1559 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1560 }
1561
1562 r = amdgpu_debugfs_regs_init(adev);
1563 if (r) {
1564 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1565 }
1566
1567 if ((amdgpu_testing & 1)) {
1568 if (adev->accel_working)
1569 amdgpu_test_moves(adev);
1570 else
1571 DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1572 }
1573 if ((amdgpu_testing & 2)) {
1574 if (adev->accel_working)
1575 amdgpu_test_syncing(adev);
1576 else
1577 DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1578 }
1579 if (amdgpu_benchmarking) {
1580 if (adev->accel_working)
1581 amdgpu_benchmark(adev, amdgpu_benchmarking);
1582 else
1583 DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1584 }
1585
1586 /* enable clockgating, etc. after ib tests, etc. since some blocks require
1587 * explicit gating rather than handling it automatically.
1588 */
1589 r = amdgpu_late_init(adev);
1590 if (r) {
1591 dev_err(adev->dev, "amdgpu_late_init failed\n");
1592 return r;
1593 }
1594
1595 return 0;
1596}
1597
1598static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1599
1600/**
1601 * amdgpu_device_fini - tear down the driver
1602 *
1603 * @adev: amdgpu_device pointer
1604 *
1605 * Tear down the driver info (all asics).
1606 * Called at driver shutdown.
1607 */
1608void amdgpu_device_fini(struct amdgpu_device *adev)
1609{
1610 int r;
1611
1612 DRM_INFO("amdgpu: finishing device.\n");
1613 adev->shutdown = true;
1614 /* evict vram memory */
1615 amdgpu_bo_evict_vram(adev);
1616 amdgpu_ib_pool_fini(adev);
1617 amdgpu_fence_driver_fini(adev);
1618 amdgpu_fbdev_fini(adev);
1619 r = amdgpu_fini(adev);
1620 kfree(adev->ip_block_status);
1621 adev->ip_block_status = NULL;
1622 adev->accel_working = false;
1623 /* free i2c buses */
1624 amdgpu_i2c_fini(adev);
1625 amdgpu_atombios_fini(adev);
1626 kfree(adev->bios);
1627 adev->bios = NULL;
1628 vga_switcheroo_unregister_client(adev->pdev);
1629 vga_client_register(adev->pdev, NULL, NULL, NULL);
1630 if (adev->rio_mem)
1631 pci_iounmap(adev->pdev, adev->rio_mem);
1632 adev->rio_mem = NULL;
1633 iounmap(adev->rmmio);
1634 adev->rmmio = NULL;
1635 amdgpu_doorbell_fini(adev);
1636 amdgpu_debugfs_regs_cleanup(adev);
1637 amdgpu_debugfs_remove_files(adev);
1638}
1639
1640
1641/*
1642 * Suspend & resume.
1643 */
1644/**
1645 * amdgpu_suspend_kms - initiate device suspend
1646 *
1647 * @pdev: drm dev pointer
1648 * @state: suspend state
1649 *
1650 * Puts the hw in the suspend state (all asics).
1651 * Returns 0 for success or an error on failure.
1652 * Called at driver suspend.
1653 */
1654int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1655{
1656 struct amdgpu_device *adev;
1657 struct drm_crtc *crtc;
1658 struct drm_connector *connector;
1659 int r;
1660
1661 if (dev == NULL || dev->dev_private == NULL) {
1662 return -ENODEV;
1663 }
1664
1665 adev = dev->dev_private;
1666
1667 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1668 return 0;
1669
1670 drm_kms_helper_poll_disable(dev);
1671
1672 /* turn off display hw */
1673 drm_modeset_lock_all(dev);
1674 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1675 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1676 }
1677 drm_modeset_unlock_all(dev);
1678
1679 /* unpin the front buffers and cursors */
1680 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1682 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1683 struct amdgpu_bo *robj;
1684
1685 if (amdgpu_crtc->cursor_bo) {
1686 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1687 r = amdgpu_bo_reserve(aobj, false);
1688 if (r == 0) {
1689 amdgpu_bo_unpin(aobj);
1690 amdgpu_bo_unreserve(aobj);
1691 }
1692 }
1693
1694 if (rfb == NULL || rfb->obj == NULL) {
1695 continue;
1696 }
1697 robj = gem_to_amdgpu_bo(rfb->obj);
1698 /* don't unpin kernel fb objects */
1699 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1700 r = amdgpu_bo_reserve(robj, false);
1701 if (r == 0) {
1702 amdgpu_bo_unpin(robj);
1703 amdgpu_bo_unreserve(robj);
1704 }
1705 }
1706 }
1707 /* evict vram memory */
1708 amdgpu_bo_evict_vram(adev);
1709
1710 amdgpu_fence_driver_suspend(adev);
1711
1712 r = amdgpu_suspend(adev);
1713
1714 /* evict remaining vram memory */
1715 amdgpu_bo_evict_vram(adev);
1716
1717 pci_save_state(dev->pdev);
1718 if (suspend) {
1719 /* Shut down the device */
1720 pci_disable_device(dev->pdev);
1721 pci_set_power_state(dev->pdev, PCI_D3hot);
1722 }
1723
1724 if (fbcon) {
1725 console_lock();
1726 amdgpu_fbdev_set_suspend(adev, 1);
1727 console_unlock();
1728 }
1729 return 0;
1730}
1731
1732/**
1733 * amdgpu_resume_kms - initiate device resume
1734 *
1735 * @pdev: drm dev pointer
1736 *
1737 * Bring the hw back to operating state (all asics).
1738 * Returns 0 for success or an error on failure.
1739 * Called at driver resume.
1740 */
1741int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1742{
1743 struct drm_connector *connector;
1744 struct amdgpu_device *adev = dev->dev_private;
1745 struct drm_crtc *crtc;
1746 int r;
1747
1748 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1749 return 0;
1750
1751 if (fbcon) {
1752 console_lock();
1753 }
1754 if (resume) {
1755 pci_set_power_state(dev->pdev, PCI_D0);
1756 pci_restore_state(dev->pdev);
1757 if (pci_enable_device(dev->pdev)) {
1758 if (fbcon)
1759 console_unlock();
1760 return -1;
1761 }
1762 }
1763
1764 /* post card */
1765 if (!amdgpu_card_posted(adev))
1766 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1767
1768 r = amdgpu_resume(adev);
1769 if (r)
1770 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
1771
1772 amdgpu_fence_driver_resume(adev);
1773
1774 if (resume) {
1775 r = amdgpu_ib_ring_tests(adev);
1776 if (r)
1777 DRM_ERROR("ib ring test failed (%d).\n", r);
1778 }
1779
1780 r = amdgpu_late_init(adev);
1781 if (r)
1782 return r;
1783
1784 /* pin cursors */
1785 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1786 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1787
1788 if (amdgpu_crtc->cursor_bo) {
1789 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1790 r = amdgpu_bo_reserve(aobj, false);
1791 if (r == 0) {
1792 r = amdgpu_bo_pin(aobj,
1793 AMDGPU_GEM_DOMAIN_VRAM,
1794 &amdgpu_crtc->cursor_addr);
1795 if (r != 0)
1796 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1797 amdgpu_bo_unreserve(aobj);
1798 }
1799 }
1800 }
1801
1802 /* blat the mode back in */
1803 if (fbcon) {
1804 drm_helper_resume_force_mode(dev);
1805 /* turn on display hw */
1806 drm_modeset_lock_all(dev);
1807 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1808 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1809 }
1810 drm_modeset_unlock_all(dev);
1811 }
1812
1813 drm_kms_helper_poll_enable(dev);
1814 drm_helper_hpd_irq_event(dev);
1815
1816 if (fbcon) {
1817 amdgpu_fbdev_set_suspend(adev, 0);
1818 console_unlock();
1819 }
1820
1821 return 0;
1822}
1823
1824/**
1825 * amdgpu_gpu_reset - reset the asic
1826 *
1827 * @adev: amdgpu device pointer
1828 *
1829 * Attempt the reset the GPU if it has hung (all asics).
1830 * Returns 0 for success or an error on failure.
1831 */
1832int amdgpu_gpu_reset(struct amdgpu_device *adev)
1833{
1834 unsigned ring_sizes[AMDGPU_MAX_RINGS];
1835 uint32_t *ring_data[AMDGPU_MAX_RINGS];
1836
1837 bool saved = false;
1838
1839 int i, r;
1840 int resched;
1841
1842 atomic_inc(&adev->gpu_reset_counter);
1843
1844 /* block TTM */
1845 resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1846
1847 r = amdgpu_suspend(adev);
1848
1849 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1850 struct amdgpu_ring *ring = adev->rings[i];
1851 if (!ring)
1852 continue;
1853
1854 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1855 if (ring_sizes[i]) {
1856 saved = true;
1857 dev_info(adev->dev, "Saved %d dwords of commands "
1858 "on ring %d.\n", ring_sizes[i], i);
1859 }
1860 }
1861
1862retry:
1863 r = amdgpu_asic_reset(adev);
1864 /* post card */
1865 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1866
1867 if (!r) {
1868 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1869 r = amdgpu_resume(adev);
1870 }
1871
1872 if (!r) {
1873 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1874 struct amdgpu_ring *ring = adev->rings[i];
1875 if (!ring)
1876 continue;
1877
1878 amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1879 ring_sizes[i] = 0;
1880 ring_data[i] = NULL;
1881 }
1882
1883 r = amdgpu_ib_ring_tests(adev);
1884 if (r) {
1885 dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1886 if (saved) {
1887 saved = false;
1888 r = amdgpu_suspend(adev);
1889 goto retry;
1890 }
1891 }
1892 } else {
1893 amdgpu_fence_driver_force_completion(adev);
1894 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1895 if (adev->rings[i])
1896 kfree(ring_data[i]);
1897 }
1898 }
1899
1900 drm_helper_resume_force_mode(adev->ddev);
1901
1902 ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1903 if (r) {
1904 /* bad news, how to tell it to userspace ? */
1905 dev_info(adev->dev, "GPU reset failed\n");
1906 }
1907
1908 return r;
1909}
1910
1911#define AMDGPU_DEFAULT_PCIE_GEN_MASK 0x30007 /* gen: chipset 1/2, asic 1/2/3 */
1912#define AMDGPU_DEFAULT_PCIE_MLW_MASK 0x2f0000 /* 1/2/4/8/16 lanes */
1913
1914void amdgpu_get_pcie_info(struct amdgpu_device *adev)
1915{
1916 u32 mask;
1917 int ret;
1918
1919 if (amdgpu_pcie_gen_cap)
1920 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
1921
1922 if (amdgpu_pcie_lane_cap)
1923 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
1924
1925 /* covers APUs as well */
1926 if (pci_is_root_bus(adev->pdev->bus)) {
1927 if (adev->pm.pcie_gen_mask == 0)
1928 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1929 if (adev->pm.pcie_mlw_mask == 0)
1930 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
1931 return;
1932 }
1933
1934 if (adev->pm.pcie_gen_mask == 0) {
1935 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
1936 if (!ret) {
1937 adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
1938 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1939 CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
1940
1941 if (mask & DRM_PCIE_SPEED_25)
1942 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
1943 if (mask & DRM_PCIE_SPEED_50)
1944 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
1945 if (mask & DRM_PCIE_SPEED_80)
1946 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
1947 } else {
1948 adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
1949 }
1950 }
1951 if (adev->pm.pcie_mlw_mask == 0) {
1952 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
1953 if (!ret) {
1954 switch (mask) {
1955 case 32:
1956 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
1957 CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1958 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1959 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1960 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1961 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1962 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1963 break;
1964 case 16:
1965 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
1966 CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1967 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1968 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1969 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1970 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1971 break;
1972 case 12:
1973 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
1974 CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1975 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1976 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1977 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1978 break;
1979 case 8:
1980 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
1981 CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1982 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1983 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1984 break;
1985 case 4:
1986 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
1987 CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1988 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1989 break;
1990 case 2:
1991 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
1992 CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
1993 break;
1994 case 1:
1995 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
1996 break;
1997 default:
1998 break;
1999 }
2000 } else {
2001 adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
2002 }
2003 }
2004}
2005
2006/*
2007 * Debugfs
2008 */
2009int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
2010 struct drm_info_list *files,
2011 unsigned nfiles)
2012{
2013 unsigned i;
2014
2015 for (i = 0; i < adev->debugfs_count; i++) {
2016 if (adev->debugfs[i].files == files) {
2017 /* Already registered */
2018 return 0;
2019 }
2020 }
2021
2022 i = adev->debugfs_count + 1;
2023 if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
2024 DRM_ERROR("Reached maximum number of debugfs components.\n");
2025 DRM_ERROR("Report so we increase "
2026 "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
2027 return -EINVAL;
2028 }
2029 adev->debugfs[adev->debugfs_count].files = files;
2030 adev->debugfs[adev->debugfs_count].num_files = nfiles;
2031 adev->debugfs_count = i;
2032#if defined(CONFIG_DEBUG_FS)
2033 drm_debugfs_create_files(files, nfiles,
2034 adev->ddev->control->debugfs_root,
2035 adev->ddev->control);
2036 drm_debugfs_create_files(files, nfiles,
2037 adev->ddev->primary->debugfs_root,
2038 adev->ddev->primary);
2039#endif
2040 return 0;
2041}
2042
2043static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
2044{
2045#if defined(CONFIG_DEBUG_FS)
2046 unsigned i;
2047
2048 for (i = 0; i < adev->debugfs_count; i++) {
2049 drm_debugfs_remove_files(adev->debugfs[i].files,
2050 adev->debugfs[i].num_files,
2051 adev->ddev->control);
2052 drm_debugfs_remove_files(adev->debugfs[i].files,
2053 adev->debugfs[i].num_files,
2054 adev->ddev->primary);
2055 }
2056#endif
2057}
2058
2059#if defined(CONFIG_DEBUG_FS)
2060
2061static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
2062 size_t size, loff_t *pos)
2063{
2064 struct amdgpu_device *adev = f->f_inode->i_private;
2065 ssize_t result = 0;
2066 int r;
2067
2068 if (size & 0x3 || *pos & 0x3)
2069 return -EINVAL;
2070
2071 while (size) {
2072 uint32_t value;
2073
2074 if (*pos > adev->rmmio_size)
2075 return result;
2076
2077 value = RREG32(*pos >> 2);
2078 r = put_user(value, (uint32_t *)buf);
2079 if (r)
2080 return r;
2081
2082 result += 4;
2083 buf += 4;
2084 *pos += 4;
2085 size -= 4;
2086 }
2087
2088 return result;
2089}
2090
2091static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
2092 size_t size, loff_t *pos)
2093{
2094 struct amdgpu_device *adev = f->f_inode->i_private;
2095 ssize_t result = 0;
2096 int r;
2097
2098 if (size & 0x3 || *pos & 0x3)
2099 return -EINVAL;
2100
2101 while (size) {
2102 uint32_t value;
2103
2104 if (*pos > adev->rmmio_size)
2105 return result;
2106
2107 r = get_user(value, (uint32_t *)buf);
2108 if (r)
2109 return r;
2110
2111 WREG32(*pos >> 2, value);
2112
2113 result += 4;
2114 buf += 4;
2115 *pos += 4;
2116 size -= 4;
2117 }
2118
2119 return result;
2120}
2121
2122static const struct file_operations amdgpu_debugfs_regs_fops = {
2123 .owner = THIS_MODULE,
2124 .read = amdgpu_debugfs_regs_read,
2125 .write = amdgpu_debugfs_regs_write,
2126 .llseek = default_llseek
2127};
2128
2129static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2130{
2131 struct drm_minor *minor = adev->ddev->primary;
2132 struct dentry *ent, *root = minor->debugfs_root;
2133
2134 ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
2135 adev, &amdgpu_debugfs_regs_fops);
2136 if (IS_ERR(ent))
2137 return PTR_ERR(ent);
2138 i_size_write(ent->d_inode, adev->rmmio_size);
2139 adev->debugfs_regs = ent;
2140
2141 return 0;
2142}
2143
2144static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
2145{
2146 debugfs_remove(adev->debugfs_regs);
2147 adev->debugfs_regs = NULL;
2148}
2149
2150int amdgpu_debugfs_init(struct drm_minor *minor)
2151{
2152 return 0;
2153}
2154
2155void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2156{
2157}
2158#else
2159static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2160{
2161 return 0;
2162}
2163static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2164#endif