Loading...
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/gpio.h>
20
21#define PCH_GPIO_ALL_PINS 0xfff /* Mask for GPIO pins 0 to 11 */
22#define GPIO_NUM_PINS 12 /* Specifies number of GPIO PINS GPIO0-GPIO11 */
23
24struct pch_regs {
25 u32 ien;
26 u32 istatus;
27 u32 idisp;
28 u32 iclr;
29 u32 imask;
30 u32 imaskclr;
31 u32 po;
32 u32 pi;
33 u32 pm;
34 u32 im0;
35 u32 im1;
36 u32 reserved[4];
37 u32 reset;
38};
39
40/**
41 * struct pch_gpio_reg_data - The register store data.
42 * @po_reg: To store contents of PO register.
43 * @pm_reg: To store contents of PM register.
44 */
45struct pch_gpio_reg_data {
46 u32 po_reg;
47 u32 pm_reg;
48};
49
50/**
51 * struct pch_gpio - GPIO private data structure.
52 * @base: PCI base address of Memory mapped I/O register.
53 * @reg: Memory mapped PCH GPIO register list.
54 * @dev: Pointer to device structure.
55 * @gpio: Data for GPIO infrastructure.
56 * @pch_gpio_reg: Memory mapped Register data is saved here
57 * when suspend.
58 */
59struct pch_gpio {
60 void __iomem *base;
61 struct pch_regs __iomem *reg;
62 struct device *dev;
63 struct gpio_chip gpio;
64 struct pch_gpio_reg_data pch_gpio_reg;
65 struct mutex lock;
66};
67
68static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
69{
70 u32 reg_val;
71 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
72
73 mutex_lock(&chip->lock);
74 reg_val = ioread32(&chip->reg->po);
75 if (val)
76 reg_val |= (1 << nr);
77 else
78 reg_val &= ~(1 << nr);
79
80 iowrite32(reg_val, &chip->reg->po);
81 mutex_unlock(&chip->lock);
82}
83
84static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
85{
86 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
87
88 return ioread32(&chip->reg->pi) & (1 << nr);
89}
90
91static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
92 int val)
93{
94 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
95 u32 pm;
96 u32 reg_val;
97
98 mutex_lock(&chip->lock);
99 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS;
100 pm |= (1 << nr);
101 iowrite32(pm, &chip->reg->pm);
102
103 reg_val = ioread32(&chip->reg->po);
104 if (val)
105 reg_val |= (1 << nr);
106 else
107 reg_val &= ~(1 << nr);
108 iowrite32(reg_val, &chip->reg->po);
109
110 mutex_unlock(&chip->lock);
111
112 return 0;
113}
114
115static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
116{
117 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
118 u32 pm;
119
120 mutex_lock(&chip->lock);
121 pm = ioread32(&chip->reg->pm) & PCH_GPIO_ALL_PINS; /*bits 0-11*/
122 pm &= ~(1 << nr);
123 iowrite32(pm, &chip->reg->pm);
124 mutex_unlock(&chip->lock);
125
126 return 0;
127}
128
129/*
130 * Save register configuration and disable interrupts.
131 */
132static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
133{
134 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
135 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
136}
137
138/*
139 * This function restores the register configuration of the GPIO device.
140 */
141static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
142{
143 /* to store contents of PO register */
144 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
145 /* to store contents of PM register */
146 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
147}
148
149static void pch_gpio_setup(struct pch_gpio *chip)
150{
151 struct gpio_chip *gpio = &chip->gpio;
152
153 gpio->label = dev_name(chip->dev);
154 gpio->owner = THIS_MODULE;
155 gpio->direction_input = pch_gpio_direction_input;
156 gpio->get = pch_gpio_get;
157 gpio->direction_output = pch_gpio_direction_output;
158 gpio->set = pch_gpio_set;
159 gpio->dbg_show = NULL;
160 gpio->base = -1;
161 gpio->ngpio = GPIO_NUM_PINS;
162 gpio->can_sleep = 0;
163}
164
165static int __devinit pch_gpio_probe(struct pci_dev *pdev,
166 const struct pci_device_id *id)
167{
168 s32 ret;
169 struct pch_gpio *chip;
170
171 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
172 if (chip == NULL)
173 return -ENOMEM;
174
175 chip->dev = &pdev->dev;
176 ret = pci_enable_device(pdev);
177 if (ret) {
178 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
179 goto err_pci_enable;
180 }
181
182 ret = pci_request_regions(pdev, KBUILD_MODNAME);
183 if (ret) {
184 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
185 goto err_request_regions;
186 }
187
188 chip->base = pci_iomap(pdev, 1, 0);
189 if (chip->base == 0) {
190 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
191 ret = -ENOMEM;
192 goto err_iomap;
193 }
194
195 chip->reg = chip->base;
196 pci_set_drvdata(pdev, chip);
197 mutex_init(&chip->lock);
198 pch_gpio_setup(chip);
199 ret = gpiochip_add(&chip->gpio);
200 if (ret) {
201 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
202 goto err_gpiochip_add;
203 }
204
205 return 0;
206
207err_gpiochip_add:
208 pci_iounmap(pdev, chip->base);
209
210err_iomap:
211 pci_release_regions(pdev);
212
213err_request_regions:
214 pci_disable_device(pdev);
215
216err_pci_enable:
217 kfree(chip);
218 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
219 return ret;
220}
221
222static void __devexit pch_gpio_remove(struct pci_dev *pdev)
223{
224 int err;
225 struct pch_gpio *chip = pci_get_drvdata(pdev);
226
227 err = gpiochip_remove(&chip->gpio);
228 if (err)
229 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
230
231 pci_iounmap(pdev, chip->base);
232 pci_release_regions(pdev);
233 pci_disable_device(pdev);
234 kfree(chip);
235}
236
237#ifdef CONFIG_PM
238static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
239{
240 s32 ret;
241 struct pch_gpio *chip = pci_get_drvdata(pdev);
242
243 pch_gpio_save_reg_conf(chip);
244 pch_gpio_restore_reg_conf(chip);
245
246 ret = pci_save_state(pdev);
247 if (ret) {
248 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
249 return ret;
250 }
251 pci_disable_device(pdev);
252 pci_set_power_state(pdev, PCI_D0);
253 ret = pci_enable_wake(pdev, PCI_D0, 1);
254 if (ret)
255 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
256
257 return 0;
258}
259
260static int pch_gpio_resume(struct pci_dev *pdev)
261{
262 s32 ret;
263 struct pch_gpio *chip = pci_get_drvdata(pdev);
264
265 ret = pci_enable_wake(pdev, PCI_D0, 0);
266
267 pci_set_power_state(pdev, PCI_D0);
268 ret = pci_enable_device(pdev);
269 if (ret) {
270 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
271 return ret;
272 }
273 pci_restore_state(pdev);
274
275 iowrite32(0x01, &chip->reg->reset);
276 iowrite32(0x00, &chip->reg->reset);
277 pch_gpio_restore_reg_conf(chip);
278
279 return 0;
280}
281#else
282#define pch_gpio_suspend NULL
283#define pch_gpio_resume NULL
284#endif
285
286#define PCI_VENDOR_ID_ROHM 0x10DB
287static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
288 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
289 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
290 { 0, }
291};
292MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
293
294static struct pci_driver pch_gpio_driver = {
295 .name = "pch_gpio",
296 .id_table = pch_gpio_pcidev_id,
297 .probe = pch_gpio_probe,
298 .remove = __devexit_p(pch_gpio_remove),
299 .suspend = pch_gpio_suspend,
300 .resume = pch_gpio_resume
301};
302
303static int __init pch_gpio_pci_init(void)
304{
305 return pci_register_driver(&pch_gpio_driver);
306}
307module_init(pch_gpio_pci_init);
308
309static void __exit pch_gpio_pci_exit(void)
310{
311 pci_unregister_driver(&pch_gpio_driver);
312}
313module_exit(pch_gpio_pci_exit);
314
315MODULE_DESCRIPTION("PCH GPIO PCI Driver");
316MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
21#include <linux/interrupt.h>
22#include <linux/irq.h>
23#include <linux/slab.h>
24
25#define PCH_EDGE_FALLING 0
26#define PCH_EDGE_RISING BIT(0)
27#define PCH_LEVEL_L BIT(1)
28#define PCH_LEVEL_H (BIT(0) | BIT(1))
29#define PCH_EDGE_BOTH BIT(2)
30#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define PCH_IRQ_BASE 24
33
34struct pch_regs {
35 u32 ien;
36 u32 istatus;
37 u32 idisp;
38 u32 iclr;
39 u32 imask;
40 u32 imaskclr;
41 u32 po;
42 u32 pi;
43 u32 pm;
44 u32 im0;
45 u32 im1;
46 u32 reserved[3];
47 u32 gpio_use_sel;
48 u32 reset;
49};
50
51enum pch_type_t {
52 INTEL_EG20T_PCH,
53 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
54 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
55};
56
57/* Specifies number of GPIO PINS */
58static int gpio_pins[] = {
59 [INTEL_EG20T_PCH] = 12,
60 [OKISEMI_ML7223m_IOH] = 8,
61 [OKISEMI_ML7223n_IOH] = 8,
62};
63
64/**
65 * struct pch_gpio_reg_data - The register store data.
66 * @ien_reg: To store contents of IEN register.
67 * @imask_reg: To store contents of IMASK register.
68 * @po_reg: To store contents of PO register.
69 * @pm_reg: To store contents of PM register.
70 * @im0_reg: To store contents of IM0 register.
71 * @im1_reg: To store contents of IM1 register.
72 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
73 * (Only ML7223 Bus-n)
74 */
75struct pch_gpio_reg_data {
76 u32 ien_reg;
77 u32 imask_reg;
78 u32 po_reg;
79 u32 pm_reg;
80 u32 im0_reg;
81 u32 im1_reg;
82 u32 gpio_use_sel_reg;
83};
84
85/**
86 * struct pch_gpio - GPIO private data structure.
87 * @base: PCI base address of Memory mapped I/O register.
88 * @reg: Memory mapped PCH GPIO register list.
89 * @dev: Pointer to device structure.
90 * @gpio: Data for GPIO infrastructure.
91 * @pch_gpio_reg: Memory mapped Register data is saved here
92 * when suspend.
93 * @lock: Used for register access protection
94 * @irq_base: Save base of IRQ number for interrupt
95 * @ioh: IOH ID
96 * @spinlock: Used for register access protection
97 */
98struct pch_gpio {
99 void __iomem *base;
100 struct pch_regs __iomem *reg;
101 struct device *dev;
102 struct gpio_chip gpio;
103 struct pch_gpio_reg_data pch_gpio_reg;
104 int irq_base;
105 enum pch_type_t ioh;
106 spinlock_t spinlock;
107};
108
109static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
110{
111 u32 reg_val;
112 struct pch_gpio *chip = gpiochip_get_data(gpio);
113 unsigned long flags;
114
115 spin_lock_irqsave(&chip->spinlock, flags);
116 reg_val = ioread32(&chip->reg->po);
117 if (val)
118 reg_val |= (1 << nr);
119 else
120 reg_val &= ~(1 << nr);
121
122 iowrite32(reg_val, &chip->reg->po);
123 spin_unlock_irqrestore(&chip->spinlock, flags);
124}
125
126static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
127{
128 struct pch_gpio *chip = gpiochip_get_data(gpio);
129
130 return (ioread32(&chip->reg->pi) >> nr) & 1;
131}
132
133static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
134 int val)
135{
136 struct pch_gpio *chip = gpiochip_get_data(gpio);
137 u32 pm;
138 u32 reg_val;
139 unsigned long flags;
140
141 spin_lock_irqsave(&chip->spinlock, flags);
142
143 reg_val = ioread32(&chip->reg->po);
144 if (val)
145 reg_val |= (1 << nr);
146 else
147 reg_val &= ~(1 << nr);
148 iowrite32(reg_val, &chip->reg->po);
149
150 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
151 pm |= (1 << nr);
152 iowrite32(pm, &chip->reg->pm);
153
154 spin_unlock_irqrestore(&chip->spinlock, flags);
155
156 return 0;
157}
158
159static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
160{
161 struct pch_gpio *chip = gpiochip_get_data(gpio);
162 u32 pm;
163 unsigned long flags;
164
165 spin_lock_irqsave(&chip->spinlock, flags);
166 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
167 pm &= ~(1 << nr);
168 iowrite32(pm, &chip->reg->pm);
169 spin_unlock_irqrestore(&chip->spinlock, flags);
170
171 return 0;
172}
173
174#ifdef CONFIG_PM
175/*
176 * Save register configuration and disable interrupts.
177 */
178static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
179{
180 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
181 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
182 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
183 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
184 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
185 if (chip->ioh == INTEL_EG20T_PCH)
186 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
187 if (chip->ioh == OKISEMI_ML7223n_IOH)
188 chip->pch_gpio_reg.gpio_use_sel_reg =\
189 ioread32(&chip->reg->gpio_use_sel);
190}
191
192/*
193 * This function restores the register configuration of the GPIO device.
194 */
195static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
196{
197 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
198 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
199 /* to store contents of PO register */
200 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
201 /* to store contents of PM register */
202 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
203 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
204 if (chip->ioh == INTEL_EG20T_PCH)
205 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
206 if (chip->ioh == OKISEMI_ML7223n_IOH)
207 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
208 &chip->reg->gpio_use_sel);
209}
210#endif
211
212static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
213{
214 struct pch_gpio *chip = gpiochip_get_data(gpio);
215 return chip->irq_base + offset;
216}
217
218static void pch_gpio_setup(struct pch_gpio *chip)
219{
220 struct gpio_chip *gpio = &chip->gpio;
221
222 gpio->label = dev_name(chip->dev);
223 gpio->parent = chip->dev;
224 gpio->owner = THIS_MODULE;
225 gpio->direction_input = pch_gpio_direction_input;
226 gpio->get = pch_gpio_get;
227 gpio->direction_output = pch_gpio_direction_output;
228 gpio->set = pch_gpio_set;
229 gpio->dbg_show = NULL;
230 gpio->base = -1;
231 gpio->ngpio = gpio_pins[chip->ioh];
232 gpio->can_sleep = false;
233 gpio->to_irq = pch_gpio_to_irq;
234}
235
236static int pch_irq_type(struct irq_data *d, unsigned int type)
237{
238 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
239 struct pch_gpio *chip = gc->private;
240 u32 im, im_pos, val;
241 u32 __iomem *im_reg;
242 unsigned long flags;
243 int ch, irq = d->irq;
244
245 ch = irq - chip->irq_base;
246 if (irq <= chip->irq_base + 7) {
247 im_reg = &chip->reg->im0;
248 im_pos = ch;
249 } else {
250 im_reg = &chip->reg->im1;
251 im_pos = ch - 8;
252 }
253 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
254 __func__, irq, type, ch, im_pos);
255
256 spin_lock_irqsave(&chip->spinlock, flags);
257
258 switch (type) {
259 case IRQ_TYPE_EDGE_RISING:
260 val = PCH_EDGE_RISING;
261 break;
262 case IRQ_TYPE_EDGE_FALLING:
263 val = PCH_EDGE_FALLING;
264 break;
265 case IRQ_TYPE_EDGE_BOTH:
266 val = PCH_EDGE_BOTH;
267 break;
268 case IRQ_TYPE_LEVEL_HIGH:
269 val = PCH_LEVEL_H;
270 break;
271 case IRQ_TYPE_LEVEL_LOW:
272 val = PCH_LEVEL_L;
273 break;
274 default:
275 goto unlock;
276 }
277
278 /* Set interrupt mode */
279 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
280 iowrite32(im | (val << (im_pos * 4)), im_reg);
281
282 /* And the handler */
283 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
284 irq_set_handler_locked(d, handle_level_irq);
285 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
286 irq_set_handler_locked(d, handle_edge_irq);
287
288unlock:
289 spin_unlock_irqrestore(&chip->spinlock, flags);
290 return 0;
291}
292
293static void pch_irq_unmask(struct irq_data *d)
294{
295 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
296 struct pch_gpio *chip = gc->private;
297
298 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
299}
300
301static void pch_irq_mask(struct irq_data *d)
302{
303 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
304 struct pch_gpio *chip = gc->private;
305
306 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
307}
308
309static void pch_irq_ack(struct irq_data *d)
310{
311 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
312 struct pch_gpio *chip = gc->private;
313
314 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
315}
316
317static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
318{
319 struct pch_gpio *chip = dev_id;
320 u32 reg_val = ioread32(&chip->reg->istatus);
321 int i, ret = IRQ_NONE;
322
323 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
324 if (reg_val & BIT(i)) {
325 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
326 __func__, i, irq, reg_val);
327 generic_handle_irq(chip->irq_base + i);
328 ret = IRQ_HANDLED;
329 }
330 }
331 return ret;
332}
333
334static void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
335 unsigned int irq_start, unsigned int num)
336{
337 struct irq_chip_generic *gc;
338 struct irq_chip_type *ct;
339
340 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
341 handle_simple_irq);
342 gc->private = chip;
343 ct = gc->chip_types;
344
345 ct->chip.irq_ack = pch_irq_ack;
346 ct->chip.irq_mask = pch_irq_mask;
347 ct->chip.irq_unmask = pch_irq_unmask;
348 ct->chip.irq_set_type = pch_irq_type;
349
350 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
351 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
352}
353
354static int pch_gpio_probe(struct pci_dev *pdev,
355 const struct pci_device_id *id)
356{
357 s32 ret;
358 struct pch_gpio *chip;
359 int irq_base;
360 u32 msk;
361
362 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
363 if (chip == NULL)
364 return -ENOMEM;
365
366 chip->dev = &pdev->dev;
367 ret = pci_enable_device(pdev);
368 if (ret) {
369 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
370 goto err_pci_enable;
371 }
372
373 ret = pci_request_regions(pdev, KBUILD_MODNAME);
374 if (ret) {
375 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
376 goto err_request_regions;
377 }
378
379 chip->base = pci_iomap(pdev, 1, 0);
380 if (!chip->base) {
381 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
382 ret = -ENOMEM;
383 goto err_iomap;
384 }
385
386 if (pdev->device == 0x8803)
387 chip->ioh = INTEL_EG20T_PCH;
388 else if (pdev->device == 0x8014)
389 chip->ioh = OKISEMI_ML7223m_IOH;
390 else if (pdev->device == 0x8043)
391 chip->ioh = OKISEMI_ML7223n_IOH;
392
393 chip->reg = chip->base;
394 pci_set_drvdata(pdev, chip);
395 spin_lock_init(&chip->spinlock);
396 pch_gpio_setup(chip);
397#ifdef CONFIG_OF_GPIO
398 chip->gpio.of_node = pdev->dev.of_node;
399#endif
400 ret = gpiochip_add_data(&chip->gpio, chip);
401 if (ret) {
402 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
403 goto err_gpiochip_add;
404 }
405
406 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
407 if (irq_base < 0) {
408 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
409 chip->irq_base = -1;
410 goto end;
411 }
412 chip->irq_base = irq_base;
413
414 /* Mask all interrupts, but enable them */
415 msk = (1 << gpio_pins[chip->ioh]) - 1;
416 iowrite32(msk, &chip->reg->imask);
417 iowrite32(msk, &chip->reg->ien);
418
419 ret = request_irq(pdev->irq, pch_gpio_handler,
420 IRQF_SHARED, KBUILD_MODNAME, chip);
421 if (ret != 0) {
422 dev_err(&pdev->dev,
423 "%s request_irq failed\n", __func__);
424 goto err_request_irq;
425 }
426
427 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
428
429end:
430 return 0;
431
432err_request_irq:
433 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
434 gpiochip_remove(&chip->gpio);
435
436err_gpiochip_add:
437 pci_iounmap(pdev, chip->base);
438
439err_iomap:
440 pci_release_regions(pdev);
441
442err_request_regions:
443 pci_disable_device(pdev);
444
445err_pci_enable:
446 kfree(chip);
447 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
448 return ret;
449}
450
451static void pch_gpio_remove(struct pci_dev *pdev)
452{
453 struct pch_gpio *chip = pci_get_drvdata(pdev);
454
455 if (chip->irq_base != -1) {
456 free_irq(pdev->irq, chip);
457
458 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
459 }
460
461 gpiochip_remove(&chip->gpio);
462 pci_iounmap(pdev, chip->base);
463 pci_release_regions(pdev);
464 pci_disable_device(pdev);
465 kfree(chip);
466}
467
468#ifdef CONFIG_PM
469static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
470{
471 s32 ret;
472 struct pch_gpio *chip = pci_get_drvdata(pdev);
473 unsigned long flags;
474
475 spin_lock_irqsave(&chip->spinlock, flags);
476 pch_gpio_save_reg_conf(chip);
477 spin_unlock_irqrestore(&chip->spinlock, flags);
478
479 ret = pci_save_state(pdev);
480 if (ret) {
481 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
482 return ret;
483 }
484 pci_disable_device(pdev);
485 pci_set_power_state(pdev, PCI_D0);
486 ret = pci_enable_wake(pdev, PCI_D0, 1);
487 if (ret)
488 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
489
490 return 0;
491}
492
493static int pch_gpio_resume(struct pci_dev *pdev)
494{
495 s32 ret;
496 struct pch_gpio *chip = pci_get_drvdata(pdev);
497 unsigned long flags;
498
499 ret = pci_enable_wake(pdev, PCI_D0, 0);
500
501 pci_set_power_state(pdev, PCI_D0);
502 ret = pci_enable_device(pdev);
503 if (ret) {
504 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
505 return ret;
506 }
507 pci_restore_state(pdev);
508
509 spin_lock_irqsave(&chip->spinlock, flags);
510 iowrite32(0x01, &chip->reg->reset);
511 iowrite32(0x00, &chip->reg->reset);
512 pch_gpio_restore_reg_conf(chip);
513 spin_unlock_irqrestore(&chip->spinlock, flags);
514
515 return 0;
516}
517#else
518#define pch_gpio_suspend NULL
519#define pch_gpio_resume NULL
520#endif
521
522#define PCI_VENDOR_ID_ROHM 0x10DB
523static const struct pci_device_id pch_gpio_pcidev_id[] = {
524 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
525 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
526 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
527 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
528 { 0, }
529};
530MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
531
532static struct pci_driver pch_gpio_driver = {
533 .name = "pch_gpio",
534 .id_table = pch_gpio_pcidev_id,
535 .probe = pch_gpio_probe,
536 .remove = pch_gpio_remove,
537 .suspend = pch_gpio_suspend,
538 .resume = pch_gpio_resume
539};
540
541module_pci_driver(pch_gpio_driver);
542
543MODULE_DESCRIPTION("PCH GPIO PCI Driver");
544MODULE_LICENSE("GPL");