1/*
  2 * Driver for the Synopsys DesignWare AHB DMA Controller
  3 *
  4 * Copyright (C) 2005-2007 Atmel Corporation
  5 * Copyright (C) 2010-2011 ST Microelectronics
  6 *
  7 * This program is free software; you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License version 2 as
  9 * published by the Free Software Foundation.
 10 */
 11
 12#include <linux/dw_dmac.h>
 13
 14#define DW_DMA_MAX_NR_CHANNELS	8
 15
 16/*
 17 * Redefine this macro to handle differences between 32- and 64-bit
 18 * addressing, big vs. little endian, etc.
 19 */
 20#define DW_REG(name)		u32 name; u32 __pad_##name
 21
 22/* Hardware register definitions. */
 23struct dw_dma_chan_regs {
 24	DW_REG(SAR);		/* Source Address Register */
 25	DW_REG(DAR);		/* Destination Address Register */
 26	DW_REG(LLP);		/* Linked List Pointer */
 27	u32	CTL_LO;		/* Control Register Low */
 28	u32	CTL_HI;		/* Control Register High */
 29	DW_REG(SSTAT);
 30	DW_REG(DSTAT);
 31	DW_REG(SSTATAR);
 32	DW_REG(DSTATAR);
 33	u32	CFG_LO;		/* Configuration Register Low */
 34	u32	CFG_HI;		/* Configuration Register High */
 35	DW_REG(SGR);
 36	DW_REG(DSR);
 37};
 38
 39struct dw_dma_irq_regs {
 40	DW_REG(XFER);
 41	DW_REG(BLOCK);
 42	DW_REG(SRC_TRAN);
 43	DW_REG(DST_TRAN);
 44	DW_REG(ERROR);
 45};
 46
 47struct dw_dma_regs {
 48	/* per-channel registers */
 49	struct dw_dma_chan_regs	CHAN[DW_DMA_MAX_NR_CHANNELS];
 50
 51	/* irq handling */
 52	struct dw_dma_irq_regs	RAW;		/* r */
 53	struct dw_dma_irq_regs	STATUS;		/* r (raw & mask) */
 54	struct dw_dma_irq_regs	MASK;		/* rw (set = irq enabled) */
 55	struct dw_dma_irq_regs	CLEAR;		/* w (ack, affects "raw") */
 56
 57	DW_REG(STATUS_INT);			/* r */
 58
 59	/* software handshaking */
 60	DW_REG(REQ_SRC);
 61	DW_REG(REQ_DST);
 62	DW_REG(SGL_REQ_SRC);
 63	DW_REG(SGL_REQ_DST);
 64	DW_REG(LAST_SRC);
 65	DW_REG(LAST_DST);
 66
 67	/* miscellaneous */
 68	DW_REG(CFG);
 69	DW_REG(CH_EN);
 70	DW_REG(ID);
 71	DW_REG(TEST);
 72
 73	/* optional encoded params, 0x3c8..0x3 */
 74};
 75
 76/* Bitfields in CTL_LO */
 77#define DWC_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
 78#define DWC_CTLL_DST_WIDTH(n)	((n)<<1)	/* bytes per element */
 79#define DWC_CTLL_SRC_WIDTH(n)	((n)<<4)
 80#define DWC_CTLL_DST_INC	(0<<7)		/* DAR update/not */
 81#define DWC_CTLL_DST_DEC	(1<<7)
 82#define DWC_CTLL_DST_FIX	(2<<7)
 83#define DWC_CTLL_SRC_INC	(0<<7)		/* SAR update/not */
 84#define DWC_CTLL_SRC_DEC	(1<<9)
 85#define DWC_CTLL_SRC_FIX	(2<<9)
 86#define DWC_CTLL_DST_MSIZE(n)	((n)<<11)	/* burst, #elements */
 87#define DWC_CTLL_SRC_MSIZE(n)	((n)<<14)
 88#define DWC_CTLL_S_GATH_EN	(1 << 17)	/* src gather, !FIX */
 89#define DWC_CTLL_D_SCAT_EN	(1 << 18)	/* dst scatter, !FIX */
 90#define DWC_CTLL_FC(n)		((n) << 20)
 91#define DWC_CTLL_FC_M2M		(0 << 20)	/* mem-to-mem */
 92#define DWC_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
 93#define DWC_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
 94#define DWC_CTLL_FC_P2P		(3 << 20)	/* periph-to-periph */
 95/* plus 4 transfer types for peripheral-as-flow-controller */
 96#define DWC_CTLL_DMS(n)		((n)<<23)	/* dst master select */
 97#define DWC_CTLL_SMS(n)		((n)<<25)	/* src master select */
 98#define DWC_CTLL_LLP_D_EN	(1 << 27)	/* dest block chain */
 99#define DWC_CTLL_LLP_S_EN	(1 << 28)	/* src block chain */
100
101/* Bitfields in CTL_HI */
102#define DWC_CTLH_DONE		0x00001000
103#define DWC_CTLH_BLOCK_TS_MASK	0x00000fff
104
105/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
106#define DWC_CFGL_CH_PRIOR_MASK	(0x7 << 5)	/* priority mask */
107#define DWC_CFGL_CH_PRIOR(x)	((x) << 5)	/* priority */
108#define DWC_CFGL_CH_SUSP	(1 << 8)	/* pause xfer */
109#define DWC_CFGL_FIFO_EMPTY	(1 << 9)	/* pause xfer */
110#define DWC_CFGL_HS_DST		(1 << 10)	/* handshake w/dst */
111#define DWC_CFGL_HS_SRC		(1 << 11)	/* handshake w/src */
112#define DWC_CFGL_MAX_BURST(x)	((x) << 20)
113#define DWC_CFGL_RELOAD_SAR	(1 << 30)
114#define DWC_CFGL_RELOAD_DAR	(1 << 31)
115
116/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
117#define DWC_CFGH_DS_UPD_EN	(1 << 5)
118#define DWC_CFGH_SS_UPD_EN	(1 << 6)
119
120/* Bitfields in SGR */
121#define DWC_SGR_SGI(x)		((x) << 0)
122#define DWC_SGR_SGC(x)		((x) << 20)
123
124/* Bitfields in DSR */
125#define DWC_DSR_DSI(x)		((x) << 0)
126#define DWC_DSR_DSC(x)		((x) << 20)
127
128/* Bitfields in CFG */
129#define DW_CFG_DMA_EN		(1 << 0)
130
131#define DW_REGLEN		0x400
132
133enum dw_dmac_flags {
134	DW_DMA_IS_CYCLIC = 0,
135};
136
137struct dw_dma_chan {
138	struct dma_chan		chan;
139	void __iomem		*ch_regs;
140	u8			mask;
141	u8			priority;
142	bool			paused;
143
144	spinlock_t		lock;
145
146	/* these other elements are all protected by lock */
147	unsigned long		flags;
148	dma_cookie_t		completed;
149	struct list_head	active_list;
150	struct list_head	queue;
151	struct list_head	free_list;
152	struct dw_cyclic_desc	*cdesc;
153
154	unsigned int		descs_allocated;
155};
156
157static inline struct dw_dma_chan_regs __iomem *
158__dwc_regs(struct dw_dma_chan *dwc)
159{
160	return dwc->ch_regs;
161}
162
163#define channel_readl(dwc, name) \
164	readl(&(__dwc_regs(dwc)->name))
165#define channel_writel(dwc, name, val) \
166	writel((val), &(__dwc_regs(dwc)->name))
167
168static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
169{
170	return container_of(chan, struct dw_dma_chan, chan);
171}
172
173struct dw_dma {
174	struct dma_device	dma;
175	void __iomem		*regs;
176	struct tasklet_struct	tasklet;
177	struct clk		*clk;
178
179	u8			all_chan_mask;
180
181	struct dw_dma_chan	chan[0];
182};
183
184static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
185{
186	return dw->regs;
187}
188
189#define dma_readl(dw, name) \
190	readl(&(__dw_regs(dw)->name))
191#define dma_writel(dw, name, val) \
192	writel((val), &(__dw_regs(dw)->name))
193
194#define channel_set_bit(dw, reg, mask) \
195	dma_writel(dw, reg, ((mask) << 8) | (mask))
196#define channel_clear_bit(dw, reg, mask) \
197	dma_writel(dw, reg, ((mask) << 8) | 0)
198
199static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
200{
201	return container_of(ddev, struct dw_dma, dma);
202}
203
204/* LLI == Linked List Item; a.k.a. DMA block descriptor */
205struct dw_lli {
206	/* values that are not changed by hardware */
207	dma_addr_t	sar;
208	dma_addr_t	dar;
209	dma_addr_t	llp;		/* chain to next lli */
210	u32		ctllo;
211	/* values that may get written back: */
212	u32		ctlhi;
213	/* sstat and dstat can snapshot peripheral register state.
214	 * silicon config may discard either or both...
215	 */
216	u32		sstat;
217	u32		dstat;
218};
219
220struct dw_desc {
221	/* FIRST values the hardware uses */
222	struct dw_lli			lli;
223
224	/* THEN values for driver housekeeping */
225	struct list_head		desc_node;
226	struct list_head		tx_list;
227	struct dma_async_tx_descriptor	txd;
228	size_t				len;
229};
230
231static inline struct dw_desc *
232txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
233{
234	return container_of(txd, struct dw_desc, txd);
235}