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1#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
5#include <linux/prctl.h>
6#include <linux/slab.h>
7#include <linux/sched.h>
8#include <linux/module.h>
9#include <linux/pm.h>
10#include <linux/clockchips.h>
11#include <linux/random.h>
12#include <linux/user-return-notifier.h>
13#include <linux/dmi.h>
14#include <linux/utsname.h>
15#include <trace/events/power.h>
16#include <linux/hw_breakpoint.h>
17#include <asm/cpu.h>
18#include <asm/system.h>
19#include <asm/apic.h>
20#include <asm/syscalls.h>
21#include <asm/idle.h>
22#include <asm/uaccess.h>
23#include <asm/i387.h>
24#include <asm/debugreg.h>
25
26struct kmem_cache *task_xstate_cachep;
27EXPORT_SYMBOL_GPL(task_xstate_cachep);
28
29int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
30{
31 int ret;
32
33 *dst = *src;
34 if (fpu_allocated(&src->thread.fpu)) {
35 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
36 ret = fpu_alloc(&dst->thread.fpu);
37 if (ret)
38 return ret;
39 fpu_copy(&dst->thread.fpu, &src->thread.fpu);
40 }
41 return 0;
42}
43
44void free_thread_xstate(struct task_struct *tsk)
45{
46 fpu_free(&tsk->thread.fpu);
47}
48
49void free_thread_info(struct thread_info *ti)
50{
51 free_thread_xstate(ti->task);
52 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
53}
54
55void arch_task_cache_init(void)
56{
57 task_xstate_cachep =
58 kmem_cache_create("task_xstate", xstate_size,
59 __alignof__(union thread_xstate),
60 SLAB_PANIC | SLAB_NOTRACK, NULL);
61}
62
63/*
64 * Free current thread data structures etc..
65 */
66void exit_thread(void)
67{
68 struct task_struct *me = current;
69 struct thread_struct *t = &me->thread;
70 unsigned long *bp = t->io_bitmap_ptr;
71
72 if (bp) {
73 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
74
75 t->io_bitmap_ptr = NULL;
76 clear_thread_flag(TIF_IO_BITMAP);
77 /*
78 * Careful, clear this in the TSS too:
79 */
80 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
81 t->io_bitmap_max = 0;
82 put_cpu();
83 kfree(bp);
84 }
85}
86
87void show_regs(struct pt_regs *regs)
88{
89 show_registers(regs);
90 show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs), 0);
91}
92
93void show_regs_common(void)
94{
95 const char *vendor, *product, *board;
96
97 vendor = dmi_get_system_info(DMI_SYS_VENDOR);
98 if (!vendor)
99 vendor = "";
100 product = dmi_get_system_info(DMI_PRODUCT_NAME);
101 if (!product)
102 product = "";
103
104 /* Board Name is optional */
105 board = dmi_get_system_info(DMI_BOARD_NAME);
106
107 printk(KERN_CONT "\n");
108 printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
109 current->pid, current->comm, print_tainted(),
110 init_utsname()->release,
111 (int)strcspn(init_utsname()->version, " "),
112 init_utsname()->version);
113 printk(KERN_CONT " %s %s", vendor, product);
114 if (board)
115 printk(KERN_CONT "/%s", board);
116 printk(KERN_CONT "\n");
117}
118
119void flush_thread(void)
120{
121 struct task_struct *tsk = current;
122
123 flush_ptrace_hw_breakpoint(tsk);
124 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
125 /*
126 * Forget coprocessor state..
127 */
128 tsk->fpu_counter = 0;
129 clear_fpu(tsk);
130 clear_used_math();
131}
132
133static void hard_disable_TSC(void)
134{
135 write_cr4(read_cr4() | X86_CR4_TSD);
136}
137
138void disable_TSC(void)
139{
140 preempt_disable();
141 if (!test_and_set_thread_flag(TIF_NOTSC))
142 /*
143 * Must flip the CPU state synchronously with
144 * TIF_NOTSC in the current running context.
145 */
146 hard_disable_TSC();
147 preempt_enable();
148}
149
150static void hard_enable_TSC(void)
151{
152 write_cr4(read_cr4() & ~X86_CR4_TSD);
153}
154
155static void enable_TSC(void)
156{
157 preempt_disable();
158 if (test_and_clear_thread_flag(TIF_NOTSC))
159 /*
160 * Must flip the CPU state synchronously with
161 * TIF_NOTSC in the current running context.
162 */
163 hard_enable_TSC();
164 preempt_enable();
165}
166
167int get_tsc_mode(unsigned long adr)
168{
169 unsigned int val;
170
171 if (test_thread_flag(TIF_NOTSC))
172 val = PR_TSC_SIGSEGV;
173 else
174 val = PR_TSC_ENABLE;
175
176 return put_user(val, (unsigned int __user *)adr);
177}
178
179int set_tsc_mode(unsigned int val)
180{
181 if (val == PR_TSC_SIGSEGV)
182 disable_TSC();
183 else if (val == PR_TSC_ENABLE)
184 enable_TSC();
185 else
186 return -EINVAL;
187
188 return 0;
189}
190
191void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
192 struct tss_struct *tss)
193{
194 struct thread_struct *prev, *next;
195
196 prev = &prev_p->thread;
197 next = &next_p->thread;
198
199 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
200 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
201 unsigned long debugctl = get_debugctlmsr();
202
203 debugctl &= ~DEBUGCTLMSR_BTF;
204 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
205 debugctl |= DEBUGCTLMSR_BTF;
206
207 update_debugctlmsr(debugctl);
208 }
209
210 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
211 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
212 /* prev and next are different */
213 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
214 hard_disable_TSC();
215 else
216 hard_enable_TSC();
217 }
218
219 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
220 /*
221 * Copy the relevant range of the IO bitmap.
222 * Normally this is 128 bytes or less:
223 */
224 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
225 max(prev->io_bitmap_max, next->io_bitmap_max));
226 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
227 /*
228 * Clear any possible leftover bits:
229 */
230 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
231 }
232 propagate_user_return_notify(prev_p, next_p);
233}
234
235int sys_fork(struct pt_regs *regs)
236{
237 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
238}
239
240/*
241 * This is trivial, and on the face of it looks like it
242 * could equally well be done in user mode.
243 *
244 * Not so, for quite unobvious reasons - register pressure.
245 * In user mode vfork() cannot have a stack frame, and if
246 * done by calling the "clone()" system call directly, you
247 * do not have enough call-clobbered registers to hold all
248 * the information you need.
249 */
250int sys_vfork(struct pt_regs *regs)
251{
252 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
253 NULL, NULL);
254}
255
256long
257sys_clone(unsigned long clone_flags, unsigned long newsp,
258 void __user *parent_tid, void __user *child_tid, struct pt_regs *regs)
259{
260 if (!newsp)
261 newsp = regs->sp;
262 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
263}
264
265/*
266 * This gets run with %si containing the
267 * function to call, and %di containing
268 * the "args".
269 */
270extern void kernel_thread_helper(void);
271
272/*
273 * Create a kernel thread
274 */
275int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
276{
277 struct pt_regs regs;
278
279 memset(®s, 0, sizeof(regs));
280
281 regs.si = (unsigned long) fn;
282 regs.di = (unsigned long) arg;
283
284#ifdef CONFIG_X86_32
285 regs.ds = __USER_DS;
286 regs.es = __USER_DS;
287 regs.fs = __KERNEL_PERCPU;
288 regs.gs = __KERNEL_STACK_CANARY;
289#else
290 regs.ss = __KERNEL_DS;
291#endif
292
293 regs.orig_ax = -1;
294 regs.ip = (unsigned long) kernel_thread_helper;
295 regs.cs = __KERNEL_CS | get_kernel_rpl();
296 regs.flags = X86_EFLAGS_IF | 0x2;
297
298 /* Ok, create the new process.. */
299 return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0, NULL, NULL);
300}
301EXPORT_SYMBOL(kernel_thread);
302
303/*
304 * sys_execve() executes a new program.
305 */
306long sys_execve(const char __user *name,
307 const char __user *const __user *argv,
308 const char __user *const __user *envp, struct pt_regs *regs)
309{
310 long error;
311 char *filename;
312
313 filename = getname(name);
314 error = PTR_ERR(filename);
315 if (IS_ERR(filename))
316 return error;
317 error = do_execve(filename, argv, envp, regs);
318
319#ifdef CONFIG_X86_32
320 if (error == 0) {
321 /* Make sure we don't return using sysenter.. */
322 set_thread_flag(TIF_IRET);
323 }
324#endif
325
326 putname(filename);
327 return error;
328}
329
330/*
331 * Idle related variables and functions
332 */
333unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
334EXPORT_SYMBOL(boot_option_idle_override);
335
336/*
337 * Powermanagement idle function, if any..
338 */
339void (*pm_idle)(void);
340#ifdef CONFIG_APM_MODULE
341EXPORT_SYMBOL(pm_idle);
342#endif
343
344#ifdef CONFIG_X86_32
345/*
346 * This halt magic was a workaround for ancient floppy DMA
347 * wreckage. It should be safe to remove.
348 */
349static int hlt_counter;
350void disable_hlt(void)
351{
352 hlt_counter++;
353}
354EXPORT_SYMBOL(disable_hlt);
355
356void enable_hlt(void)
357{
358 hlt_counter--;
359}
360EXPORT_SYMBOL(enable_hlt);
361
362static inline int hlt_use_halt(void)
363{
364 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
365}
366#else
367static inline int hlt_use_halt(void)
368{
369 return 1;
370}
371#endif
372
373/*
374 * We use this if we don't have any better
375 * idle routine..
376 */
377void default_idle(void)
378{
379 if (hlt_use_halt()) {
380 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
381 trace_cpu_idle(1, smp_processor_id());
382 current_thread_info()->status &= ~TS_POLLING;
383 /*
384 * TS_POLLING-cleared state must be visible before we
385 * test NEED_RESCHED:
386 */
387 smp_mb();
388
389 if (!need_resched())
390 safe_halt(); /* enables interrupts racelessly */
391 else
392 local_irq_enable();
393 current_thread_info()->status |= TS_POLLING;
394 trace_power_end(smp_processor_id());
395 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
396 } else {
397 local_irq_enable();
398 /* loop is done by the caller */
399 cpu_relax();
400 }
401}
402#ifdef CONFIG_APM_MODULE
403EXPORT_SYMBOL(default_idle);
404#endif
405
406void stop_this_cpu(void *dummy)
407{
408 local_irq_disable();
409 /*
410 * Remove this CPU:
411 */
412 set_cpu_online(smp_processor_id(), false);
413 disable_local_APIC();
414
415 for (;;) {
416 if (hlt_works(smp_processor_id()))
417 halt();
418 }
419}
420
421static void do_nothing(void *unused)
422{
423}
424
425/*
426 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
427 * pm_idle and update to new pm_idle value. Required while changing pm_idle
428 * handler on SMP systems.
429 *
430 * Caller must have changed pm_idle to the new value before the call. Old
431 * pm_idle value will not be used by any CPU after the return of this function.
432 */
433void cpu_idle_wait(void)
434{
435 smp_mb();
436 /* kick all the CPUs so that they exit out of pm_idle */
437 smp_call_function(do_nothing, NULL, 1);
438}
439EXPORT_SYMBOL_GPL(cpu_idle_wait);
440
441/* Default MONITOR/MWAIT with no hints, used for default C1 state */
442static void mwait_idle(void)
443{
444 if (!need_resched()) {
445 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
446 trace_cpu_idle(1, smp_processor_id());
447 if (this_cpu_has(X86_FEATURE_CLFLUSH_MONITOR))
448 clflush((void *)¤t_thread_info()->flags);
449
450 __monitor((void *)¤t_thread_info()->flags, 0, 0);
451 smp_mb();
452 if (!need_resched())
453 __sti_mwait(0, 0);
454 else
455 local_irq_enable();
456 trace_power_end(smp_processor_id());
457 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
458 } else
459 local_irq_enable();
460}
461
462/*
463 * On SMP it's slightly faster (but much more power-consuming!)
464 * to poll the ->work.need_resched flag instead of waiting for the
465 * cross-CPU IPI to arrive. Use this option with caution.
466 */
467static void poll_idle(void)
468{
469 trace_power_start(POWER_CSTATE, 0, smp_processor_id());
470 trace_cpu_idle(0, smp_processor_id());
471 local_irq_enable();
472 while (!need_resched())
473 cpu_relax();
474 trace_power_end(smp_processor_id());
475 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
476}
477
478/*
479 * mwait selection logic:
480 *
481 * It depends on the CPU. For AMD CPUs that support MWAIT this is
482 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
483 * then depend on a clock divisor and current Pstate of the core. If
484 * all cores of a processor are in halt state (C1) the processor can
485 * enter the C1E (C1 enhanced) state. If mwait is used this will never
486 * happen.
487 *
488 * idle=mwait overrides this decision and forces the usage of mwait.
489 */
490
491#define MWAIT_INFO 0x05
492#define MWAIT_ECX_EXTENDED_INFO 0x01
493#define MWAIT_EDX_C1 0xf0
494
495int mwait_usable(const struct cpuinfo_x86 *c)
496{
497 u32 eax, ebx, ecx, edx;
498
499 if (boot_option_idle_override == IDLE_FORCE_MWAIT)
500 return 1;
501
502 if (c->cpuid_level < MWAIT_INFO)
503 return 0;
504
505 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
506 /* Check, whether EDX has extended info about MWAIT */
507 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
508 return 1;
509
510 /*
511 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
512 * C1 supports MWAIT
513 */
514 return (edx & MWAIT_EDX_C1);
515}
516
517bool amd_e400_c1e_detected;
518EXPORT_SYMBOL(amd_e400_c1e_detected);
519
520static cpumask_var_t amd_e400_c1e_mask;
521
522void amd_e400_remove_cpu(int cpu)
523{
524 if (amd_e400_c1e_mask != NULL)
525 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
526}
527
528/*
529 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
530 * pending message MSR. If we detect C1E, then we handle it the same
531 * way as C3 power states (local apic timer and TSC stop)
532 */
533static void amd_e400_idle(void)
534{
535 if (need_resched())
536 return;
537
538 if (!amd_e400_c1e_detected) {
539 u32 lo, hi;
540
541 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
542
543 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
544 amd_e400_c1e_detected = true;
545 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
546 mark_tsc_unstable("TSC halt in AMD C1E");
547 printk(KERN_INFO "System has AMD C1E enabled\n");
548 }
549 }
550
551 if (amd_e400_c1e_detected) {
552 int cpu = smp_processor_id();
553
554 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
555 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
556 /*
557 * Force broadcast so ACPI can not interfere.
558 */
559 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
560 &cpu);
561 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
562 cpu);
563 }
564 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
565
566 default_idle();
567
568 /*
569 * The switch back from broadcast mode needs to be
570 * called with interrupts disabled.
571 */
572 local_irq_disable();
573 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
574 local_irq_enable();
575 } else
576 default_idle();
577}
578
579void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
580{
581#ifdef CONFIG_SMP
582 if (pm_idle == poll_idle && smp_num_siblings > 1) {
583 printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
584 " performance may degrade.\n");
585 }
586#endif
587 if (pm_idle)
588 return;
589
590 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
591 /*
592 * One CPU supports mwait => All CPUs supports mwait
593 */
594 printk(KERN_INFO "using mwait in idle threads.\n");
595 pm_idle = mwait_idle;
596 } else if (cpu_has_amd_erratum(amd_erratum_400)) {
597 /* E400: APIC timer interrupt does not wake up CPU from C1e */
598 printk(KERN_INFO "using AMD E400 aware idle routine\n");
599 pm_idle = amd_e400_idle;
600 } else
601 pm_idle = default_idle;
602}
603
604void __init init_amd_e400_c1e_mask(void)
605{
606 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
607 if (pm_idle == amd_e400_idle)
608 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
609}
610
611static int __init idle_setup(char *str)
612{
613 if (!str)
614 return -EINVAL;
615
616 if (!strcmp(str, "poll")) {
617 printk("using polling idle threads.\n");
618 pm_idle = poll_idle;
619 boot_option_idle_override = IDLE_POLL;
620 } else if (!strcmp(str, "mwait")) {
621 boot_option_idle_override = IDLE_FORCE_MWAIT;
622 WARN_ONCE(1, "\"idle=mwait\" will be removed in 2012\n");
623 } else if (!strcmp(str, "halt")) {
624 /*
625 * When the boot option of idle=halt is added, halt is
626 * forced to be used for CPU idle. In such case CPU C2/C3
627 * won't be used again.
628 * To continue to load the CPU idle driver, don't touch
629 * the boot_option_idle_override.
630 */
631 pm_idle = default_idle;
632 boot_option_idle_override = IDLE_HALT;
633 } else if (!strcmp(str, "nomwait")) {
634 /*
635 * If the boot option of "idle=nomwait" is added,
636 * it means that mwait will be disabled for CPU C2/C3
637 * states. In such case it won't touch the variable
638 * of boot_option_idle_override.
639 */
640 boot_option_idle_override = IDLE_NOMWAIT;
641 } else
642 return -1;
643
644 return 0;
645}
646early_param("idle", idle_setup);
647
648unsigned long arch_align_stack(unsigned long sp)
649{
650 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
651 sp -= get_random_int() % 8192;
652 return sp & ~0xf;
653}
654
655unsigned long arch_randomize_brk(struct mm_struct *mm)
656{
657 unsigned long range_end = mm->brk + 0x02000000;
658 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
659}
660
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/errno.h>
4#include <linux/kernel.h>
5#include <linux/mm.h>
6#include <linux/smp.h>
7#include <linux/prctl.h>
8#include <linux/slab.h>
9#include <linux/sched.h>
10#include <linux/module.h>
11#include <linux/pm.h>
12#include <linux/tick.h>
13#include <linux/random.h>
14#include <linux/user-return-notifier.h>
15#include <linux/dmi.h>
16#include <linux/utsname.h>
17#include <linux/stackprotector.h>
18#include <linux/tick.h>
19#include <linux/cpuidle.h>
20#include <trace/events/power.h>
21#include <linux/hw_breakpoint.h>
22#include <asm/cpu.h>
23#include <asm/apic.h>
24#include <asm/syscalls.h>
25#include <asm/idle.h>
26#include <asm/uaccess.h>
27#include <asm/mwait.h>
28#include <asm/fpu/internal.h>
29#include <asm/debugreg.h>
30#include <asm/nmi.h>
31#include <asm/tlbflush.h>
32#include <asm/mce.h>
33#include <asm/vm86.h>
34
35/*
36 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
37 * no more per-task TSS's. The TSS size is kept cacheline-aligned
38 * so they are allowed to end up in the .data..cacheline_aligned
39 * section. Since TSS's are completely CPU-local, we want them
40 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
41 */
42__visible DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss) = {
43 .x86_tss = {
44 .sp0 = TOP_OF_INIT_STACK,
45#ifdef CONFIG_X86_32
46 .ss0 = __KERNEL_DS,
47 .ss1 = __KERNEL_CS,
48 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
49#endif
50 },
51#ifdef CONFIG_X86_32
52 /*
53 * Note that the .io_bitmap member must be extra-big. This is because
54 * the CPU will access an additional byte beyond the end of the IO
55 * permission bitmap. The extra byte must be all 1 bits, and must
56 * be within the limit.
57 */
58 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 },
59#endif
60#ifdef CONFIG_X86_32
61 .SYSENTER_stack_canary = STACK_END_MAGIC,
62#endif
63};
64EXPORT_PER_CPU_SYMBOL(cpu_tss);
65
66#ifdef CONFIG_X86_64
67static DEFINE_PER_CPU(unsigned char, is_idle);
68static ATOMIC_NOTIFIER_HEAD(idle_notifier);
69
70void idle_notifier_register(struct notifier_block *n)
71{
72 atomic_notifier_chain_register(&idle_notifier, n);
73}
74EXPORT_SYMBOL_GPL(idle_notifier_register);
75
76void idle_notifier_unregister(struct notifier_block *n)
77{
78 atomic_notifier_chain_unregister(&idle_notifier, n);
79}
80EXPORT_SYMBOL_GPL(idle_notifier_unregister);
81#endif
82
83/*
84 * this gets called so that we can store lazy state into memory and copy the
85 * current task into the new thread.
86 */
87int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88{
89 memcpy(dst, src, arch_task_struct_size);
90#ifdef CONFIG_VM86
91 dst->thread.vm86 = NULL;
92#endif
93
94 return fpu__copy(&dst->thread.fpu, &src->thread.fpu);
95}
96
97/*
98 * Free current thread data structures etc..
99 */
100void exit_thread(void)
101{
102 struct task_struct *me = current;
103 struct thread_struct *t = &me->thread;
104 unsigned long *bp = t->io_bitmap_ptr;
105 struct fpu *fpu = &t->fpu;
106
107 if (bp) {
108 struct tss_struct *tss = &per_cpu(cpu_tss, get_cpu());
109
110 t->io_bitmap_ptr = NULL;
111 clear_thread_flag(TIF_IO_BITMAP);
112 /*
113 * Careful, clear this in the TSS too:
114 */
115 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
116 t->io_bitmap_max = 0;
117 put_cpu();
118 kfree(bp);
119 }
120
121 free_vm86(t);
122
123 fpu__drop(fpu);
124}
125
126void flush_thread(void)
127{
128 struct task_struct *tsk = current;
129
130 flush_ptrace_hw_breakpoint(tsk);
131 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
132
133 fpu__clear(&tsk->thread.fpu);
134}
135
136static void hard_disable_TSC(void)
137{
138 cr4_set_bits(X86_CR4_TSD);
139}
140
141void disable_TSC(void)
142{
143 preempt_disable();
144 if (!test_and_set_thread_flag(TIF_NOTSC))
145 /*
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
148 */
149 hard_disable_TSC();
150 preempt_enable();
151}
152
153static void hard_enable_TSC(void)
154{
155 cr4_clear_bits(X86_CR4_TSD);
156}
157
158static void enable_TSC(void)
159{
160 preempt_disable();
161 if (test_and_clear_thread_flag(TIF_NOTSC))
162 /*
163 * Must flip the CPU state synchronously with
164 * TIF_NOTSC in the current running context.
165 */
166 hard_enable_TSC();
167 preempt_enable();
168}
169
170int get_tsc_mode(unsigned long adr)
171{
172 unsigned int val;
173
174 if (test_thread_flag(TIF_NOTSC))
175 val = PR_TSC_SIGSEGV;
176 else
177 val = PR_TSC_ENABLE;
178
179 return put_user(val, (unsigned int __user *)adr);
180}
181
182int set_tsc_mode(unsigned int val)
183{
184 if (val == PR_TSC_SIGSEGV)
185 disable_TSC();
186 else if (val == PR_TSC_ENABLE)
187 enable_TSC();
188 else
189 return -EINVAL;
190
191 return 0;
192}
193
194void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
195 struct tss_struct *tss)
196{
197 struct thread_struct *prev, *next;
198
199 prev = &prev_p->thread;
200 next = &next_p->thread;
201
202 if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
203 test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
204 unsigned long debugctl = get_debugctlmsr();
205
206 debugctl &= ~DEBUGCTLMSR_BTF;
207 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
208 debugctl |= DEBUGCTLMSR_BTF;
209
210 update_debugctlmsr(debugctl);
211 }
212
213 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
214 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
215 /* prev and next are different */
216 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
217 hard_disable_TSC();
218 else
219 hard_enable_TSC();
220 }
221
222 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
223 /*
224 * Copy the relevant range of the IO bitmap.
225 * Normally this is 128 bytes or less:
226 */
227 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
228 max(prev->io_bitmap_max, next->io_bitmap_max));
229 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
230 /*
231 * Clear any possible leftover bits:
232 */
233 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
234 }
235 propagate_user_return_notify(prev_p, next_p);
236}
237
238/*
239 * Idle related variables and functions
240 */
241unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
242EXPORT_SYMBOL(boot_option_idle_override);
243
244static void (*x86_idle)(void);
245
246#ifndef CONFIG_SMP
247static inline void play_dead(void)
248{
249 BUG();
250}
251#endif
252
253#ifdef CONFIG_X86_64
254void enter_idle(void)
255{
256 this_cpu_write(is_idle, 1);
257 atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
258}
259
260static void __exit_idle(void)
261{
262 if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
263 return;
264 atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
265}
266
267/* Called from interrupts to signify idle end */
268void exit_idle(void)
269{
270 /* idle loop has pid 0 */
271 if (current->pid)
272 return;
273 __exit_idle();
274}
275#endif
276
277void arch_cpu_idle_enter(void)
278{
279 local_touch_nmi();
280 enter_idle();
281}
282
283void arch_cpu_idle_exit(void)
284{
285 __exit_idle();
286}
287
288void arch_cpu_idle_dead(void)
289{
290 play_dead();
291}
292
293/*
294 * Called from the generic idle code.
295 */
296void arch_cpu_idle(void)
297{
298 x86_idle();
299}
300
301/*
302 * We use this if we don't have any better idle routine..
303 */
304void default_idle(void)
305{
306 trace_cpu_idle_rcuidle(1, smp_processor_id());
307 safe_halt();
308 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
309}
310#ifdef CONFIG_APM_MODULE
311EXPORT_SYMBOL(default_idle);
312#endif
313
314#ifdef CONFIG_XEN
315bool xen_set_default_idle(void)
316{
317 bool ret = !!x86_idle;
318
319 x86_idle = default_idle;
320
321 return ret;
322}
323#endif
324void stop_this_cpu(void *dummy)
325{
326 local_irq_disable();
327 /*
328 * Remove this CPU:
329 */
330 set_cpu_online(smp_processor_id(), false);
331 disable_local_APIC();
332 mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
333
334 for (;;)
335 halt();
336}
337
338bool amd_e400_c1e_detected;
339EXPORT_SYMBOL(amd_e400_c1e_detected);
340
341static cpumask_var_t amd_e400_c1e_mask;
342
343void amd_e400_remove_cpu(int cpu)
344{
345 if (amd_e400_c1e_mask != NULL)
346 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
347}
348
349/*
350 * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
351 * pending message MSR. If we detect C1E, then we handle it the same
352 * way as C3 power states (local apic timer and TSC stop)
353 */
354static void amd_e400_idle(void)
355{
356 if (!amd_e400_c1e_detected) {
357 u32 lo, hi;
358
359 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
360
361 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
362 amd_e400_c1e_detected = true;
363 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
364 mark_tsc_unstable("TSC halt in AMD C1E");
365 pr_info("System has AMD C1E enabled\n");
366 }
367 }
368
369 if (amd_e400_c1e_detected) {
370 int cpu = smp_processor_id();
371
372 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
373 cpumask_set_cpu(cpu, amd_e400_c1e_mask);
374 /* Force broadcast so ACPI can not interfere. */
375 tick_broadcast_force();
376 pr_info("Switch to broadcast mode on CPU%d\n", cpu);
377 }
378 tick_broadcast_enter();
379
380 default_idle();
381
382 /*
383 * The switch back from broadcast mode needs to be
384 * called with interrupts disabled.
385 */
386 local_irq_disable();
387 tick_broadcast_exit();
388 local_irq_enable();
389 } else
390 default_idle();
391}
392
393/*
394 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
395 * We can't rely on cpuidle installing MWAIT, because it will not load
396 * on systems that support only C1 -- so the boot default must be MWAIT.
397 *
398 * Some AMD machines are the opposite, they depend on using HALT.
399 *
400 * So for default C1, which is used during boot until cpuidle loads,
401 * use MWAIT-C1 on Intel HW that has it, else use HALT.
402 */
403static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
404{
405 if (c->x86_vendor != X86_VENDOR_INTEL)
406 return 0;
407
408 if (!cpu_has(c, X86_FEATURE_MWAIT))
409 return 0;
410
411 return 1;
412}
413
414/*
415 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
416 * with interrupts enabled and no flags, which is backwards compatible with the
417 * original MWAIT implementation.
418 */
419static void mwait_idle(void)
420{
421 if (!current_set_polling_and_test()) {
422 trace_cpu_idle_rcuidle(1, smp_processor_id());
423 if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
424 mb(); /* quirk */
425 clflush((void *)¤t_thread_info()->flags);
426 mb(); /* quirk */
427 }
428
429 __monitor((void *)¤t_thread_info()->flags, 0, 0);
430 if (!need_resched())
431 __sti_mwait(0, 0);
432 else
433 local_irq_enable();
434 trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
435 } else {
436 local_irq_enable();
437 }
438 __current_clr_polling();
439}
440
441void select_idle_routine(const struct cpuinfo_x86 *c)
442{
443#ifdef CONFIG_SMP
444 if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
445 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
446#endif
447 if (x86_idle || boot_option_idle_override == IDLE_POLL)
448 return;
449
450 if (cpu_has_bug(c, X86_BUG_AMD_APIC_C1E)) {
451 /* E400: APIC timer interrupt does not wake up CPU from C1e */
452 pr_info("using AMD E400 aware idle routine\n");
453 x86_idle = amd_e400_idle;
454 } else if (prefer_mwait_c1_over_halt(c)) {
455 pr_info("using mwait in idle threads\n");
456 x86_idle = mwait_idle;
457 } else
458 x86_idle = default_idle;
459}
460
461void __init init_amd_e400_c1e_mask(void)
462{
463 /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
464 if (x86_idle == amd_e400_idle)
465 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
466}
467
468static int __init idle_setup(char *str)
469{
470 if (!str)
471 return -EINVAL;
472
473 if (!strcmp(str, "poll")) {
474 pr_info("using polling idle threads\n");
475 boot_option_idle_override = IDLE_POLL;
476 cpu_idle_poll_ctrl(true);
477 } else if (!strcmp(str, "halt")) {
478 /*
479 * When the boot option of idle=halt is added, halt is
480 * forced to be used for CPU idle. In such case CPU C2/C3
481 * won't be used again.
482 * To continue to load the CPU idle driver, don't touch
483 * the boot_option_idle_override.
484 */
485 x86_idle = default_idle;
486 boot_option_idle_override = IDLE_HALT;
487 } else if (!strcmp(str, "nomwait")) {
488 /*
489 * If the boot option of "idle=nomwait" is added,
490 * it means that mwait will be disabled for CPU C2/C3
491 * states. In such case it won't touch the variable
492 * of boot_option_idle_override.
493 */
494 boot_option_idle_override = IDLE_NOMWAIT;
495 } else
496 return -1;
497
498 return 0;
499}
500early_param("idle", idle_setup);
501
502unsigned long arch_align_stack(unsigned long sp)
503{
504 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
505 sp -= get_random_int() % 8192;
506 return sp & ~0xf;
507}
508
509unsigned long arch_randomize_brk(struct mm_struct *mm)
510{
511 unsigned long range_end = mm->brk + 0x02000000;
512 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
513}
514
515/*
516 * Called from fs/proc with a reference on @p to find the function
517 * which called into schedule(). This needs to be done carefully
518 * because the task might wake up and we might look at a stack
519 * changing under us.
520 */
521unsigned long get_wchan(struct task_struct *p)
522{
523 unsigned long start, bottom, top, sp, fp, ip;
524 int count = 0;
525
526 if (!p || p == current || p->state == TASK_RUNNING)
527 return 0;
528
529 start = (unsigned long)task_stack_page(p);
530 if (!start)
531 return 0;
532
533 /*
534 * Layout of the stack page:
535 *
536 * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
537 * PADDING
538 * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
539 * stack
540 * ----------- bottom = start + sizeof(thread_info)
541 * thread_info
542 * ----------- start
543 *
544 * The tasks stack pointer points at the location where the
545 * framepointer is stored. The data on the stack is:
546 * ... IP FP ... IP FP
547 *
548 * We need to read FP and IP, so we need to adjust the upper
549 * bound by another unsigned long.
550 */
551 top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
552 top -= 2 * sizeof(unsigned long);
553 bottom = start + sizeof(struct thread_info);
554
555 sp = READ_ONCE(p->thread.sp);
556 if (sp < bottom || sp > top)
557 return 0;
558
559 fp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
560 do {
561 if (fp < bottom || fp > top)
562 return 0;
563 ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
564 if (!in_sched_functions(ip))
565 return ip;
566 fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
567 } while (count++ < 16 && p->state != TASK_RUNNING);
568 return 0;
569}