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1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * A code-rewriter that enables instruction single-stepping.
15 * Derived from iLib's single-stepping code.
16 */
17
18#ifndef __tilegx__ /* Hardware support for single step unavailable. */
19
20/* These functions are only used on the TILE platform */
21#include <linux/slab.h>
22#include <linux/thread_info.h>
23#include <linux/uaccess.h>
24#include <linux/mman.h>
25#include <linux/types.h>
26#include <linux/err.h>
27#include <asm/cacheflush.h>
28#include <asm/opcode-tile.h>
29#include <asm/opcode_constants.h>
30#include <arch/abi.h>
31
32#define signExtend17(val) sign_extend((val), 17)
33#define TILE_X1_MASK (0xffffffffULL << 31)
34
35int unaligned_printk;
36
37static int __init setup_unaligned_printk(char *str)
38{
39 long val;
40 if (strict_strtol(str, 0, &val) != 0)
41 return 0;
42 unaligned_printk = val;
43 pr_info("Printk for each unaligned data accesses is %s\n",
44 unaligned_printk ? "enabled" : "disabled");
45 return 1;
46}
47__setup("unaligned_printk=", setup_unaligned_printk);
48
49unsigned int unaligned_fixup_count;
50
51enum mem_op {
52 MEMOP_NONE,
53 MEMOP_LOAD,
54 MEMOP_STORE,
55 MEMOP_LOAD_POSTINCR,
56 MEMOP_STORE_POSTINCR
57};
58
59static inline tile_bundle_bits set_BrOff_X1(tile_bundle_bits n, s32 offset)
60{
61 tile_bundle_bits result;
62
63 /* mask out the old offset */
64 tile_bundle_bits mask = create_BrOff_X1(-1);
65 result = n & (~mask);
66
67 /* or in the new offset */
68 result |= create_BrOff_X1(offset);
69
70 return result;
71}
72
73static inline tile_bundle_bits move_X1(tile_bundle_bits n, int dest, int src)
74{
75 tile_bundle_bits result;
76 tile_bundle_bits op;
77
78 result = n & (~TILE_X1_MASK);
79
80 op = create_Opcode_X1(SPECIAL_0_OPCODE_X1) |
81 create_RRROpcodeExtension_X1(OR_SPECIAL_0_OPCODE_X1) |
82 create_Dest_X1(dest) |
83 create_SrcB_X1(TREG_ZERO) |
84 create_SrcA_X1(src) ;
85
86 result |= op;
87 return result;
88}
89
90static inline tile_bundle_bits nop_X1(tile_bundle_bits n)
91{
92 return move_X1(n, TREG_ZERO, TREG_ZERO);
93}
94
95static inline tile_bundle_bits addi_X1(
96 tile_bundle_bits n, int dest, int src, int imm)
97{
98 n &= ~TILE_X1_MASK;
99
100 n |= (create_SrcA_X1(src) |
101 create_Dest_X1(dest) |
102 create_Imm8_X1(imm) |
103 create_S_X1(0) |
104 create_Opcode_X1(IMM_0_OPCODE_X1) |
105 create_ImmOpcodeExtension_X1(ADDI_IMM_0_OPCODE_X1));
106
107 return n;
108}
109
110static tile_bundle_bits rewrite_load_store_unaligned(
111 struct single_step_state *state,
112 tile_bundle_bits bundle,
113 struct pt_regs *regs,
114 enum mem_op mem_op,
115 int size, int sign_ext)
116{
117 unsigned char __user *addr;
118 int val_reg, addr_reg, err, val;
119
120 /* Get address and value registers */
121 if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) {
122 addr_reg = get_SrcA_Y2(bundle);
123 val_reg = get_SrcBDest_Y2(bundle);
124 } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
125 addr_reg = get_SrcA_X1(bundle);
126 val_reg = get_Dest_X1(bundle);
127 } else {
128 addr_reg = get_SrcA_X1(bundle);
129 val_reg = get_SrcB_X1(bundle);
130 }
131
132 /*
133 * If registers are not GPRs, don't try to handle it.
134 *
135 * FIXME: we could handle non-GPR loads by getting the real value
136 * from memory, writing it to the single step buffer, using a
137 * temp_reg to hold a pointer to that memory, then executing that
138 * instruction and resetting temp_reg. For non-GPR stores, it's a
139 * little trickier; we could use the single step buffer for that
140 * too, but we'd have to add some more state bits so that we could
141 * call back in here to copy that value to the real target. For
142 * now, we just handle the simple case.
143 */
144 if ((val_reg >= PTREGS_NR_GPRS &&
145 (val_reg != TREG_ZERO ||
146 mem_op == MEMOP_LOAD ||
147 mem_op == MEMOP_LOAD_POSTINCR)) ||
148 addr_reg >= PTREGS_NR_GPRS)
149 return bundle;
150
151 /* If it's aligned, don't handle it specially */
152 addr = (void __user *)regs->regs[addr_reg];
153 if (((unsigned long)addr % size) == 0)
154 return bundle;
155
156#ifndef __LITTLE_ENDIAN
157# error We assume little-endian representation with copy_xx_user size 2 here
158#endif
159 /* Handle unaligned load/store */
160 if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
161 unsigned short val_16;
162 switch (size) {
163 case 2:
164 err = copy_from_user(&val_16, addr, sizeof(val_16));
165 val = sign_ext ? ((short)val_16) : val_16;
166 break;
167 case 4:
168 err = copy_from_user(&val, addr, sizeof(val));
169 break;
170 default:
171 BUG();
172 }
173 if (err == 0) {
174 state->update_reg = val_reg;
175 state->update_value = val;
176 state->update = 1;
177 }
178 } else {
179 val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg];
180 err = copy_to_user(addr, &val, size);
181 }
182
183 if (err) {
184 siginfo_t info = {
185 .si_signo = SIGSEGV,
186 .si_code = SEGV_MAPERR,
187 .si_addr = addr
188 };
189 trace_unhandled_signal("segfault", regs,
190 (unsigned long)addr, SIGSEGV);
191 force_sig_info(info.si_signo, &info, current);
192 return (tile_bundle_bits) 0;
193 }
194
195 if (unaligned_fixup == 0) {
196 siginfo_t info = {
197 .si_signo = SIGBUS,
198 .si_code = BUS_ADRALN,
199 .si_addr = addr
200 };
201 trace_unhandled_signal("unaligned trap", regs,
202 (unsigned long)addr, SIGBUS);
203 force_sig_info(info.si_signo, &info, current);
204 return (tile_bundle_bits) 0;
205 }
206
207 if (unaligned_printk || unaligned_fixup_count == 0) {
208 pr_info("Process %d/%s: PC %#lx: Fixup of"
209 " unaligned %s at %#lx.\n",
210 current->pid, current->comm, regs->pc,
211 (mem_op == MEMOP_LOAD ||
212 mem_op == MEMOP_LOAD_POSTINCR) ?
213 "load" : "store",
214 (unsigned long)addr);
215 if (!unaligned_printk) {
216#define P pr_info
217P("\n");
218P("Unaligned fixups in the kernel will slow your application considerably.\n");
219P("To find them, write a \"1\" to /proc/sys/tile/unaligned_fixup/printk,\n");
220P("which requests the kernel show all unaligned fixups, or write a \"0\"\n");
221P("to /proc/sys/tile/unaligned_fixup/enabled, in which case each unaligned\n");
222P("access will become a SIGBUS you can debug. No further warnings will be\n");
223P("shown so as to avoid additional slowdown, but you can track the number\n");
224P("of fixups performed via /proc/sys/tile/unaligned_fixup/count.\n");
225P("Use the tile-addr2line command (see \"info addr2line\") to decode PCs.\n");
226P("\n");
227#undef P
228 }
229 }
230 ++unaligned_fixup_count;
231
232 if (bundle & TILE_BUNDLE_Y_ENCODING_MASK) {
233 /* Convert the Y2 instruction to a prefetch. */
234 bundle &= ~(create_SrcBDest_Y2(-1) |
235 create_Opcode_Y2(-1));
236 bundle |= (create_SrcBDest_Y2(TREG_ZERO) |
237 create_Opcode_Y2(LW_OPCODE_Y2));
238 /* Replace the load postincr with an addi */
239 } else if (mem_op == MEMOP_LOAD_POSTINCR) {
240 bundle = addi_X1(bundle, addr_reg, addr_reg,
241 get_Imm8_X1(bundle));
242 /* Replace the store postincr with an addi */
243 } else if (mem_op == MEMOP_STORE_POSTINCR) {
244 bundle = addi_X1(bundle, addr_reg, addr_reg,
245 get_Dest_Imm8_X1(bundle));
246 } else {
247 /* Convert the X1 instruction to a nop. */
248 bundle &= ~(create_Opcode_X1(-1) |
249 create_UnShOpcodeExtension_X1(-1) |
250 create_UnOpcodeExtension_X1(-1));
251 bundle |= (create_Opcode_X1(SHUN_0_OPCODE_X1) |
252 create_UnShOpcodeExtension_X1(
253 UN_0_SHUN_0_OPCODE_X1) |
254 create_UnOpcodeExtension_X1(
255 NOP_UN_0_SHUN_0_OPCODE_X1));
256 }
257
258 return bundle;
259}
260
261/*
262 * Called after execve() has started the new image. This allows us
263 * to reset the info state. Note that the the mmap'ed memory, if there
264 * was any, has already been unmapped by the exec.
265 */
266void single_step_execve(void)
267{
268 struct thread_info *ti = current_thread_info();
269 kfree(ti->step_state);
270 ti->step_state = NULL;
271}
272
273/**
274 * single_step_once() - entry point when single stepping has been triggered.
275 * @regs: The machine register state
276 *
277 * When we arrive at this routine via a trampoline, the single step
278 * engine copies the executing bundle to the single step buffer.
279 * If the instruction is a condition branch, then the target is
280 * reset to one past the next instruction. If the instruction
281 * sets the lr, then that is noted. If the instruction is a jump
282 * or call, then the new target pc is preserved and the current
283 * bundle instruction set to null.
284 *
285 * The necessary post-single-step rewriting information is stored in
286 * single_step_state-> We use data segment values because the
287 * stack will be rewound when we run the rewritten single-stepped
288 * instruction.
289 */
290void single_step_once(struct pt_regs *regs)
291{
292 extern tile_bundle_bits __single_step_ill_insn;
293 extern tile_bundle_bits __single_step_j_insn;
294 extern tile_bundle_bits __single_step_addli_insn;
295 extern tile_bundle_bits __single_step_auli_insn;
296 struct thread_info *info = (void *)current_thread_info();
297 struct single_step_state *state = info->step_state;
298 int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
299 tile_bundle_bits __user *buffer, *pc;
300 tile_bundle_bits bundle;
301 int temp_reg;
302 int target_reg = TREG_LR;
303 int err;
304 enum mem_op mem_op = MEMOP_NONE;
305 int size = 0, sign_ext = 0; /* happy compiler */
306
307 asm(
308" .pushsection .rodata.single_step\n"
309" .align 8\n"
310" .globl __single_step_ill_insn\n"
311"__single_step_ill_insn:\n"
312" ill\n"
313" .globl __single_step_addli_insn\n"
314"__single_step_addli_insn:\n"
315" { nop; addli r0, zero, 0 }\n"
316" .globl __single_step_auli_insn\n"
317"__single_step_auli_insn:\n"
318" { nop; auli r0, r0, 0 }\n"
319" .globl __single_step_j_insn\n"
320"__single_step_j_insn:\n"
321" j .\n"
322" .popsection\n"
323 );
324
325 /*
326 * Enable interrupts here to allow touching userspace and the like.
327 * The callers expect this: do_trap() already has interrupts
328 * enabled, and do_work_pending() handles functions that enable
329 * interrupts internally.
330 */
331 local_irq_enable();
332
333 if (state == NULL) {
334 /* allocate a page of writable, executable memory */
335 state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
336 if (state == NULL) {
337 pr_err("Out of kernel memory trying to single-step\n");
338 return;
339 }
340
341 /* allocate a cache line of writable, executable memory */
342 down_write(¤t->mm->mmap_sem);
343 buffer = (void __user *) do_mmap(NULL, 0, 64,
344 PROT_EXEC | PROT_READ | PROT_WRITE,
345 MAP_PRIVATE | MAP_ANONYMOUS,
346 0);
347 up_write(¤t->mm->mmap_sem);
348
349 if (IS_ERR((void __force *)buffer)) {
350 kfree(state);
351 pr_err("Out of kernel pages trying to single-step\n");
352 return;
353 }
354
355 state->buffer = buffer;
356 state->is_enabled = 0;
357
358 info->step_state = state;
359
360 /* Validate our stored instruction patterns */
361 BUG_ON(get_Opcode_X1(__single_step_addli_insn) !=
362 ADDLI_OPCODE_X1);
363 BUG_ON(get_Opcode_X1(__single_step_auli_insn) !=
364 AULI_OPCODE_X1);
365 BUG_ON(get_SrcA_X1(__single_step_addli_insn) != TREG_ZERO);
366 BUG_ON(get_Dest_X1(__single_step_addli_insn) != 0);
367 BUG_ON(get_JOffLong_X1(__single_step_j_insn) != 0);
368 }
369
370 /*
371 * If we are returning from a syscall, we still haven't hit the
372 * "ill" for the swint1 instruction. So back the PC up to be
373 * pointing at the swint1, but we'll actually return directly
374 * back to the "ill" so we come back in via SIGILL as if we
375 * had "executed" the swint1 without ever being in kernel space.
376 */
377 if (regs->faultnum == INT_SWINT_1)
378 regs->pc -= 8;
379
380 pc = (tile_bundle_bits __user *)(regs->pc);
381 if (get_user(bundle, pc) != 0) {
382 pr_err("Couldn't read instruction at %p trying to step\n", pc);
383 return;
384 }
385
386 /* We'll follow the instruction with 2 ill op bundles */
387 state->orig_pc = (unsigned long)pc;
388 state->next_pc = (unsigned long)(pc + 1);
389 state->branch_next_pc = 0;
390 state->update = 0;
391
392 if (!(bundle & TILE_BUNDLE_Y_ENCODING_MASK)) {
393 /* two wide, check for control flow */
394 int opcode = get_Opcode_X1(bundle);
395
396 switch (opcode) {
397 /* branches */
398 case BRANCH_OPCODE_X1:
399 {
400 s32 offset = signExtend17(get_BrOff_X1(bundle));
401
402 /*
403 * For branches, we use a rewriting trick to let the
404 * hardware evaluate whether the branch is taken or
405 * untaken. We record the target offset and then
406 * rewrite the branch instruction to target 1 insn
407 * ahead if the branch is taken. We then follow the
408 * rewritten branch with two bundles, each containing
409 * an "ill" instruction. The supervisor examines the
410 * pc after the single step code is executed, and if
411 * the pc is the first ill instruction, then the
412 * branch (if any) was not taken. If the pc is the
413 * second ill instruction, then the branch was
414 * taken. The new pc is computed for these cases, and
415 * inserted into the registers for the thread. If
416 * the pc is the start of the single step code, then
417 * an exception or interrupt was taken before the
418 * code started processing, and the same "original"
419 * pc is restored. This change, different from the
420 * original implementation, has the advantage of
421 * executing a single user instruction.
422 */
423 state->branch_next_pc = (unsigned long)(pc + offset);
424
425 /* rewrite branch offset to go forward one bundle */
426 bundle = set_BrOff_X1(bundle, 2);
427 }
428 break;
429
430 /* jumps */
431 case JALB_OPCODE_X1:
432 case JALF_OPCODE_X1:
433 state->update = 1;
434 state->next_pc =
435 (unsigned long) (pc + get_JOffLong_X1(bundle));
436 break;
437
438 case JB_OPCODE_X1:
439 case JF_OPCODE_X1:
440 state->next_pc =
441 (unsigned long) (pc + get_JOffLong_X1(bundle));
442 bundle = nop_X1(bundle);
443 break;
444
445 case SPECIAL_0_OPCODE_X1:
446 switch (get_RRROpcodeExtension_X1(bundle)) {
447 /* jump-register */
448 case JALRP_SPECIAL_0_OPCODE_X1:
449 case JALR_SPECIAL_0_OPCODE_X1:
450 state->update = 1;
451 state->next_pc =
452 regs->regs[get_SrcA_X1(bundle)];
453 break;
454
455 case JRP_SPECIAL_0_OPCODE_X1:
456 case JR_SPECIAL_0_OPCODE_X1:
457 state->next_pc =
458 regs->regs[get_SrcA_X1(bundle)];
459 bundle = nop_X1(bundle);
460 break;
461
462 case LNK_SPECIAL_0_OPCODE_X1:
463 state->update = 1;
464 target_reg = get_Dest_X1(bundle);
465 break;
466
467 /* stores */
468 case SH_SPECIAL_0_OPCODE_X1:
469 mem_op = MEMOP_STORE;
470 size = 2;
471 break;
472
473 case SW_SPECIAL_0_OPCODE_X1:
474 mem_op = MEMOP_STORE;
475 size = 4;
476 break;
477 }
478 break;
479
480 /* loads and iret */
481 case SHUN_0_OPCODE_X1:
482 if (get_UnShOpcodeExtension_X1(bundle) ==
483 UN_0_SHUN_0_OPCODE_X1) {
484 switch (get_UnOpcodeExtension_X1(bundle)) {
485 case LH_UN_0_SHUN_0_OPCODE_X1:
486 mem_op = MEMOP_LOAD;
487 size = 2;
488 sign_ext = 1;
489 break;
490
491 case LH_U_UN_0_SHUN_0_OPCODE_X1:
492 mem_op = MEMOP_LOAD;
493 size = 2;
494 sign_ext = 0;
495 break;
496
497 case LW_UN_0_SHUN_0_OPCODE_X1:
498 mem_op = MEMOP_LOAD;
499 size = 4;
500 break;
501
502 case IRET_UN_0_SHUN_0_OPCODE_X1:
503 {
504 unsigned long ex0_0 = __insn_mfspr(
505 SPR_EX_CONTEXT_0_0);
506 unsigned long ex0_1 = __insn_mfspr(
507 SPR_EX_CONTEXT_0_1);
508 /*
509 * Special-case it if we're iret'ing
510 * to PL0 again. Otherwise just let
511 * it run and it will generate SIGILL.
512 */
513 if (EX1_PL(ex0_1) == USER_PL) {
514 state->next_pc = ex0_0;
515 regs->ex1 = ex0_1;
516 bundle = nop_X1(bundle);
517 }
518 }
519 }
520 }
521 break;
522
523#if CHIP_HAS_WH64()
524 /* postincrement operations */
525 case IMM_0_OPCODE_X1:
526 switch (get_ImmOpcodeExtension_X1(bundle)) {
527 case LWADD_IMM_0_OPCODE_X1:
528 mem_op = MEMOP_LOAD_POSTINCR;
529 size = 4;
530 break;
531
532 case LHADD_IMM_0_OPCODE_X1:
533 mem_op = MEMOP_LOAD_POSTINCR;
534 size = 2;
535 sign_ext = 1;
536 break;
537
538 case LHADD_U_IMM_0_OPCODE_X1:
539 mem_op = MEMOP_LOAD_POSTINCR;
540 size = 2;
541 sign_ext = 0;
542 break;
543
544 case SWADD_IMM_0_OPCODE_X1:
545 mem_op = MEMOP_STORE_POSTINCR;
546 size = 4;
547 break;
548
549 case SHADD_IMM_0_OPCODE_X1:
550 mem_op = MEMOP_STORE_POSTINCR;
551 size = 2;
552 break;
553
554 default:
555 break;
556 }
557 break;
558#endif /* CHIP_HAS_WH64() */
559 }
560
561 if (state->update) {
562 /*
563 * Get an available register. We start with a
564 * bitmask with 1's for available registers.
565 * We truncate to the low 32 registers since
566 * we are guaranteed to have set bits in the
567 * low 32 bits, then use ctz to pick the first.
568 */
569 u32 mask = (u32) ~((1ULL << get_Dest_X0(bundle)) |
570 (1ULL << get_SrcA_X0(bundle)) |
571 (1ULL << get_SrcB_X0(bundle)) |
572 (1ULL << target_reg));
573 temp_reg = __builtin_ctz(mask);
574 state->update_reg = temp_reg;
575 state->update_value = regs->regs[temp_reg];
576 regs->regs[temp_reg] = (unsigned long) (pc+1);
577 regs->flags |= PT_FLAGS_RESTORE_REGS;
578 bundle = move_X1(bundle, target_reg, temp_reg);
579 }
580 } else {
581 int opcode = get_Opcode_Y2(bundle);
582
583 switch (opcode) {
584 /* loads */
585 case LH_OPCODE_Y2:
586 mem_op = MEMOP_LOAD;
587 size = 2;
588 sign_ext = 1;
589 break;
590
591 case LH_U_OPCODE_Y2:
592 mem_op = MEMOP_LOAD;
593 size = 2;
594 sign_ext = 0;
595 break;
596
597 case LW_OPCODE_Y2:
598 mem_op = MEMOP_LOAD;
599 size = 4;
600 break;
601
602 /* stores */
603 case SH_OPCODE_Y2:
604 mem_op = MEMOP_STORE;
605 size = 2;
606 break;
607
608 case SW_OPCODE_Y2:
609 mem_op = MEMOP_STORE;
610 size = 4;
611 break;
612 }
613 }
614
615 /*
616 * Check if we need to rewrite an unaligned load/store.
617 * Returning zero is a special value meaning we need to SIGSEGV.
618 */
619 if (mem_op != MEMOP_NONE && unaligned_fixup >= 0) {
620 bundle = rewrite_load_store_unaligned(state, bundle, regs,
621 mem_op, size, sign_ext);
622 if (bundle == 0)
623 return;
624 }
625
626 /* write the bundle to our execution area */
627 buffer = state->buffer;
628 err = __put_user(bundle, buffer++);
629
630 /*
631 * If we're really single-stepping, we take an INT_ILL after.
632 * If we're just handling an unaligned access, we can just
633 * jump directly back to where we were in user code.
634 */
635 if (is_single_step) {
636 err |= __put_user(__single_step_ill_insn, buffer++);
637 err |= __put_user(__single_step_ill_insn, buffer++);
638 } else {
639 long delta;
640
641 if (state->update) {
642 /* We have some state to update; do it inline */
643 int ha16;
644 bundle = __single_step_addli_insn;
645 bundle |= create_Dest_X1(state->update_reg);
646 bundle |= create_Imm16_X1(state->update_value);
647 err |= __put_user(bundle, buffer++);
648 bundle = __single_step_auli_insn;
649 bundle |= create_Dest_X1(state->update_reg);
650 bundle |= create_SrcA_X1(state->update_reg);
651 ha16 = (state->update_value + 0x8000) >> 16;
652 bundle |= create_Imm16_X1(ha16);
653 err |= __put_user(bundle, buffer++);
654 state->update = 0;
655 }
656
657 /* End with a jump back to the next instruction */
658 delta = ((regs->pc + TILE_BUNDLE_SIZE_IN_BYTES) -
659 (unsigned long)buffer) >>
660 TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES;
661 bundle = __single_step_j_insn;
662 bundle |= create_JOffLong_X1(delta);
663 err |= __put_user(bundle, buffer++);
664 }
665
666 if (err) {
667 pr_err("Fault when writing to single-step buffer\n");
668 return;
669 }
670
671 /*
672 * Flush the buffer.
673 * We do a local flush only, since this is a thread-specific buffer.
674 */
675 __flush_icache_range((unsigned long)state->buffer,
676 (unsigned long)buffer);
677
678 /* Indicate enabled */
679 state->is_enabled = is_single_step;
680 regs->pc = (unsigned long)state->buffer;
681
682 /* Fault immediately if we are coming back from a syscall. */
683 if (regs->faultnum == INT_SWINT_1)
684 regs->pc += 8;
685}
686
687#else
688#include <linux/smp.h>
689#include <linux/ptrace.h>
690#include <arch/spr_def.h>
691
692static DEFINE_PER_CPU(unsigned long, ss_saved_pc);
693
694
695/*
696 * Called directly on the occasion of an interrupt.
697 *
698 * If the process doesn't have single step set, then we use this as an
699 * opportunity to turn single step off.
700 *
701 * It has been mentioned that we could conditionally turn off single stepping
702 * on each entry into the kernel and rely on single_step_once to turn it
703 * on for the processes that matter (as we already do), but this
704 * implementation is somewhat more efficient in that we muck with registers
705 * once on a bum interrupt rather than on every entry into the kernel.
706 *
707 * If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred,
708 * so we have to run through this process again before we can say that an
709 * instruction has executed.
710 *
711 * swint will set CANCELED, but it's a legitimate instruction. Fortunately
712 * it changes the PC. If it hasn't changed, then we know that the interrupt
713 * wasn't generated by swint and we'll need to run this process again before
714 * we can say an instruction has executed.
715 *
716 * If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get
717 * on with our lives.
718 */
719
720void gx_singlestep_handle(struct pt_regs *regs, int fault_num)
721{
722 unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
723 struct thread_info *info = (void *)current_thread_info();
724 int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
725 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
726
727 if (is_single_step == 0) {
728 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0);
729
730 } else if ((*ss_pc != regs->pc) ||
731 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) {
732
733 ptrace_notify(SIGTRAP);
734 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
735 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
736 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
737 }
738}
739
740
741/*
742 * Called from need_singlestep. Set up the control registers and the enable
743 * register, then return back.
744 */
745
746void single_step_once(struct pt_regs *regs)
747{
748 unsigned long *ss_pc = &__get_cpu_var(ss_saved_pc);
749 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
750
751 *ss_pc = regs->pc;
752 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
753 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
754 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
755 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL);
756}
757
758void single_step_execve(void)
759{
760 /* Nothing */
761}
762
763#endif /* !__tilegx__ */
1/*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 *
14 * A code-rewriter that enables instruction single-stepping.
15 */
16
17#include <linux/smp.h>
18#include <linux/ptrace.h>
19#include <linux/slab.h>
20#include <linux/thread_info.h>
21#include <linux/uaccess.h>
22#include <linux/mman.h>
23#include <linux/types.h>
24#include <linux/err.h>
25#include <linux/prctl.h>
26#include <asm/cacheflush.h>
27#include <asm/traps.h>
28#include <asm/uaccess.h>
29#include <asm/unaligned.h>
30#include <arch/abi.h>
31#include <arch/spr_def.h>
32#include <arch/opcode.h>
33
34
35#ifndef __tilegx__ /* Hardware support for single step unavailable. */
36
37#define signExtend17(val) sign_extend((val), 17)
38#define TILE_X1_MASK (0xffffffffULL << 31)
39
40enum mem_op {
41 MEMOP_NONE,
42 MEMOP_LOAD,
43 MEMOP_STORE,
44 MEMOP_LOAD_POSTINCR,
45 MEMOP_STORE_POSTINCR
46};
47
48static inline tilepro_bundle_bits set_BrOff_X1(tilepro_bundle_bits n,
49 s32 offset)
50{
51 tilepro_bundle_bits result;
52
53 /* mask out the old offset */
54 tilepro_bundle_bits mask = create_BrOff_X1(-1);
55 result = n & (~mask);
56
57 /* or in the new offset */
58 result |= create_BrOff_X1(offset);
59
60 return result;
61}
62
63static inline tilepro_bundle_bits move_X1(tilepro_bundle_bits n, int dest,
64 int src)
65{
66 tilepro_bundle_bits result;
67 tilepro_bundle_bits op;
68
69 result = n & (~TILE_X1_MASK);
70
71 op = create_Opcode_X1(SPECIAL_0_OPCODE_X1) |
72 create_RRROpcodeExtension_X1(OR_SPECIAL_0_OPCODE_X1) |
73 create_Dest_X1(dest) |
74 create_SrcB_X1(TREG_ZERO) |
75 create_SrcA_X1(src) ;
76
77 result |= op;
78 return result;
79}
80
81static inline tilepro_bundle_bits nop_X1(tilepro_bundle_bits n)
82{
83 return move_X1(n, TREG_ZERO, TREG_ZERO);
84}
85
86static inline tilepro_bundle_bits addi_X1(
87 tilepro_bundle_bits n, int dest, int src, int imm)
88{
89 n &= ~TILE_X1_MASK;
90
91 n |= (create_SrcA_X1(src) |
92 create_Dest_X1(dest) |
93 create_Imm8_X1(imm) |
94 create_S_X1(0) |
95 create_Opcode_X1(IMM_0_OPCODE_X1) |
96 create_ImmOpcodeExtension_X1(ADDI_IMM_0_OPCODE_X1));
97
98 return n;
99}
100
101static tilepro_bundle_bits rewrite_load_store_unaligned(
102 struct single_step_state *state,
103 tilepro_bundle_bits bundle,
104 struct pt_regs *regs,
105 enum mem_op mem_op,
106 int size, int sign_ext)
107{
108 unsigned char __user *addr;
109 int val_reg, addr_reg, err, val;
110 int align_ctl;
111
112 align_ctl = unaligned_fixup;
113 switch (task_thread_info(current)->align_ctl) {
114 case PR_UNALIGN_NOPRINT:
115 align_ctl = 1;
116 break;
117 case PR_UNALIGN_SIGBUS:
118 align_ctl = 0;
119 break;
120 }
121
122 /* Get address and value registers */
123 if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) {
124 addr_reg = get_SrcA_Y2(bundle);
125 val_reg = get_SrcBDest_Y2(bundle);
126 } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
127 addr_reg = get_SrcA_X1(bundle);
128 val_reg = get_Dest_X1(bundle);
129 } else {
130 addr_reg = get_SrcA_X1(bundle);
131 val_reg = get_SrcB_X1(bundle);
132 }
133
134 /*
135 * If registers are not GPRs, don't try to handle it.
136 *
137 * FIXME: we could handle non-GPR loads by getting the real value
138 * from memory, writing it to the single step buffer, using a
139 * temp_reg to hold a pointer to that memory, then executing that
140 * instruction and resetting temp_reg. For non-GPR stores, it's a
141 * little trickier; we could use the single step buffer for that
142 * too, but we'd have to add some more state bits so that we could
143 * call back in here to copy that value to the real target. For
144 * now, we just handle the simple case.
145 */
146 if ((val_reg >= PTREGS_NR_GPRS &&
147 (val_reg != TREG_ZERO ||
148 mem_op == MEMOP_LOAD ||
149 mem_op == MEMOP_LOAD_POSTINCR)) ||
150 addr_reg >= PTREGS_NR_GPRS)
151 return bundle;
152
153 /* If it's aligned, don't handle it specially */
154 addr = (void __user *)regs->regs[addr_reg];
155 if (((unsigned long)addr % size) == 0)
156 return bundle;
157
158 /*
159 * Return SIGBUS with the unaligned address, if requested.
160 * Note that we return SIGBUS even for completely invalid addresses
161 * as long as they are in fact unaligned; this matches what the
162 * tilepro hardware would be doing, if it could provide us with the
163 * actual bad address in an SPR, which it doesn't.
164 */
165 if (align_ctl == 0) {
166 siginfo_t info = {
167 .si_signo = SIGBUS,
168 .si_code = BUS_ADRALN,
169 .si_addr = addr
170 };
171 trace_unhandled_signal("unaligned trap", regs,
172 (unsigned long)addr, SIGBUS);
173 force_sig_info(info.si_signo, &info, current);
174 return (tilepro_bundle_bits) 0;
175 }
176
177 /* Handle unaligned load/store */
178 if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) {
179 unsigned short val_16;
180 switch (size) {
181 case 2:
182 err = copy_from_user(&val_16, addr, sizeof(val_16));
183 val = sign_ext ? ((short)val_16) : val_16;
184 break;
185 case 4:
186 err = copy_from_user(&val, addr, sizeof(val));
187 break;
188 default:
189 BUG();
190 }
191 if (err == 0) {
192 state->update_reg = val_reg;
193 state->update_value = val;
194 state->update = 1;
195 }
196 } else {
197 unsigned short val_16;
198 val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg];
199 switch (size) {
200 case 2:
201 val_16 = val;
202 err = copy_to_user(addr, &val_16, sizeof(val_16));
203 break;
204 case 4:
205 err = copy_to_user(addr, &val, sizeof(val));
206 break;
207 default:
208 BUG();
209 }
210 }
211
212 if (err) {
213 siginfo_t info = {
214 .si_signo = SIGBUS,
215 .si_code = BUS_ADRALN,
216 .si_addr = addr
217 };
218 trace_unhandled_signal("bad address for unaligned fixup", regs,
219 (unsigned long)addr, SIGBUS);
220 force_sig_info(info.si_signo, &info, current);
221 return (tilepro_bundle_bits) 0;
222 }
223
224 if (unaligned_printk || unaligned_fixup_count == 0) {
225 pr_info("Process %d/%s: PC %#lx: Fixup of unaligned %s at %#lx\n",
226 current->pid, current->comm, regs->pc,
227 mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR ?
228 "load" : "store",
229 (unsigned long)addr);
230 if (!unaligned_printk) {
231#define P pr_info
232P("\n");
233P("Unaligned fixups in the kernel will slow your application considerably.\n");
234P("To find them, write a \"1\" to /proc/sys/tile/unaligned_fixup/printk,\n");
235P("which requests the kernel show all unaligned fixups, or write a \"0\"\n");
236P("to /proc/sys/tile/unaligned_fixup/enabled, in which case each unaligned\n");
237P("access will become a SIGBUS you can debug. No further warnings will be\n");
238P("shown so as to avoid additional slowdown, but you can track the number\n");
239P("of fixups performed via /proc/sys/tile/unaligned_fixup/count.\n");
240P("Use the tile-addr2line command (see \"info addr2line\") to decode PCs.\n");
241P("\n");
242#undef P
243 }
244 }
245 ++unaligned_fixup_count;
246
247 if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) {
248 /* Convert the Y2 instruction to a prefetch. */
249 bundle &= ~(create_SrcBDest_Y2(-1) |
250 create_Opcode_Y2(-1));
251 bundle |= (create_SrcBDest_Y2(TREG_ZERO) |
252 create_Opcode_Y2(LW_OPCODE_Y2));
253 /* Replace the load postincr with an addi */
254 } else if (mem_op == MEMOP_LOAD_POSTINCR) {
255 bundle = addi_X1(bundle, addr_reg, addr_reg,
256 get_Imm8_X1(bundle));
257 /* Replace the store postincr with an addi */
258 } else if (mem_op == MEMOP_STORE_POSTINCR) {
259 bundle = addi_X1(bundle, addr_reg, addr_reg,
260 get_Dest_Imm8_X1(bundle));
261 } else {
262 /* Convert the X1 instruction to a nop. */
263 bundle &= ~(create_Opcode_X1(-1) |
264 create_UnShOpcodeExtension_X1(-1) |
265 create_UnOpcodeExtension_X1(-1));
266 bundle |= (create_Opcode_X1(SHUN_0_OPCODE_X1) |
267 create_UnShOpcodeExtension_X1(
268 UN_0_SHUN_0_OPCODE_X1) |
269 create_UnOpcodeExtension_X1(
270 NOP_UN_0_SHUN_0_OPCODE_X1));
271 }
272
273 return bundle;
274}
275
276/*
277 * Called after execve() has started the new image. This allows us
278 * to reset the info state. Note that the the mmap'ed memory, if there
279 * was any, has already been unmapped by the exec.
280 */
281void single_step_execve(void)
282{
283 struct thread_info *ti = current_thread_info();
284 kfree(ti->step_state);
285 ti->step_state = NULL;
286}
287
288/*
289 * single_step_once() - entry point when single stepping has been triggered.
290 * @regs: The machine register state
291 *
292 * When we arrive at this routine via a trampoline, the single step
293 * engine copies the executing bundle to the single step buffer.
294 * If the instruction is a condition branch, then the target is
295 * reset to one past the next instruction. If the instruction
296 * sets the lr, then that is noted. If the instruction is a jump
297 * or call, then the new target pc is preserved and the current
298 * bundle instruction set to null.
299 *
300 * The necessary post-single-step rewriting information is stored in
301 * single_step_state-> We use data segment values because the
302 * stack will be rewound when we run the rewritten single-stepped
303 * instruction.
304 */
305void single_step_once(struct pt_regs *regs)
306{
307 extern tilepro_bundle_bits __single_step_ill_insn;
308 extern tilepro_bundle_bits __single_step_j_insn;
309 extern tilepro_bundle_bits __single_step_addli_insn;
310 extern tilepro_bundle_bits __single_step_auli_insn;
311 struct thread_info *info = (void *)current_thread_info();
312 struct single_step_state *state = info->step_state;
313 int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
314 tilepro_bundle_bits __user *buffer, *pc;
315 tilepro_bundle_bits bundle;
316 int temp_reg;
317 int target_reg = TREG_LR;
318 int err;
319 enum mem_op mem_op = MEMOP_NONE;
320 int size = 0, sign_ext = 0; /* happy compiler */
321 int align_ctl;
322
323 align_ctl = unaligned_fixup;
324 switch (task_thread_info(current)->align_ctl) {
325 case PR_UNALIGN_NOPRINT:
326 align_ctl = 1;
327 break;
328 case PR_UNALIGN_SIGBUS:
329 align_ctl = 0;
330 break;
331 }
332
333 asm(
334" .pushsection .rodata.single_step\n"
335" .align 8\n"
336" .globl __single_step_ill_insn\n"
337"__single_step_ill_insn:\n"
338" ill\n"
339" .globl __single_step_addli_insn\n"
340"__single_step_addli_insn:\n"
341" { nop; addli r0, zero, 0 }\n"
342" .globl __single_step_auli_insn\n"
343"__single_step_auli_insn:\n"
344" { nop; auli r0, r0, 0 }\n"
345" .globl __single_step_j_insn\n"
346"__single_step_j_insn:\n"
347" j .\n"
348" .popsection\n"
349 );
350
351 /*
352 * Enable interrupts here to allow touching userspace and the like.
353 * The callers expect this: do_trap() already has interrupts
354 * enabled, and do_work_pending() handles functions that enable
355 * interrupts internally.
356 */
357 local_irq_enable();
358
359 if (state == NULL) {
360 /* allocate a page of writable, executable memory */
361 state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
362 if (state == NULL) {
363 pr_err("Out of kernel memory trying to single-step\n");
364 return;
365 }
366
367 /* allocate a cache line of writable, executable memory */
368 buffer = (void __user *) vm_mmap(NULL, 0, 64,
369 PROT_EXEC | PROT_READ | PROT_WRITE,
370 MAP_PRIVATE | MAP_ANONYMOUS,
371 0);
372
373 if (IS_ERR((void __force *)buffer)) {
374 kfree(state);
375 pr_err("Out of kernel pages trying to single-step\n");
376 return;
377 }
378
379 state->buffer = buffer;
380 state->is_enabled = 0;
381
382 info->step_state = state;
383
384 /* Validate our stored instruction patterns */
385 BUG_ON(get_Opcode_X1(__single_step_addli_insn) !=
386 ADDLI_OPCODE_X1);
387 BUG_ON(get_Opcode_X1(__single_step_auli_insn) !=
388 AULI_OPCODE_X1);
389 BUG_ON(get_SrcA_X1(__single_step_addli_insn) != TREG_ZERO);
390 BUG_ON(get_Dest_X1(__single_step_addli_insn) != 0);
391 BUG_ON(get_JOffLong_X1(__single_step_j_insn) != 0);
392 }
393
394 /*
395 * If we are returning from a syscall, we still haven't hit the
396 * "ill" for the swint1 instruction. So back the PC up to be
397 * pointing at the swint1, but we'll actually return directly
398 * back to the "ill" so we come back in via SIGILL as if we
399 * had "executed" the swint1 without ever being in kernel space.
400 */
401 if (regs->faultnum == INT_SWINT_1)
402 regs->pc -= 8;
403
404 pc = (tilepro_bundle_bits __user *)(regs->pc);
405 if (get_user(bundle, pc) != 0) {
406 pr_err("Couldn't read instruction at %p trying to step\n", pc);
407 return;
408 }
409
410 /* We'll follow the instruction with 2 ill op bundles */
411 state->orig_pc = (unsigned long)pc;
412 state->next_pc = (unsigned long)(pc + 1);
413 state->branch_next_pc = 0;
414 state->update = 0;
415
416 if (!(bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK)) {
417 /* two wide, check for control flow */
418 int opcode = get_Opcode_X1(bundle);
419
420 switch (opcode) {
421 /* branches */
422 case BRANCH_OPCODE_X1:
423 {
424 s32 offset = signExtend17(get_BrOff_X1(bundle));
425
426 /*
427 * For branches, we use a rewriting trick to let the
428 * hardware evaluate whether the branch is taken or
429 * untaken. We record the target offset and then
430 * rewrite the branch instruction to target 1 insn
431 * ahead if the branch is taken. We then follow the
432 * rewritten branch with two bundles, each containing
433 * an "ill" instruction. The supervisor examines the
434 * pc after the single step code is executed, and if
435 * the pc is the first ill instruction, then the
436 * branch (if any) was not taken. If the pc is the
437 * second ill instruction, then the branch was
438 * taken. The new pc is computed for these cases, and
439 * inserted into the registers for the thread. If
440 * the pc is the start of the single step code, then
441 * an exception or interrupt was taken before the
442 * code started processing, and the same "original"
443 * pc is restored. This change, different from the
444 * original implementation, has the advantage of
445 * executing a single user instruction.
446 */
447 state->branch_next_pc = (unsigned long)(pc + offset);
448
449 /* rewrite branch offset to go forward one bundle */
450 bundle = set_BrOff_X1(bundle, 2);
451 }
452 break;
453
454 /* jumps */
455 case JALB_OPCODE_X1:
456 case JALF_OPCODE_X1:
457 state->update = 1;
458 state->next_pc =
459 (unsigned long) (pc + get_JOffLong_X1(bundle));
460 break;
461
462 case JB_OPCODE_X1:
463 case JF_OPCODE_X1:
464 state->next_pc =
465 (unsigned long) (pc + get_JOffLong_X1(bundle));
466 bundle = nop_X1(bundle);
467 break;
468
469 case SPECIAL_0_OPCODE_X1:
470 switch (get_RRROpcodeExtension_X1(bundle)) {
471 /* jump-register */
472 case JALRP_SPECIAL_0_OPCODE_X1:
473 case JALR_SPECIAL_0_OPCODE_X1:
474 state->update = 1;
475 state->next_pc =
476 regs->regs[get_SrcA_X1(bundle)];
477 break;
478
479 case JRP_SPECIAL_0_OPCODE_X1:
480 case JR_SPECIAL_0_OPCODE_X1:
481 state->next_pc =
482 regs->regs[get_SrcA_X1(bundle)];
483 bundle = nop_X1(bundle);
484 break;
485
486 case LNK_SPECIAL_0_OPCODE_X1:
487 state->update = 1;
488 target_reg = get_Dest_X1(bundle);
489 break;
490
491 /* stores */
492 case SH_SPECIAL_0_OPCODE_X1:
493 mem_op = MEMOP_STORE;
494 size = 2;
495 break;
496
497 case SW_SPECIAL_0_OPCODE_X1:
498 mem_op = MEMOP_STORE;
499 size = 4;
500 break;
501 }
502 break;
503
504 /* loads and iret */
505 case SHUN_0_OPCODE_X1:
506 if (get_UnShOpcodeExtension_X1(bundle) ==
507 UN_0_SHUN_0_OPCODE_X1) {
508 switch (get_UnOpcodeExtension_X1(bundle)) {
509 case LH_UN_0_SHUN_0_OPCODE_X1:
510 mem_op = MEMOP_LOAD;
511 size = 2;
512 sign_ext = 1;
513 break;
514
515 case LH_U_UN_0_SHUN_0_OPCODE_X1:
516 mem_op = MEMOP_LOAD;
517 size = 2;
518 sign_ext = 0;
519 break;
520
521 case LW_UN_0_SHUN_0_OPCODE_X1:
522 mem_op = MEMOP_LOAD;
523 size = 4;
524 break;
525
526 case IRET_UN_0_SHUN_0_OPCODE_X1:
527 {
528 unsigned long ex0_0 = __insn_mfspr(
529 SPR_EX_CONTEXT_0_0);
530 unsigned long ex0_1 = __insn_mfspr(
531 SPR_EX_CONTEXT_0_1);
532 /*
533 * Special-case it if we're iret'ing
534 * to PL0 again. Otherwise just let
535 * it run and it will generate SIGILL.
536 */
537 if (EX1_PL(ex0_1) == USER_PL) {
538 state->next_pc = ex0_0;
539 regs->ex1 = ex0_1;
540 bundle = nop_X1(bundle);
541 }
542 }
543 }
544 }
545 break;
546
547 /* postincrement operations */
548 case IMM_0_OPCODE_X1:
549 switch (get_ImmOpcodeExtension_X1(bundle)) {
550 case LWADD_IMM_0_OPCODE_X1:
551 mem_op = MEMOP_LOAD_POSTINCR;
552 size = 4;
553 break;
554
555 case LHADD_IMM_0_OPCODE_X1:
556 mem_op = MEMOP_LOAD_POSTINCR;
557 size = 2;
558 sign_ext = 1;
559 break;
560
561 case LHADD_U_IMM_0_OPCODE_X1:
562 mem_op = MEMOP_LOAD_POSTINCR;
563 size = 2;
564 sign_ext = 0;
565 break;
566
567 case SWADD_IMM_0_OPCODE_X1:
568 mem_op = MEMOP_STORE_POSTINCR;
569 size = 4;
570 break;
571
572 case SHADD_IMM_0_OPCODE_X1:
573 mem_op = MEMOP_STORE_POSTINCR;
574 size = 2;
575 break;
576
577 default:
578 break;
579 }
580 break;
581 }
582
583 if (state->update) {
584 /*
585 * Get an available register. We start with a
586 * bitmask with 1's for available registers.
587 * We truncate to the low 32 registers since
588 * we are guaranteed to have set bits in the
589 * low 32 bits, then use ctz to pick the first.
590 */
591 u32 mask = (u32) ~((1ULL << get_Dest_X0(bundle)) |
592 (1ULL << get_SrcA_X0(bundle)) |
593 (1ULL << get_SrcB_X0(bundle)) |
594 (1ULL << target_reg));
595 temp_reg = __builtin_ctz(mask);
596 state->update_reg = temp_reg;
597 state->update_value = regs->regs[temp_reg];
598 regs->regs[temp_reg] = (unsigned long) (pc+1);
599 regs->flags |= PT_FLAGS_RESTORE_REGS;
600 bundle = move_X1(bundle, target_reg, temp_reg);
601 }
602 } else {
603 int opcode = get_Opcode_Y2(bundle);
604
605 switch (opcode) {
606 /* loads */
607 case LH_OPCODE_Y2:
608 mem_op = MEMOP_LOAD;
609 size = 2;
610 sign_ext = 1;
611 break;
612
613 case LH_U_OPCODE_Y2:
614 mem_op = MEMOP_LOAD;
615 size = 2;
616 sign_ext = 0;
617 break;
618
619 case LW_OPCODE_Y2:
620 mem_op = MEMOP_LOAD;
621 size = 4;
622 break;
623
624 /* stores */
625 case SH_OPCODE_Y2:
626 mem_op = MEMOP_STORE;
627 size = 2;
628 break;
629
630 case SW_OPCODE_Y2:
631 mem_op = MEMOP_STORE;
632 size = 4;
633 break;
634 }
635 }
636
637 /*
638 * Check if we need to rewrite an unaligned load/store.
639 * Returning zero is a special value meaning we generated a signal.
640 */
641 if (mem_op != MEMOP_NONE && align_ctl >= 0) {
642 bundle = rewrite_load_store_unaligned(state, bundle, regs,
643 mem_op, size, sign_ext);
644 if (bundle == 0)
645 return;
646 }
647
648 /* write the bundle to our execution area */
649 buffer = state->buffer;
650 err = __put_user(bundle, buffer++);
651
652 /*
653 * If we're really single-stepping, we take an INT_ILL after.
654 * If we're just handling an unaligned access, we can just
655 * jump directly back to where we were in user code.
656 */
657 if (is_single_step) {
658 err |= __put_user(__single_step_ill_insn, buffer++);
659 err |= __put_user(__single_step_ill_insn, buffer++);
660 } else {
661 long delta;
662
663 if (state->update) {
664 /* We have some state to update; do it inline */
665 int ha16;
666 bundle = __single_step_addli_insn;
667 bundle |= create_Dest_X1(state->update_reg);
668 bundle |= create_Imm16_X1(state->update_value);
669 err |= __put_user(bundle, buffer++);
670 bundle = __single_step_auli_insn;
671 bundle |= create_Dest_X1(state->update_reg);
672 bundle |= create_SrcA_X1(state->update_reg);
673 ha16 = (state->update_value + 0x8000) >> 16;
674 bundle |= create_Imm16_X1(ha16);
675 err |= __put_user(bundle, buffer++);
676 state->update = 0;
677 }
678
679 /* End with a jump back to the next instruction */
680 delta = ((regs->pc + TILEPRO_BUNDLE_SIZE_IN_BYTES) -
681 (unsigned long)buffer) >>
682 TILEPRO_LOG2_BUNDLE_ALIGNMENT_IN_BYTES;
683 bundle = __single_step_j_insn;
684 bundle |= create_JOffLong_X1(delta);
685 err |= __put_user(bundle, buffer++);
686 }
687
688 if (err) {
689 pr_err("Fault when writing to single-step buffer\n");
690 return;
691 }
692
693 /*
694 * Flush the buffer.
695 * We do a local flush only, since this is a thread-specific buffer.
696 */
697 __flush_icache_range((unsigned long)state->buffer,
698 (unsigned long)buffer);
699
700 /* Indicate enabled */
701 state->is_enabled = is_single_step;
702 regs->pc = (unsigned long)state->buffer;
703
704 /* Fault immediately if we are coming back from a syscall. */
705 if (regs->faultnum == INT_SWINT_1)
706 regs->pc += 8;
707}
708
709#else
710
711static DEFINE_PER_CPU(unsigned long, ss_saved_pc);
712
713
714/*
715 * Called directly on the occasion of an interrupt.
716 *
717 * If the process doesn't have single step set, then we use this as an
718 * opportunity to turn single step off.
719 *
720 * It has been mentioned that we could conditionally turn off single stepping
721 * on each entry into the kernel and rely on single_step_once to turn it
722 * on for the processes that matter (as we already do), but this
723 * implementation is somewhat more efficient in that we muck with registers
724 * once on a bum interrupt rather than on every entry into the kernel.
725 *
726 * If SINGLE_STEP_CONTROL_K has CANCELED set, then an interrupt occurred,
727 * so we have to run through this process again before we can say that an
728 * instruction has executed.
729 *
730 * swint will set CANCELED, but it's a legitimate instruction. Fortunately
731 * it changes the PC. If it hasn't changed, then we know that the interrupt
732 * wasn't generated by swint and we'll need to run this process again before
733 * we can say an instruction has executed.
734 *
735 * If either CANCELED == 0 or the PC's changed, we send out SIGTRAPs and get
736 * on with our lives.
737 */
738
739void gx_singlestep_handle(struct pt_regs *regs, int fault_num)
740{
741 unsigned long *ss_pc = this_cpu_ptr(&ss_saved_pc);
742 struct thread_info *info = (void *)current_thread_info();
743 int is_single_step = test_ti_thread_flag(info, TIF_SINGLESTEP);
744 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
745
746 if (is_single_step == 0) {
747 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 0);
748
749 } else if ((*ss_pc != regs->pc) ||
750 (!(control & SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK))) {
751
752 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
753 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
754 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
755 send_sigtrap(current, regs);
756 }
757}
758
759
760/*
761 * Called from need_singlestep. Set up the control registers and the enable
762 * register, then return back.
763 */
764
765void single_step_once(struct pt_regs *regs)
766{
767 unsigned long *ss_pc = this_cpu_ptr(&ss_saved_pc);
768 unsigned long control = __insn_mfspr(SPR_SINGLE_STEP_CONTROL_K);
769
770 *ss_pc = regs->pc;
771 control |= SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK;
772 control |= SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK;
773 __insn_mtspr(SPR_SINGLE_STEP_CONTROL_K, control);
774 __insn_mtspr(SPR_SINGLE_STEP_EN_K_K, 1 << USER_PL);
775}
776
777void single_step_execve(void)
778{
779 /* Nothing */
780}
781
782#endif /* !__tilegx__ */