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1/*
2 * arch/s390/kernel/head64.S
3 *
4 * Copyright (C) IBM Corp. 1999,2010
5 *
6 * Author(s): Hartmut Penner <hp@de.ibm.com>
7 * Martin Schwidefsky <schwidefsky@de.ibm.com>
8 * Rob van der Heij <rvdhei@iae.nl>
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
10 *
11 */
12
13#include <linux/init.h>
14#include <linux/linkage.h>
15#include <asm/asm-offsets.h>
16#include <asm/thread_info.h>
17#include <asm/page.h>
18
19__HEAD
20ENTRY(startup_continue)
21 larl %r1,sched_clock_base_cc
22 mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
23 larl %r13,.LPG1 # get base
24 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
25 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
26 # move IPL device to lowcore
27 lghi %r0,__LC_PASTE
28 stg %r0,__LC_VDSO_PER_CPU
29#
30# Setup stack
31#
32 larl %r15,init_thread_union
33 stg %r15,__LC_THREAD_INFO # cache thread info in lowcore
34 lg %r14,__TI_task(%r15) # cache current in lowcore
35 stg %r14,__LC_CURRENT
36 aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
37 stg %r15,__LC_KERNEL_STACK # set end of kernel stack
38 aghi %r15,-160
39#
40# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
41# and create a kernel NSS if the SAVESYS= parm is defined
42#
43 brasl %r14,startup_init
44 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
45 # virtual and never return ...
46 .align 16
47.LPG1:
48.Lentry:.quad 0x0000000180000000,_stext
49.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
50 .quad 0 # cr1: primary space segment table
51 .quad .Lduct # cr2: dispatchable unit control table
52 .quad 0 # cr3: instruction authorization
53 .quad 0 # cr4: instruction authorization
54 .quad .Lduct # cr5: primary-aste origin
55 .quad 0 # cr6: I/O interrupts
56 .quad 0 # cr7: secondary space segment table
57 .quad 0 # cr8: access registers translation
58 .quad 0 # cr9: tracing off
59 .quad 0 # cr10: tracing off
60 .quad 0 # cr11: tracing off
61 .quad 0 # cr12: tracing off
62 .quad 0 # cr13: home space segment table
63 .quad 0xc0000000 # cr14: machine check handling off
64 .quad 0 # cr15: linkage stack operations
65.Lpcmsk:.quad 0x0000000180000000
66.L4malign:.quad 0xffffffffffc00000
67.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
68.Lnop: .long 0x07000700
69.Lparmaddr:
70 .quad PARMAREA
71 .align 64
72.Lduct: .long 0,0,0,0,.Lduald,0,0,0
73 .long 0,0,0,0,0,0,0,0
74 .align 128
75.Lduald:.rept 8
76 .long 0x80000000,0,0,0 # invalid access-list entries
77 .endr
78
79ENTRY(_ehead)
80
81#ifdef CONFIG_SHARED_KERNEL
82 .org 0x100000 - 0x11000 # head.o ends at 0x11000
83#endif
84
85#
86# startup-code, running in absolute addressing mode
87#
88ENTRY(_stext)
89 basr %r13,0 # get base
90.LPG3:
91# check control registers
92 stctg %c0,%c15,0(%r15)
93 oi 6(%r15),0x40 # enable sigp emergency signal
94 oi 4(%r15),0x10 # switch on low address proctection
95 lctlg %c0,%c15,0(%r15)
96
97 lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
98 brasl %r14,start_kernel # go to C code
99#
100# We returned from start_kernel ?!? PANIK
101#
102 basr %r13,0
103 lpswe .Ldw-.(%r13) # load disabled wait psw
104
105 .align 8
106.Ldw: .quad 0x0002000180000000,0x0000000000000000
107.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
1/*
2 * Copyright IBM Corp. 1999, 2010
3 *
4 * Author(s): Hartmut Penner <hp@de.ibm.com>
5 * Martin Schwidefsky <schwidefsky@de.ibm.com>
6 * Rob van der Heij <rvdhei@iae.nl>
7 * Heiko Carstens <heiko.carstens@de.ibm.com>
8 *
9 */
10
11#include <linux/init.h>
12#include <linux/linkage.h>
13#include <asm/asm-offsets.h>
14#include <asm/thread_info.h>
15#include <asm/page.h>
16
17__HEAD
18ENTRY(startup_continue)
19 tm __LC_STFLE_FAC_LIST+5,0x80 # LPP available ?
20 jz 0f
21 xc __LC_LPP+1(7,0),__LC_LPP+1 # clear lpp and current_pid
22 mvi __LC_LPP,0x80 # and set LPP_MAGIC
23 .insn s,0xb2800000,__LC_LPP # load program parameter
240: larl %r1,sched_clock_base_cc
25 mvc 0(8,%r1),__LC_LAST_UPDATE_CLOCK
26 larl %r13,.LPG1 # get base
27 lctlg %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
28 lg %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
29 # move IPL device to lowcore
30 lghi %r0,__LC_PASTE
31 stg %r0,__LC_VDSO_PER_CPU
32#
33# Setup stack
34#
35 larl %r15,init_thread_union
36 stg %r15,__LC_THREAD_INFO # cache thread info in lowcore
37 lg %r14,__TI_task(%r15) # cache current in lowcore
38 stg %r14,__LC_CURRENT
39 aghi %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
40 stg %r15,__LC_KERNEL_STACK # set end of kernel stack
41 aghi %r15,-160
42#
43# Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
44# and create a kernel NSS if the SAVESYS= parm is defined
45#
46 brasl %r14,startup_init
47 lpswe .Lentry-.LPG1(13) # jump to _stext in primary-space,
48 # virtual and never return ...
49 .align 16
50.LPG1:
51.Lentry:.quad 0x0000000180000000,_stext
52.Lctl: .quad 0x04040000 # cr0: AFP registers & secondary space
53 .quad 0 # cr1: primary space segment table
54 .quad .Lduct # cr2: dispatchable unit control table
55 .quad 0 # cr3: instruction authorization
56 .quad 0 # cr4: instruction authorization
57 .quad .Lduct # cr5: primary-aste origin
58 .quad 0 # cr6: I/O interrupts
59 .quad 0 # cr7: secondary space segment table
60 .quad 0 # cr8: access registers translation
61 .quad 0 # cr9: tracing off
62 .quad 0 # cr10: tracing off
63 .quad 0 # cr11: tracing off
64 .quad 0 # cr12: tracing off
65 .quad 0 # cr13: home space segment table
66 .quad 0xc0000000 # cr14: machine check handling off
67 .quad .Llinkage_stack # cr15: linkage stack operations
68.Lpcmsk:.quad 0x0000000180000000
69.L4malign:.quad 0xffffffffffc00000
70.Lscan2g:.quad 0x80000000 + 0x20000 - 8 # 2GB + 128K - 8
71.Lnop: .long 0x07000700
72.Lparmaddr:
73 .quad PARMAREA
74 .align 64
75.Lduct: .long 0,.Laste,.Laste,0,.Lduald,0,0,0
76 .long 0,0,0,0,0,0,0,0
77.Laste: .quad 0,0xffffffffffffffff,0,0,0,0,0,0
78 .align 128
79.Lduald:.rept 8
80 .long 0x80000000,0,0,0 # invalid access-list entries
81 .endr
82.Llinkage_stack:
83 .long 0,0,0x89000000,0,0,0,0x8a000000,0
84
85ENTRY(_ehead)
86
87 .org 0x100000 - 0x11000 # head.o ends at 0x11000
88#
89# startup-code, running in absolute addressing mode
90#
91ENTRY(_stext)
92 basr %r13,0 # get base
93.LPG3:
94# check control registers
95 stctg %c0,%c15,0(%r15)
96 oi 6(%r15),0x60 # enable sigp emergency & external call
97 oi 4(%r15),0x10 # switch on low address proctection
98 lctlg %c0,%c15,0(%r15)
99
100 lam 0,15,.Laregs-.LPG3(%r13) # load acrs needed by uaccess
101 brasl %r14,start_kernel # go to C code
102#
103# We returned from start_kernel ?!? PANIK
104#
105 basr %r13,0
106 lpswe .Ldw-.(%r13) # load disabled wait psw
107
108 .align 8
109.Ldw: .quad 0x0002000180000000,0x0000000000000000
110.Laregs:.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0