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1/*
2 * sc-rm7k.c: RM7000 cache management functions.
3 *
4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
5 */
6
7#undef DEBUG
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/mm.h>
12#include <linux/bitops.h>
13
14#include <asm/addrspace.h>
15#include <asm/bcache.h>
16#include <asm/cacheops.h>
17#include <asm/mipsregs.h>
18#include <asm/processor.h>
19#include <asm/sections.h>
20#include <asm/cacheflush.h> /* for run_uncached() */
21
22/* Primary cache parameters. */
23#define sc_lsize 32
24#define tc_pagesize (32*128)
25
26/* Secondary cache parameters. */
27#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
28
29/* Tertiary cache parameters */
30#define tc_lsize 32
31
32extern unsigned long icache_way_size, dcache_way_size;
33static unsigned long tcache_size;
34
35#include <asm/r4kcache.h>
36
37static int rm7k_tcache_init;
38
39/*
40 * Writeback and invalidate the primary cache dcache before DMA.
41 * (XXX These need to be fixed ...)
42 */
43static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
44{
45 unsigned long end, a;
46
47 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
48
49 /* Catch bad driver code */
50 BUG_ON(size == 0);
51
52 blast_scache_range(addr, addr + size);
53
54 if (!rm7k_tcache_init)
55 return;
56
57 a = addr & ~(tc_pagesize - 1);
58 end = (addr + size - 1) & ~(tc_pagesize - 1);
59 while(1) {
60 invalidate_tcache_page(a); /* Page_Invalidate_T */
61 if (a == end)
62 break;
63 a += tc_pagesize;
64 }
65}
66
67static void rm7k_sc_inv(unsigned long addr, unsigned long size)
68{
69 unsigned long end, a;
70
71 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
72
73 /* Catch bad driver code */
74 BUG_ON(size == 0);
75
76 blast_inv_scache_range(addr, addr + size);
77
78 if (!rm7k_tcache_init)
79 return;
80
81 a = addr & ~(tc_pagesize - 1);
82 end = (addr + size - 1) & ~(tc_pagesize - 1);
83 while(1) {
84 invalidate_tcache_page(a); /* Page_Invalidate_T */
85 if (a == end)
86 break;
87 a += tc_pagesize;
88 }
89}
90
91static void blast_rm7k_tcache(void)
92{
93 unsigned long start = CKSEG0ADDR(0);
94 unsigned long end = start + tcache_size;
95
96 write_c0_taglo(0);
97
98 while (start < end) {
99 cache_op(Page_Invalidate_T, start);
100 start += tc_pagesize;
101 }
102}
103
104/*
105 * This function is executed in uncached address space.
106 */
107static __cpuinit void __rm7k_tc_enable(void)
108{
109 int i;
110
111 set_c0_config(RM7K_CONF_TE);
112
113 write_c0_taglo(0);
114 write_c0_taghi(0);
115
116 for (i = 0; i < tcache_size; i += tc_lsize)
117 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
118}
119
120static __cpuinit void rm7k_tc_enable(void)
121{
122 if (read_c0_config() & RM7K_CONF_TE)
123 return;
124
125 BUG_ON(tcache_size == 0);
126
127 run_uncached(__rm7k_tc_enable);
128}
129
130/*
131 * This function is executed in uncached address space.
132 */
133static __cpuinit void __rm7k_sc_enable(void)
134{
135 int i;
136
137 set_c0_config(RM7K_CONF_SE);
138
139 write_c0_taglo(0);
140 write_c0_taghi(0);
141
142 for (i = 0; i < scache_size; i += sc_lsize)
143 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
144}
145
146static __cpuinit void rm7k_sc_enable(void)
147{
148 if (read_c0_config() & RM7K_CONF_SE)
149 return;
150
151 pr_info("Enabling secondary cache...\n");
152 run_uncached(__rm7k_sc_enable);
153
154 if (rm7k_tcache_init)
155 rm7k_tc_enable();
156}
157
158static void rm7k_tc_disable(void)
159{
160 unsigned long flags;
161
162 local_irq_save(flags);
163 blast_rm7k_tcache();
164 clear_c0_config(RM7K_CONF_TE);
165 local_irq_save(flags);
166}
167
168static void rm7k_sc_disable(void)
169{
170 clear_c0_config(RM7K_CONF_SE);
171
172 if (rm7k_tcache_init)
173 rm7k_tc_disable();
174}
175
176static struct bcache_ops rm7k_sc_ops = {
177 .bc_enable = rm7k_sc_enable,
178 .bc_disable = rm7k_sc_disable,
179 .bc_wback_inv = rm7k_sc_wback_inv,
180 .bc_inv = rm7k_sc_inv
181};
182
183/*
184 * This is a probing function like the one found in c-r4k.c, we look for the
185 * wrap around point with different addresses.
186 */
187static __cpuinit void __probe_tcache(void)
188{
189 unsigned long flags, addr, begin, end, pow2;
190
191 begin = (unsigned long) &_stext;
192 begin &= ~((8 * 1024 * 1024) - 1);
193 end = begin + (8 * 1024 * 1024);
194
195 local_irq_save(flags);
196
197 set_c0_config(RM7K_CONF_TE);
198
199 /* Fill size-multiple lines with a valid tag */
200 pow2 = (256 * 1024);
201 for (addr = begin; addr <= end; addr = (begin + pow2)) {
202 unsigned long *p = (unsigned long *) addr;
203 __asm__ __volatile__("nop" : : "r" (*p));
204 pow2 <<= 1;
205 }
206
207 /* Load first line with a 0 tag, to check after */
208 write_c0_taglo(0);
209 write_c0_taghi(0);
210 cache_op(Index_Store_Tag_T, begin);
211
212 /* Look for the wrap-around */
213 pow2 = (512 * 1024);
214 for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
215 cache_op(Index_Load_Tag_T, addr);
216 if (!read_c0_taglo())
217 break;
218 pow2 <<= 1;
219 }
220
221 addr -= begin;
222 tcache_size = addr;
223
224 clear_c0_config(RM7K_CONF_TE);
225
226 local_irq_restore(flags);
227}
228
229void __cpuinit rm7k_sc_init(void)
230{
231 struct cpuinfo_mips *c = ¤t_cpu_data;
232 unsigned int config = read_c0_config();
233
234 if ((config & RM7K_CONF_SC))
235 return;
236
237 c->scache.linesz = sc_lsize;
238 c->scache.ways = 4;
239 c->scache.waybit= __ffs(scache_size / c->scache.ways);
240 c->scache.waysize = scache_size / c->scache.ways;
241 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
242 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
243 (scache_size >> 10), sc_lsize);
244
245 if (!(config & RM7K_CONF_SE))
246 rm7k_sc_enable();
247
248 bcops = &rm7k_sc_ops;
249
250 /*
251 * While we're at it let's deal with the tertiary cache.
252 */
253
254 rm7k_tcache_init = 0;
255 tcache_size = 0;
256
257 if (config & RM7K_CONF_TC)
258 return;
259
260 /*
261 * No efficient way to ask the hardware for the size of the tcache,
262 * so must probe for it.
263 */
264 run_uncached(__probe_tcache);
265 rm7k_tc_enable();
266 rm7k_tcache_init = 1;
267 c->tcache.linesz = tc_lsize;
268 c->tcache.ways = 1;
269 pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
270}
1/*
2 * sc-rm7k.c: RM7000 cache management functions.
3 *
4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
5 */
6
7#undef DEBUG
8
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/bitops.h>
12
13#include <asm/addrspace.h>
14#include <asm/bcache.h>
15#include <asm/cacheops.h>
16#include <asm/mipsregs.h>
17#include <asm/processor.h>
18#include <asm/sections.h>
19#include <asm/cacheflush.h> /* for run_uncached() */
20
21/* Primary cache parameters. */
22#define sc_lsize 32
23#define tc_pagesize (32*128)
24
25/* Secondary cache parameters. */
26#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
27
28/* Tertiary cache parameters */
29#define tc_lsize 32
30
31extern unsigned long icache_way_size, dcache_way_size;
32static unsigned long tcache_size;
33
34#include <asm/r4kcache.h>
35
36static int rm7k_tcache_init;
37
38/*
39 * Writeback and invalidate the primary cache dcache before DMA.
40 * (XXX These need to be fixed ...)
41 */
42static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
43{
44 unsigned long end, a;
45
46 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
47
48 /* Catch bad driver code */
49 BUG_ON(size == 0);
50
51 blast_scache_range(addr, addr + size);
52
53 if (!rm7k_tcache_init)
54 return;
55
56 a = addr & ~(tc_pagesize - 1);
57 end = (addr + size - 1) & ~(tc_pagesize - 1);
58 while(1) {
59 invalidate_tcache_page(a); /* Page_Invalidate_T */
60 if (a == end)
61 break;
62 a += tc_pagesize;
63 }
64}
65
66static void rm7k_sc_inv(unsigned long addr, unsigned long size)
67{
68 unsigned long end, a;
69
70 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
71
72 /* Catch bad driver code */
73 BUG_ON(size == 0);
74
75 blast_inv_scache_range(addr, addr + size);
76
77 if (!rm7k_tcache_init)
78 return;
79
80 a = addr & ~(tc_pagesize - 1);
81 end = (addr + size - 1) & ~(tc_pagesize - 1);
82 while(1) {
83 invalidate_tcache_page(a); /* Page_Invalidate_T */
84 if (a == end)
85 break;
86 a += tc_pagesize;
87 }
88}
89
90static void blast_rm7k_tcache(void)
91{
92 unsigned long start = CKSEG0ADDR(0);
93 unsigned long end = start + tcache_size;
94
95 write_c0_taglo(0);
96
97 while (start < end) {
98 cache_op(Page_Invalidate_T, start);
99 start += tc_pagesize;
100 }
101}
102
103/*
104 * This function is executed in uncached address space.
105 */
106static void __rm7k_tc_enable(void)
107{
108 int i;
109
110 set_c0_config(RM7K_CONF_TE);
111
112 write_c0_taglo(0);
113 write_c0_taghi(0);
114
115 for (i = 0; i < tcache_size; i += tc_lsize)
116 cache_op(Index_Store_Tag_T, CKSEG0ADDR(i));
117}
118
119static void rm7k_tc_enable(void)
120{
121 if (read_c0_config() & RM7K_CONF_TE)
122 return;
123
124 BUG_ON(tcache_size == 0);
125
126 run_uncached(__rm7k_tc_enable);
127}
128
129/*
130 * This function is executed in uncached address space.
131 */
132static void __rm7k_sc_enable(void)
133{
134 int i;
135
136 set_c0_config(RM7K_CONF_SE);
137
138 write_c0_taglo(0);
139 write_c0_taghi(0);
140
141 for (i = 0; i < scache_size; i += sc_lsize)
142 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
143}
144
145static void rm7k_sc_enable(void)
146{
147 if (read_c0_config() & RM7K_CONF_SE)
148 return;
149
150 pr_info("Enabling secondary cache...\n");
151 run_uncached(__rm7k_sc_enable);
152
153 if (rm7k_tcache_init)
154 rm7k_tc_enable();
155}
156
157static void rm7k_tc_disable(void)
158{
159 unsigned long flags;
160
161 local_irq_save(flags);
162 blast_rm7k_tcache();
163 clear_c0_config(RM7K_CONF_TE);
164 local_irq_save(flags);
165}
166
167static void rm7k_sc_disable(void)
168{
169 clear_c0_config(RM7K_CONF_SE);
170
171 if (rm7k_tcache_init)
172 rm7k_tc_disable();
173}
174
175static struct bcache_ops rm7k_sc_ops = {
176 .bc_enable = rm7k_sc_enable,
177 .bc_disable = rm7k_sc_disable,
178 .bc_wback_inv = rm7k_sc_wback_inv,
179 .bc_inv = rm7k_sc_inv
180};
181
182/*
183 * This is a probing function like the one found in c-r4k.c, we look for the
184 * wrap around point with different addresses.
185 */
186static void __probe_tcache(void)
187{
188 unsigned long flags, addr, begin, end, pow2;
189
190 begin = (unsigned long) &_stext;
191 begin &= ~((8 * 1024 * 1024) - 1);
192 end = begin + (8 * 1024 * 1024);
193
194 local_irq_save(flags);
195
196 set_c0_config(RM7K_CONF_TE);
197
198 /* Fill size-multiple lines with a valid tag */
199 pow2 = (256 * 1024);
200 for (addr = begin; addr <= end; addr = (begin + pow2)) {
201 unsigned long *p = (unsigned long *) addr;
202 __asm__ __volatile__("nop" : : "r" (*p));
203 pow2 <<= 1;
204 }
205
206 /* Load first line with a 0 tag, to check after */
207 write_c0_taglo(0);
208 write_c0_taghi(0);
209 cache_op(Index_Store_Tag_T, begin);
210
211 /* Look for the wrap-around */
212 pow2 = (512 * 1024);
213 for (addr = begin + (512 * 1024); addr <= end; addr = begin + pow2) {
214 cache_op(Index_Load_Tag_T, addr);
215 if (!read_c0_taglo())
216 break;
217 pow2 <<= 1;
218 }
219
220 addr -= begin;
221 tcache_size = addr;
222
223 clear_c0_config(RM7K_CONF_TE);
224
225 local_irq_restore(flags);
226}
227
228void rm7k_sc_init(void)
229{
230 struct cpuinfo_mips *c = ¤t_cpu_data;
231 unsigned int config = read_c0_config();
232
233 if ((config & RM7K_CONF_SC))
234 return;
235
236 c->scache.linesz = sc_lsize;
237 c->scache.ways = 4;
238 c->scache.waybit= __ffs(scache_size / c->scache.ways);
239 c->scache.waysize = scache_size / c->scache.ways;
240 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
241 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
242 (scache_size >> 10), sc_lsize);
243
244 if (!(config & RM7K_CONF_SE))
245 rm7k_sc_enable();
246
247 bcops = &rm7k_sc_ops;
248
249 /*
250 * While we're at it let's deal with the tertiary cache.
251 */
252
253 rm7k_tcache_init = 0;
254 tcache_size = 0;
255
256 if (config & RM7K_CONF_TC)
257 return;
258
259 /*
260 * No efficient way to ask the hardware for the size of the tcache,
261 * so must probe for it.
262 */
263 run_uncached(__probe_tcache);
264 rm7k_tc_enable();
265 rm7k_tcache_init = 1;
266 c->tcache.linesz = tc_lsize;
267 c->tcache.ways = 1;
268 pr_info("Tertiary cache size %ldK.\n", (tcache_size >> 10));
269}