1#ifndef _ASM_SMTC_MT_H
 2#define _ASM_SMTC_MT_H
 3
 4/*
 5 * Definitions for SMTC multitasking on MIPS MT cores
 6 */
 7
 8#include <asm/mips_mt.h>
 9#include <asm/smtc_ipi.h>
10
11/*
12 * System-wide SMTC status information
13 */
14
15extern unsigned int smtc_status;
16
17#define SMTC_TLB_SHARED	0x00000001
18#define SMTC_MTC_ACTIVE	0x00000002
19
20/*
21 * TLB/ASID Management information
22 */
23
24#define MAX_SMTC_TLBS 2
25#define MAX_SMTC_ASIDS 256
26#if NR_CPUS <= 8
27typedef char asiduse;
28#else
29#if NR_CPUS <= 16
30typedef short asiduse;
31#else
32typedef long asiduse;
33#endif
34#endif
35
36extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
37
38struct mm_struct;
39struct task_struct;
40
41void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
42void self_ipi(struct smtc_ipi *);
43void smtc_flush_tlb_asid(unsigned long asid);
44extern int smtc_build_cpu_map(int startslot);
45extern void smtc_prepare_cpus(int cpus);
46extern void smtc_smp_finish(void);
47extern void smtc_boot_secondary(int cpu, struct task_struct *t);
48extern void smtc_cpus_done(void);
49extern void smtc_init_secondary(void);
50
51
52/*
53 * Sharing the TLB between multiple VPEs means that the
54 * "random" index selection function is not allowed to
55 * select the current value of the Index register. To
56 * avoid additional TLB pressure, the Index registers
57 * are "parked" with an non-Valid value.
58 */
59
60#define PARKED_INDEX	((unsigned int)0x80000000)
61
62/*
63 * Define low-level interrupt mask for IPIs, if necessary.
64 * By default, use SW interrupt 1, which requires no external
65 * hardware support, but which works only for single-core
66 * MIPS MT systems.
67 */
68#ifndef MIPS_CPU_IPI_IRQ
69#define MIPS_CPU_IPI_IRQ 1
70#endif
71
72#endif /*  _ASM_SMTC_MT_H */