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1/*
2 * PCI Register definitions for the MIPS System Controller.
3 *
4 * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
12#define __ASM_MIPS_BOARDS_MSC01_IC_H
13
14/*****************************************************************************
15 * Register offset addresses
16 *****************************************************************************/
17
18#define MSC01_IC_RST_OFS 0x00008 /* Software reset */
19#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
20#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
21#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
22#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
23#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
24#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
25#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
26#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
27#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
28#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */
29#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */
30#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */
31#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */
32#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
33#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */
34#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */
35#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */
36#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */
37#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */
38#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */
39#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */
40#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
44
45/*****************************************************************************
46 * Register field encodings
47 *****************************************************************************/
48
49#define MSC01_IC_RST_RST_SHF 0
50#define MSC01_IC_RST_RST_MSK 0x00000001
51#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK
52#define MSC01_IC_LVL_LVL_SHF 0
53#define MSC01_IC_LVL_LVL_MSK 0x000000ff
54#define MSC01_IC_LVL_SPUR_SHF 16
55#define MSC01_IC_LVL_SPUR_MSK 0x00010000
56#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK
57#define MSC01_IC_RAMW_RIPL_SHF 0
58#define MSC01_IC_RAMW_RIPL_MSK 0x0000003f
59#define MSC01_IC_RAMW_DATA_SHF 6
60#define MSC01_IC_RAMW_DATA_MSK 0x00000fc0
61#define MSC01_IC_RAMW_ADDR_SHF 25
62#define MSC01_IC_RAMW_ADDR_MSK 0x7e000000
63#define MSC01_IC_RAMW_READ_SHF 31
64#define MSC01_IC_RAMW_READ_MSK 0x80000000
65#define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK
66#define MSC01_IC_OSB_OSB_SHF 0
67#define MSC01_IC_OSB_OSB_MSK 0x000000ff
68#define MSC01_IC_OSA_OSA_SHF 0
69#define MSC01_IC_OSA_OSA_MSK 0x000000ff
70#define MSC01_IC_GENA_GENA_SHF 0
71#define MSC01_IC_GENA_GENA_MSK 0x00000001
72#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK
73#define MSC01_IC_CFG_DIS_SHF 0
74#define MSC01_IC_CFG_DIS_MSK 0x00000001
75#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK
76#define MSC01_IC_CFG_SHFT_SHF 8
77#define MSC01_IC_CFG_SHFT_MSK 0x00000f00
78#define MSC01_IC_TCFG_ENA_SHF 0
79#define MSC01_IC_TCFG_ENA_MSK 0x00000001
80#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK
81#define MSC01_IC_TCFG_INT_SHF 8
82#define MSC01_IC_TCFG_INT_MSK 0x00000100
83#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK
84#define MSC01_IC_TCFG_EDGE_SHF 16
85#define MSC01_IC_TCFG_EDGE_MSK 0x00010000
86#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK
87#define MSC01_IC_SUP_PRI_SHF 0
88#define MSC01_IC_SUP_PRI_MSK 0x00000007
89#define MSC01_IC_SUP_EDGE_SHF 8
90#define MSC01_IC_SUP_EDGE_MSK 0x00000100
91#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK
92#define MSC01_IC_SUP_STEP 8
93
94/*
95 * MIPS System controller interrupt register base.
96 *
97 */
98
99/*****************************************************************************
100 * Absolute register addresses
101 *****************************************************************************/
102
103#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
104#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
105#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
106#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
107#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
108#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
109#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
110#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
111#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
112#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
113#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
114#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
115#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
116#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
117#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
118#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
119#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
120#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
121#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
122#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
123#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
124#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
125#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
126#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
127#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
128#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
129
130/*
131 * Soc-it interrupts are configurable.
132 * Every board describes its IRQ mapping with this table.
133 */
134typedef struct msc_irqmap {
135 int im_irq;
136 int im_type;
137 int im_lvl;
138} msc_irqmap_t;
139
140/* im_type */
141#define MSC01_IRQ_LEVEL 0
142#define MSC01_IRQ_EDGE 1
143
144extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
145extern void ll_msc_irq(void);
146
147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
1/*
2 * PCI Register definitions for the MIPS System Controller.
3 *
4 * Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
12#define __ASM_MIPS_BOARDS_MSC01_IC_H
13
14/*****************************************************************************
15 * Register offset addresses
16 *****************************************************************************/
17
18#define MSC01_IC_RST_OFS 0x00008 /* Software reset */
19#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
20#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
21#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
22#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
23#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
24#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
25#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
26#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
27#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
28#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */
29#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */
30#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */
31#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */
32#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
33#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */
34#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */
35#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */
36#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */
37#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */
38#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */
39#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */
40#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
44
45/*****************************************************************************
46 * Register field encodings
47 *****************************************************************************/
48
49#define MSC01_IC_RST_RST_SHF 0
50#define MSC01_IC_RST_RST_MSK 0x00000001
51#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK
52#define MSC01_IC_LVL_LVL_SHF 0
53#define MSC01_IC_LVL_LVL_MSK 0x000000ff
54#define MSC01_IC_LVL_SPUR_SHF 16
55#define MSC01_IC_LVL_SPUR_MSK 0x00010000
56#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK
57#define MSC01_IC_RAMW_RIPL_SHF 0
58#define MSC01_IC_RAMW_RIPL_MSK 0x0000003f
59#define MSC01_IC_RAMW_DATA_SHF 6
60#define MSC01_IC_RAMW_DATA_MSK 0x00000fc0
61#define MSC01_IC_RAMW_ADDR_SHF 25
62#define MSC01_IC_RAMW_ADDR_MSK 0x7e000000
63#define MSC01_IC_RAMW_READ_SHF 31
64#define MSC01_IC_RAMW_READ_MSK 0x80000000
65#define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK
66#define MSC01_IC_OSB_OSB_SHF 0
67#define MSC01_IC_OSB_OSB_MSK 0x000000ff
68#define MSC01_IC_OSA_OSA_SHF 0
69#define MSC01_IC_OSA_OSA_MSK 0x000000ff
70#define MSC01_IC_GENA_GENA_SHF 0
71#define MSC01_IC_GENA_GENA_MSK 0x00000001
72#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK
73#define MSC01_IC_CFG_DIS_SHF 0
74#define MSC01_IC_CFG_DIS_MSK 0x00000001
75#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK
76#define MSC01_IC_CFG_SHFT_SHF 8
77#define MSC01_IC_CFG_SHFT_MSK 0x00000f00
78#define MSC01_IC_TCFG_ENA_SHF 0
79#define MSC01_IC_TCFG_ENA_MSK 0x00000001
80#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK
81#define MSC01_IC_TCFG_INT_SHF 8
82#define MSC01_IC_TCFG_INT_MSK 0x00000100
83#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK
84#define MSC01_IC_TCFG_EDGE_SHF 16
85#define MSC01_IC_TCFG_EDGE_MSK 0x00010000
86#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK
87#define MSC01_IC_SUP_PRI_SHF 0
88#define MSC01_IC_SUP_PRI_MSK 0x00000007
89#define MSC01_IC_SUP_EDGE_SHF 8
90#define MSC01_IC_SUP_EDGE_MSK 0x00000100
91#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK
92#define MSC01_IC_SUP_STEP 8
93
94/*
95 * MIPS System controller interrupt register base.
96 *
97 */
98
99/*****************************************************************************
100 * Absolute register addresses
101 *****************************************************************************/
102
103#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
104#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
105#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
106#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
107#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
108#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
109#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
110#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
111#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
112#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
113#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
114#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
115#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
116#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
117#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
118#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
119#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
120#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
121#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
122#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
123#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
124#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
125#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
126#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
127#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
128#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
129
130/*
131 * Soc-it interrupts are configurable.
132 * Every board describes its IRQ mapping with this table.
133 */
134typedef struct msc_irqmap {
135 int im_irq;
136 int im_type;
137 int im_lvl;
138} msc_irqmap_t;
139
140/* im_type */
141#define MSC01_IRQ_LEVEL 0
142#define MSC01_IRQ_EDGE 1
143
144extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
145extern void ll_msc_irq(void);
146
147#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */