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1/*
2 * linux/arch/arm/kernel/head-nommu.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (C) 2003-2006 Hyok S. Choi
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Common kernel startup code (non-paged MM)
12 *
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/ptrace.h>
19#include <asm/asm-offsets.h>
20#include <asm/thread_info.h>
21#include <asm/system.h>
22
23/*
24 * Kernel startup entry point.
25 * ---------------------------
26 *
27 * This is normally called from the decompressor code. The requirements
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
29 * r1 = machine nr.
30 *
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
32 * numbers for r1.
33 *
34 */
35 .arm
36
37 __HEAD
38ENTRY(stext)
39
40 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
41 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
42 THUMB( .thumb ) @ switch to Thumb now.
43 THUMB(1: )
44
45 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
46 @ and irqs disabled
47#ifndef CONFIG_CPU_CP15
48 ldr r9, =CONFIG_PROCESSOR_ID
49#else
50 mrc p15, 0, r9, c0, c0 @ get processor id
51#endif
52 bl __lookup_processor_type @ r5=procinfo r9=cpuid
53 movs r10, r5 @ invalid processor (r5=0)?
54 beq __error_p @ yes, error 'p'
55
56 adr lr, BSYM(__after_proc_init) @ return (PIC) address
57 ARM( add pc, r10, #PROCINFO_INITFUNC )
58 THUMB( add r12, r10, #PROCINFO_INITFUNC )
59 THUMB( mov pc, r12 )
60ENDPROC(stext)
61
62/*
63 * Set the Control Register and Read the process ID.
64 */
65__after_proc_init:
66#ifdef CONFIG_CPU_CP15
67 /*
68 * CP15 system control register value returned in r0 from
69 * the CPU init function.
70 */
71#ifdef CONFIG_ALIGNMENT_TRAP
72 orr r0, r0, #CR_A
73#else
74 bic r0, r0, #CR_A
75#endif
76#ifdef CONFIG_CPU_DCACHE_DISABLE
77 bic r0, r0, #CR_C
78#endif
79#ifdef CONFIG_CPU_BPREDICT_DISABLE
80 bic r0, r0, #CR_Z
81#endif
82#ifdef CONFIG_CPU_ICACHE_DISABLE
83 bic r0, r0, #CR_I
84#endif
85#ifdef CONFIG_CPU_HIGH_VECTOR
86 orr r0, r0, #CR_V
87#else
88 bic r0, r0, #CR_V
89#endif
90 mcr p15, 0, r0, c1, c0, 0 @ write control reg
91#endif /* CONFIG_CPU_CP15 */
92
93 b __mmap_switched @ clear the BSS and jump
94 @ to start_kernel
95ENDPROC(__after_proc_init)
96 .ltorg
97
98#include "head-common.S"
1/*
2 * linux/arch/arm/kernel/head-nommu.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (C) 2003-2006 Hyok S. Choi
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Common kernel startup code (non-paged MM)
12 *
13 */
14#include <linux/linkage.h>
15#include <linux/init.h>
16
17#include <asm/assembler.h>
18#include <asm/ptrace.h>
19#include <asm/asm-offsets.h>
20#include <asm/memory.h>
21#include <asm/cp15.h>
22#include <asm/thread_info.h>
23#include <asm/v7m.h>
24#include <asm/mpu.h>
25#include <asm/page.h>
26
27/*
28 * Kernel startup entry point.
29 * ---------------------------
30 *
31 * This is normally called from the decompressor code. The requirements
32 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
33 * r1 = machine nr.
34 *
35 * See linux/arch/arm/tools/mach-types for the complete list of machine
36 * numbers for r1.
37 *
38 */
39
40 __HEAD
41
42#ifdef CONFIG_CPU_THUMBONLY
43 .thumb
44ENTRY(stext)
45#else
46 .arm
47ENTRY(stext)
48
49 THUMB( badr r9, 1f ) @ Kernel is always entered in ARM.
50 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
51 THUMB( .thumb ) @ switch to Thumb now.
52 THUMB(1: )
53#endif
54
55 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
56 @ and irqs disabled
57#if defined(CONFIG_CPU_CP15)
58 mrc p15, 0, r9, c0, c0 @ get processor id
59#elif defined(CONFIG_CPU_V7M)
60 ldr r9, =BASEADDR_V7M_SCB
61 ldr r9, [r9, V7M_SCB_CPUID]
62#else
63 ldr r9, =CONFIG_PROCESSOR_ID
64#endif
65 bl __lookup_processor_type @ r5=procinfo r9=cpuid
66 movs r10, r5 @ invalid processor (r5=0)?
67 beq __error_p @ yes, error 'p'
68
69#ifdef CONFIG_ARM_MPU
70 /* Calculate the size of a region covering just the kernel */
71 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
72 ldr r6, =(_end) @ Cover whole kernel
73 sub r6, r6, r5 @ Minimum size of region to map
74 clz r6, r6 @ Region size must be 2^N...
75 rsb r6, r6, #31 @ ...so round up region size
76 lsl r6, r6, #MPU_RSR_SZ @ Put size in right field
77 orr r6, r6, #(1 << MPU_RSR_EN) @ Set region enabled bit
78 bl __setup_mpu
79#endif
80
81 badr lr, 1f @ return (PIC) address
82 ldr r12, [r10, #PROCINFO_INITFUNC]
83 add r12, r12, r10
84 ret r12
851: bl __after_proc_init
86 b __mmap_switched
87ENDPROC(stext)
88
89#ifdef CONFIG_SMP
90 .text
91ENTRY(secondary_startup)
92 /*
93 * Common entry point for secondary CPUs.
94 *
95 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
96 * the processor type - there is no need to check the machine type
97 * as it has already been validated by the primary processor.
98 */
99 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
100#ifndef CONFIG_CPU_CP15
101 ldr r9, =CONFIG_PROCESSOR_ID
102#else
103 mrc p15, 0, r9, c0, c0 @ get processor id
104#endif
105 bl __lookup_processor_type @ r5=procinfo r9=cpuid
106 movs r10, r5 @ invalid processor?
107 beq __error_p @ yes, error 'p'
108
109 ldr r7, __secondary_data
110
111#ifdef CONFIG_ARM_MPU
112 /* Use MPU region info supplied by __cpu_up */
113 ldr r6, [r7] @ get secondary_data.mpu_szr
114 bl __setup_mpu @ Initialize the MPU
115#endif
116
117 badr lr, 1f @ return (PIC) address
118 ldr r12, [r10, #PROCINFO_INITFUNC]
119 add r12, r12, r10
120 ret r12
1211: bl __after_proc_init
122 ldr sp, [r7, #12] @ set up the stack pointer
123 mov fp, #0
124 b secondary_start_kernel
125ENDPROC(secondary_startup)
126
127 .type __secondary_data, %object
128__secondary_data:
129 .long secondary_data
130#endif /* CONFIG_SMP */
131
132/*
133 * Set the Control Register and Read the process ID.
134 */
135__after_proc_init:
136#ifdef CONFIG_CPU_CP15
137 /*
138 * CP15 system control register value returned in r0 from
139 * the CPU init function.
140 */
141#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
142 orr r0, r0, #CR_A
143#else
144 bic r0, r0, #CR_A
145#endif
146#ifdef CONFIG_CPU_DCACHE_DISABLE
147 bic r0, r0, #CR_C
148#endif
149#ifdef CONFIG_CPU_BPREDICT_DISABLE
150 bic r0, r0, #CR_Z
151#endif
152#ifdef CONFIG_CPU_ICACHE_DISABLE
153 bic r0, r0, #CR_I
154#endif
155#ifdef CONFIG_CPU_HIGH_VECTOR
156 orr r0, r0, #CR_V
157#else
158 bic r0, r0, #CR_V
159#endif
160 mcr p15, 0, r0, c1, c0, 0 @ write control reg
161#endif /* CONFIG_CPU_CP15 */
162 ret lr
163ENDPROC(__after_proc_init)
164 .ltorg
165
166#ifdef CONFIG_ARM_MPU
167
168
169/* Set which MPU region should be programmed */
170.macro set_region_nr tmp, rgnr
171 mov \tmp, \rgnr @ Use static region numbers
172 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
173.endm
174
175/* Setup a single MPU region, either D or I side (D-side for unified) */
176.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
177 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
178 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
179 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
180.endm
181
182/*
183 * Setup the MPU and initial MPU Regions. We create the following regions:
184 * Region 0: Use this for probing the MPU details, so leave disabled.
185 * Region 1: Background region - covers the whole of RAM as strongly ordered
186 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
187 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
188 *
189 * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
190*/
191
192ENTRY(__setup_mpu)
193
194 /* Probe for v7 PMSA compliance */
195 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0
196 and r0, r0, #(MMFR0_PMSA) @ PMSA field
197 teq r0, #(MMFR0_PMSAv7) @ PMSA v7
198 bne __error_p @ Fail: ARM_MPU on NOT v7 PMSA
199
200 /* Determine whether the D/I-side memory map is unified. We set the
201 * flags here and continue to use them for the rest of this function */
202 mrc p15, 0, r0, c0, c0, 4 @ MPUIR
203 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU
204 beq __error_p @ Fail: ARM_MPU and no MPU
205 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified
206
207 /* Setup second region first to free up r6 */
208 set_region_nr r0, #MPU_RAM_REGION
209 isb
210 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
211 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
212 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
213
214 setup_region r0, r5, r6, MPU_DATA_SIDE @ PHYS_OFFSET, shared, enabled
215 beq 1f @ Memory-map not unified
216 setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
2171: isb
218
219 /* First/background region */
220 set_region_nr r0, #MPU_BG_REGION
221 isb
222 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */
223 mov r0, #0 @ BG region starts at 0x0
224 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
225 mov r6, #MPU_RSR_ALL_MEM @ 4GB region, enabled
226
227 setup_region r0, r5, r6, MPU_DATA_SIDE @ 0x0, BG region, enabled
228 beq 2f @ Memory-map not unified
229 setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
2302: isb
231
232 /* Vectors region */
233 set_region_nr r0, #MPU_VECTORS_REGION
234 isb
235 /* Shared, inaccessible to PL0, rw PL1 */
236 mov r0, #CONFIG_VECTORS_BASE @ Cover from VECTORS_BASE
237 ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
238 /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
239 mov r6, #(((2 * PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
240
241 setup_region r0, r5, r6, MPU_DATA_SIDE @ VECTORS_BASE, PL0 NA, enabled
242 beq 3f @ Memory-map not unified
243 setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
2443: isb
245
246 /* Enable the MPU */
247 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
248 bic r0, r0, #CR_BR @ Disable the 'default mem-map'
249 orr r0, r0, #CR_M @ Set SCTRL.M (MPU on)
250 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
251 isb
252 ret lr
253ENDPROC(__setup_mpu)
254#endif
255#include "head-common.S"