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1#ifndef __ALPHA_IRONGATE__H__
2#define __ALPHA_IRONGATE__H__
3
4#include <linux/types.h>
5#include <asm/compiler.h>
6
7/*
8 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
9 * which provides memory controller and PCI access for NAUTILUS-based
10 * EV6 (21264) systems.
11 *
12 * This file is based on:
13 *
14 * IronGate management library, (c) 1999 Alpha Processor, Inc.
15 * Copyright (C) 1999 Alpha Processor, Inc.,
16 * (David Daniel, Stig Telfer, Soohoon Lee)
17 */
18
19/*
20 * The 21264 supports, and internally recognizes, a 44-bit physical
21 * address space that is divided equally between memory address space
22 * and I/O address space. Memory address space resides in the lower
23 * half of the physical address space (PA[43]=0) and I/O address space
24 * resides in the upper half of the physical address space (PA[43]=1).
25 */
26
27/*
28 * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
29 * through the routines given is 32-bit.
30 *
31 * The first 0x40 bytes are standard as per the PCI spec.
32 */
33
34typedef volatile __u32 igcsr32;
35
36typedef struct {
37 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
38 igcsr32 stat_cmd; /* 0x04 - status, command */
39 igcsr32 class; /* 0x08 - class code, rev ID */
40 igcsr32 latency; /* 0x0C - header type, PCI latency */
41 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
42 igcsr32 bar1; /* 0x14 - BAR1 - GART */
43 igcsr32 bar2; /* 0x18 - Power Management reg block */
44
45 igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
46
47 igcsr32 capptr; /* 0x34 - Capabilities pointer */
48
49 igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
50
51 igcsr32 bacsr10; /* 0x40 - base address chip selects */
52 igcsr32 bacsr32; /* 0x44 - base address chip selects */
53 igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
54 761: ECC, mode/status */
55
56 igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
57
58 igcsr32 drammap; /* 0x50 - address mapping control */
59 igcsr32 dramtm; /* 0x54 - timing, driver strength */
60 igcsr32 dramms; /* 0x58 - DRAM mode/status */
61
62 igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
63
64 igcsr32 biu0; /* 0x60 - bus interface unit */
65 igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
66
67 igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
68
69 igcsr32 mro; /* 0x70 - memory request optimiser */
70
71 igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
72
73 igcsr32 whami; /* 0x80 - who am I */
74 igcsr32 pciarb; /* 0x84 - PCI arbitration control */
75 igcsr32 pcicfg; /* 0x88 - PCI config status */
76
77 igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
78
79 igcsr32 pci_mem; /* 0x9C - PCI top of memory,
80 761 only */
81
82 /* AGP (bus 1) control registers */
83 igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
84 igcsr32 agpstat; /* 0xA4 - AGP status register */
85 igcsr32 agpcmd; /* 0xA8 - AGP control register */
86 igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
87 igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
88} Irongate0;
89
90
91typedef struct {
92
93 igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
94 igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
95 igcsr32 class; /* 0x08 - subclass, baseclass etc */
96 igcsr32 htype; /* 0x0C - header type (at 0x0E) */
97 igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
98 igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
99 igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
100 igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
101 igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
102 igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
103 igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
104 igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
105 igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
106
107} Irongate1;
108
109extern igcsr32 *IronECC;
110
111/*
112 * Memory spaces:
113 */
114
115/* Irongate is consistent with a subset of the Tsunami memory map */
116#ifdef USE_48_BIT_KSEG
117#define IRONGATE_BIAS 0x80000000000UL
118#else
119#define IRONGATE_BIAS 0x10000000000UL
120#endif
121
122
123#define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
124#define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
125#define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
126#define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
127
128/*
129 * PCI Configuration space accesses are formed like so:
130 *
131 * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
132 * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
133 * ---bus numer--- -device-- -fun- ---register----
134 */
135
136#define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
137 ((dev)<<11) | \
138 ((fun)<<8) | \
139 (reg) )
140
141#define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
142#define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
143
144/*
145 * Data structure for handling IRONGATE machine checks:
146 * This is the standard OSF logout frame
147 */
148
149#define SCB_Q_SYSERR 0x620 /* OSF definitions */
150#define SCB_Q_PROCERR 0x630
151#define SCB_Q_SYSMCHK 0x660
152#define SCB_Q_PROCMCHK 0x670
153
154struct el_IRONGATE_sysdata_mcheck {
155 __u32 FrameSize; /* Bytes, including this field */
156 __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
157 __u32 CpuOffset; /* Offset to CPU-specific into */
158 __u32 SystemOffset; /* Offset to system-specific info */
159 __u32 MCHK_Code;
160 __u32 MCHK_Frame_Rev;
161 __u64 I_STAT;
162 __u64 DC_STAT;
163 __u64 C_ADDR;
164 __u64 DC1_SYNDROME;
165 __u64 DC0_SYNDROME;
166 __u64 C_STAT;
167 __u64 C_STS;
168 __u64 RESERVED0;
169 __u64 EXC_ADDR;
170 __u64 IER_CM;
171 __u64 ISUM;
172 __u64 MM_STAT;
173 __u64 PAL_BASE;
174 __u64 I_CTL;
175 __u64 PCTX;
176};
177
178
179#ifdef __KERNEL__
180
181#ifndef __EXTERN_INLINE
182#define __EXTERN_INLINE extern inline
183#define __IO_EXTERN_INLINE
184#endif
185
186/*
187 * I/O functions:
188 *
189 * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
190 * K7 can only use linear accesses to get at PCI memory and I/O spaces.
191 */
192
193/*
194 * Memory functions. All accesses are done through linear space.
195 */
196
197__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
198{
199 return (void __iomem *)(addr + IRONGATE_IO);
200}
201
202extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
203extern void irongate_iounmap(volatile void __iomem *addr);
204
205__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
206{
207 return addr >= IRONGATE_MEM;
208}
209
210__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
211{
212 unsigned long addr = (unsigned long)xaddr;
213 return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
214}
215
216#undef __IO_PREFIX
217#define __IO_PREFIX irongate
218#define irongate_trivial_rw_bw 1
219#define irongate_trivial_rw_lq 1
220#define irongate_trivial_io_bw 1
221#define irongate_trivial_io_lq 1
222#define irongate_trivial_iounmap 0
223#include <asm/io_trivial.h>
224
225#ifdef __IO_EXTERN_INLINE
226#undef __EXTERN_INLINE
227#undef __IO_EXTERN_INLINE
228#endif
229
230#endif /* __KERNEL__ */
231
232#endif /* __ALPHA_IRONGATE__H__ */
1#ifndef __ALPHA_IRONGATE__H__
2#define __ALPHA_IRONGATE__H__
3
4#include <linux/types.h>
5#include <asm/compiler.h>
6
7/*
8 * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
9 * which provides memory controller and PCI access for NAUTILUS-based
10 * EV6 (21264) systems.
11 *
12 * This file is based on:
13 *
14 * IronGate management library, (c) 1999 Alpha Processor, Inc.
15 * Copyright (C) 1999 Alpha Processor, Inc.,
16 * (David Daniel, Stig Telfer, Soohoon Lee)
17 */
18
19/*
20 * The 21264 supports, and internally recognizes, a 44-bit physical
21 * address space that is divided equally between memory address space
22 * and I/O address space. Memory address space resides in the lower
23 * half of the physical address space (PA[43]=0) and I/O address space
24 * resides in the upper half of the physical address space (PA[43]=1).
25 */
26
27/*
28 * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
29 * through the routines given is 32-bit.
30 *
31 * The first 0x40 bytes are standard as per the PCI spec.
32 */
33
34typedef volatile __u32 igcsr32;
35
36typedef struct {
37 igcsr32 dev_vendor; /* 0x00 - device ID, vendor ID */
38 igcsr32 stat_cmd; /* 0x04 - status, command */
39 igcsr32 class; /* 0x08 - class code, rev ID */
40 igcsr32 latency; /* 0x0C - header type, PCI latency */
41 igcsr32 bar0; /* 0x10 - BAR0 - AGP */
42 igcsr32 bar1; /* 0x14 - BAR1 - GART */
43 igcsr32 bar2; /* 0x18 - Power Management reg block */
44
45 igcsr32 rsrvd0[6]; /* 0x1C-0x33 reserved */
46
47 igcsr32 capptr; /* 0x34 - Capabilities pointer */
48
49 igcsr32 rsrvd1[2]; /* 0x38-0x3F reserved */
50
51 igcsr32 bacsr10; /* 0x40 - base address chip selects */
52 igcsr32 bacsr32; /* 0x44 - base address chip selects */
53 igcsr32 bacsr54_eccms761; /* 0x48 - 751: base addr. chip selects
54 761: ECC, mode/status */
55
56 igcsr32 rsrvd2[1]; /* 0x4C-0x4F reserved */
57
58 igcsr32 drammap; /* 0x50 - address mapping control */
59 igcsr32 dramtm; /* 0x54 - timing, driver strength */
60 igcsr32 dramms; /* 0x58 - DRAM mode/status */
61
62 igcsr32 rsrvd3[1]; /* 0x5C-0x5F reserved */
63
64 igcsr32 biu0; /* 0x60 - bus interface unit */
65 igcsr32 biusip; /* 0x64 - Serial initialisation pkt */
66
67 igcsr32 rsrvd4[2]; /* 0x68-0x6F reserved */
68
69 igcsr32 mro; /* 0x70 - memory request optimiser */
70
71 igcsr32 rsrvd5[3]; /* 0x74-0x7F reserved */
72
73 igcsr32 whami; /* 0x80 - who am I */
74 igcsr32 pciarb; /* 0x84 - PCI arbitration control */
75 igcsr32 pcicfg; /* 0x88 - PCI config status */
76
77 igcsr32 rsrvd6[4]; /* 0x8C-0x9B reserved */
78
79 igcsr32 pci_mem; /* 0x9C - PCI top of memory,
80 761 only */
81
82 /* AGP (bus 1) control registers */
83 igcsr32 agpcap; /* 0xA0 - AGP Capability Identifier */
84 igcsr32 agpstat; /* 0xA4 - AGP status register */
85 igcsr32 agpcmd; /* 0xA8 - AGP control register */
86 igcsr32 agpva; /* 0xAC - AGP Virtual Address Space */
87 igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
88} Irongate0;
89
90
91typedef struct {
92
93 igcsr32 dev_vendor; /* 0x00 - Device and Vendor IDs */
94 igcsr32 stat_cmd; /* 0x04 - Status and Command regs */
95 igcsr32 class; /* 0x08 - subclass, baseclass etc */
96 igcsr32 htype; /* 0x0C - header type (at 0x0E) */
97 igcsr32 rsrvd0[2]; /* 0x10-0x17 reserved */
98 igcsr32 busnos; /* 0x18 - Primary, secondary bus nos */
99 igcsr32 io_baselim_regs; /* 0x1C - IO base, IO lim, AGP status */
100 igcsr32 mem_baselim; /* 0x20 - memory base, memory lim */
101 igcsr32 pfmem_baselim; /* 0x24 - prefetchable base, lim */
102 igcsr32 rsrvd1[2]; /* 0x28-0x2F reserved */
103 igcsr32 io_baselim; /* 0x30 - IO base, IO limit */
104 igcsr32 rsrvd2[2]; /* 0x34-0x3B - reserved */
105 igcsr32 interrupt; /* 0x3C - interrupt, PCI bridge ctrl */
106
107} Irongate1;
108
109extern igcsr32 *IronECC;
110
111/*
112 * Memory spaces:
113 */
114
115/* Irongate is consistent with a subset of the Tsunami memory map */
116#ifdef USE_48_BIT_KSEG
117#define IRONGATE_BIAS 0x80000000000UL
118#else
119#define IRONGATE_BIAS 0x10000000000UL
120#endif
121
122
123#define IRONGATE_MEM (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
124#define IRONGATE_IACK_SC (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
125#define IRONGATE_IO (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
126#define IRONGATE_CONF (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
127
128/*
129 * PCI Configuration space accesses are formed like so:
130 *
131 * 0x1FE << 24 | : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
132 * : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
133 * ---bus numer--- -device-- -fun- ---register----
134 */
135
136#define IGCSR(dev,fun,reg) ( IRONGATE_CONF | \
137 ((dev)<<11) | \
138 ((fun)<<8) | \
139 (reg) )
140
141#define IRONGATE0 ((Irongate0 *) IGCSR(0, 0, 0))
142#define IRONGATE1 ((Irongate1 *) IGCSR(1, 0, 0))
143
144/*
145 * Data structure for handling IRONGATE machine checks:
146 * This is the standard OSF logout frame
147 */
148
149#define SCB_Q_SYSERR 0x620 /* OSF definitions */
150#define SCB_Q_PROCERR 0x630
151#define SCB_Q_SYSMCHK 0x660
152#define SCB_Q_PROCMCHK 0x670
153
154struct el_IRONGATE_sysdata_mcheck {
155 __u32 FrameSize; /* Bytes, including this field */
156 __u32 FrameFlags; /* <31> = Retry, <30> = Second Error */
157 __u32 CpuOffset; /* Offset to CPU-specific into */
158 __u32 SystemOffset; /* Offset to system-specific info */
159 __u32 MCHK_Code;
160 __u32 MCHK_Frame_Rev;
161 __u64 I_STAT;
162 __u64 DC_STAT;
163 __u64 C_ADDR;
164 __u64 DC1_SYNDROME;
165 __u64 DC0_SYNDROME;
166 __u64 C_STAT;
167 __u64 C_STS;
168 __u64 RESERVED0;
169 __u64 EXC_ADDR;
170 __u64 IER_CM;
171 __u64 ISUM;
172 __u64 MM_STAT;
173 __u64 PAL_BASE;
174 __u64 I_CTL;
175 __u64 PCTX;
176};
177
178
179#ifdef __KERNEL__
180
181#ifndef __EXTERN_INLINE
182#define __EXTERN_INLINE extern inline
183#define __IO_EXTERN_INLINE
184#endif
185
186/*
187 * I/O functions:
188 *
189 * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
190 * K7 can only use linear accesses to get at PCI memory and I/O spaces.
191 */
192
193/*
194 * Memory functions. All accesses are done through linear space.
195 */
196
197__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
198{
199 return (void __iomem *)(addr + IRONGATE_IO);
200}
201
202extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
203extern void irongate_iounmap(volatile void __iomem *addr);
204
205__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
206{
207 return addr >= IRONGATE_MEM;
208}
209
210__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
211{
212 unsigned long addr = (unsigned long)xaddr;
213 return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
214}
215
216#undef __IO_PREFIX
217#define __IO_PREFIX irongate
218#define irongate_trivial_rw_bw 1
219#define irongate_trivial_rw_lq 1
220#define irongate_trivial_io_bw 1
221#define irongate_trivial_io_lq 1
222#define irongate_trivial_iounmap 0
223#include <asm/io_trivial.h>
224
225#ifdef __IO_EXTERN_INLINE
226#undef __EXTERN_INLINE
227#undef __IO_EXTERN_INLINE
228#endif
229
230#endif /* __KERNEL__ */
231
232#endif /* __ALPHA_IRONGATE__H__ */