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1/*
2 * Copyright (C) 2013 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __MSM_DRM_H__
19#define __MSM_DRM_H__
20
21#include "drm.h"
22
23/* Please note that modifications to all structs defined here are
24 * subject to backwards-compatibility constraints:
25 * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
26 * user/kernel compatibility
27 * 2) Keep fields aligned to their size
28 * 3) Because of how drm_ioctl() works, we can add new fields at
29 * the end of an ioctl if some care is taken: drm_ioctl() will
30 * zero out the new fields at the tail of the ioctl, so a zero
31 * value should have a backwards compatible meaning. And for
32 * output params, userspace won't see the newly added output
33 * fields.. so that has to be somehow ok.
34 */
35
36#define MSM_PIPE_NONE 0x00
37#define MSM_PIPE_2D0 0x01
38#define MSM_PIPE_2D1 0x02
39#define MSM_PIPE_3D0 0x10
40
41/* timeouts are specified in clock-monotonic absolute times (to simplify
42 * restarting interrupted ioctls). The following struct is logically the
43 * same as 'struct timespec' but 32/64b ABI safe.
44 */
45struct drm_msm_timespec {
46 __s64 tv_sec; /* seconds */
47 __s64 tv_nsec; /* nanoseconds */
48};
49
50#define MSM_PARAM_GPU_ID 0x01
51#define MSM_PARAM_GMEM_SIZE 0x02
52#define MSM_PARAM_CHIP_ID 0x03
53#define MSM_PARAM_MAX_FREQ 0x04
54#define MSM_PARAM_TIMESTAMP 0x05
55
56struct drm_msm_param {
57 __u32 pipe; /* in, MSM_PIPE_x */
58 __u32 param; /* in, MSM_PARAM_x */
59 __u64 value; /* out (get_param) or in (set_param) */
60};
61
62/*
63 * GEM buffers:
64 */
65
66#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
67#define MSM_BO_GPU_READONLY 0x00000002
68#define MSM_BO_CACHE_MASK 0x000f0000
69/* cache modes */
70#define MSM_BO_CACHED 0x00010000
71#define MSM_BO_WC 0x00020000
72#define MSM_BO_UNCACHED 0x00040000
73
74#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
75 MSM_BO_GPU_READONLY | \
76 MSM_BO_CACHED | \
77 MSM_BO_WC | \
78 MSM_BO_UNCACHED)
79
80struct drm_msm_gem_new {
81 __u64 size; /* in */
82 __u32 flags; /* in, mask of MSM_BO_x */
83 __u32 handle; /* out */
84};
85
86struct drm_msm_gem_info {
87 __u32 handle; /* in */
88 __u32 pad;
89 __u64 offset; /* out, offset to pass to mmap() */
90};
91
92#define MSM_PREP_READ 0x01
93#define MSM_PREP_WRITE 0x02
94#define MSM_PREP_NOSYNC 0x04
95
96#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
97
98struct drm_msm_gem_cpu_prep {
99 __u32 handle; /* in */
100 __u32 op; /* in, mask of MSM_PREP_x */
101 struct drm_msm_timespec timeout; /* in */
102};
103
104struct drm_msm_gem_cpu_fini {
105 __u32 handle; /* in */
106};
107
108/*
109 * Cmdstream Submission:
110 */
111
112/* The value written into the cmdstream is logically:
113 *
114 * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
115 *
116 * When we have GPU's w/ >32bit ptrs, it should be possible to deal
117 * with this by emit'ing two reloc entries with appropriate shift
118 * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
119 *
120 * NOTE that reloc's must be sorted by order of increasing submit_offset,
121 * otherwise EINVAL.
122 */
123struct drm_msm_gem_submit_reloc {
124 __u32 submit_offset; /* in, offset from submit_bo */
125 __u32 or; /* in, value OR'd with result */
126 __s32 shift; /* in, amount of left shift (can be negative) */
127 __u32 reloc_idx; /* in, index of reloc_bo buffer */
128 __u64 reloc_offset; /* in, offset from start of reloc_bo */
129};
130
131/* submit-types:
132 * BUF - this cmd buffer is executed normally.
133 * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
134 * processed normally, but the kernel does not setup an IB to
135 * this buffer in the first-level ringbuffer
136 * CTX_RESTORE_BUF - only executed if there has been a GPU context
137 * switch since the last SUBMIT ioctl
138 */
139#define MSM_SUBMIT_CMD_BUF 0x0001
140#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
141#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
142struct drm_msm_gem_submit_cmd {
143 __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
144 __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
145 __u32 submit_offset; /* in, offset into submit_bo */
146 __u32 size; /* in, cmdstream size */
147 __u32 pad;
148 __u32 nr_relocs; /* in, number of submit_reloc's */
149 __u64 __user relocs; /* in, ptr to array of submit_reloc's */
150};
151
152/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
153 * cmdstream buffer(s) themselves or reloc entries) has one (and only
154 * one) entry in the submit->bos[] table.
155 *
156 * As a optimization, the current buffer (gpu virtual address) can be
157 * passed back through the 'presumed' field. If on a subsequent reloc,
158 * userspace passes back a 'presumed' address that is still valid,
159 * then patching the cmdstream for this entry is skipped. This can
160 * avoid kernel needing to map/access the cmdstream bo in the common
161 * case.
162 */
163#define MSM_SUBMIT_BO_READ 0x0001
164#define MSM_SUBMIT_BO_WRITE 0x0002
165
166#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
167
168struct drm_msm_gem_submit_bo {
169 __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
170 __u32 handle; /* in, GEM handle */
171 __u64 presumed; /* in/out, presumed buffer address */
172};
173
174/* Each cmdstream submit consists of a table of buffers involved, and
175 * one or more cmdstream buffers. This allows for conditional execution
176 * (context-restore), and IB buffers needed for per tile/bin draw cmds.
177 */
178struct drm_msm_gem_submit {
179 __u32 pipe; /* in, MSM_PIPE_x */
180 __u32 fence; /* out */
181 __u32 nr_bos; /* in, number of submit_bo's */
182 __u32 nr_cmds; /* in, number of submit_cmd's */
183 __u64 __user bos; /* in, ptr to array of submit_bo's */
184 __u64 __user cmds; /* in, ptr to array of submit_cmd's */
185};
186
187/* The normal way to synchronize with the GPU is just to CPU_PREP on
188 * a buffer if you need to access it from the CPU (other cmdstream
189 * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
190 * handle the required synchronization under the hood). This ioctl
191 * mainly just exists as a way to implement the gallium pipe_fence
192 * APIs without requiring a dummy bo to synchronize on.
193 */
194struct drm_msm_wait_fence {
195 __u32 fence; /* in */
196 __u32 pad;
197 struct drm_msm_timespec timeout; /* in */
198};
199
200#define DRM_MSM_GET_PARAM 0x00
201/* placeholder:
202#define DRM_MSM_SET_PARAM 0x01
203 */
204#define DRM_MSM_GEM_NEW 0x02
205#define DRM_MSM_GEM_INFO 0x03
206#define DRM_MSM_GEM_CPU_PREP 0x04
207#define DRM_MSM_GEM_CPU_FINI 0x05
208#define DRM_MSM_GEM_SUBMIT 0x06
209#define DRM_MSM_WAIT_FENCE 0x07
210#define DRM_MSM_NUM_IOCTLS 0x08
211
212#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
213#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
214#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
215#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
216#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
217#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
218#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
219
220#endif /* __MSM_DRM_H__ */