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1/*
2 * hw.h - DesignWare HS OTG Controller hardware definitions
3 *
4 * Copyright 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_HW_H__
38#define __DWC2_HW_H__
39
40#define HSOTG_REG(x) (x)
41
42#define GOTGCTL HSOTG_REG(0x000)
43#define GOTGCTL_CHIRPEN (1 << 27)
44#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
45#define GOTGCTL_MULT_VALID_BC_SHIFT 22
46#define GOTGCTL_OTGVER (1 << 20)
47#define GOTGCTL_BSESVLD (1 << 19)
48#define GOTGCTL_ASESVLD (1 << 18)
49#define GOTGCTL_DBNC_SHORT (1 << 17)
50#define GOTGCTL_CONID_B (1 << 16)
51#define GOTGCTL_DEVHNPEN (1 << 11)
52#define GOTGCTL_HSTSETHNPEN (1 << 10)
53#define GOTGCTL_HNPREQ (1 << 9)
54#define GOTGCTL_HSTNEGSCS (1 << 8)
55#define GOTGCTL_SESREQ (1 << 1)
56#define GOTGCTL_SESREQSCS (1 << 0)
57
58#define GOTGINT HSOTG_REG(0x004)
59#define GOTGINT_DBNCE_DONE (1 << 19)
60#define GOTGINT_A_DEV_TOUT_CHG (1 << 18)
61#define GOTGINT_HST_NEG_DET (1 << 17)
62#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9)
63#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8)
64#define GOTGINT_SES_END_DET (1 << 2)
65
66#define GAHBCFG HSOTG_REG(0x008)
67#define GAHBCFG_AHB_SINGLE (1 << 23)
68#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22)
69#define GAHBCFG_REM_MEM_SUPP (1 << 21)
70#define GAHBCFG_P_TXF_EMP_LVL (1 << 8)
71#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7)
72#define GAHBCFG_DMA_EN (1 << 5)
73#define GAHBCFG_HBSTLEN_MASK (0xf << 1)
74#define GAHBCFG_HBSTLEN_SHIFT 1
75#define GAHBCFG_HBSTLEN_SINGLE 0
76#define GAHBCFG_HBSTLEN_INCR 1
77#define GAHBCFG_HBSTLEN_INCR4 3
78#define GAHBCFG_HBSTLEN_INCR8 5
79#define GAHBCFG_HBSTLEN_INCR16 7
80#define GAHBCFG_GLBL_INTR_EN (1 << 0)
81#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
82 GAHBCFG_NP_TXF_EMP_LVL | \
83 GAHBCFG_DMA_EN | \
84 GAHBCFG_GLBL_INTR_EN)
85
86#define GUSBCFG HSOTG_REG(0x00C)
87#define GUSBCFG_FORCEDEVMODE (1 << 30)
88#define GUSBCFG_FORCEHOSTMODE (1 << 29)
89#define GUSBCFG_TXENDDELAY (1 << 28)
90#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27)
91#define GUSBCFG_ICUSBCAP (1 << 26)
92#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25)
93#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24)
94#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23)
95#define GUSBCFG_TERMSELDLPULSE (1 << 22)
96#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21)
97#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20)
98#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19)
99#define GUSBCFG_ULPI_AUTO_RES (1 << 18)
100#define GUSBCFG_ULPI_FS_LS (1 << 17)
101#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16)
102#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15)
103#define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
104#define GUSBCFG_USBTRDTIM_SHIFT 10
105#define GUSBCFG_HNPCAP (1 << 9)
106#define GUSBCFG_SRPCAP (1 << 8)
107#define GUSBCFG_DDRSEL (1 << 7)
108#define GUSBCFG_PHYSEL (1 << 6)
109#define GUSBCFG_FSINTF (1 << 5)
110#define GUSBCFG_ULPI_UTMI_SEL (1 << 4)
111#define GUSBCFG_PHYIF16 (1 << 3)
112#define GUSBCFG_PHYIF8 (0 << 3)
113#define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
114#define GUSBCFG_TOUTCAL_SHIFT 0
115#define GUSBCFG_TOUTCAL_LIMIT 0x7
116#define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
117
118#define GRSTCTL HSOTG_REG(0x010)
119#define GRSTCTL_AHBIDLE (1 << 31)
120#define GRSTCTL_DMAREQ (1 << 30)
121#define GRSTCTL_TXFNUM_MASK (0x1f << 6)
122#define GRSTCTL_TXFNUM_SHIFT 6
123#define GRSTCTL_TXFNUM_LIMIT 0x1f
124#define GRSTCTL_TXFNUM(_x) ((_x) << 6)
125#define GRSTCTL_TXFFLSH (1 << 5)
126#define GRSTCTL_RXFFLSH (1 << 4)
127#define GRSTCTL_IN_TKNQ_FLSH (1 << 3)
128#define GRSTCTL_FRMCNTRRST (1 << 2)
129#define GRSTCTL_HSFTRST (1 << 1)
130#define GRSTCTL_CSFTRST (1 << 0)
131
132#define GINTSTS HSOTG_REG(0x014)
133#define GINTMSK HSOTG_REG(0x018)
134#define GINTSTS_WKUPINT (1 << 31)
135#define GINTSTS_SESSREQINT (1 << 30)
136#define GINTSTS_DISCONNINT (1 << 29)
137#define GINTSTS_CONIDSTSCHNG (1 << 28)
138#define GINTSTS_LPMTRANRCVD (1 << 27)
139#define GINTSTS_PTXFEMP (1 << 26)
140#define GINTSTS_HCHINT (1 << 25)
141#define GINTSTS_PRTINT (1 << 24)
142#define GINTSTS_RESETDET (1 << 23)
143#define GINTSTS_FET_SUSP (1 << 22)
144#define GINTSTS_INCOMPL_IP (1 << 21)
145#define GINTSTS_INCOMPL_SOOUT (1 << 21)
146#define GINTSTS_INCOMPL_SOIN (1 << 20)
147#define GINTSTS_OEPINT (1 << 19)
148#define GINTSTS_IEPINT (1 << 18)
149#define GINTSTS_EPMIS (1 << 17)
150#define GINTSTS_RESTOREDONE (1 << 16)
151#define GINTSTS_EOPF (1 << 15)
152#define GINTSTS_ISOUTDROP (1 << 14)
153#define GINTSTS_ENUMDONE (1 << 13)
154#define GINTSTS_USBRST (1 << 12)
155#define GINTSTS_USBSUSP (1 << 11)
156#define GINTSTS_ERLYSUSP (1 << 10)
157#define GINTSTS_I2CINT (1 << 9)
158#define GINTSTS_ULPI_CK_INT (1 << 8)
159#define GINTSTS_GOUTNAKEFF (1 << 7)
160#define GINTSTS_GINNAKEFF (1 << 6)
161#define GINTSTS_NPTXFEMP (1 << 5)
162#define GINTSTS_RXFLVL (1 << 4)
163#define GINTSTS_SOF (1 << 3)
164#define GINTSTS_OTGINT (1 << 2)
165#define GINTSTS_MODEMIS (1 << 1)
166#define GINTSTS_CURMODE_HOST (1 << 0)
167
168#define GRXSTSR HSOTG_REG(0x01C)
169#define GRXSTSP HSOTG_REG(0x020)
170#define GRXSTS_FN_MASK (0x7f << 25)
171#define GRXSTS_FN_SHIFT 25
172#define GRXSTS_PKTSTS_MASK (0xf << 17)
173#define GRXSTS_PKTSTS_SHIFT 17
174#define GRXSTS_PKTSTS_GLOBALOUTNAK 1
175#define GRXSTS_PKTSTS_OUTRX 2
176#define GRXSTS_PKTSTS_HCHIN 2
177#define GRXSTS_PKTSTS_OUTDONE 3
178#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
179#define GRXSTS_PKTSTS_SETUPDONE 4
180#define GRXSTS_PKTSTS_DATATOGGLEERR 5
181#define GRXSTS_PKTSTS_SETUPRX 6
182#define GRXSTS_PKTSTS_HCHHALTED 7
183#define GRXSTS_HCHNUM_MASK (0xf << 0)
184#define GRXSTS_HCHNUM_SHIFT 0
185#define GRXSTS_DPID_MASK (0x3 << 15)
186#define GRXSTS_DPID_SHIFT 15
187#define GRXSTS_BYTECNT_MASK (0x7ff << 4)
188#define GRXSTS_BYTECNT_SHIFT 4
189#define GRXSTS_EPNUM_MASK (0xf << 0)
190#define GRXSTS_EPNUM_SHIFT 0
191
192#define GRXFSIZ HSOTG_REG(0x024)
193#define GRXFSIZ_DEPTH_MASK (0xffff << 0)
194#define GRXFSIZ_DEPTH_SHIFT 0
195
196#define GNPTXFSIZ HSOTG_REG(0x028)
197/* Use FIFOSIZE_* constants to access this register */
198
199#define GNPTXSTS HSOTG_REG(0x02C)
200#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
201#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
202#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
203#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
204#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
205#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
206#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
207#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
208
209#define GI2CCTL HSOTG_REG(0x0030)
210#define GI2CCTL_BSYDNE (1 << 31)
211#define GI2CCTL_RW (1 << 30)
212#define GI2CCTL_I2CDATSE0 (1 << 28)
213#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
214#define GI2CCTL_I2CDEVADDR_SHIFT 26
215#define GI2CCTL_I2CSUSPCTL (1 << 25)
216#define GI2CCTL_ACK (1 << 24)
217#define GI2CCTL_I2CEN (1 << 23)
218#define GI2CCTL_ADDR_MASK (0x7f << 16)
219#define GI2CCTL_ADDR_SHIFT 16
220#define GI2CCTL_REGADDR_MASK (0xff << 8)
221#define GI2CCTL_REGADDR_SHIFT 8
222#define GI2CCTL_RWDATA_MASK (0xff << 0)
223#define GI2CCTL_RWDATA_SHIFT 0
224
225#define GPVNDCTL HSOTG_REG(0x0034)
226#define GGPIO HSOTG_REG(0x0038)
227#define GUID HSOTG_REG(0x003c)
228#define GSNPSID HSOTG_REG(0x0040)
229#define GHWCFG1 HSOTG_REG(0x0044)
230
231#define GHWCFG2 HSOTG_REG(0x0048)
232#define GHWCFG2_OTG_ENABLE_IC_USB (1 << 31)
233#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
234#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
235#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
236#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
237#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
238#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
239#define GHWCFG2_MULTI_PROC_INT (1 << 20)
240#define GHWCFG2_DYNAMIC_FIFO (1 << 19)
241#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18)
242#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
243#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
244#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
245#define GHWCFG2_NUM_DEV_EP_SHIFT 10
246#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
247#define GHWCFG2_FS_PHY_TYPE_SHIFT 8
248#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
249#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
250#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
251#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
252#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
253#define GHWCFG2_HS_PHY_TYPE_SHIFT 6
254#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
255#define GHWCFG2_HS_PHY_TYPE_UTMI 1
256#define GHWCFG2_HS_PHY_TYPE_ULPI 2
257#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
258#define GHWCFG2_POINT2POINT (1 << 5)
259#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
260#define GHWCFG2_ARCHITECTURE_SHIFT 3
261#define GHWCFG2_SLAVE_ONLY_ARCH 0
262#define GHWCFG2_EXT_DMA_ARCH 1
263#define GHWCFG2_INT_DMA_ARCH 2
264#define GHWCFG2_OP_MODE_MASK (0x7 << 0)
265#define GHWCFG2_OP_MODE_SHIFT 0
266#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
267#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
268#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
269#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
270#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
271#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
272#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
273#define GHWCFG2_OP_MODE_UNDEFINED 7
274
275#define GHWCFG3 HSOTG_REG(0x004c)
276#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
277#define GHWCFG3_DFIFO_DEPTH_SHIFT 16
278#define GHWCFG3_OTG_LPM_EN (1 << 15)
279#define GHWCFG3_BC_SUPPORT (1 << 14)
280#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13)
281#define GHWCFG3_ADP_SUPP (1 << 12)
282#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11)
283#define GHWCFG3_OPTIONAL_FEATURES (1 << 10)
284#define GHWCFG3_VENDOR_CTRL_IF (1 << 9)
285#define GHWCFG3_I2C (1 << 8)
286#define GHWCFG3_OTG_FUNC (1 << 7)
287#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
288#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
289#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
290#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
291
292#define GHWCFG4 HSOTG_REG(0x0050)
293#define GHWCFG4_DESC_DMA_DYN (1 << 31)
294#define GHWCFG4_DESC_DMA (1 << 30)
295#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
296#define GHWCFG4_NUM_IN_EPS_SHIFT 26
297#define GHWCFG4_DED_FIFO_EN (1 << 25)
298#define GHWCFG4_DED_FIFO_SHIFT 25
299#define GHWCFG4_SESSION_END_FILT_EN (1 << 24)
300#define GHWCFG4_B_VALID_FILT_EN (1 << 23)
301#define GHWCFG4_A_VALID_FILT_EN (1 << 22)
302#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21)
303#define GHWCFG4_IDDIG_FILT_EN (1 << 20)
304#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
305#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
306#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
307#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
308#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
309#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
310#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
311#define GHWCFG4_XHIBER (1 << 7)
312#define GHWCFG4_HIBER (1 << 6)
313#define GHWCFG4_MIN_AHB_FREQ (1 << 5)
314#define GHWCFG4_POWER_OPTIMIZ (1 << 4)
315#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
316#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
317
318#define GLPMCFG HSOTG_REG(0x0054)
319#define GLPMCFG_INV_SEL_HSIC (1 << 31)
320#define GLPMCFG_HSIC_CONNECT (1 << 30)
321#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25)
322#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25
323#define GLPMCFG_SEND_LPM (1 << 24)
324#define GLPMCFG_RETRY_COUNT_MASK (0x7 << 21)
325#define GLPMCFG_RETRY_COUNT_SHIFT 21
326#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17)
327#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17
328#define GLPMCFG_SLEEP_STATE_RESUMEOK (1 << 16)
329#define GLPMCFG_PRT_SLEEP_STS (1 << 15)
330#define GLPMCFG_LPM_RESP_MASK (0x3 << 13)
331#define GLPMCFG_LPM_RESP_SHIFT 13
332#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
333#define GLPMCFG_HIRD_THRES_SHIFT 8
334#define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
335#define GLPMCFG_EN_UTMI_SLEEP (1 << 7)
336#define GLPMCFG_REM_WKUP_EN (1 << 6)
337#define GLPMCFG_HIRD_MASK (0xf << 2)
338#define GLPMCFG_HIRD_SHIFT 2
339#define GLPMCFG_APPL_RESP (1 << 1)
340#define GLPMCFG_LPM_CAP_EN (1 << 0)
341
342#define GPWRDN HSOTG_REG(0x0058)
343#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
344#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
345#define GPWRDN_ADP_INT (1 << 23)
346#define GPWRDN_BSESSVLD (1 << 22)
347#define GPWRDN_IDSTS (1 << 21)
348#define GPWRDN_LINESTATE_MASK (0x3 << 19)
349#define GPWRDN_LINESTATE_SHIFT 19
350#define GPWRDN_STS_CHGINT_MSK (1 << 18)
351#define GPWRDN_STS_CHGINT (1 << 17)
352#define GPWRDN_SRP_DET_MSK (1 << 16)
353#define GPWRDN_SRP_DET (1 << 15)
354#define GPWRDN_CONNECT_DET_MSK (1 << 14)
355#define GPWRDN_CONNECT_DET (1 << 13)
356#define GPWRDN_DISCONN_DET_MSK (1 << 12)
357#define GPWRDN_DISCONN_DET (1 << 11)
358#define GPWRDN_RST_DET_MSK (1 << 10)
359#define GPWRDN_RST_DET (1 << 9)
360#define GPWRDN_LNSTSCHG_MSK (1 << 8)
361#define GPWRDN_LNSTSCHG (1 << 7)
362#define GPWRDN_DIS_VBUS (1 << 6)
363#define GPWRDN_PWRDNSWTCH (1 << 5)
364#define GPWRDN_PWRDNRSTN (1 << 4)
365#define GPWRDN_PWRDNCLMP (1 << 3)
366#define GPWRDN_RESTORE (1 << 2)
367#define GPWRDN_PMUACTV (1 << 1)
368#define GPWRDN_PMUINTSEL (1 << 0)
369
370#define GDFIFOCFG HSOTG_REG(0x005c)
371#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
372#define GDFIFOCFG_EPINFOBASE_SHIFT 16
373#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
374#define GDFIFOCFG_GDFIFOCFG_SHIFT 0
375
376#define ADPCTL HSOTG_REG(0x0060)
377#define ADPCTL_AR_MASK (0x3 << 27)
378#define ADPCTL_AR_SHIFT 27
379#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26)
380#define ADPCTL_ADP_SNS_INT_MSK (1 << 25)
381#define ADPCTL_ADP_PRB_INT_MSK (1 << 24)
382#define ADPCTL_ADP_TMOUT_INT (1 << 23)
383#define ADPCTL_ADP_SNS_INT (1 << 22)
384#define ADPCTL_ADP_PRB_INT (1 << 21)
385#define ADPCTL_ADPENA (1 << 20)
386#define ADPCTL_ADPRES (1 << 19)
387#define ADPCTL_ENASNS (1 << 18)
388#define ADPCTL_ENAPRB (1 << 17)
389#define ADPCTL_RTIM_MASK (0x7ff << 6)
390#define ADPCTL_RTIM_SHIFT 6
391#define ADPCTL_PRB_PER_MASK (0x3 << 4)
392#define ADPCTL_PRB_PER_SHIFT 4
393#define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
394#define ADPCTL_PRB_DELTA_SHIFT 2
395#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
396#define ADPCTL_PRB_DSCHRG_SHIFT 0
397
398#define HPTXFSIZ HSOTG_REG(0x100)
399/* Use FIFOSIZE_* constants to access this register */
400
401#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
402/* Use FIFOSIZE_* constants to access this register */
403
404/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
405#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
406#define FIFOSIZE_DEPTH_SHIFT 16
407#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
408#define FIFOSIZE_STARTADDR_SHIFT 0
409#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
410
411/* Device mode registers */
412
413#define DCFG HSOTG_REG(0x800)
414#define DCFG_EPMISCNT_MASK (0x1f << 18)
415#define DCFG_EPMISCNT_SHIFT 18
416#define DCFG_EPMISCNT_LIMIT 0x1f
417#define DCFG_EPMISCNT(_x) ((_x) << 18)
418#define DCFG_PERFRINT_MASK (0x3 << 11)
419#define DCFG_PERFRINT_SHIFT 11
420#define DCFG_PERFRINT_LIMIT 0x3
421#define DCFG_PERFRINT(_x) ((_x) << 11)
422#define DCFG_DEVADDR_MASK (0x7f << 4)
423#define DCFG_DEVADDR_SHIFT 4
424#define DCFG_DEVADDR_LIMIT 0x7f
425#define DCFG_DEVADDR(_x) ((_x) << 4)
426#define DCFG_NZ_STS_OUT_HSHK (1 << 2)
427#define DCFG_DEVSPD_MASK (0x3 << 0)
428#define DCFG_DEVSPD_SHIFT 0
429#define DCFG_DEVSPD_HS 0
430#define DCFG_DEVSPD_FS 1
431#define DCFG_DEVSPD_LS 2
432#define DCFG_DEVSPD_FS48 3
433
434#define DCTL HSOTG_REG(0x804)
435#define DCTL_PWRONPRGDONE (1 << 11)
436#define DCTL_CGOUTNAK (1 << 10)
437#define DCTL_SGOUTNAK (1 << 9)
438#define DCTL_CGNPINNAK (1 << 8)
439#define DCTL_SGNPINNAK (1 << 7)
440#define DCTL_TSTCTL_MASK (0x7 << 4)
441#define DCTL_TSTCTL_SHIFT 4
442#define DCTL_GOUTNAKSTS (1 << 3)
443#define DCTL_GNPINNAKSTS (1 << 2)
444#define DCTL_SFTDISCON (1 << 1)
445#define DCTL_RMTWKUPSIG (1 << 0)
446
447#define DSTS HSOTG_REG(0x808)
448#define DSTS_SOFFN_MASK (0x3fff << 8)
449#define DSTS_SOFFN_SHIFT 8
450#define DSTS_SOFFN_LIMIT 0x3fff
451#define DSTS_SOFFN(_x) ((_x) << 8)
452#define DSTS_ERRATICERR (1 << 3)
453#define DSTS_ENUMSPD_MASK (0x3 << 1)
454#define DSTS_ENUMSPD_SHIFT 1
455#define DSTS_ENUMSPD_HS 0
456#define DSTS_ENUMSPD_FS 1
457#define DSTS_ENUMSPD_LS 2
458#define DSTS_ENUMSPD_FS48 3
459#define DSTS_SUSPSTS (1 << 0)
460
461#define DIEPMSK HSOTG_REG(0x810)
462#define DIEPMSK_TXFIFOEMPTY (1 << 7)
463#define DIEPMSK_INEPNAKEFFMSK (1 << 6)
464#define DIEPMSK_INTKNEPMISMSK (1 << 5)
465#define DIEPMSK_INTKNTXFEMPMSK (1 << 4)
466#define DIEPMSK_TIMEOUTMSK (1 << 3)
467#define DIEPMSK_AHBERRMSK (1 << 2)
468#define DIEPMSK_EPDISBLDMSK (1 << 1)
469#define DIEPMSK_XFERCOMPLMSK (1 << 0)
470
471#define DOEPMSK HSOTG_REG(0x814)
472#define DOEPMSK_BACK2BACKSETUP (1 << 6)
473#define DOEPMSK_OUTTKNEPDISMSK (1 << 4)
474#define DOEPMSK_SETUPMSK (1 << 3)
475#define DOEPMSK_AHBERRMSK (1 << 2)
476#define DOEPMSK_EPDISBLDMSK (1 << 1)
477#define DOEPMSK_XFERCOMPLMSK (1 << 0)
478
479#define DAINT HSOTG_REG(0x818)
480#define DAINTMSK HSOTG_REG(0x81C)
481#define DAINT_OUTEP_SHIFT 16
482#define DAINT_OUTEP(_x) (1 << ((_x) + 16))
483#define DAINT_INEP(_x) (1 << (_x))
484
485#define DTKNQR1 HSOTG_REG(0x820)
486#define DTKNQR2 HSOTG_REG(0x824)
487#define DTKNQR3 HSOTG_REG(0x830)
488#define DTKNQR4 HSOTG_REG(0x834)
489
490#define DVBUSDIS HSOTG_REG(0x828)
491#define DVBUSPULSE HSOTG_REG(0x82C)
492
493#define DIEPCTL0 HSOTG_REG(0x900)
494#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
495
496#define DOEPCTL0 HSOTG_REG(0xB00)
497#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
498
499/* EP0 specialness:
500 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
501 * bits[25..22] - should always be zero, this isn't a periodic endpoint
502 * bits[10..0] - MPS setting different for EP0
503 */
504#define D0EPCTL_MPS_MASK (0x3 << 0)
505#define D0EPCTL_MPS_SHIFT 0
506#define D0EPCTL_MPS_64 0
507#define D0EPCTL_MPS_32 1
508#define D0EPCTL_MPS_16 2
509#define D0EPCTL_MPS_8 3
510
511#define DXEPCTL_EPENA (1 << 31)
512#define DXEPCTL_EPDIS (1 << 30)
513#define DXEPCTL_SETD1PID (1 << 29)
514#define DXEPCTL_SETODDFR (1 << 29)
515#define DXEPCTL_SETD0PID (1 << 28)
516#define DXEPCTL_SETEVENFR (1 << 28)
517#define DXEPCTL_SNAK (1 << 27)
518#define DXEPCTL_CNAK (1 << 26)
519#define DXEPCTL_TXFNUM_MASK (0xf << 22)
520#define DXEPCTL_TXFNUM_SHIFT 22
521#define DXEPCTL_TXFNUM_LIMIT 0xf
522#define DXEPCTL_TXFNUM(_x) ((_x) << 22)
523#define DXEPCTL_STALL (1 << 21)
524#define DXEPCTL_SNP (1 << 20)
525#define DXEPCTL_EPTYPE_MASK (0x3 << 18)
526#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
527#define DXEPCTL_EPTYPE_ISO (0x1 << 18)
528#define DXEPCTL_EPTYPE_BULK (0x2 << 18)
529#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
530
531#define DXEPCTL_NAKSTS (1 << 17)
532#define DXEPCTL_DPID (1 << 16)
533#define DXEPCTL_EOFRNUM (1 << 16)
534#define DXEPCTL_USBACTEP (1 << 15)
535#define DXEPCTL_NEXTEP_MASK (0xf << 11)
536#define DXEPCTL_NEXTEP_SHIFT 11
537#define DXEPCTL_NEXTEP_LIMIT 0xf
538#define DXEPCTL_NEXTEP(_x) ((_x) << 11)
539#define DXEPCTL_MPS_MASK (0x7ff << 0)
540#define DXEPCTL_MPS_SHIFT 0
541#define DXEPCTL_MPS_LIMIT 0x7ff
542#define DXEPCTL_MPS(_x) ((_x) << 0)
543
544#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
545#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
546#define DXEPINT_SETUP_RCVD (1 << 15)
547#define DXEPINT_INEPNAKEFF (1 << 6)
548#define DXEPINT_BACK2BACKSETUP (1 << 6)
549#define DXEPINT_INTKNEPMIS (1 << 5)
550#define DXEPINT_INTKNTXFEMP (1 << 4)
551#define DXEPINT_OUTTKNEPDIS (1 << 4)
552#define DXEPINT_TIMEOUT (1 << 3)
553#define DXEPINT_SETUP (1 << 3)
554#define DXEPINT_AHBERR (1 << 2)
555#define DXEPINT_EPDISBLD (1 << 1)
556#define DXEPINT_XFERCOMPL (1 << 0)
557
558#define DIEPTSIZ0 HSOTG_REG(0x910)
559#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
560#define DIEPTSIZ0_PKTCNT_SHIFT 19
561#define DIEPTSIZ0_PKTCNT_LIMIT 0x3
562#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
563#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
564#define DIEPTSIZ0_XFERSIZE_SHIFT 0
565#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
566#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
567
568#define DOEPTSIZ0 HSOTG_REG(0xB10)
569#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
570#define DOEPTSIZ0_SUPCNT_SHIFT 29
571#define DOEPTSIZ0_SUPCNT_LIMIT 0x3
572#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
573#define DOEPTSIZ0_PKTCNT (1 << 19)
574#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
575#define DOEPTSIZ0_XFERSIZE_SHIFT 0
576
577#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
578#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
579#define DXEPTSIZ_MC_MASK (0x3 << 29)
580#define DXEPTSIZ_MC_SHIFT 29
581#define DXEPTSIZ_MC_LIMIT 0x3
582#define DXEPTSIZ_MC(_x) ((_x) << 29)
583#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
584#define DXEPTSIZ_PKTCNT_SHIFT 19
585#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
586#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
587#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
588#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
589#define DXEPTSIZ_XFERSIZE_SHIFT 0
590#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
591#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
592#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
593
594#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
595#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
596
597#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
598
599#define PCGCTL HSOTG_REG(0x0e00)
600#define PCGCTL_IF_DEV_MODE (1 << 31)
601#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
602#define PCGCTL_P2HD_PRT_SPD_SHIFT 29
603#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
604#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
605#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
606#define PCGCTL_MAC_DEV_ADDR_SHIFT 20
607#define PCGCTL_MAX_TERMSEL (1 << 19)
608#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
609#define PCGCTL_MAX_XCVRSELECT_SHIFT 17
610#define PCGCTL_PORT_POWER (1 << 16)
611#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
612#define PCGCTL_PRT_CLK_SEL_SHIFT 14
613#define PCGCTL_ESS_REG_RESTORED (1 << 13)
614#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12)
615#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11)
616#define PCGCTL_ENBL_EXTND_HIBER (1 << 10)
617#define PCGCTL_RESTOREMODE (1 << 9)
618#define PCGCTL_RESETAFTSUSP (1 << 8)
619#define PCGCTL_DEEP_SLEEP (1 << 7)
620#define PCGCTL_PHY_IN_SLEEP (1 << 6)
621#define PCGCTL_ENBL_SLEEP_GATING (1 << 5)
622#define PCGCTL_RSTPDWNMODULE (1 << 3)
623#define PCGCTL_PWRCLMP (1 << 2)
624#define PCGCTL_GATEHCLK (1 << 1)
625#define PCGCTL_STOPPCLK (1 << 0)
626
627#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
628
629/* Host Mode Registers */
630
631#define HCFG HSOTG_REG(0x0400)
632#define HCFG_MODECHTIMEN (1 << 31)
633#define HCFG_PERSCHEDENA (1 << 26)
634#define HCFG_FRLISTEN_MASK (0x3 << 24)
635#define HCFG_FRLISTEN_SHIFT 24
636#define HCFG_FRLISTEN_8 (0 << 24)
637#define FRLISTEN_8_SIZE 8
638#define HCFG_FRLISTEN_16 (1 << 24)
639#define FRLISTEN_16_SIZE 16
640#define HCFG_FRLISTEN_32 (2 << 24)
641#define FRLISTEN_32_SIZE 32
642#define HCFG_FRLISTEN_64 (3 << 24)
643#define FRLISTEN_64_SIZE 64
644#define HCFG_DESCDMA (1 << 23)
645#define HCFG_RESVALID_MASK (0xff << 8)
646#define HCFG_RESVALID_SHIFT 8
647#define HCFG_ENA32KHZ (1 << 7)
648#define HCFG_FSLSSUPP (1 << 2)
649#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
650#define HCFG_FSLSPCLKSEL_SHIFT 0
651#define HCFG_FSLSPCLKSEL_30_60_MHZ 0
652#define HCFG_FSLSPCLKSEL_48_MHZ 1
653#define HCFG_FSLSPCLKSEL_6_MHZ 2
654
655#define HFIR HSOTG_REG(0x0404)
656#define HFIR_FRINT_MASK (0xffff << 0)
657#define HFIR_FRINT_SHIFT 0
658#define HFIR_RLDCTRL (1 << 16)
659
660#define HFNUM HSOTG_REG(0x0408)
661#define HFNUM_FRREM_MASK (0xffff << 16)
662#define HFNUM_FRREM_SHIFT 16
663#define HFNUM_FRNUM_MASK (0xffff << 0)
664#define HFNUM_FRNUM_SHIFT 0
665#define HFNUM_MAX_FRNUM 0x3fff
666
667#define HPTXSTS HSOTG_REG(0x0410)
668#define TXSTS_QTOP_ODD (1 << 31)
669#define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
670#define TXSTS_QTOP_CHNEP_SHIFT 27
671#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
672#define TXSTS_QTOP_TOKEN_SHIFT 25
673#define TXSTS_QTOP_TERMINATE (1 << 24)
674#define TXSTS_QSPCAVAIL_MASK (0xff << 16)
675#define TXSTS_QSPCAVAIL_SHIFT 16
676#define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
677#define TXSTS_FSPCAVAIL_SHIFT 0
678
679#define HAINT HSOTG_REG(0x0414)
680#define HAINTMSK HSOTG_REG(0x0418)
681#define HFLBADDR HSOTG_REG(0x041c)
682
683#define HPRT0 HSOTG_REG(0x0440)
684#define HPRT0_SPD_MASK (0x3 << 17)
685#define HPRT0_SPD_SHIFT 17
686#define HPRT0_SPD_HIGH_SPEED 0
687#define HPRT0_SPD_FULL_SPEED 1
688#define HPRT0_SPD_LOW_SPEED 2
689#define HPRT0_TSTCTL_MASK (0xf << 13)
690#define HPRT0_TSTCTL_SHIFT 13
691#define HPRT0_PWR (1 << 12)
692#define HPRT0_LNSTS_MASK (0x3 << 10)
693#define HPRT0_LNSTS_SHIFT 10
694#define HPRT0_RST (1 << 8)
695#define HPRT0_SUSP (1 << 7)
696#define HPRT0_RES (1 << 6)
697#define HPRT0_OVRCURRCHG (1 << 5)
698#define HPRT0_OVRCURRACT (1 << 4)
699#define HPRT0_ENACHG (1 << 3)
700#define HPRT0_ENA (1 << 2)
701#define HPRT0_CONNDET (1 << 1)
702#define HPRT0_CONNSTS (1 << 0)
703
704#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
705#define HCCHAR_CHENA (1 << 31)
706#define HCCHAR_CHDIS (1 << 30)
707#define HCCHAR_ODDFRM (1 << 29)
708#define HCCHAR_DEVADDR_MASK (0x7f << 22)
709#define HCCHAR_DEVADDR_SHIFT 22
710#define HCCHAR_MULTICNT_MASK (0x3 << 20)
711#define HCCHAR_MULTICNT_SHIFT 20
712#define HCCHAR_EPTYPE_MASK (0x3 << 18)
713#define HCCHAR_EPTYPE_SHIFT 18
714#define HCCHAR_LSPDDEV (1 << 17)
715#define HCCHAR_EPDIR (1 << 15)
716#define HCCHAR_EPNUM_MASK (0xf << 11)
717#define HCCHAR_EPNUM_SHIFT 11
718#define HCCHAR_MPS_MASK (0x7ff << 0)
719#define HCCHAR_MPS_SHIFT 0
720
721#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
722#define HCSPLT_SPLTENA (1 << 31)
723#define HCSPLT_COMPSPLT (1 << 16)
724#define HCSPLT_XACTPOS_MASK (0x3 << 14)
725#define HCSPLT_XACTPOS_SHIFT 14
726#define HCSPLT_XACTPOS_MID 0
727#define HCSPLT_XACTPOS_END 1
728#define HCSPLT_XACTPOS_BEGIN 2
729#define HCSPLT_XACTPOS_ALL 3
730#define HCSPLT_HUBADDR_MASK (0x7f << 7)
731#define HCSPLT_HUBADDR_SHIFT 7
732#define HCSPLT_PRTADDR_MASK (0x7f << 0)
733#define HCSPLT_PRTADDR_SHIFT 0
734
735#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
736#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
737#define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
738#define HCINTMSK_FRM_LIST_ROLL (1 << 13)
739#define HCINTMSK_XCS_XACT (1 << 12)
740#define HCINTMSK_BNA (1 << 11)
741#define HCINTMSK_DATATGLERR (1 << 10)
742#define HCINTMSK_FRMOVRUN (1 << 9)
743#define HCINTMSK_BBLERR (1 << 8)
744#define HCINTMSK_XACTERR (1 << 7)
745#define HCINTMSK_NYET (1 << 6)
746#define HCINTMSK_ACK (1 << 5)
747#define HCINTMSK_NAK (1 << 4)
748#define HCINTMSK_STALL (1 << 3)
749#define HCINTMSK_AHBERR (1 << 2)
750#define HCINTMSK_CHHLTD (1 << 1)
751#define HCINTMSK_XFERCOMPL (1 << 0)
752
753#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
754#define TSIZ_DOPNG (1 << 31)
755#define TSIZ_SC_MC_PID_MASK (0x3 << 29)
756#define TSIZ_SC_MC_PID_SHIFT 29
757#define TSIZ_SC_MC_PID_DATA0 0
758#define TSIZ_SC_MC_PID_DATA2 1
759#define TSIZ_SC_MC_PID_DATA1 2
760#define TSIZ_SC_MC_PID_MDATA 3
761#define TSIZ_SC_MC_PID_SETUP 3
762#define TSIZ_PKTCNT_MASK (0x3ff << 19)
763#define TSIZ_PKTCNT_SHIFT 19
764#define TSIZ_NTD_MASK (0xff << 8)
765#define TSIZ_NTD_SHIFT 8
766#define TSIZ_SCHINFO_MASK (0xff << 0)
767#define TSIZ_SCHINFO_SHIFT 0
768#define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
769#define TSIZ_XFERSIZE_SHIFT 0
770
771#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
772
773#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
774
775#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
776
777/**
778 * struct dwc2_hcd_dma_desc - Host-mode DMA descriptor structure
779 *
780 * @status: DMA descriptor status quadlet
781 * @buf: DMA descriptor data buffer pointer
782 *
783 * DMA Descriptor structure contains two quadlets:
784 * Status quadlet and Data buffer pointer.
785 */
786struct dwc2_hcd_dma_desc {
787 u32 status;
788 u32 buf;
789};
790
791#define HOST_DMA_A (1 << 31)
792#define HOST_DMA_STS_MASK (0x3 << 28)
793#define HOST_DMA_STS_SHIFT 28
794#define HOST_DMA_STS_PKTERR (1 << 28)
795#define HOST_DMA_EOL (1 << 26)
796#define HOST_DMA_IOC (1 << 25)
797#define HOST_DMA_SUP (1 << 24)
798#define HOST_DMA_ALT_QTD (1 << 23)
799#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
800#define HOST_DMA_QTD_OFFSET_SHIFT 17
801#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
802#define HOST_DMA_ISOC_NBYTES_SHIFT 0
803#define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
804#define HOST_DMA_NBYTES_SHIFT 0
805
806#define MAX_DMA_DESC_SIZE 131071
807#define MAX_DMA_DESC_NUM_GENERIC 64
808#define MAX_DMA_DESC_NUM_HS_ISOC 256
809
810#endif /* __DWC2_HW_H__ */