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1/*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
61#include <asm/system.h>
62#include <asm/io.h>
63#include <asm/irq.h>
64#include <asm/dma.h>
65#include <linux/bitops.h>
66#include <asm/types.h>
67#include <linux/termios.h>
68#include <linux/workqueue.h>
69#include <linux/hdlc.h>
70#include <linux/synclink.h>
71
72#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
73#define SYNCLINK_GENERIC_HDLC 1
74#else
75#define SYNCLINK_GENERIC_HDLC 0
76#endif
77
78#define GET_USER(error,value,addr) error = get_user(value,addr)
79#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
80#define PUT_USER(error,value,addr) error = put_user(value,addr)
81#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
82
83#include <asm/uaccess.h>
84
85static MGSL_PARAMS default_params = {
86 MGSL_MODE_HDLC, /* unsigned long mode */
87 0, /* unsigned char loopback; */
88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
90 0, /* unsigned long clock_speed; */
91 0xff, /* unsigned char addr_filter; */
92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
95 9600, /* unsigned long data_rate; */
96 8, /* unsigned char data_bits; */
97 1, /* unsigned char stop_bits; */
98 ASYNC_PARITY_NONE /* unsigned char parity; */
99};
100
101/* size in bytes of DMA data buffers */
102#define SCABUFSIZE 1024
103#define SCA_MEM_SIZE 0x40000
104#define SCA_BASE_SIZE 512
105#define SCA_REG_SIZE 16
106#define SCA_MAX_PORTS 4
107#define SCAMAXDESC 128
108
109#define BUFFERLISTSIZE 4096
110
111/* SCA-I style DMA buffer descriptor */
112typedef struct _SCADESC
113{
114 u16 next; /* lower l6 bits of next descriptor addr */
115 u16 buf_ptr; /* lower 16 bits of buffer addr */
116 u8 buf_base; /* upper 8 bits of buffer addr */
117 u8 pad1;
118 u16 length; /* length of buffer */
119 u8 status; /* status of buffer */
120 u8 pad2;
121} SCADESC, *PSCADESC;
122
123typedef struct _SCADESC_EX
124{
125 /* device driver bookkeeping section */
126 char *virt_addr; /* virtual address of data buffer */
127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
128} SCADESC_EX, *PSCADESC_EX;
129
130/* The queue of BH actions to be performed */
131
132#define BH_RECEIVE 1
133#define BH_TRANSMIT 2
134#define BH_STATUS 4
135
136#define IO_PIN_SHUTDOWN_LIMIT 100
137
138struct _input_signal_events {
139 int ri_up;
140 int ri_down;
141 int dsr_up;
142 int dsr_down;
143 int dcd_up;
144 int dcd_down;
145 int cts_up;
146 int cts_down;
147};
148
149/*
150 * Device instance data structure
151 */
152typedef struct _synclinkmp_info {
153 void *if_ptr; /* General purpose pointer (used by SPPP) */
154 int magic;
155 struct tty_port port;
156 int line;
157 unsigned short close_delay;
158 unsigned short closing_wait; /* time to wait before closing */
159
160 struct mgsl_icount icount;
161
162 int timeout;
163 int x_char; /* xon/xoff character */
164 u16 read_status_mask1; /* break detection (SR1 indications) */
165 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
166 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
167 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
168 unsigned char *tx_buf;
169 int tx_put;
170 int tx_get;
171 int tx_count;
172
173 wait_queue_head_t status_event_wait_q;
174 wait_queue_head_t event_wait_q;
175 struct timer_list tx_timer; /* HDLC transmit timeout timer */
176 struct _synclinkmp_info *next_device; /* device list link */
177 struct timer_list status_timer; /* input signal status check timer */
178
179 spinlock_t lock; /* spinlock for synchronizing with ISR */
180 struct work_struct task; /* task structure for scheduling bh */
181
182 u32 max_frame_size; /* as set by device config */
183
184 u32 pending_bh;
185
186 bool bh_running; /* Protection from multiple */
187 int isr_overflow;
188 bool bh_requested;
189
190 int dcd_chkcount; /* check counts to prevent */
191 int cts_chkcount; /* too many IRQs if a signal */
192 int dsr_chkcount; /* is floating */
193 int ri_chkcount;
194
195 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
196 unsigned long buffer_list_phys;
197
198 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
199 SCADESC *rx_buf_list; /* list of receive buffer entries */
200 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
201 unsigned int current_rx_buf;
202
203 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
204 SCADESC *tx_buf_list; /* list of transmit buffer entries */
205 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
206 unsigned int last_tx_buf;
207
208 unsigned char *tmp_rx_buf;
209 unsigned int tmp_rx_buf_count;
210
211 bool rx_enabled;
212 bool rx_overflow;
213
214 bool tx_enabled;
215 bool tx_active;
216 u32 idle_mode;
217
218 unsigned char ie0_value;
219 unsigned char ie1_value;
220 unsigned char ie2_value;
221 unsigned char ctrlreg_value;
222 unsigned char old_signals;
223
224 char device_name[25]; /* device instance name */
225
226 int port_count;
227 int adapter_num;
228 int port_num;
229
230 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
231
232 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
233
234 unsigned int irq_level; /* interrupt level */
235 unsigned long irq_flags;
236 bool irq_requested; /* true if IRQ requested */
237
238 MGSL_PARAMS params; /* communications parameters */
239
240 unsigned char serial_signals; /* current serial signal states */
241
242 bool irq_occurred; /* for diagnostics use */
243 unsigned int init_error; /* Initialization startup error */
244
245 u32 last_mem_alloc;
246 unsigned char* memory_base; /* shared memory address (PCI only) */
247 u32 phys_memory_base;
248 int shared_mem_requested;
249
250 unsigned char* sca_base; /* HD64570 SCA Memory address */
251 u32 phys_sca_base;
252 u32 sca_offset;
253 bool sca_base_requested;
254
255 unsigned char* lcr_base; /* local config registers (PCI only) */
256 u32 phys_lcr_base;
257 u32 lcr_offset;
258 int lcr_mem_requested;
259
260 unsigned char* statctrl_base; /* status/control register memory */
261 u32 phys_statctrl_base;
262 u32 statctrl_offset;
263 bool sca_statctrl_requested;
264
265 u32 misc_ctrl_value;
266 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
267 char char_buf[MAX_ASYNC_BUFFER_SIZE];
268 bool drop_rts_on_tx_done;
269
270 struct _input_signal_events input_signal_events;
271
272 /* SPPP/Cisco HDLC device parts */
273 int netcount;
274 spinlock_t netlock;
275
276#if SYNCLINK_GENERIC_HDLC
277 struct net_device *netdev;
278#endif
279
280} SLMP_INFO;
281
282#define MGSL_MAGIC 0x5401
283
284/*
285 * define serial signal status change macros
286 */
287#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
288#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
289#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
290#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
291
292/* Common Register macros */
293#define LPR 0x00
294#define PABR0 0x02
295#define PABR1 0x03
296#define WCRL 0x04
297#define WCRM 0x05
298#define WCRH 0x06
299#define DPCR 0x08
300#define DMER 0x09
301#define ISR0 0x10
302#define ISR1 0x11
303#define ISR2 0x12
304#define IER0 0x14
305#define IER1 0x15
306#define IER2 0x16
307#define ITCR 0x18
308#define INTVR 0x1a
309#define IMVR 0x1c
310
311/* MSCI Register macros */
312#define TRB 0x20
313#define TRBL 0x20
314#define TRBH 0x21
315#define SR0 0x22
316#define SR1 0x23
317#define SR2 0x24
318#define SR3 0x25
319#define FST 0x26
320#define IE0 0x28
321#define IE1 0x29
322#define IE2 0x2a
323#define FIE 0x2b
324#define CMD 0x2c
325#define MD0 0x2e
326#define MD1 0x2f
327#define MD2 0x30
328#define CTL 0x31
329#define SA0 0x32
330#define SA1 0x33
331#define IDL 0x34
332#define TMC 0x35
333#define RXS 0x36
334#define TXS 0x37
335#define TRC0 0x38
336#define TRC1 0x39
337#define RRC 0x3a
338#define CST0 0x3c
339#define CST1 0x3d
340
341/* Timer Register Macros */
342#define TCNT 0x60
343#define TCNTL 0x60
344#define TCNTH 0x61
345#define TCONR 0x62
346#define TCONRL 0x62
347#define TCONRH 0x63
348#define TMCS 0x64
349#define TEPR 0x65
350
351/* DMA Controller Register macros */
352#define DARL 0x80
353#define DARH 0x81
354#define DARB 0x82
355#define BAR 0x80
356#define BARL 0x80
357#define BARH 0x81
358#define BARB 0x82
359#define SAR 0x84
360#define SARL 0x84
361#define SARH 0x85
362#define SARB 0x86
363#define CPB 0x86
364#define CDA 0x88
365#define CDAL 0x88
366#define CDAH 0x89
367#define EDA 0x8a
368#define EDAL 0x8a
369#define EDAH 0x8b
370#define BFL 0x8c
371#define BFLL 0x8c
372#define BFLH 0x8d
373#define BCR 0x8e
374#define BCRL 0x8e
375#define BCRH 0x8f
376#define DSR 0x90
377#define DMR 0x91
378#define FCT 0x93
379#define DIR 0x94
380#define DCMD 0x95
381
382/* combine with timer or DMA register address */
383#define TIMER0 0x00
384#define TIMER1 0x08
385#define TIMER2 0x10
386#define TIMER3 0x18
387#define RXDMA 0x00
388#define TXDMA 0x20
389
390/* SCA Command Codes */
391#define NOOP 0x00
392#define TXRESET 0x01
393#define TXENABLE 0x02
394#define TXDISABLE 0x03
395#define TXCRCINIT 0x04
396#define TXCRCEXCL 0x05
397#define TXEOM 0x06
398#define TXABORT 0x07
399#define MPON 0x08
400#define TXBUFCLR 0x09
401#define RXRESET 0x11
402#define RXENABLE 0x12
403#define RXDISABLE 0x13
404#define RXCRCINIT 0x14
405#define RXREJECT 0x15
406#define SEARCHMP 0x16
407#define RXCRCEXCL 0x17
408#define RXCRCCALC 0x18
409#define CHRESET 0x21
410#define HUNT 0x31
411
412/* DMA command codes */
413#define SWABORT 0x01
414#define FEICLEAR 0x02
415
416/* IE0 */
417#define TXINTE BIT7
418#define RXINTE BIT6
419#define TXRDYE BIT1
420#define RXRDYE BIT0
421
422/* IE1 & SR1 */
423#define UDRN BIT7
424#define IDLE BIT6
425#define SYNCD BIT4
426#define FLGD BIT4
427#define CCTS BIT3
428#define CDCD BIT2
429#define BRKD BIT1
430#define ABTD BIT1
431#define GAPD BIT1
432#define BRKE BIT0
433#define IDLD BIT0
434
435/* IE2 & SR2 */
436#define EOM BIT7
437#define PMP BIT6
438#define SHRT BIT6
439#define PE BIT5
440#define ABT BIT5
441#define FRME BIT4
442#define RBIT BIT4
443#define OVRN BIT3
444#define CRCE BIT2
445
446
447/*
448 * Global linked list of SyncLink devices
449 */
450static SLMP_INFO *synclinkmp_device_list = NULL;
451static int synclinkmp_adapter_count = -1;
452static int synclinkmp_device_count = 0;
453
454/*
455 * Set this param to non-zero to load eax with the
456 * .text section address and breakpoint on module load.
457 * This is useful for use with gdb and add-symbol-file command.
458 */
459static int break_on_load = 0;
460
461/*
462 * Driver major number, defaults to zero to get auto
463 * assigned major number. May be forced as module parameter.
464 */
465static int ttymajor = 0;
466
467/*
468 * Array of user specified options for ISA adapters.
469 */
470static int debug_level = 0;
471static int maxframe[MAX_DEVICES] = {0,};
472
473module_param(break_on_load, bool, 0);
474module_param(ttymajor, int, 0);
475module_param(debug_level, int, 0);
476module_param_array(maxframe, int, NULL, 0);
477
478static char *driver_name = "SyncLink MultiPort driver";
479static char *driver_version = "$Revision: 4.38 $";
480
481static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
482static void synclinkmp_remove_one(struct pci_dev *dev);
483
484static struct pci_device_id synclinkmp_pci_tbl[] = {
485 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
486 { 0, }, /* terminate list */
487};
488MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
489
490MODULE_LICENSE("GPL");
491
492static struct pci_driver synclinkmp_pci_driver = {
493 .name = "synclinkmp",
494 .id_table = synclinkmp_pci_tbl,
495 .probe = synclinkmp_init_one,
496 .remove = __devexit_p(synclinkmp_remove_one),
497};
498
499
500static struct tty_driver *serial_driver;
501
502/* number of characters left in xmit buffer before we ask for more */
503#define WAKEUP_CHARS 256
504
505
506/* tty callbacks */
507
508static int open(struct tty_struct *tty, struct file * filp);
509static void close(struct tty_struct *tty, struct file * filp);
510static void hangup(struct tty_struct *tty);
511static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
512
513static int write(struct tty_struct *tty, const unsigned char *buf, int count);
514static int put_char(struct tty_struct *tty, unsigned char ch);
515static void send_xchar(struct tty_struct *tty, char ch);
516static void wait_until_sent(struct tty_struct *tty, int timeout);
517static int write_room(struct tty_struct *tty);
518static void flush_chars(struct tty_struct *tty);
519static void flush_buffer(struct tty_struct *tty);
520static void tx_hold(struct tty_struct *tty);
521static void tx_release(struct tty_struct *tty);
522
523static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
524static int chars_in_buffer(struct tty_struct *tty);
525static void throttle(struct tty_struct * tty);
526static void unthrottle(struct tty_struct * tty);
527static int set_break(struct tty_struct *tty, int break_state);
528
529#if SYNCLINK_GENERIC_HDLC
530#define dev_to_port(D) (dev_to_hdlc(D)->priv)
531static void hdlcdev_tx_done(SLMP_INFO *info);
532static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
533static int hdlcdev_init(SLMP_INFO *info);
534static void hdlcdev_exit(SLMP_INFO *info);
535#endif
536
537/* ioctl handlers */
538
539static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
540static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
541static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
542static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
543static int set_txidle(SLMP_INFO *info, int idle_mode);
544static int tx_enable(SLMP_INFO *info, int enable);
545static int tx_abort(SLMP_INFO *info);
546static int rx_enable(SLMP_INFO *info, int enable);
547static int modem_input_wait(SLMP_INFO *info,int arg);
548static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
549static int tiocmget(struct tty_struct *tty);
550static int tiocmset(struct tty_struct *tty,
551 unsigned int set, unsigned int clear);
552static int set_break(struct tty_struct *tty, int break_state);
553
554static void add_device(SLMP_INFO *info);
555static void device_init(int adapter_num, struct pci_dev *pdev);
556static int claim_resources(SLMP_INFO *info);
557static void release_resources(SLMP_INFO *info);
558
559static int startup(SLMP_INFO *info);
560static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
561static int carrier_raised(struct tty_port *port);
562static void shutdown(SLMP_INFO *info);
563static void program_hw(SLMP_INFO *info);
564static void change_params(SLMP_INFO *info);
565
566static bool init_adapter(SLMP_INFO *info);
567static bool register_test(SLMP_INFO *info);
568static bool irq_test(SLMP_INFO *info);
569static bool loopback_test(SLMP_INFO *info);
570static int adapter_test(SLMP_INFO *info);
571static bool memory_test(SLMP_INFO *info);
572
573static void reset_adapter(SLMP_INFO *info);
574static void reset_port(SLMP_INFO *info);
575static void async_mode(SLMP_INFO *info);
576static void hdlc_mode(SLMP_INFO *info);
577
578static void rx_stop(SLMP_INFO *info);
579static void rx_start(SLMP_INFO *info);
580static void rx_reset_buffers(SLMP_INFO *info);
581static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
582static bool rx_get_frame(SLMP_INFO *info);
583
584static void tx_start(SLMP_INFO *info);
585static void tx_stop(SLMP_INFO *info);
586static void tx_load_fifo(SLMP_INFO *info);
587static void tx_set_idle(SLMP_INFO *info);
588static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
589
590static void get_signals(SLMP_INFO *info);
591static void set_signals(SLMP_INFO *info);
592static void enable_loopback(SLMP_INFO *info, int enable);
593static void set_rate(SLMP_INFO *info, u32 data_rate);
594
595static int bh_action(SLMP_INFO *info);
596static void bh_handler(struct work_struct *work);
597static void bh_receive(SLMP_INFO *info);
598static void bh_transmit(SLMP_INFO *info);
599static void bh_status(SLMP_INFO *info);
600static void isr_timer(SLMP_INFO *info);
601static void isr_rxint(SLMP_INFO *info);
602static void isr_rxrdy(SLMP_INFO *info);
603static void isr_txint(SLMP_INFO *info);
604static void isr_txrdy(SLMP_INFO *info);
605static void isr_rxdmaok(SLMP_INFO *info);
606static void isr_rxdmaerror(SLMP_INFO *info);
607static void isr_txdmaok(SLMP_INFO *info);
608static void isr_txdmaerror(SLMP_INFO *info);
609static void isr_io_pin(SLMP_INFO *info, u16 status);
610
611static int alloc_dma_bufs(SLMP_INFO *info);
612static void free_dma_bufs(SLMP_INFO *info);
613static int alloc_buf_list(SLMP_INFO *info);
614static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
615static int alloc_tmp_rx_buf(SLMP_INFO *info);
616static void free_tmp_rx_buf(SLMP_INFO *info);
617
618static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
619static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
620static void tx_timeout(unsigned long context);
621static void status_timeout(unsigned long context);
622
623static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
624static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
625static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
626static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
627static unsigned char read_status_reg(SLMP_INFO * info);
628static void write_control_reg(SLMP_INFO * info);
629
630
631static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
632static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
633static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
634
635static u32 misc_ctrl_value = 0x007e4040;
636static u32 lcr1_brdr_value = 0x00800028;
637
638static u32 read_ahead_count = 8;
639
640/* DPCR, DMA Priority Control
641 *
642 * 07..05 Not used, must be 0
643 * 04 BRC, bus release condition: 0=all transfers complete
644 * 1=release after 1 xfer on all channels
645 * 03 CCC, channel change condition: 0=every cycle
646 * 1=after each channel completes all xfers
647 * 02..00 PR<2..0>, priority 100=round robin
648 *
649 * 00000100 = 0x00
650 */
651static unsigned char dma_priority = 0x04;
652
653// Number of bytes that can be written to shared RAM
654// in a single write operation
655static u32 sca_pci_load_interval = 64;
656
657/*
658 * 1st function defined in .text section. Calling this function in
659 * init_module() followed by a breakpoint allows a remote debugger
660 * (gdb) to get the .text address for the add-symbol-file command.
661 * This allows remote debugging of dynamically loadable modules.
662 */
663static void* synclinkmp_get_text_ptr(void);
664static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
665
666static inline int sanity_check(SLMP_INFO *info,
667 char *name, const char *routine)
668{
669#ifdef SANITY_CHECK
670 static const char *badmagic =
671 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
672 static const char *badinfo =
673 "Warning: null synclinkmp_struct for (%s) in %s\n";
674
675 if (!info) {
676 printk(badinfo, name, routine);
677 return 1;
678 }
679 if (info->magic != MGSL_MAGIC) {
680 printk(badmagic, name, routine);
681 return 1;
682 }
683#else
684 if (!info)
685 return 1;
686#endif
687 return 0;
688}
689
690/**
691 * line discipline callback wrappers
692 *
693 * The wrappers maintain line discipline references
694 * while calling into the line discipline.
695 *
696 * ldisc_receive_buf - pass receive data to line discipline
697 */
698
699static void ldisc_receive_buf(struct tty_struct *tty,
700 const __u8 *data, char *flags, int count)
701{
702 struct tty_ldisc *ld;
703 if (!tty)
704 return;
705 ld = tty_ldisc_ref(tty);
706 if (ld) {
707 if (ld->ops->receive_buf)
708 ld->ops->receive_buf(tty, data, flags, count);
709 tty_ldisc_deref(ld);
710 }
711}
712
713/* tty callbacks */
714
715/* Called when a port is opened. Init and enable port.
716 */
717static int open(struct tty_struct *tty, struct file *filp)
718{
719 SLMP_INFO *info;
720 int retval, line;
721 unsigned long flags;
722
723 line = tty->index;
724 if ((line < 0) || (line >= synclinkmp_device_count)) {
725 printk("%s(%d): open with invalid line #%d.\n",
726 __FILE__,__LINE__,line);
727 return -ENODEV;
728 }
729
730 info = synclinkmp_device_list;
731 while(info && info->line != line)
732 info = info->next_device;
733 if (sanity_check(info, tty->name, "open"))
734 return -ENODEV;
735 if ( info->init_error ) {
736 printk("%s(%d):%s device is not allocated, init error=%d\n",
737 __FILE__,__LINE__,info->device_name,info->init_error);
738 return -ENODEV;
739 }
740
741 tty->driver_data = info;
742 info->port.tty = tty;
743
744 if (debug_level >= DEBUG_LEVEL_INFO)
745 printk("%s(%d):%s open(), old ref count = %d\n",
746 __FILE__,__LINE__,tty->driver->name, info->port.count);
747
748 /* If port is closing, signal caller to try again */
749 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
750 if (info->port.flags & ASYNC_CLOSING)
751 interruptible_sleep_on(&info->port.close_wait);
752 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
753 -EAGAIN : -ERESTARTSYS);
754 goto cleanup;
755 }
756
757 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
758
759 spin_lock_irqsave(&info->netlock, flags);
760 if (info->netcount) {
761 retval = -EBUSY;
762 spin_unlock_irqrestore(&info->netlock, flags);
763 goto cleanup;
764 }
765 info->port.count++;
766 spin_unlock_irqrestore(&info->netlock, flags);
767
768 if (info->port.count == 1) {
769 /* 1st open on this device, init hardware */
770 retval = startup(info);
771 if (retval < 0)
772 goto cleanup;
773 }
774
775 retval = block_til_ready(tty, filp, info);
776 if (retval) {
777 if (debug_level >= DEBUG_LEVEL_INFO)
778 printk("%s(%d):%s block_til_ready() returned %d\n",
779 __FILE__,__LINE__, info->device_name, retval);
780 goto cleanup;
781 }
782
783 if (debug_level >= DEBUG_LEVEL_INFO)
784 printk("%s(%d):%s open() success\n",
785 __FILE__,__LINE__, info->device_name);
786 retval = 0;
787
788cleanup:
789 if (retval) {
790 if (tty->count == 1)
791 info->port.tty = NULL; /* tty layer will release tty struct */
792 if(info->port.count)
793 info->port.count--;
794 }
795
796 return retval;
797}
798
799/* Called when port is closed. Wait for remaining data to be
800 * sent. Disable port and free resources.
801 */
802static void close(struct tty_struct *tty, struct file *filp)
803{
804 SLMP_INFO * info = tty->driver_data;
805
806 if (sanity_check(info, tty->name, "close"))
807 return;
808
809 if (debug_level >= DEBUG_LEVEL_INFO)
810 printk("%s(%d):%s close() entry, count=%d\n",
811 __FILE__,__LINE__, info->device_name, info->port.count);
812
813 if (tty_port_close_start(&info->port, tty, filp) == 0)
814 goto cleanup;
815
816 mutex_lock(&info->port.mutex);
817 if (info->port.flags & ASYNC_INITIALIZED)
818 wait_until_sent(tty, info->timeout);
819
820 flush_buffer(tty);
821 tty_ldisc_flush(tty);
822 shutdown(info);
823 mutex_unlock(&info->port.mutex);
824
825 tty_port_close_end(&info->port, tty);
826 info->port.tty = NULL;
827cleanup:
828 if (debug_level >= DEBUG_LEVEL_INFO)
829 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
830 tty->driver->name, info->port.count);
831}
832
833/* Called by tty_hangup() when a hangup is signaled.
834 * This is the same as closing all open descriptors for the port.
835 */
836static void hangup(struct tty_struct *tty)
837{
838 SLMP_INFO *info = tty->driver_data;
839 unsigned long flags;
840
841 if (debug_level >= DEBUG_LEVEL_INFO)
842 printk("%s(%d):%s hangup()\n",
843 __FILE__,__LINE__, info->device_name );
844
845 if (sanity_check(info, tty->name, "hangup"))
846 return;
847
848 mutex_lock(&info->port.mutex);
849 flush_buffer(tty);
850 shutdown(info);
851
852 spin_lock_irqsave(&info->port.lock, flags);
853 info->port.count = 0;
854 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
855 info->port.tty = NULL;
856 spin_unlock_irqrestore(&info->port.lock, flags);
857 mutex_unlock(&info->port.mutex);
858
859 wake_up_interruptible(&info->port.open_wait);
860}
861
862/* Set new termios settings
863 */
864static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
865{
866 SLMP_INFO *info = tty->driver_data;
867 unsigned long flags;
868
869 if (debug_level >= DEBUG_LEVEL_INFO)
870 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
871 tty->driver->name );
872
873 change_params(info);
874
875 /* Handle transition to B0 status */
876 if (old_termios->c_cflag & CBAUD &&
877 !(tty->termios->c_cflag & CBAUD)) {
878 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
879 spin_lock_irqsave(&info->lock,flags);
880 set_signals(info);
881 spin_unlock_irqrestore(&info->lock,flags);
882 }
883
884 /* Handle transition away from B0 status */
885 if (!(old_termios->c_cflag & CBAUD) &&
886 tty->termios->c_cflag & CBAUD) {
887 info->serial_signals |= SerialSignal_DTR;
888 if (!(tty->termios->c_cflag & CRTSCTS) ||
889 !test_bit(TTY_THROTTLED, &tty->flags)) {
890 info->serial_signals |= SerialSignal_RTS;
891 }
892 spin_lock_irqsave(&info->lock,flags);
893 set_signals(info);
894 spin_unlock_irqrestore(&info->lock,flags);
895 }
896
897 /* Handle turning off CRTSCTS */
898 if (old_termios->c_cflag & CRTSCTS &&
899 !(tty->termios->c_cflag & CRTSCTS)) {
900 tty->hw_stopped = 0;
901 tx_release(tty);
902 }
903}
904
905/* Send a block of data
906 *
907 * Arguments:
908 *
909 * tty pointer to tty information structure
910 * buf pointer to buffer containing send data
911 * count size of send data in bytes
912 *
913 * Return Value: number of characters written
914 */
915static int write(struct tty_struct *tty,
916 const unsigned char *buf, int count)
917{
918 int c, ret = 0;
919 SLMP_INFO *info = tty->driver_data;
920 unsigned long flags;
921
922 if (debug_level >= DEBUG_LEVEL_INFO)
923 printk("%s(%d):%s write() count=%d\n",
924 __FILE__,__LINE__,info->device_name,count);
925
926 if (sanity_check(info, tty->name, "write"))
927 goto cleanup;
928
929 if (!info->tx_buf)
930 goto cleanup;
931
932 if (info->params.mode == MGSL_MODE_HDLC) {
933 if (count > info->max_frame_size) {
934 ret = -EIO;
935 goto cleanup;
936 }
937 if (info->tx_active)
938 goto cleanup;
939 if (info->tx_count) {
940 /* send accumulated data from send_char() calls */
941 /* as frame and wait before accepting more data. */
942 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
943 goto start;
944 }
945 ret = info->tx_count = count;
946 tx_load_dma_buffer(info, buf, count);
947 goto start;
948 }
949
950 for (;;) {
951 c = min_t(int, count,
952 min(info->max_frame_size - info->tx_count - 1,
953 info->max_frame_size - info->tx_put));
954 if (c <= 0)
955 break;
956
957 memcpy(info->tx_buf + info->tx_put, buf, c);
958
959 spin_lock_irqsave(&info->lock,flags);
960 info->tx_put += c;
961 if (info->tx_put >= info->max_frame_size)
962 info->tx_put -= info->max_frame_size;
963 info->tx_count += c;
964 spin_unlock_irqrestore(&info->lock,flags);
965
966 buf += c;
967 count -= c;
968 ret += c;
969 }
970
971 if (info->params.mode == MGSL_MODE_HDLC) {
972 if (count) {
973 ret = info->tx_count = 0;
974 goto cleanup;
975 }
976 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
977 }
978start:
979 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
980 spin_lock_irqsave(&info->lock,flags);
981 if (!info->tx_active)
982 tx_start(info);
983 spin_unlock_irqrestore(&info->lock,flags);
984 }
985
986cleanup:
987 if (debug_level >= DEBUG_LEVEL_INFO)
988 printk( "%s(%d):%s write() returning=%d\n",
989 __FILE__,__LINE__,info->device_name,ret);
990 return ret;
991}
992
993/* Add a character to the transmit buffer.
994 */
995static int put_char(struct tty_struct *tty, unsigned char ch)
996{
997 SLMP_INFO *info = tty->driver_data;
998 unsigned long flags;
999 int ret = 0;
1000
1001 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1002 printk( "%s(%d):%s put_char(%d)\n",
1003 __FILE__,__LINE__,info->device_name,ch);
1004 }
1005
1006 if (sanity_check(info, tty->name, "put_char"))
1007 return 0;
1008
1009 if (!info->tx_buf)
1010 return 0;
1011
1012 spin_lock_irqsave(&info->lock,flags);
1013
1014 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1015 !info->tx_active ) {
1016
1017 if (info->tx_count < info->max_frame_size - 1) {
1018 info->tx_buf[info->tx_put++] = ch;
1019 if (info->tx_put >= info->max_frame_size)
1020 info->tx_put -= info->max_frame_size;
1021 info->tx_count++;
1022 ret = 1;
1023 }
1024 }
1025
1026 spin_unlock_irqrestore(&info->lock,flags);
1027 return ret;
1028}
1029
1030/* Send a high-priority XON/XOFF character
1031 */
1032static void send_xchar(struct tty_struct *tty, char ch)
1033{
1034 SLMP_INFO *info = tty->driver_data;
1035 unsigned long flags;
1036
1037 if (debug_level >= DEBUG_LEVEL_INFO)
1038 printk("%s(%d):%s send_xchar(%d)\n",
1039 __FILE__,__LINE__, info->device_name, ch );
1040
1041 if (sanity_check(info, tty->name, "send_xchar"))
1042 return;
1043
1044 info->x_char = ch;
1045 if (ch) {
1046 /* Make sure transmit interrupts are on */
1047 spin_lock_irqsave(&info->lock,flags);
1048 if (!info->tx_enabled)
1049 tx_start(info);
1050 spin_unlock_irqrestore(&info->lock,flags);
1051 }
1052}
1053
1054/* Wait until the transmitter is empty.
1055 */
1056static void wait_until_sent(struct tty_struct *tty, int timeout)
1057{
1058 SLMP_INFO * info = tty->driver_data;
1059 unsigned long orig_jiffies, char_time;
1060
1061 if (!info )
1062 return;
1063
1064 if (debug_level >= DEBUG_LEVEL_INFO)
1065 printk("%s(%d):%s wait_until_sent() entry\n",
1066 __FILE__,__LINE__, info->device_name );
1067
1068 if (sanity_check(info, tty->name, "wait_until_sent"))
1069 return;
1070
1071 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1072 goto exit;
1073
1074 orig_jiffies = jiffies;
1075
1076 /* Set check interval to 1/5 of estimated time to
1077 * send a character, and make it at least 1. The check
1078 * interval should also be less than the timeout.
1079 * Note: use tight timings here to satisfy the NIST-PCTS.
1080 */
1081
1082 if ( info->params.data_rate ) {
1083 char_time = info->timeout/(32 * 5);
1084 if (!char_time)
1085 char_time++;
1086 } else
1087 char_time = 1;
1088
1089 if (timeout)
1090 char_time = min_t(unsigned long, char_time, timeout);
1091
1092 if ( info->params.mode == MGSL_MODE_HDLC ) {
1093 while (info->tx_active) {
1094 msleep_interruptible(jiffies_to_msecs(char_time));
1095 if (signal_pending(current))
1096 break;
1097 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1098 break;
1099 }
1100 } else {
1101 /*
1102 * TODO: determine if there is something similar to USC16C32
1103 * TXSTATUS_ALL_SENT status
1104 */
1105 while ( info->tx_active && info->tx_enabled) {
1106 msleep_interruptible(jiffies_to_msecs(char_time));
1107 if (signal_pending(current))
1108 break;
1109 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1110 break;
1111 }
1112 }
1113
1114exit:
1115 if (debug_level >= DEBUG_LEVEL_INFO)
1116 printk("%s(%d):%s wait_until_sent() exit\n",
1117 __FILE__,__LINE__, info->device_name );
1118}
1119
1120/* Return the count of free bytes in transmit buffer
1121 */
1122static int write_room(struct tty_struct *tty)
1123{
1124 SLMP_INFO *info = tty->driver_data;
1125 int ret;
1126
1127 if (sanity_check(info, tty->name, "write_room"))
1128 return 0;
1129
1130 if (info->params.mode == MGSL_MODE_HDLC) {
1131 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1132 } else {
1133 ret = info->max_frame_size - info->tx_count - 1;
1134 if (ret < 0)
1135 ret = 0;
1136 }
1137
1138 if (debug_level >= DEBUG_LEVEL_INFO)
1139 printk("%s(%d):%s write_room()=%d\n",
1140 __FILE__, __LINE__, info->device_name, ret);
1141
1142 return ret;
1143}
1144
1145/* enable transmitter and send remaining buffered characters
1146 */
1147static void flush_chars(struct tty_struct *tty)
1148{
1149 SLMP_INFO *info = tty->driver_data;
1150 unsigned long flags;
1151
1152 if ( debug_level >= DEBUG_LEVEL_INFO )
1153 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1154 __FILE__,__LINE__,info->device_name,info->tx_count);
1155
1156 if (sanity_check(info, tty->name, "flush_chars"))
1157 return;
1158
1159 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1160 !info->tx_buf)
1161 return;
1162
1163 if ( debug_level >= DEBUG_LEVEL_INFO )
1164 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1165 __FILE__,__LINE__,info->device_name );
1166
1167 spin_lock_irqsave(&info->lock,flags);
1168
1169 if (!info->tx_active) {
1170 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1171 info->tx_count ) {
1172 /* operating in synchronous (frame oriented) mode */
1173 /* copy data from circular tx_buf to */
1174 /* transmit DMA buffer. */
1175 tx_load_dma_buffer(info,
1176 info->tx_buf,info->tx_count);
1177 }
1178 tx_start(info);
1179 }
1180
1181 spin_unlock_irqrestore(&info->lock,flags);
1182}
1183
1184/* Discard all data in the send buffer
1185 */
1186static void flush_buffer(struct tty_struct *tty)
1187{
1188 SLMP_INFO *info = tty->driver_data;
1189 unsigned long flags;
1190
1191 if (debug_level >= DEBUG_LEVEL_INFO)
1192 printk("%s(%d):%s flush_buffer() entry\n",
1193 __FILE__,__LINE__, info->device_name );
1194
1195 if (sanity_check(info, tty->name, "flush_buffer"))
1196 return;
1197
1198 spin_lock_irqsave(&info->lock,flags);
1199 info->tx_count = info->tx_put = info->tx_get = 0;
1200 del_timer(&info->tx_timer);
1201 spin_unlock_irqrestore(&info->lock,flags);
1202
1203 tty_wakeup(tty);
1204}
1205
1206/* throttle (stop) transmitter
1207 */
1208static void tx_hold(struct tty_struct *tty)
1209{
1210 SLMP_INFO *info = tty->driver_data;
1211 unsigned long flags;
1212
1213 if (sanity_check(info, tty->name, "tx_hold"))
1214 return;
1215
1216 if ( debug_level >= DEBUG_LEVEL_INFO )
1217 printk("%s(%d):%s tx_hold()\n",
1218 __FILE__,__LINE__,info->device_name);
1219
1220 spin_lock_irqsave(&info->lock,flags);
1221 if (info->tx_enabled)
1222 tx_stop(info);
1223 spin_unlock_irqrestore(&info->lock,flags);
1224}
1225
1226/* release (start) transmitter
1227 */
1228static void tx_release(struct tty_struct *tty)
1229{
1230 SLMP_INFO *info = tty->driver_data;
1231 unsigned long flags;
1232
1233 if (sanity_check(info, tty->name, "tx_release"))
1234 return;
1235
1236 if ( debug_level >= DEBUG_LEVEL_INFO )
1237 printk("%s(%d):%s tx_release()\n",
1238 __FILE__,__LINE__,info->device_name);
1239
1240 spin_lock_irqsave(&info->lock,flags);
1241 if (!info->tx_enabled)
1242 tx_start(info);
1243 spin_unlock_irqrestore(&info->lock,flags);
1244}
1245
1246/* Service an IOCTL request
1247 *
1248 * Arguments:
1249 *
1250 * tty pointer to tty instance data
1251 * cmd IOCTL command code
1252 * arg command argument/context
1253 *
1254 * Return Value: 0 if success, otherwise error code
1255 */
1256static int ioctl(struct tty_struct *tty,
1257 unsigned int cmd, unsigned long arg)
1258{
1259 SLMP_INFO *info = tty->driver_data;
1260 void __user *argp = (void __user *)arg;
1261
1262 if (debug_level >= DEBUG_LEVEL_INFO)
1263 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1264 info->device_name, cmd );
1265
1266 if (sanity_check(info, tty->name, "ioctl"))
1267 return -ENODEV;
1268
1269 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1270 (cmd != TIOCMIWAIT)) {
1271 if (tty->flags & (1 << TTY_IO_ERROR))
1272 return -EIO;
1273 }
1274
1275 switch (cmd) {
1276 case MGSL_IOCGPARAMS:
1277 return get_params(info, argp);
1278 case MGSL_IOCSPARAMS:
1279 return set_params(info, argp);
1280 case MGSL_IOCGTXIDLE:
1281 return get_txidle(info, argp);
1282 case MGSL_IOCSTXIDLE:
1283 return set_txidle(info, (int)arg);
1284 case MGSL_IOCTXENABLE:
1285 return tx_enable(info, (int)arg);
1286 case MGSL_IOCRXENABLE:
1287 return rx_enable(info, (int)arg);
1288 case MGSL_IOCTXABORT:
1289 return tx_abort(info);
1290 case MGSL_IOCGSTATS:
1291 return get_stats(info, argp);
1292 case MGSL_IOCWAITEVENT:
1293 return wait_mgsl_event(info, argp);
1294 case MGSL_IOCLOOPTXDONE:
1295 return 0; // TODO: Not supported, need to document
1296 /* Wait for modem input (DCD,RI,DSR,CTS) change
1297 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1298 */
1299 case TIOCMIWAIT:
1300 return modem_input_wait(info,(int)arg);
1301
1302 /*
1303 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1304 * Return: write counters to the user passed counter struct
1305 * NB: both 1->0 and 0->1 transitions are counted except for
1306 * RI where only 0->1 is counted.
1307 */
1308 default:
1309 return -ENOIOCTLCMD;
1310 }
1311 return 0;
1312}
1313
1314static int get_icount(struct tty_struct *tty,
1315 struct serial_icounter_struct *icount)
1316{
1317 SLMP_INFO *info = tty->driver_data;
1318 struct mgsl_icount cnow; /* kernel counter temps */
1319 unsigned long flags;
1320
1321 spin_lock_irqsave(&info->lock,flags);
1322 cnow = info->icount;
1323 spin_unlock_irqrestore(&info->lock,flags);
1324
1325 icount->cts = cnow.cts;
1326 icount->dsr = cnow.dsr;
1327 icount->rng = cnow.rng;
1328 icount->dcd = cnow.dcd;
1329 icount->rx = cnow.rx;
1330 icount->tx = cnow.tx;
1331 icount->frame = cnow.frame;
1332 icount->overrun = cnow.overrun;
1333 icount->parity = cnow.parity;
1334 icount->brk = cnow.brk;
1335 icount->buf_overrun = cnow.buf_overrun;
1336
1337 return 0;
1338}
1339
1340/*
1341 * /proc fs routines....
1342 */
1343
1344static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1345{
1346 char stat_buf[30];
1347 unsigned long flags;
1348
1349 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1350 "\tIRQ=%d MaxFrameSize=%u\n",
1351 info->device_name,
1352 info->phys_sca_base,
1353 info->phys_memory_base,
1354 info->phys_statctrl_base,
1355 info->phys_lcr_base,
1356 info->irq_level,
1357 info->max_frame_size );
1358
1359 /* output current serial signal states */
1360 spin_lock_irqsave(&info->lock,flags);
1361 get_signals(info);
1362 spin_unlock_irqrestore(&info->lock,flags);
1363
1364 stat_buf[0] = 0;
1365 stat_buf[1] = 0;
1366 if (info->serial_signals & SerialSignal_RTS)
1367 strcat(stat_buf, "|RTS");
1368 if (info->serial_signals & SerialSignal_CTS)
1369 strcat(stat_buf, "|CTS");
1370 if (info->serial_signals & SerialSignal_DTR)
1371 strcat(stat_buf, "|DTR");
1372 if (info->serial_signals & SerialSignal_DSR)
1373 strcat(stat_buf, "|DSR");
1374 if (info->serial_signals & SerialSignal_DCD)
1375 strcat(stat_buf, "|CD");
1376 if (info->serial_signals & SerialSignal_RI)
1377 strcat(stat_buf, "|RI");
1378
1379 if (info->params.mode == MGSL_MODE_HDLC) {
1380 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1381 info->icount.txok, info->icount.rxok);
1382 if (info->icount.txunder)
1383 seq_printf(m, " txunder:%d", info->icount.txunder);
1384 if (info->icount.txabort)
1385 seq_printf(m, " txabort:%d", info->icount.txabort);
1386 if (info->icount.rxshort)
1387 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1388 if (info->icount.rxlong)
1389 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1390 if (info->icount.rxover)
1391 seq_printf(m, " rxover:%d", info->icount.rxover);
1392 if (info->icount.rxcrc)
1393 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1394 } else {
1395 seq_printf(m, "\tASYNC tx:%d rx:%d",
1396 info->icount.tx, info->icount.rx);
1397 if (info->icount.frame)
1398 seq_printf(m, " fe:%d", info->icount.frame);
1399 if (info->icount.parity)
1400 seq_printf(m, " pe:%d", info->icount.parity);
1401 if (info->icount.brk)
1402 seq_printf(m, " brk:%d", info->icount.brk);
1403 if (info->icount.overrun)
1404 seq_printf(m, " oe:%d", info->icount.overrun);
1405 }
1406
1407 /* Append serial signal status to end */
1408 seq_printf(m, " %s\n", stat_buf+1);
1409
1410 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1411 info->tx_active,info->bh_requested,info->bh_running,
1412 info->pending_bh);
1413}
1414
1415/* Called to print information about devices
1416 */
1417static int synclinkmp_proc_show(struct seq_file *m, void *v)
1418{
1419 SLMP_INFO *info;
1420
1421 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1422
1423 info = synclinkmp_device_list;
1424 while( info ) {
1425 line_info(m, info);
1426 info = info->next_device;
1427 }
1428 return 0;
1429}
1430
1431static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1432{
1433 return single_open(file, synclinkmp_proc_show, NULL);
1434}
1435
1436static const struct file_operations synclinkmp_proc_fops = {
1437 .owner = THIS_MODULE,
1438 .open = synclinkmp_proc_open,
1439 .read = seq_read,
1440 .llseek = seq_lseek,
1441 .release = single_release,
1442};
1443
1444/* Return the count of bytes in transmit buffer
1445 */
1446static int chars_in_buffer(struct tty_struct *tty)
1447{
1448 SLMP_INFO *info = tty->driver_data;
1449
1450 if (sanity_check(info, tty->name, "chars_in_buffer"))
1451 return 0;
1452
1453 if (debug_level >= DEBUG_LEVEL_INFO)
1454 printk("%s(%d):%s chars_in_buffer()=%d\n",
1455 __FILE__, __LINE__, info->device_name, info->tx_count);
1456
1457 return info->tx_count;
1458}
1459
1460/* Signal remote device to throttle send data (our receive data)
1461 */
1462static void throttle(struct tty_struct * tty)
1463{
1464 SLMP_INFO *info = tty->driver_data;
1465 unsigned long flags;
1466
1467 if (debug_level >= DEBUG_LEVEL_INFO)
1468 printk("%s(%d):%s throttle() entry\n",
1469 __FILE__,__LINE__, info->device_name );
1470
1471 if (sanity_check(info, tty->name, "throttle"))
1472 return;
1473
1474 if (I_IXOFF(tty))
1475 send_xchar(tty, STOP_CHAR(tty));
1476
1477 if (tty->termios->c_cflag & CRTSCTS) {
1478 spin_lock_irqsave(&info->lock,flags);
1479 info->serial_signals &= ~SerialSignal_RTS;
1480 set_signals(info);
1481 spin_unlock_irqrestore(&info->lock,flags);
1482 }
1483}
1484
1485/* Signal remote device to stop throttling send data (our receive data)
1486 */
1487static void unthrottle(struct tty_struct * tty)
1488{
1489 SLMP_INFO *info = tty->driver_data;
1490 unsigned long flags;
1491
1492 if (debug_level >= DEBUG_LEVEL_INFO)
1493 printk("%s(%d):%s unthrottle() entry\n",
1494 __FILE__,__LINE__, info->device_name );
1495
1496 if (sanity_check(info, tty->name, "unthrottle"))
1497 return;
1498
1499 if (I_IXOFF(tty)) {
1500 if (info->x_char)
1501 info->x_char = 0;
1502 else
1503 send_xchar(tty, START_CHAR(tty));
1504 }
1505
1506 if (tty->termios->c_cflag & CRTSCTS) {
1507 spin_lock_irqsave(&info->lock,flags);
1508 info->serial_signals |= SerialSignal_RTS;
1509 set_signals(info);
1510 spin_unlock_irqrestore(&info->lock,flags);
1511 }
1512}
1513
1514/* set or clear transmit break condition
1515 * break_state -1=set break condition, 0=clear
1516 */
1517static int set_break(struct tty_struct *tty, int break_state)
1518{
1519 unsigned char RegValue;
1520 SLMP_INFO * info = tty->driver_data;
1521 unsigned long flags;
1522
1523 if (debug_level >= DEBUG_LEVEL_INFO)
1524 printk("%s(%d):%s set_break(%d)\n",
1525 __FILE__,__LINE__, info->device_name, break_state);
1526
1527 if (sanity_check(info, tty->name, "set_break"))
1528 return -EINVAL;
1529
1530 spin_lock_irqsave(&info->lock,flags);
1531 RegValue = read_reg(info, CTL);
1532 if (break_state == -1)
1533 RegValue |= BIT3;
1534 else
1535 RegValue &= ~BIT3;
1536 write_reg(info, CTL, RegValue);
1537 spin_unlock_irqrestore(&info->lock,flags);
1538 return 0;
1539}
1540
1541#if SYNCLINK_GENERIC_HDLC
1542
1543/**
1544 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1545 * set encoding and frame check sequence (FCS) options
1546 *
1547 * dev pointer to network device structure
1548 * encoding serial encoding setting
1549 * parity FCS setting
1550 *
1551 * returns 0 if success, otherwise error code
1552 */
1553static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1554 unsigned short parity)
1555{
1556 SLMP_INFO *info = dev_to_port(dev);
1557 unsigned char new_encoding;
1558 unsigned short new_crctype;
1559
1560 /* return error if TTY interface open */
1561 if (info->port.count)
1562 return -EBUSY;
1563
1564 switch (encoding)
1565 {
1566 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1567 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1568 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1569 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1570 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1571 default: return -EINVAL;
1572 }
1573
1574 switch (parity)
1575 {
1576 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1577 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1578 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1579 default: return -EINVAL;
1580 }
1581
1582 info->params.encoding = new_encoding;
1583 info->params.crc_type = new_crctype;
1584
1585 /* if network interface up, reprogram hardware */
1586 if (info->netcount)
1587 program_hw(info);
1588
1589 return 0;
1590}
1591
1592/**
1593 * called by generic HDLC layer to send frame
1594 *
1595 * skb socket buffer containing HDLC frame
1596 * dev pointer to network device structure
1597 */
1598static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1599 struct net_device *dev)
1600{
1601 SLMP_INFO *info = dev_to_port(dev);
1602 unsigned long flags;
1603
1604 if (debug_level >= DEBUG_LEVEL_INFO)
1605 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1606
1607 /* stop sending until this frame completes */
1608 netif_stop_queue(dev);
1609
1610 /* copy data to device buffers */
1611 info->tx_count = skb->len;
1612 tx_load_dma_buffer(info, skb->data, skb->len);
1613
1614 /* update network statistics */
1615 dev->stats.tx_packets++;
1616 dev->stats.tx_bytes += skb->len;
1617
1618 /* done with socket buffer, so free it */
1619 dev_kfree_skb(skb);
1620
1621 /* save start time for transmit timeout detection */
1622 dev->trans_start = jiffies;
1623
1624 /* start hardware transmitter if necessary */
1625 spin_lock_irqsave(&info->lock,flags);
1626 if (!info->tx_active)
1627 tx_start(info);
1628 spin_unlock_irqrestore(&info->lock,flags);
1629
1630 return NETDEV_TX_OK;
1631}
1632
1633/**
1634 * called by network layer when interface enabled
1635 * claim resources and initialize hardware
1636 *
1637 * dev pointer to network device structure
1638 *
1639 * returns 0 if success, otherwise error code
1640 */
1641static int hdlcdev_open(struct net_device *dev)
1642{
1643 SLMP_INFO *info = dev_to_port(dev);
1644 int rc;
1645 unsigned long flags;
1646
1647 if (debug_level >= DEBUG_LEVEL_INFO)
1648 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1649
1650 /* generic HDLC layer open processing */
1651 if ((rc = hdlc_open(dev)))
1652 return rc;
1653
1654 /* arbitrate between network and tty opens */
1655 spin_lock_irqsave(&info->netlock, flags);
1656 if (info->port.count != 0 || info->netcount != 0) {
1657 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1658 spin_unlock_irqrestore(&info->netlock, flags);
1659 return -EBUSY;
1660 }
1661 info->netcount=1;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663
1664 /* claim resources and init adapter */
1665 if ((rc = startup(info)) != 0) {
1666 spin_lock_irqsave(&info->netlock, flags);
1667 info->netcount=0;
1668 spin_unlock_irqrestore(&info->netlock, flags);
1669 return rc;
1670 }
1671
1672 /* assert DTR and RTS, apply hardware settings */
1673 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1674 program_hw(info);
1675
1676 /* enable network layer transmit */
1677 dev->trans_start = jiffies;
1678 netif_start_queue(dev);
1679
1680 /* inform generic HDLC layer of current DCD status */
1681 spin_lock_irqsave(&info->lock, flags);
1682 get_signals(info);
1683 spin_unlock_irqrestore(&info->lock, flags);
1684 if (info->serial_signals & SerialSignal_DCD)
1685 netif_carrier_on(dev);
1686 else
1687 netif_carrier_off(dev);
1688 return 0;
1689}
1690
1691/**
1692 * called by network layer when interface is disabled
1693 * shutdown hardware and release resources
1694 *
1695 * dev pointer to network device structure
1696 *
1697 * returns 0 if success, otherwise error code
1698 */
1699static int hdlcdev_close(struct net_device *dev)
1700{
1701 SLMP_INFO *info = dev_to_port(dev);
1702 unsigned long flags;
1703
1704 if (debug_level >= DEBUG_LEVEL_INFO)
1705 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1706
1707 netif_stop_queue(dev);
1708
1709 /* shutdown adapter and release resources */
1710 shutdown(info);
1711
1712 hdlc_close(dev);
1713
1714 spin_lock_irqsave(&info->netlock, flags);
1715 info->netcount=0;
1716 spin_unlock_irqrestore(&info->netlock, flags);
1717
1718 return 0;
1719}
1720
1721/**
1722 * called by network layer to process IOCTL call to network device
1723 *
1724 * dev pointer to network device structure
1725 * ifr pointer to network interface request structure
1726 * cmd IOCTL command code
1727 *
1728 * returns 0 if success, otherwise error code
1729 */
1730static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1731{
1732 const size_t size = sizeof(sync_serial_settings);
1733 sync_serial_settings new_line;
1734 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1735 SLMP_INFO *info = dev_to_port(dev);
1736 unsigned int flags;
1737
1738 if (debug_level >= DEBUG_LEVEL_INFO)
1739 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1740
1741 /* return error if TTY interface open */
1742 if (info->port.count)
1743 return -EBUSY;
1744
1745 if (cmd != SIOCWANDEV)
1746 return hdlc_ioctl(dev, ifr, cmd);
1747
1748 switch(ifr->ifr_settings.type) {
1749 case IF_GET_IFACE: /* return current sync_serial_settings */
1750
1751 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1752 if (ifr->ifr_settings.size < size) {
1753 ifr->ifr_settings.size = size; /* data size wanted */
1754 return -ENOBUFS;
1755 }
1756
1757 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1758 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1759 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1760 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1761
1762 switch (flags){
1763 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1764 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1765 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1766 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1767 default: new_line.clock_type = CLOCK_DEFAULT;
1768 }
1769
1770 new_line.clock_rate = info->params.clock_speed;
1771 new_line.loopback = info->params.loopback ? 1:0;
1772
1773 if (copy_to_user(line, &new_line, size))
1774 return -EFAULT;
1775 return 0;
1776
1777 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1778
1779 if(!capable(CAP_NET_ADMIN))
1780 return -EPERM;
1781 if (copy_from_user(&new_line, line, size))
1782 return -EFAULT;
1783
1784 switch (new_line.clock_type)
1785 {
1786 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1787 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1788 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1789 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1790 case CLOCK_DEFAULT: flags = info->params.flags &
1791 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1792 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1793 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1794 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1795 default: return -EINVAL;
1796 }
1797
1798 if (new_line.loopback != 0 && new_line.loopback != 1)
1799 return -EINVAL;
1800
1801 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1802 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1803 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1804 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1805 info->params.flags |= flags;
1806
1807 info->params.loopback = new_line.loopback;
1808
1809 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1810 info->params.clock_speed = new_line.clock_rate;
1811 else
1812 info->params.clock_speed = 0;
1813
1814 /* if network interface up, reprogram hardware */
1815 if (info->netcount)
1816 program_hw(info);
1817 return 0;
1818
1819 default:
1820 return hdlc_ioctl(dev, ifr, cmd);
1821 }
1822}
1823
1824/**
1825 * called by network layer when transmit timeout is detected
1826 *
1827 * dev pointer to network device structure
1828 */
1829static void hdlcdev_tx_timeout(struct net_device *dev)
1830{
1831 SLMP_INFO *info = dev_to_port(dev);
1832 unsigned long flags;
1833
1834 if (debug_level >= DEBUG_LEVEL_INFO)
1835 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1836
1837 dev->stats.tx_errors++;
1838 dev->stats.tx_aborted_errors++;
1839
1840 spin_lock_irqsave(&info->lock,flags);
1841 tx_stop(info);
1842 spin_unlock_irqrestore(&info->lock,flags);
1843
1844 netif_wake_queue(dev);
1845}
1846
1847/**
1848 * called by device driver when transmit completes
1849 * reenable network layer transmit if stopped
1850 *
1851 * info pointer to device instance information
1852 */
1853static void hdlcdev_tx_done(SLMP_INFO *info)
1854{
1855 if (netif_queue_stopped(info->netdev))
1856 netif_wake_queue(info->netdev);
1857}
1858
1859/**
1860 * called by device driver when frame received
1861 * pass frame to network layer
1862 *
1863 * info pointer to device instance information
1864 * buf pointer to buffer contianing frame data
1865 * size count of data bytes in buf
1866 */
1867static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1868{
1869 struct sk_buff *skb = dev_alloc_skb(size);
1870 struct net_device *dev = info->netdev;
1871
1872 if (debug_level >= DEBUG_LEVEL_INFO)
1873 printk("hdlcdev_rx(%s)\n",dev->name);
1874
1875 if (skb == NULL) {
1876 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1877 dev->name);
1878 dev->stats.rx_dropped++;
1879 return;
1880 }
1881
1882 memcpy(skb_put(skb, size), buf, size);
1883
1884 skb->protocol = hdlc_type_trans(skb, dev);
1885
1886 dev->stats.rx_packets++;
1887 dev->stats.rx_bytes += size;
1888
1889 netif_rx(skb);
1890}
1891
1892static const struct net_device_ops hdlcdev_ops = {
1893 .ndo_open = hdlcdev_open,
1894 .ndo_stop = hdlcdev_close,
1895 .ndo_change_mtu = hdlc_change_mtu,
1896 .ndo_start_xmit = hdlc_start_xmit,
1897 .ndo_do_ioctl = hdlcdev_ioctl,
1898 .ndo_tx_timeout = hdlcdev_tx_timeout,
1899};
1900
1901/**
1902 * called by device driver when adding device instance
1903 * do generic HDLC initialization
1904 *
1905 * info pointer to device instance information
1906 *
1907 * returns 0 if success, otherwise error code
1908 */
1909static int hdlcdev_init(SLMP_INFO *info)
1910{
1911 int rc;
1912 struct net_device *dev;
1913 hdlc_device *hdlc;
1914
1915 /* allocate and initialize network and HDLC layer objects */
1916
1917 if (!(dev = alloc_hdlcdev(info))) {
1918 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1919 return -ENOMEM;
1920 }
1921
1922 /* for network layer reporting purposes only */
1923 dev->mem_start = info->phys_sca_base;
1924 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1925 dev->irq = info->irq_level;
1926
1927 /* network layer callbacks and settings */
1928 dev->netdev_ops = &hdlcdev_ops;
1929 dev->watchdog_timeo = 10 * HZ;
1930 dev->tx_queue_len = 50;
1931
1932 /* generic HDLC layer callbacks and settings */
1933 hdlc = dev_to_hdlc(dev);
1934 hdlc->attach = hdlcdev_attach;
1935 hdlc->xmit = hdlcdev_xmit;
1936
1937 /* register objects with HDLC layer */
1938 if ((rc = register_hdlc_device(dev))) {
1939 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1940 free_netdev(dev);
1941 return rc;
1942 }
1943
1944 info->netdev = dev;
1945 return 0;
1946}
1947
1948/**
1949 * called by device driver when removing device instance
1950 * do generic HDLC cleanup
1951 *
1952 * info pointer to device instance information
1953 */
1954static void hdlcdev_exit(SLMP_INFO *info)
1955{
1956 unregister_hdlc_device(info->netdev);
1957 free_netdev(info->netdev);
1958 info->netdev = NULL;
1959}
1960
1961#endif /* CONFIG_HDLC */
1962
1963
1964/* Return next bottom half action to perform.
1965 * Return Value: BH action code or 0 if nothing to do.
1966 */
1967static int bh_action(SLMP_INFO *info)
1968{
1969 unsigned long flags;
1970 int rc = 0;
1971
1972 spin_lock_irqsave(&info->lock,flags);
1973
1974 if (info->pending_bh & BH_RECEIVE) {
1975 info->pending_bh &= ~BH_RECEIVE;
1976 rc = BH_RECEIVE;
1977 } else if (info->pending_bh & BH_TRANSMIT) {
1978 info->pending_bh &= ~BH_TRANSMIT;
1979 rc = BH_TRANSMIT;
1980 } else if (info->pending_bh & BH_STATUS) {
1981 info->pending_bh &= ~BH_STATUS;
1982 rc = BH_STATUS;
1983 }
1984
1985 if (!rc) {
1986 /* Mark BH routine as complete */
1987 info->bh_running = false;
1988 info->bh_requested = false;
1989 }
1990
1991 spin_unlock_irqrestore(&info->lock,flags);
1992
1993 return rc;
1994}
1995
1996/* Perform bottom half processing of work items queued by ISR.
1997 */
1998static void bh_handler(struct work_struct *work)
1999{
2000 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2001 int action;
2002
2003 if (!info)
2004 return;
2005
2006 if ( debug_level >= DEBUG_LEVEL_BH )
2007 printk( "%s(%d):%s bh_handler() entry\n",
2008 __FILE__,__LINE__,info->device_name);
2009
2010 info->bh_running = true;
2011
2012 while((action = bh_action(info)) != 0) {
2013
2014 /* Process work item */
2015 if ( debug_level >= DEBUG_LEVEL_BH )
2016 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2017 __FILE__,__LINE__,info->device_name, action);
2018
2019 switch (action) {
2020
2021 case BH_RECEIVE:
2022 bh_receive(info);
2023 break;
2024 case BH_TRANSMIT:
2025 bh_transmit(info);
2026 break;
2027 case BH_STATUS:
2028 bh_status(info);
2029 break;
2030 default:
2031 /* unknown work item ID */
2032 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2033 __FILE__,__LINE__,info->device_name,action);
2034 break;
2035 }
2036 }
2037
2038 if ( debug_level >= DEBUG_LEVEL_BH )
2039 printk( "%s(%d):%s bh_handler() exit\n",
2040 __FILE__,__LINE__,info->device_name);
2041}
2042
2043static void bh_receive(SLMP_INFO *info)
2044{
2045 if ( debug_level >= DEBUG_LEVEL_BH )
2046 printk( "%s(%d):%s bh_receive()\n",
2047 __FILE__,__LINE__,info->device_name);
2048
2049 while( rx_get_frame(info) );
2050}
2051
2052static void bh_transmit(SLMP_INFO *info)
2053{
2054 struct tty_struct *tty = info->port.tty;
2055
2056 if ( debug_level >= DEBUG_LEVEL_BH )
2057 printk( "%s(%d):%s bh_transmit() entry\n",
2058 __FILE__,__LINE__,info->device_name);
2059
2060 if (tty)
2061 tty_wakeup(tty);
2062}
2063
2064static void bh_status(SLMP_INFO *info)
2065{
2066 if ( debug_level >= DEBUG_LEVEL_BH )
2067 printk( "%s(%d):%s bh_status() entry\n",
2068 __FILE__,__LINE__,info->device_name);
2069
2070 info->ri_chkcount = 0;
2071 info->dsr_chkcount = 0;
2072 info->dcd_chkcount = 0;
2073 info->cts_chkcount = 0;
2074}
2075
2076static void isr_timer(SLMP_INFO * info)
2077{
2078 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2079
2080 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2081 write_reg(info, IER2, 0);
2082
2083 /* TMCS, Timer Control/Status Register
2084 *
2085 * 07 CMF, Compare match flag (read only) 1=match
2086 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2087 * 05 Reserved, must be 0
2088 * 04 TME, Timer Enable
2089 * 03..00 Reserved, must be 0
2090 *
2091 * 0000 0000
2092 */
2093 write_reg(info, (unsigned char)(timer + TMCS), 0);
2094
2095 info->irq_occurred = true;
2096
2097 if ( debug_level >= DEBUG_LEVEL_ISR )
2098 printk("%s(%d):%s isr_timer()\n",
2099 __FILE__,__LINE__,info->device_name);
2100}
2101
2102static void isr_rxint(SLMP_INFO * info)
2103{
2104 struct tty_struct *tty = info->port.tty;
2105 struct mgsl_icount *icount = &info->icount;
2106 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2107 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2108
2109 /* clear status bits */
2110 if (status)
2111 write_reg(info, SR1, status);
2112
2113 if (status2)
2114 write_reg(info, SR2, status2);
2115
2116 if ( debug_level >= DEBUG_LEVEL_ISR )
2117 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2118 __FILE__,__LINE__,info->device_name,status,status2);
2119
2120 if (info->params.mode == MGSL_MODE_ASYNC) {
2121 if (status & BRKD) {
2122 icount->brk++;
2123
2124 /* process break detection if tty control
2125 * is not set to ignore it
2126 */
2127 if ( tty ) {
2128 if (!(status & info->ignore_status_mask1)) {
2129 if (info->read_status_mask1 & BRKD) {
2130 tty_insert_flip_char(tty, 0, TTY_BREAK);
2131 if (info->port.flags & ASYNC_SAK)
2132 do_SAK(tty);
2133 }
2134 }
2135 }
2136 }
2137 }
2138 else {
2139 if (status & (FLGD|IDLD)) {
2140 if (status & FLGD)
2141 info->icount.exithunt++;
2142 else if (status & IDLD)
2143 info->icount.rxidle++;
2144 wake_up_interruptible(&info->event_wait_q);
2145 }
2146 }
2147
2148 if (status & CDCD) {
2149 /* simulate a common modem status change interrupt
2150 * for our handler
2151 */
2152 get_signals( info );
2153 isr_io_pin(info,
2154 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2155 }
2156}
2157
2158/*
2159 * handle async rx data interrupts
2160 */
2161static void isr_rxrdy(SLMP_INFO * info)
2162{
2163 u16 status;
2164 unsigned char DataByte;
2165 struct tty_struct *tty = info->port.tty;
2166 struct mgsl_icount *icount = &info->icount;
2167
2168 if ( debug_level >= DEBUG_LEVEL_ISR )
2169 printk("%s(%d):%s isr_rxrdy\n",
2170 __FILE__,__LINE__,info->device_name);
2171
2172 while((status = read_reg(info,CST0)) & BIT0)
2173 {
2174 int flag = 0;
2175 bool over = false;
2176 DataByte = read_reg(info,TRB);
2177
2178 icount->rx++;
2179
2180 if ( status & (PE + FRME + OVRN) ) {
2181 printk("%s(%d):%s rxerr=%04X\n",
2182 __FILE__,__LINE__,info->device_name,status);
2183
2184 /* update error statistics */
2185 if (status & PE)
2186 icount->parity++;
2187 else if (status & FRME)
2188 icount->frame++;
2189 else if (status & OVRN)
2190 icount->overrun++;
2191
2192 /* discard char if tty control flags say so */
2193 if (status & info->ignore_status_mask2)
2194 continue;
2195
2196 status &= info->read_status_mask2;
2197
2198 if ( tty ) {
2199 if (status & PE)
2200 flag = TTY_PARITY;
2201 else if (status & FRME)
2202 flag = TTY_FRAME;
2203 if (status & OVRN) {
2204 /* Overrun is special, since it's
2205 * reported immediately, and doesn't
2206 * affect the current character
2207 */
2208 over = true;
2209 }
2210 }
2211 } /* end of if (error) */
2212
2213 if ( tty ) {
2214 tty_insert_flip_char(tty, DataByte, flag);
2215 if (over)
2216 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2217 }
2218 }
2219
2220 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2221 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2222 __FILE__,__LINE__,info->device_name,
2223 icount->rx,icount->brk,icount->parity,
2224 icount->frame,icount->overrun);
2225 }
2226
2227 if ( tty )
2228 tty_flip_buffer_push(tty);
2229}
2230
2231static void isr_txeom(SLMP_INFO * info, unsigned char status)
2232{
2233 if ( debug_level >= DEBUG_LEVEL_ISR )
2234 printk("%s(%d):%s isr_txeom status=%02x\n",
2235 __FILE__,__LINE__,info->device_name,status);
2236
2237 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2238 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2239 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2240
2241 if (status & UDRN) {
2242 write_reg(info, CMD, TXRESET);
2243 write_reg(info, CMD, TXENABLE);
2244 } else
2245 write_reg(info, CMD, TXBUFCLR);
2246
2247 /* disable and clear tx interrupts */
2248 info->ie0_value &= ~TXRDYE;
2249 info->ie1_value &= ~(IDLE + UDRN);
2250 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2251 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2252
2253 if ( info->tx_active ) {
2254 if (info->params.mode != MGSL_MODE_ASYNC) {
2255 if (status & UDRN)
2256 info->icount.txunder++;
2257 else if (status & IDLE)
2258 info->icount.txok++;
2259 }
2260
2261 info->tx_active = false;
2262 info->tx_count = info->tx_put = info->tx_get = 0;
2263
2264 del_timer(&info->tx_timer);
2265
2266 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2267 info->serial_signals &= ~SerialSignal_RTS;
2268 info->drop_rts_on_tx_done = false;
2269 set_signals(info);
2270 }
2271
2272#if SYNCLINK_GENERIC_HDLC
2273 if (info->netcount)
2274 hdlcdev_tx_done(info);
2275 else
2276#endif
2277 {
2278 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2279 tx_stop(info);
2280 return;
2281 }
2282 info->pending_bh |= BH_TRANSMIT;
2283 }
2284 }
2285}
2286
2287
2288/*
2289 * handle tx status interrupts
2290 */
2291static void isr_txint(SLMP_INFO * info)
2292{
2293 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2294
2295 /* clear status bits */
2296 write_reg(info, SR1, status);
2297
2298 if ( debug_level >= DEBUG_LEVEL_ISR )
2299 printk("%s(%d):%s isr_txint status=%02x\n",
2300 __FILE__,__LINE__,info->device_name,status);
2301
2302 if (status & (UDRN + IDLE))
2303 isr_txeom(info, status);
2304
2305 if (status & CCTS) {
2306 /* simulate a common modem status change interrupt
2307 * for our handler
2308 */
2309 get_signals( info );
2310 isr_io_pin(info,
2311 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2312
2313 }
2314}
2315
2316/*
2317 * handle async tx data interrupts
2318 */
2319static void isr_txrdy(SLMP_INFO * info)
2320{
2321 if ( debug_level >= DEBUG_LEVEL_ISR )
2322 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2323 __FILE__,__LINE__,info->device_name,info->tx_count);
2324
2325 if (info->params.mode != MGSL_MODE_ASYNC) {
2326 /* disable TXRDY IRQ, enable IDLE IRQ */
2327 info->ie0_value &= ~TXRDYE;
2328 info->ie1_value |= IDLE;
2329 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2330 return;
2331 }
2332
2333 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2334 tx_stop(info);
2335 return;
2336 }
2337
2338 if ( info->tx_count )
2339 tx_load_fifo( info );
2340 else {
2341 info->tx_active = false;
2342 info->ie0_value &= ~TXRDYE;
2343 write_reg(info, IE0, info->ie0_value);
2344 }
2345
2346 if (info->tx_count < WAKEUP_CHARS)
2347 info->pending_bh |= BH_TRANSMIT;
2348}
2349
2350static void isr_rxdmaok(SLMP_INFO * info)
2351{
2352 /* BIT7 = EOT (end of transfer)
2353 * BIT6 = EOM (end of message/frame)
2354 */
2355 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2356
2357 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2358 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2359
2360 if ( debug_level >= DEBUG_LEVEL_ISR )
2361 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2362 __FILE__,__LINE__,info->device_name,status);
2363
2364 info->pending_bh |= BH_RECEIVE;
2365}
2366
2367static void isr_rxdmaerror(SLMP_INFO * info)
2368{
2369 /* BIT5 = BOF (buffer overflow)
2370 * BIT4 = COF (counter overflow)
2371 */
2372 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2373
2374 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2375 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2376
2377 if ( debug_level >= DEBUG_LEVEL_ISR )
2378 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2379 __FILE__,__LINE__,info->device_name,status);
2380
2381 info->rx_overflow = true;
2382 info->pending_bh |= BH_RECEIVE;
2383}
2384
2385static void isr_txdmaok(SLMP_INFO * info)
2386{
2387 unsigned char status_reg1 = read_reg(info, SR1);
2388
2389 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2390 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2391 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2392
2393 if ( debug_level >= DEBUG_LEVEL_ISR )
2394 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2395 __FILE__,__LINE__,info->device_name,status_reg1);
2396
2397 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2398 write_reg16(info, TRC0, 0);
2399 info->ie0_value |= TXRDYE;
2400 write_reg(info, IE0, info->ie0_value);
2401}
2402
2403static void isr_txdmaerror(SLMP_INFO * info)
2404{
2405 /* BIT5 = BOF (buffer overflow)
2406 * BIT4 = COF (counter overflow)
2407 */
2408 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2409
2410 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2411 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2412
2413 if ( debug_level >= DEBUG_LEVEL_ISR )
2414 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2415 __FILE__,__LINE__,info->device_name,status);
2416}
2417
2418/* handle input serial signal changes
2419 */
2420static void isr_io_pin( SLMP_INFO *info, u16 status )
2421{
2422 struct mgsl_icount *icount;
2423
2424 if ( debug_level >= DEBUG_LEVEL_ISR )
2425 printk("%s(%d):isr_io_pin status=%04X\n",
2426 __FILE__,__LINE__,status);
2427
2428 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2429 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2430 icount = &info->icount;
2431 /* update input line counters */
2432 if (status & MISCSTATUS_RI_LATCHED) {
2433 icount->rng++;
2434 if ( status & SerialSignal_RI )
2435 info->input_signal_events.ri_up++;
2436 else
2437 info->input_signal_events.ri_down++;
2438 }
2439 if (status & MISCSTATUS_DSR_LATCHED) {
2440 icount->dsr++;
2441 if ( status & SerialSignal_DSR )
2442 info->input_signal_events.dsr_up++;
2443 else
2444 info->input_signal_events.dsr_down++;
2445 }
2446 if (status & MISCSTATUS_DCD_LATCHED) {
2447 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2448 info->ie1_value &= ~CDCD;
2449 write_reg(info, IE1, info->ie1_value);
2450 }
2451 icount->dcd++;
2452 if (status & SerialSignal_DCD) {
2453 info->input_signal_events.dcd_up++;
2454 } else
2455 info->input_signal_events.dcd_down++;
2456#if SYNCLINK_GENERIC_HDLC
2457 if (info->netcount) {
2458 if (status & SerialSignal_DCD)
2459 netif_carrier_on(info->netdev);
2460 else
2461 netif_carrier_off(info->netdev);
2462 }
2463#endif
2464 }
2465 if (status & MISCSTATUS_CTS_LATCHED)
2466 {
2467 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2468 info->ie1_value &= ~CCTS;
2469 write_reg(info, IE1, info->ie1_value);
2470 }
2471 icount->cts++;
2472 if ( status & SerialSignal_CTS )
2473 info->input_signal_events.cts_up++;
2474 else
2475 info->input_signal_events.cts_down++;
2476 }
2477 wake_up_interruptible(&info->status_event_wait_q);
2478 wake_up_interruptible(&info->event_wait_q);
2479
2480 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2481 (status & MISCSTATUS_DCD_LATCHED) ) {
2482 if ( debug_level >= DEBUG_LEVEL_ISR )
2483 printk("%s CD now %s...", info->device_name,
2484 (status & SerialSignal_DCD) ? "on" : "off");
2485 if (status & SerialSignal_DCD)
2486 wake_up_interruptible(&info->port.open_wait);
2487 else {
2488 if ( debug_level >= DEBUG_LEVEL_ISR )
2489 printk("doing serial hangup...");
2490 if (info->port.tty)
2491 tty_hangup(info->port.tty);
2492 }
2493 }
2494
2495 if ( (info->port.flags & ASYNC_CTS_FLOW) &&
2496 (status & MISCSTATUS_CTS_LATCHED) ) {
2497 if ( info->port.tty ) {
2498 if (info->port.tty->hw_stopped) {
2499 if (status & SerialSignal_CTS) {
2500 if ( debug_level >= DEBUG_LEVEL_ISR )
2501 printk("CTS tx start...");
2502 info->port.tty->hw_stopped = 0;
2503 tx_start(info);
2504 info->pending_bh |= BH_TRANSMIT;
2505 return;
2506 }
2507 } else {
2508 if (!(status & SerialSignal_CTS)) {
2509 if ( debug_level >= DEBUG_LEVEL_ISR )
2510 printk("CTS tx stop...");
2511 info->port.tty->hw_stopped = 1;
2512 tx_stop(info);
2513 }
2514 }
2515 }
2516 }
2517 }
2518
2519 info->pending_bh |= BH_STATUS;
2520}
2521
2522/* Interrupt service routine entry point.
2523 *
2524 * Arguments:
2525 * irq interrupt number that caused interrupt
2526 * dev_id device ID supplied during interrupt registration
2527 * regs interrupted processor context
2528 */
2529static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2530{
2531 SLMP_INFO *info = dev_id;
2532 unsigned char status, status0, status1=0;
2533 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2534 unsigned char timerstatus0, timerstatus1=0;
2535 unsigned char shift;
2536 unsigned int i;
2537 unsigned short tmp;
2538
2539 if ( debug_level >= DEBUG_LEVEL_ISR )
2540 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2541 __FILE__, __LINE__, info->irq_level);
2542
2543 spin_lock(&info->lock);
2544
2545 for(;;) {
2546
2547 /* get status for SCA0 (ports 0-1) */
2548 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2549 status0 = (unsigned char)tmp;
2550 dmastatus0 = (unsigned char)(tmp>>8);
2551 timerstatus0 = read_reg(info, ISR2);
2552
2553 if ( debug_level >= DEBUG_LEVEL_ISR )
2554 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2555 __FILE__, __LINE__, info->device_name,
2556 status0, dmastatus0, timerstatus0);
2557
2558 if (info->port_count == 4) {
2559 /* get status for SCA1 (ports 2-3) */
2560 tmp = read_reg16(info->port_array[2], ISR0);
2561 status1 = (unsigned char)tmp;
2562 dmastatus1 = (unsigned char)(tmp>>8);
2563 timerstatus1 = read_reg(info->port_array[2], ISR2);
2564
2565 if ( debug_level >= DEBUG_LEVEL_ISR )
2566 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2567 __FILE__,__LINE__,info->device_name,
2568 status1,dmastatus1,timerstatus1);
2569 }
2570
2571 if (!status0 && !dmastatus0 && !timerstatus0 &&
2572 !status1 && !dmastatus1 && !timerstatus1)
2573 break;
2574
2575 for(i=0; i < info->port_count ; i++) {
2576 if (info->port_array[i] == NULL)
2577 continue;
2578 if (i < 2) {
2579 status = status0;
2580 dmastatus = dmastatus0;
2581 } else {
2582 status = status1;
2583 dmastatus = dmastatus1;
2584 }
2585
2586 shift = i & 1 ? 4 :0;
2587
2588 if (status & BIT0 << shift)
2589 isr_rxrdy(info->port_array[i]);
2590 if (status & BIT1 << shift)
2591 isr_txrdy(info->port_array[i]);
2592 if (status & BIT2 << shift)
2593 isr_rxint(info->port_array[i]);
2594 if (status & BIT3 << shift)
2595 isr_txint(info->port_array[i]);
2596
2597 if (dmastatus & BIT0 << shift)
2598 isr_rxdmaerror(info->port_array[i]);
2599 if (dmastatus & BIT1 << shift)
2600 isr_rxdmaok(info->port_array[i]);
2601 if (dmastatus & BIT2 << shift)
2602 isr_txdmaerror(info->port_array[i]);
2603 if (dmastatus & BIT3 << shift)
2604 isr_txdmaok(info->port_array[i]);
2605 }
2606
2607 if (timerstatus0 & (BIT5 | BIT4))
2608 isr_timer(info->port_array[0]);
2609 if (timerstatus0 & (BIT7 | BIT6))
2610 isr_timer(info->port_array[1]);
2611 if (timerstatus1 & (BIT5 | BIT4))
2612 isr_timer(info->port_array[2]);
2613 if (timerstatus1 & (BIT7 | BIT6))
2614 isr_timer(info->port_array[3]);
2615 }
2616
2617 for(i=0; i < info->port_count ; i++) {
2618 SLMP_INFO * port = info->port_array[i];
2619
2620 /* Request bottom half processing if there's something
2621 * for it to do and the bh is not already running.
2622 *
2623 * Note: startup adapter diags require interrupts.
2624 * do not request bottom half processing if the
2625 * device is not open in a normal mode.
2626 */
2627 if ( port && (port->port.count || port->netcount) &&
2628 port->pending_bh && !port->bh_running &&
2629 !port->bh_requested ) {
2630 if ( debug_level >= DEBUG_LEVEL_ISR )
2631 printk("%s(%d):%s queueing bh task.\n",
2632 __FILE__,__LINE__,port->device_name);
2633 schedule_work(&port->task);
2634 port->bh_requested = true;
2635 }
2636 }
2637
2638 spin_unlock(&info->lock);
2639
2640 if ( debug_level >= DEBUG_LEVEL_ISR )
2641 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2642 __FILE__, __LINE__, info->irq_level);
2643 return IRQ_HANDLED;
2644}
2645
2646/* Initialize and start device.
2647 */
2648static int startup(SLMP_INFO * info)
2649{
2650 if ( debug_level >= DEBUG_LEVEL_INFO )
2651 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2652
2653 if (info->port.flags & ASYNC_INITIALIZED)
2654 return 0;
2655
2656 if (!info->tx_buf) {
2657 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2658 if (!info->tx_buf) {
2659 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2660 __FILE__,__LINE__,info->device_name);
2661 return -ENOMEM;
2662 }
2663 }
2664
2665 info->pending_bh = 0;
2666
2667 memset(&info->icount, 0, sizeof(info->icount));
2668
2669 /* program hardware for current parameters */
2670 reset_port(info);
2671
2672 change_params(info);
2673
2674 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2675
2676 if (info->port.tty)
2677 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2678
2679 info->port.flags |= ASYNC_INITIALIZED;
2680
2681 return 0;
2682}
2683
2684/* Called by close() and hangup() to shutdown hardware
2685 */
2686static void shutdown(SLMP_INFO * info)
2687{
2688 unsigned long flags;
2689
2690 if (!(info->port.flags & ASYNC_INITIALIZED))
2691 return;
2692
2693 if (debug_level >= DEBUG_LEVEL_INFO)
2694 printk("%s(%d):%s synclinkmp_shutdown()\n",
2695 __FILE__,__LINE__, info->device_name );
2696
2697 /* clear status wait queue because status changes */
2698 /* can't happen after shutting down the hardware */
2699 wake_up_interruptible(&info->status_event_wait_q);
2700 wake_up_interruptible(&info->event_wait_q);
2701
2702 del_timer(&info->tx_timer);
2703 del_timer(&info->status_timer);
2704
2705 kfree(info->tx_buf);
2706 info->tx_buf = NULL;
2707
2708 spin_lock_irqsave(&info->lock,flags);
2709
2710 reset_port(info);
2711
2712 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2713 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2714 set_signals(info);
2715 }
2716
2717 spin_unlock_irqrestore(&info->lock,flags);
2718
2719 if (info->port.tty)
2720 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2721
2722 info->port.flags &= ~ASYNC_INITIALIZED;
2723}
2724
2725static void program_hw(SLMP_INFO *info)
2726{
2727 unsigned long flags;
2728
2729 spin_lock_irqsave(&info->lock,flags);
2730
2731 rx_stop(info);
2732 tx_stop(info);
2733
2734 info->tx_count = info->tx_put = info->tx_get = 0;
2735
2736 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2737 hdlc_mode(info);
2738 else
2739 async_mode(info);
2740
2741 set_signals(info);
2742
2743 info->dcd_chkcount = 0;
2744 info->cts_chkcount = 0;
2745 info->ri_chkcount = 0;
2746 info->dsr_chkcount = 0;
2747
2748 info->ie1_value |= (CDCD|CCTS);
2749 write_reg(info, IE1, info->ie1_value);
2750
2751 get_signals(info);
2752
2753 if (info->netcount || (info->port.tty && info->port.tty->termios->c_cflag & CREAD) )
2754 rx_start(info);
2755
2756 spin_unlock_irqrestore(&info->lock,flags);
2757}
2758
2759/* Reconfigure adapter based on new parameters
2760 */
2761static void change_params(SLMP_INFO *info)
2762{
2763 unsigned cflag;
2764 int bits_per_char;
2765
2766 if (!info->port.tty || !info->port.tty->termios)
2767 return;
2768
2769 if (debug_level >= DEBUG_LEVEL_INFO)
2770 printk("%s(%d):%s change_params()\n",
2771 __FILE__,__LINE__, info->device_name );
2772
2773 cflag = info->port.tty->termios->c_cflag;
2774
2775 /* if B0 rate (hangup) specified then negate DTR and RTS */
2776 /* otherwise assert DTR and RTS */
2777 if (cflag & CBAUD)
2778 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2779 else
2780 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2781
2782 /* byte size and parity */
2783
2784 switch (cflag & CSIZE) {
2785 case CS5: info->params.data_bits = 5; break;
2786 case CS6: info->params.data_bits = 6; break;
2787 case CS7: info->params.data_bits = 7; break;
2788 case CS8: info->params.data_bits = 8; break;
2789 /* Never happens, but GCC is too dumb to figure it out */
2790 default: info->params.data_bits = 7; break;
2791 }
2792
2793 if (cflag & CSTOPB)
2794 info->params.stop_bits = 2;
2795 else
2796 info->params.stop_bits = 1;
2797
2798 info->params.parity = ASYNC_PARITY_NONE;
2799 if (cflag & PARENB) {
2800 if (cflag & PARODD)
2801 info->params.parity = ASYNC_PARITY_ODD;
2802 else
2803 info->params.parity = ASYNC_PARITY_EVEN;
2804#ifdef CMSPAR
2805 if (cflag & CMSPAR)
2806 info->params.parity = ASYNC_PARITY_SPACE;
2807#endif
2808 }
2809
2810 /* calculate number of jiffies to transmit a full
2811 * FIFO (32 bytes) at specified data rate
2812 */
2813 bits_per_char = info->params.data_bits +
2814 info->params.stop_bits + 1;
2815
2816 /* if port data rate is set to 460800 or less then
2817 * allow tty settings to override, otherwise keep the
2818 * current data rate.
2819 */
2820 if (info->params.data_rate <= 460800) {
2821 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2822 }
2823
2824 if ( info->params.data_rate ) {
2825 info->timeout = (32*HZ*bits_per_char) /
2826 info->params.data_rate;
2827 }
2828 info->timeout += HZ/50; /* Add .02 seconds of slop */
2829
2830 if (cflag & CRTSCTS)
2831 info->port.flags |= ASYNC_CTS_FLOW;
2832 else
2833 info->port.flags &= ~ASYNC_CTS_FLOW;
2834
2835 if (cflag & CLOCAL)
2836 info->port.flags &= ~ASYNC_CHECK_CD;
2837 else
2838 info->port.flags |= ASYNC_CHECK_CD;
2839
2840 /* process tty input control flags */
2841
2842 info->read_status_mask2 = OVRN;
2843 if (I_INPCK(info->port.tty))
2844 info->read_status_mask2 |= PE | FRME;
2845 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2846 info->read_status_mask1 |= BRKD;
2847 if (I_IGNPAR(info->port.tty))
2848 info->ignore_status_mask2 |= PE | FRME;
2849 if (I_IGNBRK(info->port.tty)) {
2850 info->ignore_status_mask1 |= BRKD;
2851 /* If ignoring parity and break indicators, ignore
2852 * overruns too. (For real raw support).
2853 */
2854 if (I_IGNPAR(info->port.tty))
2855 info->ignore_status_mask2 |= OVRN;
2856 }
2857
2858 program_hw(info);
2859}
2860
2861static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2862{
2863 int err;
2864
2865 if (debug_level >= DEBUG_LEVEL_INFO)
2866 printk("%s(%d):%s get_params()\n",
2867 __FILE__,__LINE__, info->device_name);
2868
2869 if (!user_icount) {
2870 memset(&info->icount, 0, sizeof(info->icount));
2871 } else {
2872 mutex_lock(&info->port.mutex);
2873 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2874 mutex_unlock(&info->port.mutex);
2875 if (err)
2876 return -EFAULT;
2877 }
2878
2879 return 0;
2880}
2881
2882static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2883{
2884 int err;
2885 if (debug_level >= DEBUG_LEVEL_INFO)
2886 printk("%s(%d):%s get_params()\n",
2887 __FILE__,__LINE__, info->device_name);
2888
2889 mutex_lock(&info->port.mutex);
2890 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2891 mutex_unlock(&info->port.mutex);
2892 if (err) {
2893 if ( debug_level >= DEBUG_LEVEL_INFO )
2894 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2895 __FILE__,__LINE__,info->device_name);
2896 return -EFAULT;
2897 }
2898
2899 return 0;
2900}
2901
2902static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2903{
2904 unsigned long flags;
2905 MGSL_PARAMS tmp_params;
2906 int err;
2907
2908 if (debug_level >= DEBUG_LEVEL_INFO)
2909 printk("%s(%d):%s set_params\n",
2910 __FILE__,__LINE__,info->device_name );
2911 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2912 if (err) {
2913 if ( debug_level >= DEBUG_LEVEL_INFO )
2914 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2915 __FILE__,__LINE__,info->device_name);
2916 return -EFAULT;
2917 }
2918
2919 mutex_lock(&info->port.mutex);
2920 spin_lock_irqsave(&info->lock,flags);
2921 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2922 spin_unlock_irqrestore(&info->lock,flags);
2923
2924 change_params(info);
2925 mutex_unlock(&info->port.mutex);
2926
2927 return 0;
2928}
2929
2930static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2931{
2932 int err;
2933
2934 if (debug_level >= DEBUG_LEVEL_INFO)
2935 printk("%s(%d):%s get_txidle()=%d\n",
2936 __FILE__,__LINE__, info->device_name, info->idle_mode);
2937
2938 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2939 if (err) {
2940 if ( debug_level >= DEBUG_LEVEL_INFO )
2941 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2942 __FILE__,__LINE__,info->device_name);
2943 return -EFAULT;
2944 }
2945
2946 return 0;
2947}
2948
2949static int set_txidle(SLMP_INFO * info, int idle_mode)
2950{
2951 unsigned long flags;
2952
2953 if (debug_level >= DEBUG_LEVEL_INFO)
2954 printk("%s(%d):%s set_txidle(%d)\n",
2955 __FILE__,__LINE__,info->device_name, idle_mode );
2956
2957 spin_lock_irqsave(&info->lock,flags);
2958 info->idle_mode = idle_mode;
2959 tx_set_idle( info );
2960 spin_unlock_irqrestore(&info->lock,flags);
2961 return 0;
2962}
2963
2964static int tx_enable(SLMP_INFO * info, int enable)
2965{
2966 unsigned long flags;
2967
2968 if (debug_level >= DEBUG_LEVEL_INFO)
2969 printk("%s(%d):%s tx_enable(%d)\n",
2970 __FILE__,__LINE__,info->device_name, enable);
2971
2972 spin_lock_irqsave(&info->lock,flags);
2973 if ( enable ) {
2974 if ( !info->tx_enabled ) {
2975 tx_start(info);
2976 }
2977 } else {
2978 if ( info->tx_enabled )
2979 tx_stop(info);
2980 }
2981 spin_unlock_irqrestore(&info->lock,flags);
2982 return 0;
2983}
2984
2985/* abort send HDLC frame
2986 */
2987static int tx_abort(SLMP_INFO * info)
2988{
2989 unsigned long flags;
2990
2991 if (debug_level >= DEBUG_LEVEL_INFO)
2992 printk("%s(%d):%s tx_abort()\n",
2993 __FILE__,__LINE__,info->device_name);
2994
2995 spin_lock_irqsave(&info->lock,flags);
2996 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2997 info->ie1_value &= ~UDRN;
2998 info->ie1_value |= IDLE;
2999 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3000 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3001
3002 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3003 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3004
3005 write_reg(info, CMD, TXABORT);
3006 }
3007 spin_unlock_irqrestore(&info->lock,flags);
3008 return 0;
3009}
3010
3011static int rx_enable(SLMP_INFO * info, int enable)
3012{
3013 unsigned long flags;
3014
3015 if (debug_level >= DEBUG_LEVEL_INFO)
3016 printk("%s(%d):%s rx_enable(%d)\n",
3017 __FILE__,__LINE__,info->device_name,enable);
3018
3019 spin_lock_irqsave(&info->lock,flags);
3020 if ( enable ) {
3021 if ( !info->rx_enabled )
3022 rx_start(info);
3023 } else {
3024 if ( info->rx_enabled )
3025 rx_stop(info);
3026 }
3027 spin_unlock_irqrestore(&info->lock,flags);
3028 return 0;
3029}
3030
3031/* wait for specified event to occur
3032 */
3033static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3034{
3035 unsigned long flags;
3036 int s;
3037 int rc=0;
3038 struct mgsl_icount cprev, cnow;
3039 int events;
3040 int mask;
3041 struct _input_signal_events oldsigs, newsigs;
3042 DECLARE_WAITQUEUE(wait, current);
3043
3044 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3045 if (rc) {
3046 return -EFAULT;
3047 }
3048
3049 if (debug_level >= DEBUG_LEVEL_INFO)
3050 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3051 __FILE__,__LINE__,info->device_name,mask);
3052
3053 spin_lock_irqsave(&info->lock,flags);
3054
3055 /* return immediately if state matches requested events */
3056 get_signals(info);
3057 s = info->serial_signals;
3058
3059 events = mask &
3060 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3061 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3062 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3063 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3064 if (events) {
3065 spin_unlock_irqrestore(&info->lock,flags);
3066 goto exit;
3067 }
3068
3069 /* save current irq counts */
3070 cprev = info->icount;
3071 oldsigs = info->input_signal_events;
3072
3073 /* enable hunt and idle irqs if needed */
3074 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3075 unsigned char oldval = info->ie1_value;
3076 unsigned char newval = oldval +
3077 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3078 (mask & MgslEvent_IdleReceived ? IDLD:0);
3079 if ( oldval != newval ) {
3080 info->ie1_value = newval;
3081 write_reg(info, IE1, info->ie1_value);
3082 }
3083 }
3084
3085 set_current_state(TASK_INTERRUPTIBLE);
3086 add_wait_queue(&info->event_wait_q, &wait);
3087
3088 spin_unlock_irqrestore(&info->lock,flags);
3089
3090 for(;;) {
3091 schedule();
3092 if (signal_pending(current)) {
3093 rc = -ERESTARTSYS;
3094 break;
3095 }
3096
3097 /* get current irq counts */
3098 spin_lock_irqsave(&info->lock,flags);
3099 cnow = info->icount;
3100 newsigs = info->input_signal_events;
3101 set_current_state(TASK_INTERRUPTIBLE);
3102 spin_unlock_irqrestore(&info->lock,flags);
3103
3104 /* if no change, wait aborted for some reason */
3105 if (newsigs.dsr_up == oldsigs.dsr_up &&
3106 newsigs.dsr_down == oldsigs.dsr_down &&
3107 newsigs.dcd_up == oldsigs.dcd_up &&
3108 newsigs.dcd_down == oldsigs.dcd_down &&
3109 newsigs.cts_up == oldsigs.cts_up &&
3110 newsigs.cts_down == oldsigs.cts_down &&
3111 newsigs.ri_up == oldsigs.ri_up &&
3112 newsigs.ri_down == oldsigs.ri_down &&
3113 cnow.exithunt == cprev.exithunt &&
3114 cnow.rxidle == cprev.rxidle) {
3115 rc = -EIO;
3116 break;
3117 }
3118
3119 events = mask &
3120 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3121 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3122 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3123 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3124 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3125 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3126 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3127 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3128 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3129 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3130 if (events)
3131 break;
3132
3133 cprev = cnow;
3134 oldsigs = newsigs;
3135 }
3136
3137 remove_wait_queue(&info->event_wait_q, &wait);
3138 set_current_state(TASK_RUNNING);
3139
3140
3141 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3142 spin_lock_irqsave(&info->lock,flags);
3143 if (!waitqueue_active(&info->event_wait_q)) {
3144 /* disable enable exit hunt mode/idle rcvd IRQs */
3145 info->ie1_value &= ~(FLGD|IDLD);
3146 write_reg(info, IE1, info->ie1_value);
3147 }
3148 spin_unlock_irqrestore(&info->lock,flags);
3149 }
3150exit:
3151 if ( rc == 0 )
3152 PUT_USER(rc, events, mask_ptr);
3153
3154 return rc;
3155}
3156
3157static int modem_input_wait(SLMP_INFO *info,int arg)
3158{
3159 unsigned long flags;
3160 int rc;
3161 struct mgsl_icount cprev, cnow;
3162 DECLARE_WAITQUEUE(wait, current);
3163
3164 /* save current irq counts */
3165 spin_lock_irqsave(&info->lock,flags);
3166 cprev = info->icount;
3167 add_wait_queue(&info->status_event_wait_q, &wait);
3168 set_current_state(TASK_INTERRUPTIBLE);
3169 spin_unlock_irqrestore(&info->lock,flags);
3170
3171 for(;;) {
3172 schedule();
3173 if (signal_pending(current)) {
3174 rc = -ERESTARTSYS;
3175 break;
3176 }
3177
3178 /* get new irq counts */
3179 spin_lock_irqsave(&info->lock,flags);
3180 cnow = info->icount;
3181 set_current_state(TASK_INTERRUPTIBLE);
3182 spin_unlock_irqrestore(&info->lock,flags);
3183
3184 /* if no change, wait aborted for some reason */
3185 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3186 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3187 rc = -EIO;
3188 break;
3189 }
3190
3191 /* check for change in caller specified modem input */
3192 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3193 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3194 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3195 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3196 rc = 0;
3197 break;
3198 }
3199
3200 cprev = cnow;
3201 }
3202 remove_wait_queue(&info->status_event_wait_q, &wait);
3203 set_current_state(TASK_RUNNING);
3204 return rc;
3205}
3206
3207/* return the state of the serial control and status signals
3208 */
3209static int tiocmget(struct tty_struct *tty)
3210{
3211 SLMP_INFO *info = tty->driver_data;
3212 unsigned int result;
3213 unsigned long flags;
3214
3215 spin_lock_irqsave(&info->lock,flags);
3216 get_signals(info);
3217 spin_unlock_irqrestore(&info->lock,flags);
3218
3219 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3220 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3221 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3222 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3223 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3224 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3225
3226 if (debug_level >= DEBUG_LEVEL_INFO)
3227 printk("%s(%d):%s tiocmget() value=%08X\n",
3228 __FILE__,__LINE__, info->device_name, result );
3229 return result;
3230}
3231
3232/* set modem control signals (DTR/RTS)
3233 */
3234static int tiocmset(struct tty_struct *tty,
3235 unsigned int set, unsigned int clear)
3236{
3237 SLMP_INFO *info = tty->driver_data;
3238 unsigned long flags;
3239
3240 if (debug_level >= DEBUG_LEVEL_INFO)
3241 printk("%s(%d):%s tiocmset(%x,%x)\n",
3242 __FILE__,__LINE__,info->device_name, set, clear);
3243
3244 if (set & TIOCM_RTS)
3245 info->serial_signals |= SerialSignal_RTS;
3246 if (set & TIOCM_DTR)
3247 info->serial_signals |= SerialSignal_DTR;
3248 if (clear & TIOCM_RTS)
3249 info->serial_signals &= ~SerialSignal_RTS;
3250 if (clear & TIOCM_DTR)
3251 info->serial_signals &= ~SerialSignal_DTR;
3252
3253 spin_lock_irqsave(&info->lock,flags);
3254 set_signals(info);
3255 spin_unlock_irqrestore(&info->lock,flags);
3256
3257 return 0;
3258}
3259
3260static int carrier_raised(struct tty_port *port)
3261{
3262 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3263 unsigned long flags;
3264
3265 spin_lock_irqsave(&info->lock,flags);
3266 get_signals(info);
3267 spin_unlock_irqrestore(&info->lock,flags);
3268
3269 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3270}
3271
3272static void dtr_rts(struct tty_port *port, int on)
3273{
3274 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3275 unsigned long flags;
3276
3277 spin_lock_irqsave(&info->lock,flags);
3278 if (on)
3279 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3280 else
3281 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3282 set_signals(info);
3283 spin_unlock_irqrestore(&info->lock,flags);
3284}
3285
3286/* Block the current process until the specified port is ready to open.
3287 */
3288static int block_til_ready(struct tty_struct *tty, struct file *filp,
3289 SLMP_INFO *info)
3290{
3291 DECLARE_WAITQUEUE(wait, current);
3292 int retval;
3293 bool do_clocal = false;
3294 bool extra_count = false;
3295 unsigned long flags;
3296 int cd;
3297 struct tty_port *port = &info->port;
3298
3299 if (debug_level >= DEBUG_LEVEL_INFO)
3300 printk("%s(%d):%s block_til_ready()\n",
3301 __FILE__,__LINE__, tty->driver->name );
3302
3303 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3304 /* nonblock mode is set or port is not enabled */
3305 /* just verify that callout device is not active */
3306 port->flags |= ASYNC_NORMAL_ACTIVE;
3307 return 0;
3308 }
3309
3310 if (tty->termios->c_cflag & CLOCAL)
3311 do_clocal = true;
3312
3313 /* Wait for carrier detect and the line to become
3314 * free (i.e., not in use by the callout). While we are in
3315 * this loop, port->count is dropped by one, so that
3316 * close() knows when to free things. We restore it upon
3317 * exit, either normal or abnormal.
3318 */
3319
3320 retval = 0;
3321 add_wait_queue(&port->open_wait, &wait);
3322
3323 if (debug_level >= DEBUG_LEVEL_INFO)
3324 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3325 __FILE__,__LINE__, tty->driver->name, port->count );
3326
3327 spin_lock_irqsave(&info->lock, flags);
3328 if (!tty_hung_up_p(filp)) {
3329 extra_count = true;
3330 port->count--;
3331 }
3332 spin_unlock_irqrestore(&info->lock, flags);
3333 port->blocked_open++;
3334
3335 while (1) {
3336 if (tty->termios->c_cflag & CBAUD)
3337 tty_port_raise_dtr_rts(port);
3338
3339 set_current_state(TASK_INTERRUPTIBLE);
3340
3341 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3342 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3343 -EAGAIN : -ERESTARTSYS;
3344 break;
3345 }
3346
3347 cd = tty_port_carrier_raised(port);
3348
3349 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd))
3350 break;
3351
3352 if (signal_pending(current)) {
3353 retval = -ERESTARTSYS;
3354 break;
3355 }
3356
3357 if (debug_level >= DEBUG_LEVEL_INFO)
3358 printk("%s(%d):%s block_til_ready() count=%d\n",
3359 __FILE__,__LINE__, tty->driver->name, port->count );
3360
3361 tty_unlock();
3362 schedule();
3363 tty_lock();
3364 }
3365
3366 set_current_state(TASK_RUNNING);
3367 remove_wait_queue(&port->open_wait, &wait);
3368
3369 if (extra_count)
3370 port->count++;
3371 port->blocked_open--;
3372
3373 if (debug_level >= DEBUG_LEVEL_INFO)
3374 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3375 __FILE__,__LINE__, tty->driver->name, port->count );
3376
3377 if (!retval)
3378 port->flags |= ASYNC_NORMAL_ACTIVE;
3379
3380 return retval;
3381}
3382
3383static int alloc_dma_bufs(SLMP_INFO *info)
3384{
3385 unsigned short BuffersPerFrame;
3386 unsigned short BufferCount;
3387
3388 // Force allocation to start at 64K boundary for each port.
3389 // This is necessary because *all* buffer descriptors for a port
3390 // *must* be in the same 64K block. All descriptors on a port
3391 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3392 // into the CBP register.
3393 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3394
3395 /* Calculate the number of DMA buffers necessary to hold the */
3396 /* largest allowable frame size. Note: If the max frame size is */
3397 /* not an even multiple of the DMA buffer size then we need to */
3398 /* round the buffer count per frame up one. */
3399
3400 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3401 if ( info->max_frame_size % SCABUFSIZE )
3402 BuffersPerFrame++;
3403
3404 /* calculate total number of data buffers (SCABUFSIZE) possible
3405 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3406 * for the descriptor list (BUFFERLISTSIZE).
3407 */
3408 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3409
3410 /* limit number of buffers to maximum amount of descriptors */
3411 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3412 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3413
3414 /* use enough buffers to transmit one max size frame */
3415 info->tx_buf_count = BuffersPerFrame + 1;
3416
3417 /* never use more than half the available buffers for transmit */
3418 if (info->tx_buf_count > (BufferCount/2))
3419 info->tx_buf_count = BufferCount/2;
3420
3421 if (info->tx_buf_count > SCAMAXDESC)
3422 info->tx_buf_count = SCAMAXDESC;
3423
3424 /* use remaining buffers for receive */
3425 info->rx_buf_count = BufferCount - info->tx_buf_count;
3426
3427 if (info->rx_buf_count > SCAMAXDESC)
3428 info->rx_buf_count = SCAMAXDESC;
3429
3430 if ( debug_level >= DEBUG_LEVEL_INFO )
3431 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3432 __FILE__,__LINE__, info->device_name,
3433 info->tx_buf_count,info->rx_buf_count);
3434
3435 if ( alloc_buf_list( info ) < 0 ||
3436 alloc_frame_bufs(info,
3437 info->rx_buf_list,
3438 info->rx_buf_list_ex,
3439 info->rx_buf_count) < 0 ||
3440 alloc_frame_bufs(info,
3441 info->tx_buf_list,
3442 info->tx_buf_list_ex,
3443 info->tx_buf_count) < 0 ||
3444 alloc_tmp_rx_buf(info) < 0 ) {
3445 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3446 __FILE__,__LINE__, info->device_name);
3447 return -ENOMEM;
3448 }
3449
3450 rx_reset_buffers( info );
3451
3452 return 0;
3453}
3454
3455/* Allocate DMA buffers for the transmit and receive descriptor lists.
3456 */
3457static int alloc_buf_list(SLMP_INFO *info)
3458{
3459 unsigned int i;
3460
3461 /* build list in adapter shared memory */
3462 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3463 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3464 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3465
3466 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3467
3468 /* Save virtual address pointers to the receive and */
3469 /* transmit buffer lists. (Receive 1st). These pointers will */
3470 /* be used by the processor to access the lists. */
3471 info->rx_buf_list = (SCADESC *)info->buffer_list;
3472
3473 info->tx_buf_list = (SCADESC *)info->buffer_list;
3474 info->tx_buf_list += info->rx_buf_count;
3475
3476 /* Build links for circular buffer entry lists (tx and rx)
3477 *
3478 * Note: links are physical addresses read by the SCA device
3479 * to determine the next buffer entry to use.
3480 */
3481
3482 for ( i = 0; i < info->rx_buf_count; i++ ) {
3483 /* calculate and store physical address of this buffer entry */
3484 info->rx_buf_list_ex[i].phys_entry =
3485 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3486
3487 /* calculate and store physical address of */
3488 /* next entry in cirular list of entries */
3489 info->rx_buf_list[i].next = info->buffer_list_phys;
3490 if ( i < info->rx_buf_count - 1 )
3491 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3492
3493 info->rx_buf_list[i].length = SCABUFSIZE;
3494 }
3495
3496 for ( i = 0; i < info->tx_buf_count; i++ ) {
3497 /* calculate and store physical address of this buffer entry */
3498 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3499 ((info->rx_buf_count + i) * sizeof(SCADESC));
3500
3501 /* calculate and store physical address of */
3502 /* next entry in cirular list of entries */
3503
3504 info->tx_buf_list[i].next = info->buffer_list_phys +
3505 info->rx_buf_count * sizeof(SCADESC);
3506
3507 if ( i < info->tx_buf_count - 1 )
3508 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3509 }
3510
3511 return 0;
3512}
3513
3514/* Allocate the frame DMA buffers used by the specified buffer list.
3515 */
3516static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3517{
3518 int i;
3519 unsigned long phys_addr;
3520
3521 for ( i = 0; i < count; i++ ) {
3522 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3523 phys_addr = info->port_array[0]->last_mem_alloc;
3524 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3525
3526 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3527 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3528 }
3529
3530 return 0;
3531}
3532
3533static void free_dma_bufs(SLMP_INFO *info)
3534{
3535 info->buffer_list = NULL;
3536 info->rx_buf_list = NULL;
3537 info->tx_buf_list = NULL;
3538}
3539
3540/* allocate buffer large enough to hold max_frame_size.
3541 * This buffer is used to pass an assembled frame to the line discipline.
3542 */
3543static int alloc_tmp_rx_buf(SLMP_INFO *info)
3544{
3545 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3546 if (info->tmp_rx_buf == NULL)
3547 return -ENOMEM;
3548 return 0;
3549}
3550
3551static void free_tmp_rx_buf(SLMP_INFO *info)
3552{
3553 kfree(info->tmp_rx_buf);
3554 info->tmp_rx_buf = NULL;
3555}
3556
3557static int claim_resources(SLMP_INFO *info)
3558{
3559 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3560 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3561 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3562 info->init_error = DiagStatus_AddressConflict;
3563 goto errout;
3564 }
3565 else
3566 info->shared_mem_requested = true;
3567
3568 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3569 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3570 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3571 info->init_error = DiagStatus_AddressConflict;
3572 goto errout;
3573 }
3574 else
3575 info->lcr_mem_requested = true;
3576
3577 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3578 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3579 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3580 info->init_error = DiagStatus_AddressConflict;
3581 goto errout;
3582 }
3583 else
3584 info->sca_base_requested = true;
3585
3586 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3587 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3588 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3589 info->init_error = DiagStatus_AddressConflict;
3590 goto errout;
3591 }
3592 else
3593 info->sca_statctrl_requested = true;
3594
3595 info->memory_base = ioremap_nocache(info->phys_memory_base,
3596 SCA_MEM_SIZE);
3597 if (!info->memory_base) {
3598 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3599 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3600 info->init_error = DiagStatus_CantAssignPciResources;
3601 goto errout;
3602 }
3603
3604 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3605 if (!info->lcr_base) {
3606 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3607 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3608 info->init_error = DiagStatus_CantAssignPciResources;
3609 goto errout;
3610 }
3611 info->lcr_base += info->lcr_offset;
3612
3613 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3614 if (!info->sca_base) {
3615 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3616 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3617 info->init_error = DiagStatus_CantAssignPciResources;
3618 goto errout;
3619 }
3620 info->sca_base += info->sca_offset;
3621
3622 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3623 PAGE_SIZE);
3624 if (!info->statctrl_base) {
3625 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3626 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3627 info->init_error = DiagStatus_CantAssignPciResources;
3628 goto errout;
3629 }
3630 info->statctrl_base += info->statctrl_offset;
3631
3632 if ( !memory_test(info) ) {
3633 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3634 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3635 info->init_error = DiagStatus_MemoryError;
3636 goto errout;
3637 }
3638
3639 return 0;
3640
3641errout:
3642 release_resources( info );
3643 return -ENODEV;
3644}
3645
3646static void release_resources(SLMP_INFO *info)
3647{
3648 if ( debug_level >= DEBUG_LEVEL_INFO )
3649 printk( "%s(%d):%s release_resources() entry\n",
3650 __FILE__,__LINE__,info->device_name );
3651
3652 if ( info->irq_requested ) {
3653 free_irq(info->irq_level, info);
3654 info->irq_requested = false;
3655 }
3656
3657 if ( info->shared_mem_requested ) {
3658 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3659 info->shared_mem_requested = false;
3660 }
3661 if ( info->lcr_mem_requested ) {
3662 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3663 info->lcr_mem_requested = false;
3664 }
3665 if ( info->sca_base_requested ) {
3666 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3667 info->sca_base_requested = false;
3668 }
3669 if ( info->sca_statctrl_requested ) {
3670 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3671 info->sca_statctrl_requested = false;
3672 }
3673
3674 if (info->memory_base){
3675 iounmap(info->memory_base);
3676 info->memory_base = NULL;
3677 }
3678
3679 if (info->sca_base) {
3680 iounmap(info->sca_base - info->sca_offset);
3681 info->sca_base=NULL;
3682 }
3683
3684 if (info->statctrl_base) {
3685 iounmap(info->statctrl_base - info->statctrl_offset);
3686 info->statctrl_base=NULL;
3687 }
3688
3689 if (info->lcr_base){
3690 iounmap(info->lcr_base - info->lcr_offset);
3691 info->lcr_base = NULL;
3692 }
3693
3694 if ( debug_level >= DEBUG_LEVEL_INFO )
3695 printk( "%s(%d):%s release_resources() exit\n",
3696 __FILE__,__LINE__,info->device_name );
3697}
3698
3699/* Add the specified device instance data structure to the
3700 * global linked list of devices and increment the device count.
3701 */
3702static void add_device(SLMP_INFO *info)
3703{
3704 info->next_device = NULL;
3705 info->line = synclinkmp_device_count;
3706 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3707
3708 if (info->line < MAX_DEVICES) {
3709 if (maxframe[info->line])
3710 info->max_frame_size = maxframe[info->line];
3711 }
3712
3713 synclinkmp_device_count++;
3714
3715 if ( !synclinkmp_device_list )
3716 synclinkmp_device_list = info;
3717 else {
3718 SLMP_INFO *current_dev = synclinkmp_device_list;
3719 while( current_dev->next_device )
3720 current_dev = current_dev->next_device;
3721 current_dev->next_device = info;
3722 }
3723
3724 if ( info->max_frame_size < 4096 )
3725 info->max_frame_size = 4096;
3726 else if ( info->max_frame_size > 65535 )
3727 info->max_frame_size = 65535;
3728
3729 printk( "SyncLink MultiPort %s: "
3730 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3731 info->device_name,
3732 info->phys_sca_base,
3733 info->phys_memory_base,
3734 info->phys_statctrl_base,
3735 info->phys_lcr_base,
3736 info->irq_level,
3737 info->max_frame_size );
3738
3739#if SYNCLINK_GENERIC_HDLC
3740 hdlcdev_init(info);
3741#endif
3742}
3743
3744static const struct tty_port_operations port_ops = {
3745 .carrier_raised = carrier_raised,
3746 .dtr_rts = dtr_rts,
3747};
3748
3749/* Allocate and initialize a device instance structure
3750 *
3751 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3752 */
3753static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3754{
3755 SLMP_INFO *info;
3756
3757 info = kzalloc(sizeof(SLMP_INFO),
3758 GFP_KERNEL);
3759
3760 if (!info) {
3761 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3762 __FILE__,__LINE__, adapter_num, port_num);
3763 } else {
3764 tty_port_init(&info->port);
3765 info->port.ops = &port_ops;
3766 info->magic = MGSL_MAGIC;
3767 INIT_WORK(&info->task, bh_handler);
3768 info->max_frame_size = 4096;
3769 info->port.close_delay = 5*HZ/10;
3770 info->port.closing_wait = 30*HZ;
3771 init_waitqueue_head(&info->status_event_wait_q);
3772 init_waitqueue_head(&info->event_wait_q);
3773 spin_lock_init(&info->netlock);
3774 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3775 info->idle_mode = HDLC_TXIDLE_FLAGS;
3776 info->adapter_num = adapter_num;
3777 info->port_num = port_num;
3778
3779 /* Copy configuration info to device instance data */
3780 info->irq_level = pdev->irq;
3781 info->phys_lcr_base = pci_resource_start(pdev,0);
3782 info->phys_sca_base = pci_resource_start(pdev,2);
3783 info->phys_memory_base = pci_resource_start(pdev,3);
3784 info->phys_statctrl_base = pci_resource_start(pdev,4);
3785
3786 /* Because veremap only works on page boundaries we must map
3787 * a larger area than is actually implemented for the LCR
3788 * memory range. We map a full page starting at the page boundary.
3789 */
3790 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3791 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3792
3793 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3794 info->phys_sca_base &= ~(PAGE_SIZE-1);
3795
3796 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3797 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3798
3799 info->bus_type = MGSL_BUS_TYPE_PCI;
3800 info->irq_flags = IRQF_SHARED;
3801
3802 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3803 setup_timer(&info->status_timer, status_timeout,
3804 (unsigned long)info);
3805
3806 /* Store the PCI9050 misc control register value because a flaw
3807 * in the PCI9050 prevents LCR registers from being read if
3808 * BIOS assigns an LCR base address with bit 7 set.
3809 *
3810 * Only the misc control register is accessed for which only
3811 * write access is needed, so set an initial value and change
3812 * bits to the device instance data as we write the value
3813 * to the actual misc control register.
3814 */
3815 info->misc_ctrl_value = 0x087e4546;
3816
3817 /* initial port state is unknown - if startup errors
3818 * occur, init_error will be set to indicate the
3819 * problem. Once the port is fully initialized,
3820 * this value will be set to 0 to indicate the
3821 * port is available.
3822 */
3823 info->init_error = -1;
3824 }
3825
3826 return info;
3827}
3828
3829static void device_init(int adapter_num, struct pci_dev *pdev)
3830{
3831 SLMP_INFO *port_array[SCA_MAX_PORTS];
3832 int port;
3833
3834 /* allocate device instances for up to SCA_MAX_PORTS devices */
3835 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3836 port_array[port] = alloc_dev(adapter_num,port,pdev);
3837 if( port_array[port] == NULL ) {
3838 for ( --port; port >= 0; --port )
3839 kfree(port_array[port]);
3840 return;
3841 }
3842 }
3843
3844 /* give copy of port_array to all ports and add to device list */
3845 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3846 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3847 add_device( port_array[port] );
3848 spin_lock_init(&port_array[port]->lock);
3849 }
3850
3851 /* Allocate and claim adapter resources */
3852 if ( !claim_resources(port_array[0]) ) {
3853
3854 alloc_dma_bufs(port_array[0]);
3855
3856 /* copy resource information from first port to others */
3857 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3858 port_array[port]->lock = port_array[0]->lock;
3859 port_array[port]->irq_level = port_array[0]->irq_level;
3860 port_array[port]->memory_base = port_array[0]->memory_base;
3861 port_array[port]->sca_base = port_array[0]->sca_base;
3862 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3863 port_array[port]->lcr_base = port_array[0]->lcr_base;
3864 alloc_dma_bufs(port_array[port]);
3865 }
3866
3867 if ( request_irq(port_array[0]->irq_level,
3868 synclinkmp_interrupt,
3869 port_array[0]->irq_flags,
3870 port_array[0]->device_name,
3871 port_array[0]) < 0 ) {
3872 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3873 __FILE__,__LINE__,
3874 port_array[0]->device_name,
3875 port_array[0]->irq_level );
3876 }
3877 else {
3878 port_array[0]->irq_requested = true;
3879 adapter_test(port_array[0]);
3880 }
3881 }
3882}
3883
3884static const struct tty_operations ops = {
3885 .open = open,
3886 .close = close,
3887 .write = write,
3888 .put_char = put_char,
3889 .flush_chars = flush_chars,
3890 .write_room = write_room,
3891 .chars_in_buffer = chars_in_buffer,
3892 .flush_buffer = flush_buffer,
3893 .ioctl = ioctl,
3894 .throttle = throttle,
3895 .unthrottle = unthrottle,
3896 .send_xchar = send_xchar,
3897 .break_ctl = set_break,
3898 .wait_until_sent = wait_until_sent,
3899 .set_termios = set_termios,
3900 .stop = tx_hold,
3901 .start = tx_release,
3902 .hangup = hangup,
3903 .tiocmget = tiocmget,
3904 .tiocmset = tiocmset,
3905 .get_icount = get_icount,
3906 .proc_fops = &synclinkmp_proc_fops,
3907};
3908
3909
3910static void synclinkmp_cleanup(void)
3911{
3912 int rc;
3913 SLMP_INFO *info;
3914 SLMP_INFO *tmp;
3915
3916 printk("Unloading %s %s\n", driver_name, driver_version);
3917
3918 if (serial_driver) {
3919 if ((rc = tty_unregister_driver(serial_driver)))
3920 printk("%s(%d) failed to unregister tty driver err=%d\n",
3921 __FILE__,__LINE__,rc);
3922 put_tty_driver(serial_driver);
3923 }
3924
3925 /* reset devices */
3926 info = synclinkmp_device_list;
3927 while(info) {
3928 reset_port(info);
3929 info = info->next_device;
3930 }
3931
3932 /* release devices */
3933 info = synclinkmp_device_list;
3934 while(info) {
3935#if SYNCLINK_GENERIC_HDLC
3936 hdlcdev_exit(info);
3937#endif
3938 free_dma_bufs(info);
3939 free_tmp_rx_buf(info);
3940 if ( info->port_num == 0 ) {
3941 if (info->sca_base)
3942 write_reg(info, LPR, 1); /* set low power mode */
3943 release_resources(info);
3944 }
3945 tmp = info;
3946 info = info->next_device;
3947 kfree(tmp);
3948 }
3949
3950 pci_unregister_driver(&synclinkmp_pci_driver);
3951}
3952
3953/* Driver initialization entry point.
3954 */
3955
3956static int __init synclinkmp_init(void)
3957{
3958 int rc;
3959
3960 if (break_on_load) {
3961 synclinkmp_get_text_ptr();
3962 BREAKPOINT();
3963 }
3964
3965 printk("%s %s\n", driver_name, driver_version);
3966
3967 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3968 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3969 return rc;
3970 }
3971
3972 serial_driver = alloc_tty_driver(128);
3973 if (!serial_driver) {
3974 rc = -ENOMEM;
3975 goto error;
3976 }
3977
3978 /* Initialize the tty_driver structure */
3979
3980 serial_driver->owner = THIS_MODULE;
3981 serial_driver->driver_name = "synclinkmp";
3982 serial_driver->name = "ttySLM";
3983 serial_driver->major = ttymajor;
3984 serial_driver->minor_start = 64;
3985 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3986 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3987 serial_driver->init_termios = tty_std_termios;
3988 serial_driver->init_termios.c_cflag =
3989 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3990 serial_driver->init_termios.c_ispeed = 9600;
3991 serial_driver->init_termios.c_ospeed = 9600;
3992 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3993 tty_set_operations(serial_driver, &ops);
3994 if ((rc = tty_register_driver(serial_driver)) < 0) {
3995 printk("%s(%d):Couldn't register serial driver\n",
3996 __FILE__,__LINE__);
3997 put_tty_driver(serial_driver);
3998 serial_driver = NULL;
3999 goto error;
4000 }
4001
4002 printk("%s %s, tty major#%d\n",
4003 driver_name, driver_version,
4004 serial_driver->major);
4005
4006 return 0;
4007
4008error:
4009 synclinkmp_cleanup();
4010 return rc;
4011}
4012
4013static void __exit synclinkmp_exit(void)
4014{
4015 synclinkmp_cleanup();
4016}
4017
4018module_init(synclinkmp_init);
4019module_exit(synclinkmp_exit);
4020
4021/* Set the port for internal loopback mode.
4022 * The TxCLK and RxCLK signals are generated from the BRG and
4023 * the TxD is looped back to the RxD internally.
4024 */
4025static void enable_loopback(SLMP_INFO *info, int enable)
4026{
4027 if (enable) {
4028 /* MD2 (Mode Register 2)
4029 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4030 */
4031 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4032
4033 /* degate external TxC clock source */
4034 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4035 write_control_reg(info);
4036
4037 /* RXS/TXS (Rx/Tx clock source)
4038 * 07 Reserved, must be 0
4039 * 06..04 Clock Source, 100=BRG
4040 * 03..00 Clock Divisor, 0000=1
4041 */
4042 write_reg(info, RXS, 0x40);
4043 write_reg(info, TXS, 0x40);
4044
4045 } else {
4046 /* MD2 (Mode Register 2)
4047 * 01..00 CNCT<1..0> Channel connection, 0=normal
4048 */
4049 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4050
4051 /* RXS/TXS (Rx/Tx clock source)
4052 * 07 Reserved, must be 0
4053 * 06..04 Clock Source, 000=RxC/TxC Pin
4054 * 03..00 Clock Divisor, 0000=1
4055 */
4056 write_reg(info, RXS, 0x00);
4057 write_reg(info, TXS, 0x00);
4058 }
4059
4060 /* set LinkSpeed if available, otherwise default to 2Mbps */
4061 if (info->params.clock_speed)
4062 set_rate(info, info->params.clock_speed);
4063 else
4064 set_rate(info, 3686400);
4065}
4066
4067/* Set the baud rate register to the desired speed
4068 *
4069 * data_rate data rate of clock in bits per second
4070 * A data rate of 0 disables the AUX clock.
4071 */
4072static void set_rate( SLMP_INFO *info, u32 data_rate )
4073{
4074 u32 TMCValue;
4075 unsigned char BRValue;
4076 u32 Divisor=0;
4077
4078 /* fBRG = fCLK/(TMC * 2^BR)
4079 */
4080 if (data_rate != 0) {
4081 Divisor = 14745600/data_rate;
4082 if (!Divisor)
4083 Divisor = 1;
4084
4085 TMCValue = Divisor;
4086
4087 BRValue = 0;
4088 if (TMCValue != 1 && TMCValue != 2) {
4089 /* BRValue of 0 provides 50/50 duty cycle *only* when
4090 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4091 * 50/50 duty cycle.
4092 */
4093 BRValue = 1;
4094 TMCValue >>= 1;
4095 }
4096
4097 /* while TMCValue is too big for TMC register, divide
4098 * by 2 and increment BR exponent.
4099 */
4100 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4101 TMCValue >>= 1;
4102
4103 write_reg(info, TXS,
4104 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4105 write_reg(info, RXS,
4106 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4107 write_reg(info, TMC, (unsigned char)TMCValue);
4108 }
4109 else {
4110 write_reg(info, TXS,0);
4111 write_reg(info, RXS,0);
4112 write_reg(info, TMC, 0);
4113 }
4114}
4115
4116/* Disable receiver
4117 */
4118static void rx_stop(SLMP_INFO *info)
4119{
4120 if (debug_level >= DEBUG_LEVEL_ISR)
4121 printk("%s(%d):%s rx_stop()\n",
4122 __FILE__,__LINE__, info->device_name );
4123
4124 write_reg(info, CMD, RXRESET);
4125
4126 info->ie0_value &= ~RXRDYE;
4127 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4128
4129 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4130 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4131 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4132
4133 info->rx_enabled = false;
4134 info->rx_overflow = false;
4135}
4136
4137/* enable the receiver
4138 */
4139static void rx_start(SLMP_INFO *info)
4140{
4141 int i;
4142
4143 if (debug_level >= DEBUG_LEVEL_ISR)
4144 printk("%s(%d):%s rx_start()\n",
4145 __FILE__,__LINE__, info->device_name );
4146
4147 write_reg(info, CMD, RXRESET);
4148
4149 if ( info->params.mode == MGSL_MODE_HDLC ) {
4150 /* HDLC, disabe IRQ on rxdata */
4151 info->ie0_value &= ~RXRDYE;
4152 write_reg(info, IE0, info->ie0_value);
4153
4154 /* Reset all Rx DMA buffers and program rx dma */
4155 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4156 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4157
4158 for (i = 0; i < info->rx_buf_count; i++) {
4159 info->rx_buf_list[i].status = 0xff;
4160
4161 // throttle to 4 shared memory writes at a time to prevent
4162 // hogging local bus (keep latency time for DMA requests low).
4163 if (!(i % 4))
4164 read_status_reg(info);
4165 }
4166 info->current_rx_buf = 0;
4167
4168 /* set current/1st descriptor address */
4169 write_reg16(info, RXDMA + CDA,
4170 info->rx_buf_list_ex[0].phys_entry);
4171
4172 /* set new last rx descriptor address */
4173 write_reg16(info, RXDMA + EDA,
4174 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4175
4176 /* set buffer length (shared by all rx dma data buffers) */
4177 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4178
4179 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4180 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4181 } else {
4182 /* async, enable IRQ on rxdata */
4183 info->ie0_value |= RXRDYE;
4184 write_reg(info, IE0, info->ie0_value);
4185 }
4186
4187 write_reg(info, CMD, RXENABLE);
4188
4189 info->rx_overflow = false;
4190 info->rx_enabled = true;
4191}
4192
4193/* Enable the transmitter and send a transmit frame if
4194 * one is loaded in the DMA buffers.
4195 */
4196static void tx_start(SLMP_INFO *info)
4197{
4198 if (debug_level >= DEBUG_LEVEL_ISR)
4199 printk("%s(%d):%s tx_start() tx_count=%d\n",
4200 __FILE__,__LINE__, info->device_name,info->tx_count );
4201
4202 if (!info->tx_enabled ) {
4203 write_reg(info, CMD, TXRESET);
4204 write_reg(info, CMD, TXENABLE);
4205 info->tx_enabled = true;
4206 }
4207
4208 if ( info->tx_count ) {
4209
4210 /* If auto RTS enabled and RTS is inactive, then assert */
4211 /* RTS and set a flag indicating that the driver should */
4212 /* negate RTS when the transmission completes. */
4213
4214 info->drop_rts_on_tx_done = false;
4215
4216 if (info->params.mode != MGSL_MODE_ASYNC) {
4217
4218 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4219 get_signals( info );
4220 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4221 info->serial_signals |= SerialSignal_RTS;
4222 set_signals( info );
4223 info->drop_rts_on_tx_done = true;
4224 }
4225 }
4226
4227 write_reg16(info, TRC0,
4228 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4229
4230 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4231 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4232
4233 /* set TX CDA (current descriptor address) */
4234 write_reg16(info, TXDMA + CDA,
4235 info->tx_buf_list_ex[0].phys_entry);
4236
4237 /* set TX EDA (last descriptor address) */
4238 write_reg16(info, TXDMA + EDA,
4239 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4240
4241 /* enable underrun IRQ */
4242 info->ie1_value &= ~IDLE;
4243 info->ie1_value |= UDRN;
4244 write_reg(info, IE1, info->ie1_value);
4245 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4246
4247 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4248 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4249
4250 mod_timer(&info->tx_timer, jiffies +
4251 msecs_to_jiffies(5000));
4252 }
4253 else {
4254 tx_load_fifo(info);
4255 /* async, enable IRQ on txdata */
4256 info->ie0_value |= TXRDYE;
4257 write_reg(info, IE0, info->ie0_value);
4258 }
4259
4260 info->tx_active = true;
4261 }
4262}
4263
4264/* stop the transmitter and DMA
4265 */
4266static void tx_stop( SLMP_INFO *info )
4267{
4268 if (debug_level >= DEBUG_LEVEL_ISR)
4269 printk("%s(%d):%s tx_stop()\n",
4270 __FILE__,__LINE__, info->device_name );
4271
4272 del_timer(&info->tx_timer);
4273
4274 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4275 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4276
4277 write_reg(info, CMD, TXRESET);
4278
4279 info->ie1_value &= ~(UDRN + IDLE);
4280 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4281 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4282
4283 info->ie0_value &= ~TXRDYE;
4284 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4285
4286 info->tx_enabled = false;
4287 info->tx_active = false;
4288}
4289
4290/* Fill the transmit FIFO until the FIFO is full or
4291 * there is no more data to load.
4292 */
4293static void tx_load_fifo(SLMP_INFO *info)
4294{
4295 u8 TwoBytes[2];
4296
4297 /* do nothing is now tx data available and no XON/XOFF pending */
4298
4299 if ( !info->tx_count && !info->x_char )
4300 return;
4301
4302 /* load the Transmit FIFO until FIFOs full or all data sent */
4303
4304 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4305
4306 /* there is more space in the transmit FIFO and */
4307 /* there is more data in transmit buffer */
4308
4309 if ( (info->tx_count > 1) && !info->x_char ) {
4310 /* write 16-bits */
4311 TwoBytes[0] = info->tx_buf[info->tx_get++];
4312 if (info->tx_get >= info->max_frame_size)
4313 info->tx_get -= info->max_frame_size;
4314 TwoBytes[1] = info->tx_buf[info->tx_get++];
4315 if (info->tx_get >= info->max_frame_size)
4316 info->tx_get -= info->max_frame_size;
4317
4318 write_reg16(info, TRB, *((u16 *)TwoBytes));
4319
4320 info->tx_count -= 2;
4321 info->icount.tx += 2;
4322 } else {
4323 /* only 1 byte left to transmit or 1 FIFO slot left */
4324
4325 if (info->x_char) {
4326 /* transmit pending high priority char */
4327 write_reg(info, TRB, info->x_char);
4328 info->x_char = 0;
4329 } else {
4330 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4331 if (info->tx_get >= info->max_frame_size)
4332 info->tx_get -= info->max_frame_size;
4333 info->tx_count--;
4334 }
4335 info->icount.tx++;
4336 }
4337 }
4338}
4339
4340/* Reset a port to a known state
4341 */
4342static void reset_port(SLMP_INFO *info)
4343{
4344 if (info->sca_base) {
4345
4346 tx_stop(info);
4347 rx_stop(info);
4348
4349 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4350 set_signals(info);
4351
4352 /* disable all port interrupts */
4353 info->ie0_value = 0;
4354 info->ie1_value = 0;
4355 info->ie2_value = 0;
4356 write_reg(info, IE0, info->ie0_value);
4357 write_reg(info, IE1, info->ie1_value);
4358 write_reg(info, IE2, info->ie2_value);
4359
4360 write_reg(info, CMD, CHRESET);
4361 }
4362}
4363
4364/* Reset all the ports to a known state.
4365 */
4366static void reset_adapter(SLMP_INFO *info)
4367{
4368 int i;
4369
4370 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4371 if (info->port_array[i])
4372 reset_port(info->port_array[i]);
4373 }
4374}
4375
4376/* Program port for asynchronous communications.
4377 */
4378static void async_mode(SLMP_INFO *info)
4379{
4380
4381 unsigned char RegValue;
4382
4383 tx_stop(info);
4384 rx_stop(info);
4385
4386 /* MD0, Mode Register 0
4387 *
4388 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4389 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4390 * 03 Reserved, must be 0
4391 * 02 CRCCC, CRC Calculation, 0=disabled
4392 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4393 *
4394 * 0000 0000
4395 */
4396 RegValue = 0x00;
4397 if (info->params.stop_bits != 1)
4398 RegValue |= BIT1;
4399 write_reg(info, MD0, RegValue);
4400
4401 /* MD1, Mode Register 1
4402 *
4403 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4404 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4405 * 03..02 RXCHR<1..0>, rx char size
4406 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4407 *
4408 * 0100 0000
4409 */
4410 RegValue = 0x40;
4411 switch (info->params.data_bits) {
4412 case 7: RegValue |= BIT4 + BIT2; break;
4413 case 6: RegValue |= BIT5 + BIT3; break;
4414 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4415 }
4416 if (info->params.parity != ASYNC_PARITY_NONE) {
4417 RegValue |= BIT1;
4418 if (info->params.parity == ASYNC_PARITY_ODD)
4419 RegValue |= BIT0;
4420 }
4421 write_reg(info, MD1, RegValue);
4422
4423 /* MD2, Mode Register 2
4424 *
4425 * 07..02 Reserved, must be 0
4426 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4427 *
4428 * 0000 0000
4429 */
4430 RegValue = 0x00;
4431 if (info->params.loopback)
4432 RegValue |= (BIT1 + BIT0);
4433 write_reg(info, MD2, RegValue);
4434
4435 /* RXS, Receive clock source
4436 *
4437 * 07 Reserved, must be 0
4438 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4439 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4440 */
4441 RegValue=BIT6;
4442 write_reg(info, RXS, RegValue);
4443
4444 /* TXS, Transmit clock source
4445 *
4446 * 07 Reserved, must be 0
4447 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4448 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4449 */
4450 RegValue=BIT6;
4451 write_reg(info, TXS, RegValue);
4452
4453 /* Control Register
4454 *
4455 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4456 */
4457 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4458 write_control_reg(info);
4459
4460 tx_set_idle(info);
4461
4462 /* RRC Receive Ready Control 0
4463 *
4464 * 07..05 Reserved, must be 0
4465 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4466 */
4467 write_reg(info, RRC, 0x00);
4468
4469 /* TRC0 Transmit Ready Control 0
4470 *
4471 * 07..05 Reserved, must be 0
4472 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4473 */
4474 write_reg(info, TRC0, 0x10);
4475
4476 /* TRC1 Transmit Ready Control 1
4477 *
4478 * 07..05 Reserved, must be 0
4479 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4480 */
4481 write_reg(info, TRC1, 0x1e);
4482
4483 /* CTL, MSCI control register
4484 *
4485 * 07..06 Reserved, set to 0
4486 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4487 * 04 IDLC, idle control, 0=mark 1=idle register
4488 * 03 BRK, break, 0=off 1 =on (async)
4489 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4490 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4491 * 00 RTS, RTS output control, 0=active 1=inactive
4492 *
4493 * 0001 0001
4494 */
4495 RegValue = 0x10;
4496 if (!(info->serial_signals & SerialSignal_RTS))
4497 RegValue |= 0x01;
4498 write_reg(info, CTL, RegValue);
4499
4500 /* enable status interrupts */
4501 info->ie0_value |= TXINTE + RXINTE;
4502 write_reg(info, IE0, info->ie0_value);
4503
4504 /* enable break detect interrupt */
4505 info->ie1_value = BRKD;
4506 write_reg(info, IE1, info->ie1_value);
4507
4508 /* enable rx overrun interrupt */
4509 info->ie2_value = OVRN;
4510 write_reg(info, IE2, info->ie2_value);
4511
4512 set_rate( info, info->params.data_rate * 16 );
4513}
4514
4515/* Program the SCA for HDLC communications.
4516 */
4517static void hdlc_mode(SLMP_INFO *info)
4518{
4519 unsigned char RegValue;
4520 u32 DpllDivisor;
4521
4522 // Can't use DPLL because SCA outputs recovered clock on RxC when
4523 // DPLL mode selected. This causes output contention with RxC receiver.
4524 // Use of DPLL would require external hardware to disable RxC receiver
4525 // when DPLL mode selected.
4526 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4527
4528 /* disable DMA interrupts */
4529 write_reg(info, TXDMA + DIR, 0);
4530 write_reg(info, RXDMA + DIR, 0);
4531
4532 /* MD0, Mode Register 0
4533 *
4534 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4535 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4536 * 03 Reserved, must be 0
4537 * 02 CRCCC, CRC Calculation, 1=enabled
4538 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4539 * 00 CRC0, CRC initial value, 1 = all 1s
4540 *
4541 * 1000 0001
4542 */
4543 RegValue = 0x81;
4544 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4545 RegValue |= BIT4;
4546 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4547 RegValue |= BIT4;
4548 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4549 RegValue |= BIT2 + BIT1;
4550 write_reg(info, MD0, RegValue);
4551
4552 /* MD1, Mode Register 1
4553 *
4554 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4555 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4556 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4557 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4558 *
4559 * 0000 0000
4560 */
4561 RegValue = 0x00;
4562 write_reg(info, MD1, RegValue);
4563
4564 /* MD2, Mode Register 2
4565 *
4566 * 07 NRZFM, 0=NRZ, 1=FM
4567 * 06..05 CODE<1..0> Encoding, 00=NRZ
4568 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4569 * 02 Reserved, must be 0
4570 * 01..00 CNCT<1..0> Channel connection, 0=normal
4571 *
4572 * 0000 0000
4573 */
4574 RegValue = 0x00;
4575 switch(info->params.encoding) {
4576 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4577 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4578 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4579 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4580#if 0
4581 case HDLC_ENCODING_NRZB: /* not supported */
4582 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4583 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4584#endif
4585 }
4586 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4587 DpllDivisor = 16;
4588 RegValue |= BIT3;
4589 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4590 DpllDivisor = 8;
4591 } else {
4592 DpllDivisor = 32;
4593 RegValue |= BIT4;
4594 }
4595 write_reg(info, MD2, RegValue);
4596
4597
4598 /* RXS, Receive clock source
4599 *
4600 * 07 Reserved, must be 0
4601 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4602 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4603 */
4604 RegValue=0;
4605 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4606 RegValue |= BIT6;
4607 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4608 RegValue |= BIT6 + BIT5;
4609 write_reg(info, RXS, RegValue);
4610
4611 /* TXS, Transmit clock source
4612 *
4613 * 07 Reserved, must be 0
4614 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4615 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4616 */
4617 RegValue=0;
4618 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4619 RegValue |= BIT6;
4620 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4621 RegValue |= BIT6 + BIT5;
4622 write_reg(info, TXS, RegValue);
4623
4624 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4625 set_rate(info, info->params.clock_speed * DpllDivisor);
4626 else
4627 set_rate(info, info->params.clock_speed);
4628
4629 /* GPDATA (General Purpose I/O Data Register)
4630 *
4631 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4632 */
4633 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4634 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4635 else
4636 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4637 write_control_reg(info);
4638
4639 /* RRC Receive Ready Control 0
4640 *
4641 * 07..05 Reserved, must be 0
4642 * 04..00 RRC<4..0> Rx FIFO trigger active
4643 */
4644 write_reg(info, RRC, rx_active_fifo_level);
4645
4646 /* TRC0 Transmit Ready Control 0
4647 *
4648 * 07..05 Reserved, must be 0
4649 * 04..00 TRC<4..0> Tx FIFO trigger active
4650 */
4651 write_reg(info, TRC0, tx_active_fifo_level);
4652
4653 /* TRC1 Transmit Ready Control 1
4654 *
4655 * 07..05 Reserved, must be 0
4656 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4657 */
4658 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4659
4660 /* DMR, DMA Mode Register
4661 *
4662 * 07..05 Reserved, must be 0
4663 * 04 TMOD, Transfer Mode: 1=chained-block
4664 * 03 Reserved, must be 0
4665 * 02 NF, Number of Frames: 1=multi-frame
4666 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4667 * 00 Reserved, must be 0
4668 *
4669 * 0001 0100
4670 */
4671 write_reg(info, TXDMA + DMR, 0x14);
4672 write_reg(info, RXDMA + DMR, 0x14);
4673
4674 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4675 write_reg(info, RXDMA + CPB,
4676 (unsigned char)(info->buffer_list_phys >> 16));
4677
4678 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4679 write_reg(info, TXDMA + CPB,
4680 (unsigned char)(info->buffer_list_phys >> 16));
4681
4682 /* enable status interrupts. other code enables/disables
4683 * the individual sources for these two interrupt classes.
4684 */
4685 info->ie0_value |= TXINTE + RXINTE;
4686 write_reg(info, IE0, info->ie0_value);
4687
4688 /* CTL, MSCI control register
4689 *
4690 * 07..06 Reserved, set to 0
4691 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4692 * 04 IDLC, idle control, 0=mark 1=idle register
4693 * 03 BRK, break, 0=off 1 =on (async)
4694 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4695 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4696 * 00 RTS, RTS output control, 0=active 1=inactive
4697 *
4698 * 0001 0001
4699 */
4700 RegValue = 0x10;
4701 if (!(info->serial_signals & SerialSignal_RTS))
4702 RegValue |= 0x01;
4703 write_reg(info, CTL, RegValue);
4704
4705 /* preamble not supported ! */
4706
4707 tx_set_idle(info);
4708 tx_stop(info);
4709 rx_stop(info);
4710
4711 set_rate(info, info->params.clock_speed);
4712
4713 if (info->params.loopback)
4714 enable_loopback(info,1);
4715}
4716
4717/* Set the transmit HDLC idle mode
4718 */
4719static void tx_set_idle(SLMP_INFO *info)
4720{
4721 unsigned char RegValue = 0xff;
4722
4723 /* Map API idle mode to SCA register bits */
4724 switch(info->idle_mode) {
4725 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4726 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4727 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4728 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4729 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4730 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4731 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4732 }
4733
4734 write_reg(info, IDL, RegValue);
4735}
4736
4737/* Query the adapter for the state of the V24 status (input) signals.
4738 */
4739static void get_signals(SLMP_INFO *info)
4740{
4741 u16 status = read_reg(info, SR3);
4742 u16 gpstatus = read_status_reg(info);
4743 u16 testbit;
4744
4745 /* clear all serial signals except DTR and RTS */
4746 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4747
4748 /* set serial signal bits to reflect MISR */
4749
4750 if (!(status & BIT3))
4751 info->serial_signals |= SerialSignal_CTS;
4752
4753 if ( !(status & BIT2))
4754 info->serial_signals |= SerialSignal_DCD;
4755
4756 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4757 if (!(gpstatus & testbit))
4758 info->serial_signals |= SerialSignal_RI;
4759
4760 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4761 if (!(gpstatus & testbit))
4762 info->serial_signals |= SerialSignal_DSR;
4763}
4764
4765/* Set the state of DTR and RTS based on contents of
4766 * serial_signals member of device context.
4767 */
4768static void set_signals(SLMP_INFO *info)
4769{
4770 unsigned char RegValue;
4771 u16 EnableBit;
4772
4773 RegValue = read_reg(info, CTL);
4774 if (info->serial_signals & SerialSignal_RTS)
4775 RegValue &= ~BIT0;
4776 else
4777 RegValue |= BIT0;
4778 write_reg(info, CTL, RegValue);
4779
4780 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4781 EnableBit = BIT1 << (info->port_num*2);
4782 if (info->serial_signals & SerialSignal_DTR)
4783 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4784 else
4785 info->port_array[0]->ctrlreg_value |= EnableBit;
4786 write_control_reg(info);
4787}
4788
4789/*******************/
4790/* DMA Buffer Code */
4791/*******************/
4792
4793/* Set the count for all receive buffers to SCABUFSIZE
4794 * and set the current buffer to the first buffer. This effectively
4795 * makes all buffers free and discards any data in buffers.
4796 */
4797static void rx_reset_buffers(SLMP_INFO *info)
4798{
4799 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4800}
4801
4802/* Free the buffers used by a received frame
4803 *
4804 * info pointer to device instance data
4805 * first index of 1st receive buffer of frame
4806 * last index of last receive buffer of frame
4807 */
4808static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4809{
4810 bool done = false;
4811
4812 while(!done) {
4813 /* reset current buffer for reuse */
4814 info->rx_buf_list[first].status = 0xff;
4815
4816 if (first == last) {
4817 done = true;
4818 /* set new last rx descriptor address */
4819 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4820 }
4821
4822 first++;
4823 if (first == info->rx_buf_count)
4824 first = 0;
4825 }
4826
4827 /* set current buffer to next buffer after last buffer of frame */
4828 info->current_rx_buf = first;
4829}
4830
4831/* Return a received frame from the receive DMA buffers.
4832 * Only frames received without errors are returned.
4833 *
4834 * Return Value: true if frame returned, otherwise false
4835 */
4836static bool rx_get_frame(SLMP_INFO *info)
4837{
4838 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4839 unsigned short status;
4840 unsigned int framesize = 0;
4841 bool ReturnCode = false;
4842 unsigned long flags;
4843 struct tty_struct *tty = info->port.tty;
4844 unsigned char addr_field = 0xff;
4845 SCADESC *desc;
4846 SCADESC_EX *desc_ex;
4847
4848CheckAgain:
4849 /* assume no frame returned, set zero length */
4850 framesize = 0;
4851 addr_field = 0xff;
4852
4853 /*
4854 * current_rx_buf points to the 1st buffer of the next available
4855 * receive frame. To find the last buffer of the frame look for
4856 * a non-zero status field in the buffer entries. (The status
4857 * field is set by the 16C32 after completing a receive frame.
4858 */
4859 StartIndex = EndIndex = info->current_rx_buf;
4860
4861 for ( ;; ) {
4862 desc = &info->rx_buf_list[EndIndex];
4863 desc_ex = &info->rx_buf_list_ex[EndIndex];
4864
4865 if (desc->status == 0xff)
4866 goto Cleanup; /* current desc still in use, no frames available */
4867
4868 if (framesize == 0 && info->params.addr_filter != 0xff)
4869 addr_field = desc_ex->virt_addr[0];
4870
4871 framesize += desc->length;
4872
4873 /* Status != 0 means last buffer of frame */
4874 if (desc->status)
4875 break;
4876
4877 EndIndex++;
4878 if (EndIndex == info->rx_buf_count)
4879 EndIndex = 0;
4880
4881 if (EndIndex == info->current_rx_buf) {
4882 /* all buffers have been 'used' but none mark */
4883 /* the end of a frame. Reset buffers and receiver. */
4884 if ( info->rx_enabled ){
4885 spin_lock_irqsave(&info->lock,flags);
4886 rx_start(info);
4887 spin_unlock_irqrestore(&info->lock,flags);
4888 }
4889 goto Cleanup;
4890 }
4891
4892 }
4893
4894 /* check status of receive frame */
4895
4896 /* frame status is byte stored after frame data
4897 *
4898 * 7 EOM (end of msg), 1 = last buffer of frame
4899 * 6 Short Frame, 1 = short frame
4900 * 5 Abort, 1 = frame aborted
4901 * 4 Residue, 1 = last byte is partial
4902 * 3 Overrun, 1 = overrun occurred during frame reception
4903 * 2 CRC, 1 = CRC error detected
4904 *
4905 */
4906 status = desc->status;
4907
4908 /* ignore CRC bit if not using CRC (bit is undefined) */
4909 /* Note:CRC is not save to data buffer */
4910 if (info->params.crc_type == HDLC_CRC_NONE)
4911 status &= ~BIT2;
4912
4913 if (framesize == 0 ||
4914 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4915 /* discard 0 byte frames, this seems to occur sometime
4916 * when remote is idling flags.
4917 */
4918 rx_free_frame_buffers(info, StartIndex, EndIndex);
4919 goto CheckAgain;
4920 }
4921
4922 if (framesize < 2)
4923 status |= BIT6;
4924
4925 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4926 /* received frame has errors,
4927 * update counts and mark frame size as 0
4928 */
4929 if (status & BIT6)
4930 info->icount.rxshort++;
4931 else if (status & BIT5)
4932 info->icount.rxabort++;
4933 else if (status & BIT3)
4934 info->icount.rxover++;
4935 else
4936 info->icount.rxcrc++;
4937
4938 framesize = 0;
4939#if SYNCLINK_GENERIC_HDLC
4940 {
4941 info->netdev->stats.rx_errors++;
4942 info->netdev->stats.rx_frame_errors++;
4943 }
4944#endif
4945 }
4946
4947 if ( debug_level >= DEBUG_LEVEL_BH )
4948 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4949 __FILE__,__LINE__,info->device_name,status,framesize);
4950
4951 if ( debug_level >= DEBUG_LEVEL_DATA )
4952 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4953 min_t(int, framesize,SCABUFSIZE),0);
4954
4955 if (framesize) {
4956 if (framesize > info->max_frame_size)
4957 info->icount.rxlong++;
4958 else {
4959 /* copy dma buffer(s) to contiguous intermediate buffer */
4960 int copy_count = framesize;
4961 int index = StartIndex;
4962 unsigned char *ptmp = info->tmp_rx_buf;
4963 info->tmp_rx_buf_count = framesize;
4964
4965 info->icount.rxok++;
4966
4967 while(copy_count) {
4968 int partial_count = min(copy_count,SCABUFSIZE);
4969 memcpy( ptmp,
4970 info->rx_buf_list_ex[index].virt_addr,
4971 partial_count );
4972 ptmp += partial_count;
4973 copy_count -= partial_count;
4974
4975 if ( ++index == info->rx_buf_count )
4976 index = 0;
4977 }
4978
4979#if SYNCLINK_GENERIC_HDLC
4980 if (info->netcount)
4981 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4982 else
4983#endif
4984 ldisc_receive_buf(tty,info->tmp_rx_buf,
4985 info->flag_buf, framesize);
4986 }
4987 }
4988 /* Free the buffers used by this frame. */
4989 rx_free_frame_buffers( info, StartIndex, EndIndex );
4990
4991 ReturnCode = true;
4992
4993Cleanup:
4994 if ( info->rx_enabled && info->rx_overflow ) {
4995 /* Receiver is enabled, but needs to restarted due to
4996 * rx buffer overflow. If buffers are empty, restart receiver.
4997 */
4998 if (info->rx_buf_list[EndIndex].status == 0xff) {
4999 spin_lock_irqsave(&info->lock,flags);
5000 rx_start(info);
5001 spin_unlock_irqrestore(&info->lock,flags);
5002 }
5003 }
5004
5005 return ReturnCode;
5006}
5007
5008/* load the transmit DMA buffer with data
5009 */
5010static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5011{
5012 unsigned short copy_count;
5013 unsigned int i = 0;
5014 SCADESC *desc;
5015 SCADESC_EX *desc_ex;
5016
5017 if ( debug_level >= DEBUG_LEVEL_DATA )
5018 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5019
5020 /* Copy source buffer to one or more DMA buffers, starting with
5021 * the first transmit dma buffer.
5022 */
5023 for(i=0;;)
5024 {
5025 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5026
5027 desc = &info->tx_buf_list[i];
5028 desc_ex = &info->tx_buf_list_ex[i];
5029
5030 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5031
5032 desc->length = copy_count;
5033 desc->status = 0;
5034
5035 buf += copy_count;
5036 count -= copy_count;
5037
5038 if (!count)
5039 break;
5040
5041 i++;
5042 if (i >= info->tx_buf_count)
5043 i = 0;
5044 }
5045
5046 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5047 info->last_tx_buf = ++i;
5048}
5049
5050static bool register_test(SLMP_INFO *info)
5051{
5052 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5053 static unsigned int count = ARRAY_SIZE(testval);
5054 unsigned int i;
5055 bool rc = true;
5056 unsigned long flags;
5057
5058 spin_lock_irqsave(&info->lock,flags);
5059 reset_port(info);
5060
5061 /* assume failure */
5062 info->init_error = DiagStatus_AddressFailure;
5063
5064 /* Write bit patterns to various registers but do it out of */
5065 /* sync, then read back and verify values. */
5066
5067 for (i = 0 ; i < count ; i++) {
5068 write_reg(info, TMC, testval[i]);
5069 write_reg(info, IDL, testval[(i+1)%count]);
5070 write_reg(info, SA0, testval[(i+2)%count]);
5071 write_reg(info, SA1, testval[(i+3)%count]);
5072
5073 if ( (read_reg(info, TMC) != testval[i]) ||
5074 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5075 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5076 (read_reg(info, SA1) != testval[(i+3)%count]) )
5077 {
5078 rc = false;
5079 break;
5080 }
5081 }
5082
5083 reset_port(info);
5084 spin_unlock_irqrestore(&info->lock,flags);
5085
5086 return rc;
5087}
5088
5089static bool irq_test(SLMP_INFO *info)
5090{
5091 unsigned long timeout;
5092 unsigned long flags;
5093
5094 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5095
5096 spin_lock_irqsave(&info->lock,flags);
5097 reset_port(info);
5098
5099 /* assume failure */
5100 info->init_error = DiagStatus_IrqFailure;
5101 info->irq_occurred = false;
5102
5103 /* setup timer0 on SCA0 to interrupt */
5104
5105 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5106 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5107
5108 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5109 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5110
5111
5112 /* TMCS, Timer Control/Status Register
5113 *
5114 * 07 CMF, Compare match flag (read only) 1=match
5115 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5116 * 05 Reserved, must be 0
5117 * 04 TME, Timer Enable
5118 * 03..00 Reserved, must be 0
5119 *
5120 * 0101 0000
5121 */
5122 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5123
5124 spin_unlock_irqrestore(&info->lock,flags);
5125
5126 timeout=100;
5127 while( timeout-- && !info->irq_occurred ) {
5128 msleep_interruptible(10);
5129 }
5130
5131 spin_lock_irqsave(&info->lock,flags);
5132 reset_port(info);
5133 spin_unlock_irqrestore(&info->lock,flags);
5134
5135 return info->irq_occurred;
5136}
5137
5138/* initialize individual SCA device (2 ports)
5139 */
5140static bool sca_init(SLMP_INFO *info)
5141{
5142 /* set wait controller to single mem partition (low), no wait states */
5143 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5144 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5145 write_reg(info, WCRL, 0); /* wait controller low range */
5146 write_reg(info, WCRM, 0); /* wait controller mid range */
5147 write_reg(info, WCRH, 0); /* wait controller high range */
5148
5149 /* DPCR, DMA Priority Control
5150 *
5151 * 07..05 Not used, must be 0
5152 * 04 BRC, bus release condition: 0=all transfers complete
5153 * 03 CCC, channel change condition: 0=every cycle
5154 * 02..00 PR<2..0>, priority 100=round robin
5155 *
5156 * 00000100 = 0x04
5157 */
5158 write_reg(info, DPCR, dma_priority);
5159
5160 /* DMA Master Enable, BIT7: 1=enable all channels */
5161 write_reg(info, DMER, 0x80);
5162
5163 /* enable all interrupt classes */
5164 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5165 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5166 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5167
5168 /* ITCR, interrupt control register
5169 * 07 IPC, interrupt priority, 0=MSCI->DMA
5170 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5171 * 04 VOS, Vector Output, 0=unmodified vector
5172 * 03..00 Reserved, must be 0
5173 */
5174 write_reg(info, ITCR, 0);
5175
5176 return true;
5177}
5178
5179/* initialize adapter hardware
5180 */
5181static bool init_adapter(SLMP_INFO *info)
5182{
5183 int i;
5184
5185 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5186 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5187 u32 readval;
5188
5189 info->misc_ctrl_value |= BIT30;
5190 *MiscCtrl = info->misc_ctrl_value;
5191
5192 /*
5193 * Force at least 170ns delay before clearing
5194 * reset bit. Each read from LCR takes at least
5195 * 30ns so 10 times for 300ns to be safe.
5196 */
5197 for(i=0;i<10;i++)
5198 readval = *MiscCtrl;
5199
5200 info->misc_ctrl_value &= ~BIT30;
5201 *MiscCtrl = info->misc_ctrl_value;
5202
5203 /* init control reg (all DTRs off, all clksel=input) */
5204 info->ctrlreg_value = 0xaa;
5205 write_control_reg(info);
5206
5207 {
5208 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5209 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5210
5211 switch(read_ahead_count)
5212 {
5213 case 16:
5214 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5215 break;
5216 case 8:
5217 lcr1_brdr_value |= BIT5 + BIT4;
5218 break;
5219 case 4:
5220 lcr1_brdr_value |= BIT5 + BIT3;
5221 break;
5222 case 0:
5223 lcr1_brdr_value |= BIT5;
5224 break;
5225 }
5226
5227 *LCR1BRDR = lcr1_brdr_value;
5228 *MiscCtrl = misc_ctrl_value;
5229 }
5230
5231 sca_init(info->port_array[0]);
5232 sca_init(info->port_array[2]);
5233
5234 return true;
5235}
5236
5237/* Loopback an HDLC frame to test the hardware
5238 * interrupt and DMA functions.
5239 */
5240static bool loopback_test(SLMP_INFO *info)
5241{
5242#define TESTFRAMESIZE 20
5243
5244 unsigned long timeout;
5245 u16 count = TESTFRAMESIZE;
5246 unsigned char buf[TESTFRAMESIZE];
5247 bool rc = false;
5248 unsigned long flags;
5249
5250 struct tty_struct *oldtty = info->port.tty;
5251 u32 speed = info->params.clock_speed;
5252
5253 info->params.clock_speed = 3686400;
5254 info->port.tty = NULL;
5255
5256 /* assume failure */
5257 info->init_error = DiagStatus_DmaFailure;
5258
5259 /* build and send transmit frame */
5260 for (count = 0; count < TESTFRAMESIZE;++count)
5261 buf[count] = (unsigned char)count;
5262
5263 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5264
5265 /* program hardware for HDLC and enabled receiver */
5266 spin_lock_irqsave(&info->lock,flags);
5267 hdlc_mode(info);
5268 enable_loopback(info,1);
5269 rx_start(info);
5270 info->tx_count = count;
5271 tx_load_dma_buffer(info,buf,count);
5272 tx_start(info);
5273 spin_unlock_irqrestore(&info->lock,flags);
5274
5275 /* wait for receive complete */
5276 /* Set a timeout for waiting for interrupt. */
5277 for ( timeout = 100; timeout; --timeout ) {
5278 msleep_interruptible(10);
5279
5280 if (rx_get_frame(info)) {
5281 rc = true;
5282 break;
5283 }
5284 }
5285
5286 /* verify received frame length and contents */
5287 if (rc &&
5288 ( info->tmp_rx_buf_count != count ||
5289 memcmp(buf, info->tmp_rx_buf,count))) {
5290 rc = false;
5291 }
5292
5293 spin_lock_irqsave(&info->lock,flags);
5294 reset_adapter(info);
5295 spin_unlock_irqrestore(&info->lock,flags);
5296
5297 info->params.clock_speed = speed;
5298 info->port.tty = oldtty;
5299
5300 return rc;
5301}
5302
5303/* Perform diagnostics on hardware
5304 */
5305static int adapter_test( SLMP_INFO *info )
5306{
5307 unsigned long flags;
5308 if ( debug_level >= DEBUG_LEVEL_INFO )
5309 printk( "%s(%d):Testing device %s\n",
5310 __FILE__,__LINE__,info->device_name );
5311
5312 spin_lock_irqsave(&info->lock,flags);
5313 init_adapter(info);
5314 spin_unlock_irqrestore(&info->lock,flags);
5315
5316 info->port_array[0]->port_count = 0;
5317
5318 if ( register_test(info->port_array[0]) &&
5319 register_test(info->port_array[1])) {
5320
5321 info->port_array[0]->port_count = 2;
5322
5323 if ( register_test(info->port_array[2]) &&
5324 register_test(info->port_array[3]) )
5325 info->port_array[0]->port_count += 2;
5326 }
5327 else {
5328 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5329 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5330 return -ENODEV;
5331 }
5332
5333 if ( !irq_test(info->port_array[0]) ||
5334 !irq_test(info->port_array[1]) ||
5335 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5336 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5337 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5338 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5339 return -ENODEV;
5340 }
5341
5342 if (!loopback_test(info->port_array[0]) ||
5343 !loopback_test(info->port_array[1]) ||
5344 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5345 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5346 printk( "%s(%d):DMA test failure for device %s\n",
5347 __FILE__,__LINE__,info->device_name);
5348 return -ENODEV;
5349 }
5350
5351 if ( debug_level >= DEBUG_LEVEL_INFO )
5352 printk( "%s(%d):device %s passed diagnostics\n",
5353 __FILE__,__LINE__,info->device_name );
5354
5355 info->port_array[0]->init_error = 0;
5356 info->port_array[1]->init_error = 0;
5357 if ( info->port_count > 2 ) {
5358 info->port_array[2]->init_error = 0;
5359 info->port_array[3]->init_error = 0;
5360 }
5361
5362 return 0;
5363}
5364
5365/* Test the shared memory on a PCI adapter.
5366 */
5367static bool memory_test(SLMP_INFO *info)
5368{
5369 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5370 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5371 unsigned long count = ARRAY_SIZE(testval);
5372 unsigned long i;
5373 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5374 unsigned long * addr = (unsigned long *)info->memory_base;
5375
5376 /* Test data lines with test pattern at one location. */
5377
5378 for ( i = 0 ; i < count ; i++ ) {
5379 *addr = testval[i];
5380 if ( *addr != testval[i] )
5381 return false;
5382 }
5383
5384 /* Test address lines with incrementing pattern over */
5385 /* entire address range. */
5386
5387 for ( i = 0 ; i < limit ; i++ ) {
5388 *addr = i * 4;
5389 addr++;
5390 }
5391
5392 addr = (unsigned long *)info->memory_base;
5393
5394 for ( i = 0 ; i < limit ; i++ ) {
5395 if ( *addr != i * 4 )
5396 return false;
5397 addr++;
5398 }
5399
5400 memset( info->memory_base, 0, SCA_MEM_SIZE );
5401 return true;
5402}
5403
5404/* Load data into PCI adapter shared memory.
5405 *
5406 * The PCI9050 releases control of the local bus
5407 * after completing the current read or write operation.
5408 *
5409 * While the PCI9050 write FIFO not empty, the
5410 * PCI9050 treats all of the writes as a single transaction
5411 * and does not release the bus. This causes DMA latency problems
5412 * at high speeds when copying large data blocks to the shared memory.
5413 *
5414 * This function breaks a write into multiple transations by
5415 * interleaving a read which flushes the write FIFO and 'completes'
5416 * the write transation. This allows any pending DMA request to gain control
5417 * of the local bus in a timely fasion.
5418 */
5419static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5420{
5421 /* A load interval of 16 allows for 4 32-bit writes at */
5422 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5423
5424 unsigned short interval = count / sca_pci_load_interval;
5425 unsigned short i;
5426
5427 for ( i = 0 ; i < interval ; i++ )
5428 {
5429 memcpy(dest, src, sca_pci_load_interval);
5430 read_status_reg(info);
5431 dest += sca_pci_load_interval;
5432 src += sca_pci_load_interval;
5433 }
5434
5435 memcpy(dest, src, count % sca_pci_load_interval);
5436}
5437
5438static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5439{
5440 int i;
5441 int linecount;
5442 if (xmit)
5443 printk("%s tx data:\n",info->device_name);
5444 else
5445 printk("%s rx data:\n",info->device_name);
5446
5447 while(count) {
5448 if (count > 16)
5449 linecount = 16;
5450 else
5451 linecount = count;
5452
5453 for(i=0;i<linecount;i++)
5454 printk("%02X ",(unsigned char)data[i]);
5455 for(;i<17;i++)
5456 printk(" ");
5457 for(i=0;i<linecount;i++) {
5458 if (data[i]>=040 && data[i]<=0176)
5459 printk("%c",data[i]);
5460 else
5461 printk(".");
5462 }
5463 printk("\n");
5464
5465 data += linecount;
5466 count -= linecount;
5467 }
5468} /* end of trace_block() */
5469
5470/* called when HDLC frame times out
5471 * update stats and do tx completion processing
5472 */
5473static void tx_timeout(unsigned long context)
5474{
5475 SLMP_INFO *info = (SLMP_INFO*)context;
5476 unsigned long flags;
5477
5478 if ( debug_level >= DEBUG_LEVEL_INFO )
5479 printk( "%s(%d):%s tx_timeout()\n",
5480 __FILE__,__LINE__,info->device_name);
5481 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5482 info->icount.txtimeout++;
5483 }
5484 spin_lock_irqsave(&info->lock,flags);
5485 info->tx_active = false;
5486 info->tx_count = info->tx_put = info->tx_get = 0;
5487
5488 spin_unlock_irqrestore(&info->lock,flags);
5489
5490#if SYNCLINK_GENERIC_HDLC
5491 if (info->netcount)
5492 hdlcdev_tx_done(info);
5493 else
5494#endif
5495 bh_transmit(info);
5496}
5497
5498/* called to periodically check the DSR/RI modem signal input status
5499 */
5500static void status_timeout(unsigned long context)
5501{
5502 u16 status = 0;
5503 SLMP_INFO *info = (SLMP_INFO*)context;
5504 unsigned long flags;
5505 unsigned char delta;
5506
5507
5508 spin_lock_irqsave(&info->lock,flags);
5509 get_signals(info);
5510 spin_unlock_irqrestore(&info->lock,flags);
5511
5512 /* check for DSR/RI state change */
5513
5514 delta = info->old_signals ^ info->serial_signals;
5515 info->old_signals = info->serial_signals;
5516
5517 if (delta & SerialSignal_DSR)
5518 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5519
5520 if (delta & SerialSignal_RI)
5521 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5522
5523 if (delta & SerialSignal_DCD)
5524 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5525
5526 if (delta & SerialSignal_CTS)
5527 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5528
5529 if (status)
5530 isr_io_pin(info,status);
5531
5532 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5533}
5534
5535
5536/* Register Access Routines -
5537 * All registers are memory mapped
5538 */
5539#define CALC_REGADDR() \
5540 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5541 if (info->port_num > 1) \
5542 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5543 if ( info->port_num & 1) { \
5544 if (Addr > 0x7f) \
5545 RegAddr += 0x40; /* DMA access */ \
5546 else if (Addr > 0x1f && Addr < 0x60) \
5547 RegAddr += 0x20; /* MSCI access */ \
5548 }
5549
5550
5551static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5552{
5553 CALC_REGADDR();
5554 return *RegAddr;
5555}
5556static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5557{
5558 CALC_REGADDR();
5559 *RegAddr = Value;
5560}
5561
5562static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5563{
5564 CALC_REGADDR();
5565 return *((u16 *)RegAddr);
5566}
5567
5568static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5569{
5570 CALC_REGADDR();
5571 *((u16 *)RegAddr) = Value;
5572}
5573
5574static unsigned char read_status_reg(SLMP_INFO * info)
5575{
5576 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5577 return *RegAddr;
5578}
5579
5580static void write_control_reg(SLMP_INFO * info)
5581{
5582 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5583 *RegAddr = info->port_array[0]->ctrlreg_value;
5584}
5585
5586
5587static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5588 const struct pci_device_id *ent)
5589{
5590 if (pci_enable_device(dev)) {
5591 printk("error enabling pci device %p\n", dev);
5592 return -EIO;
5593 }
5594 device_init( ++synclinkmp_adapter_count, dev );
5595 return 0;
5596}
5597
5598static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5599{
5600}
1/*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28#define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29#if defined(__i386__)
30# define BREAKPOINT() asm(" int $3");
31#else
32# define BREAKPOINT() { }
33#endif
34
35#define MAX_DEVICES 12
36
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/signal.h>
40#include <linux/sched.h>
41#include <linux/timer.h>
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/tty.h>
45#include <linux/tty_flip.h>
46#include <linux/serial.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/ptrace.h>
51#include <linux/ioport.h>
52#include <linux/mm.h>
53#include <linux/seq_file.h>
54#include <linux/slab.h>
55#include <linux/netdevice.h>
56#include <linux/vmalloc.h>
57#include <linux/init.h>
58#include <linux/delay.h>
59#include <linux/ioctl.h>
60
61#include <asm/io.h>
62#include <asm/irq.h>
63#include <asm/dma.h>
64#include <linux/bitops.h>
65#include <asm/types.h>
66#include <linux/termios.h>
67#include <linux/workqueue.h>
68#include <linux/hdlc.h>
69#include <linux/synclink.h>
70
71#if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72#define SYNCLINK_GENERIC_HDLC 1
73#else
74#define SYNCLINK_GENERIC_HDLC 0
75#endif
76
77#define GET_USER(error,value,addr) error = get_user(value,addr)
78#define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79#define PUT_USER(error,value,addr) error = put_user(value,addr)
80#define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82#include <asm/uaccess.h>
83
84static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98};
99
100/* size in bytes of DMA data buffers */
101#define SCABUFSIZE 1024
102#define SCA_MEM_SIZE 0x40000
103#define SCA_BASE_SIZE 512
104#define SCA_REG_SIZE 16
105#define SCA_MAX_PORTS 4
106#define SCAMAXDESC 128
107
108#define BUFFERLISTSIZE 4096
109
110/* SCA-I style DMA buffer descriptor */
111typedef struct _SCADESC
112{
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120} SCADESC, *PSCADESC;
121
122typedef struct _SCADESC_EX
123{
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127} SCADESC_EX, *PSCADESC_EX;
128
129/* The queue of BH actions to be performed */
130
131#define BH_RECEIVE 1
132#define BH_TRANSMIT 2
133#define BH_STATUS 4
134
135#define IO_PIN_SHUTDOWN_LIMIT 100
136
137struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146};
147
148/*
149 * Device instance data structure
150 */
151typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274#if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276#endif
277
278} SLMP_INFO;
279
280#define MGSL_MAGIC 0x5401
281
282/*
283 * define serial signal status change macros
284 */
285#define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286#define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287#define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288#define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290/* Common Register macros */
291#define LPR 0x00
292#define PABR0 0x02
293#define PABR1 0x03
294#define WCRL 0x04
295#define WCRM 0x05
296#define WCRH 0x06
297#define DPCR 0x08
298#define DMER 0x09
299#define ISR0 0x10
300#define ISR1 0x11
301#define ISR2 0x12
302#define IER0 0x14
303#define IER1 0x15
304#define IER2 0x16
305#define ITCR 0x18
306#define INTVR 0x1a
307#define IMVR 0x1c
308
309/* MSCI Register macros */
310#define TRB 0x20
311#define TRBL 0x20
312#define TRBH 0x21
313#define SR0 0x22
314#define SR1 0x23
315#define SR2 0x24
316#define SR3 0x25
317#define FST 0x26
318#define IE0 0x28
319#define IE1 0x29
320#define IE2 0x2a
321#define FIE 0x2b
322#define CMD 0x2c
323#define MD0 0x2e
324#define MD1 0x2f
325#define MD2 0x30
326#define CTL 0x31
327#define SA0 0x32
328#define SA1 0x33
329#define IDL 0x34
330#define TMC 0x35
331#define RXS 0x36
332#define TXS 0x37
333#define TRC0 0x38
334#define TRC1 0x39
335#define RRC 0x3a
336#define CST0 0x3c
337#define CST1 0x3d
338
339/* Timer Register Macros */
340#define TCNT 0x60
341#define TCNTL 0x60
342#define TCNTH 0x61
343#define TCONR 0x62
344#define TCONRL 0x62
345#define TCONRH 0x63
346#define TMCS 0x64
347#define TEPR 0x65
348
349/* DMA Controller Register macros */
350#define DARL 0x80
351#define DARH 0x81
352#define DARB 0x82
353#define BAR 0x80
354#define BARL 0x80
355#define BARH 0x81
356#define BARB 0x82
357#define SAR 0x84
358#define SARL 0x84
359#define SARH 0x85
360#define SARB 0x86
361#define CPB 0x86
362#define CDA 0x88
363#define CDAL 0x88
364#define CDAH 0x89
365#define EDA 0x8a
366#define EDAL 0x8a
367#define EDAH 0x8b
368#define BFL 0x8c
369#define BFLL 0x8c
370#define BFLH 0x8d
371#define BCR 0x8e
372#define BCRL 0x8e
373#define BCRH 0x8f
374#define DSR 0x90
375#define DMR 0x91
376#define FCT 0x93
377#define DIR 0x94
378#define DCMD 0x95
379
380/* combine with timer or DMA register address */
381#define TIMER0 0x00
382#define TIMER1 0x08
383#define TIMER2 0x10
384#define TIMER3 0x18
385#define RXDMA 0x00
386#define TXDMA 0x20
387
388/* SCA Command Codes */
389#define NOOP 0x00
390#define TXRESET 0x01
391#define TXENABLE 0x02
392#define TXDISABLE 0x03
393#define TXCRCINIT 0x04
394#define TXCRCEXCL 0x05
395#define TXEOM 0x06
396#define TXABORT 0x07
397#define MPON 0x08
398#define TXBUFCLR 0x09
399#define RXRESET 0x11
400#define RXENABLE 0x12
401#define RXDISABLE 0x13
402#define RXCRCINIT 0x14
403#define RXREJECT 0x15
404#define SEARCHMP 0x16
405#define RXCRCEXCL 0x17
406#define RXCRCCALC 0x18
407#define CHRESET 0x21
408#define HUNT 0x31
409
410/* DMA command codes */
411#define SWABORT 0x01
412#define FEICLEAR 0x02
413
414/* IE0 */
415#define TXINTE BIT7
416#define RXINTE BIT6
417#define TXRDYE BIT1
418#define RXRDYE BIT0
419
420/* IE1 & SR1 */
421#define UDRN BIT7
422#define IDLE BIT6
423#define SYNCD BIT4
424#define FLGD BIT4
425#define CCTS BIT3
426#define CDCD BIT2
427#define BRKD BIT1
428#define ABTD BIT1
429#define GAPD BIT1
430#define BRKE BIT0
431#define IDLD BIT0
432
433/* IE2 & SR2 */
434#define EOM BIT7
435#define PMP BIT6
436#define SHRT BIT6
437#define PE BIT5
438#define ABT BIT5
439#define FRME BIT4
440#define RBIT BIT4
441#define OVRN BIT3
442#define CRCE BIT2
443
444
445/*
446 * Global linked list of SyncLink devices
447 */
448static SLMP_INFO *synclinkmp_device_list = NULL;
449static int synclinkmp_adapter_count = -1;
450static int synclinkmp_device_count = 0;
451
452/*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457static bool break_on_load = 0;
458
459/*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463static int ttymajor = 0;
464
465/*
466 * Array of user specified options for ISA adapters.
467 */
468static int debug_level = 0;
469static int maxframe[MAX_DEVICES] = {0,};
470
471module_param(break_on_load, bool, 0);
472module_param(ttymajor, int, 0);
473module_param(debug_level, int, 0);
474module_param_array(maxframe, int, NULL, 0);
475
476static char *driver_name = "SyncLink MultiPort driver";
477static char *driver_version = "$Revision: 4.38 $";
478
479static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480static void synclinkmp_remove_one(struct pci_dev *dev);
481
482static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485};
486MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488MODULE_LICENSE("GPL");
489
490static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495};
496
497
498static struct tty_driver *serial_driver;
499
500/* number of characters left in xmit buffer before we ask for more */
501#define WAKEUP_CHARS 256
502
503
504/* tty callbacks */
505
506static int open(struct tty_struct *tty, struct file * filp);
507static void close(struct tty_struct *tty, struct file * filp);
508static void hangup(struct tty_struct *tty);
509static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512static int put_char(struct tty_struct *tty, unsigned char ch);
513static void send_xchar(struct tty_struct *tty, char ch);
514static void wait_until_sent(struct tty_struct *tty, int timeout);
515static int write_room(struct tty_struct *tty);
516static void flush_chars(struct tty_struct *tty);
517static void flush_buffer(struct tty_struct *tty);
518static void tx_hold(struct tty_struct *tty);
519static void tx_release(struct tty_struct *tty);
520
521static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522static int chars_in_buffer(struct tty_struct *tty);
523static void throttle(struct tty_struct * tty);
524static void unthrottle(struct tty_struct * tty);
525static int set_break(struct tty_struct *tty, int break_state);
526
527#if SYNCLINK_GENERIC_HDLC
528#define dev_to_port(D) (dev_to_hdlc(D)->priv)
529static void hdlcdev_tx_done(SLMP_INFO *info);
530static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531static int hdlcdev_init(SLMP_INFO *info);
532static void hdlcdev_exit(SLMP_INFO *info);
533#endif
534
535/* ioctl handlers */
536
537static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541static int set_txidle(SLMP_INFO *info, int idle_mode);
542static int tx_enable(SLMP_INFO *info, int enable);
543static int tx_abort(SLMP_INFO *info);
544static int rx_enable(SLMP_INFO *info, int enable);
545static int modem_input_wait(SLMP_INFO *info,int arg);
546static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547static int tiocmget(struct tty_struct *tty);
548static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550static int set_break(struct tty_struct *tty, int break_state);
551
552static int add_device(SLMP_INFO *info);
553static int device_init(int adapter_num, struct pci_dev *pdev);
554static int claim_resources(SLMP_INFO *info);
555static void release_resources(SLMP_INFO *info);
556
557static int startup(SLMP_INFO *info);
558static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559static int carrier_raised(struct tty_port *port);
560static void shutdown(SLMP_INFO *info);
561static void program_hw(SLMP_INFO *info);
562static void change_params(SLMP_INFO *info);
563
564static bool init_adapter(SLMP_INFO *info);
565static bool register_test(SLMP_INFO *info);
566static bool irq_test(SLMP_INFO *info);
567static bool loopback_test(SLMP_INFO *info);
568static int adapter_test(SLMP_INFO *info);
569static bool memory_test(SLMP_INFO *info);
570
571static void reset_adapter(SLMP_INFO *info);
572static void reset_port(SLMP_INFO *info);
573static void async_mode(SLMP_INFO *info);
574static void hdlc_mode(SLMP_INFO *info);
575
576static void rx_stop(SLMP_INFO *info);
577static void rx_start(SLMP_INFO *info);
578static void rx_reset_buffers(SLMP_INFO *info);
579static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580static bool rx_get_frame(SLMP_INFO *info);
581
582static void tx_start(SLMP_INFO *info);
583static void tx_stop(SLMP_INFO *info);
584static void tx_load_fifo(SLMP_INFO *info);
585static void tx_set_idle(SLMP_INFO *info);
586static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588static void get_signals(SLMP_INFO *info);
589static void set_signals(SLMP_INFO *info);
590static void enable_loopback(SLMP_INFO *info, int enable);
591static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593static int bh_action(SLMP_INFO *info);
594static void bh_handler(struct work_struct *work);
595static void bh_receive(SLMP_INFO *info);
596static void bh_transmit(SLMP_INFO *info);
597static void bh_status(SLMP_INFO *info);
598static void isr_timer(SLMP_INFO *info);
599static void isr_rxint(SLMP_INFO *info);
600static void isr_rxrdy(SLMP_INFO *info);
601static void isr_txint(SLMP_INFO *info);
602static void isr_txrdy(SLMP_INFO *info);
603static void isr_rxdmaok(SLMP_INFO *info);
604static void isr_rxdmaerror(SLMP_INFO *info);
605static void isr_txdmaok(SLMP_INFO *info);
606static void isr_txdmaerror(SLMP_INFO *info);
607static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609static int alloc_dma_bufs(SLMP_INFO *info);
610static void free_dma_bufs(SLMP_INFO *info);
611static int alloc_buf_list(SLMP_INFO *info);
612static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613static int alloc_tmp_rx_buf(SLMP_INFO *info);
614static void free_tmp_rx_buf(SLMP_INFO *info);
615
616static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618static void tx_timeout(unsigned long context);
619static void status_timeout(unsigned long context);
620
621static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625static unsigned char read_status_reg(SLMP_INFO * info);
626static void write_control_reg(SLMP_INFO * info);
627
628
629static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633static u32 misc_ctrl_value = 0x007e4040;
634static u32 lcr1_brdr_value = 0x00800028;
635
636static u32 read_ahead_count = 8;
637
638/* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649static unsigned char dma_priority = 0x04;
650
651// Number of bytes that can be written to shared RAM
652// in a single write operation
653static u32 sca_pci_load_interval = 64;
654
655/*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661static void* synclinkmp_get_text_ptr(void);
662static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666{
667#ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681#else
682 if (!info)
683 return 1;
684#endif
685 return 0;
686}
687
688/**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699{
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709}
710
711/* tty callbacks */
712
713static int install(struct tty_driver *driver, struct tty_struct *tty)
714{
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739}
740
741/* Called when a port is opened. Init and enable port.
742 */
743static int open(struct tty_struct *tty, struct file *filp)
744{
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795}
796
797/* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800static void close(struct tty_struct *tty, struct file *filp)
801{
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (info->port.flags & ASYNC_INITIALIZED)
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829}
830
831/* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834static void hangup(struct tty_struct *tty)
835{
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
853 info->port.tty = NULL;
854 spin_unlock_irqrestore(&info->port.lock, flags);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858}
859
860/* Set new termios settings
861 */
862static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863{
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !test_bit(TTY_THROTTLED, &tty->flags))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896}
897
898/* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910{
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984}
985
986/* Add a character to the transmit buffer.
987 */
988static int put_char(struct tty_struct *tty, unsigned char ch)
989{
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021}
1022
1023/* Send a high-priority XON/XOFF character
1024 */
1025static void send_xchar(struct tty_struct *tty, char ch)
1026{
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045}
1046
1047/* Wait until the transmitter is empty.
1048 */
1049static void wait_until_sent(struct tty_struct *tty, int timeout)
1050{
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!test_bit(ASYNCB_INITIALIZED, &info->port.flags))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111}
1112
1113/* Return the count of free bytes in transmit buffer
1114 */
1115static int write_room(struct tty_struct *tty)
1116{
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136}
1137
1138/* enable transmitter and send remaining buffered characters
1139 */
1140static void flush_chars(struct tty_struct *tty)
1141{
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175}
1176
1177/* Discard all data in the send buffer
1178 */
1179static void flush_buffer(struct tty_struct *tty)
1180{
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197}
1198
1199/* throttle (stop) transmitter
1200 */
1201static void tx_hold(struct tty_struct *tty)
1202{
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217}
1218
1219/* release (start) transmitter
1220 */
1221static void tx_release(struct tty_struct *tty)
1222{
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237}
1238
1239/* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
1249static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251{
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty->flags & (1 << TTY_IO_ERROR))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305}
1306
1307static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309{
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331}
1332
1333/*
1334 * /proc fs routines....
1335 */
1336
1337static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338{
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400 /* Append serial signal status to end */
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406}
1407
1408/* Called to print information about devices
1409 */
1410static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411{
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422}
1423
1424static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425{
1426 return single_open(file, synclinkmp_proc_show, NULL);
1427}
1428
1429static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435};
1436
1437/* Return the count of bytes in transmit buffer
1438 */
1439static int chars_in_buffer(struct tty_struct *tty)
1440{
1441 SLMP_INFO *info = tty->driver_data;
1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451}
1452
1453/* Signal remote device to throttle send data (our receive data)
1454 */
1455static void throttle(struct tty_struct * tty)
1456{
1457 SLMP_INFO *info = tty->driver_data;
1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
1470 if (C_CRTSCTS(tty)) {
1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476}
1477
1478/* Signal remote device to stop throttling send data (our receive data)
1479 */
1480static void unthrottle(struct tty_struct * tty)
1481{
1482 SLMP_INFO *info = tty->driver_data;
1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
1499 if (C_CRTSCTS(tty)) {
1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505}
1506
1507/* set or clear transmit break condition
1508 * break_state -1=set break condition, 0=clear
1509 */
1510static int set_break(struct tty_struct *tty, int break_state)
1511{
1512 unsigned char RegValue;
1513 SLMP_INFO * info = tty->driver_data;
1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
1521 return -EINVAL;
1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531 return 0;
1532}
1533
1534#if SYNCLINK_GENERIC_HDLC
1535
1536/**
1537 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1538 * set encoding and frame check sequence (FCS) options
1539 *
1540 * dev pointer to network device structure
1541 * encoding serial encoding setting
1542 * parity FCS setting
1543 *
1544 * returns 0 if success, otherwise error code
1545 */
1546static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548{
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553 /* return error if TTY interface open */
1554 if (info->port.count)
1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
1576 info->params.crc_type = new_crctype;
1577
1578 /* if network interface up, reprogram hardware */
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583}
1584
1585/**
1586 * called by generic HDLC layer to send frame
1587 *
1588 * skb socket buffer containing HDLC frame
1589 * dev pointer to network device structure
1590 */
1591static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1593{
1594 SLMP_INFO *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600 /* stop sending until this frame completes */
1601 netif_stop_queue(dev);
1602
1603 /* copy data to device buffers */
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607 /* update network statistics */
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1610
1611 /* done with socket buffer, so free it */
1612 dev_kfree_skb(skb);
1613
1614 /* save start time for transmit timeout detection */
1615 dev->trans_start = jiffies;
1616
1617 /* start hardware transmitter if necessary */
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
1623 return NETDEV_TX_OK;
1624}
1625
1626/**
1627 * called by network layer when interface enabled
1628 * claim resources and initialize hardware
1629 *
1630 * dev pointer to network device structure
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634static int hdlcdev_open(struct net_device *dev)
1635{
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643 /* generic HDLC layer open processing */
1644 rc = hdlc_open(dev);
1645 if (rc)
1646 return rc;
1647
1648 /* arbitrate between network and tty opens */
1649 spin_lock_irqsave(&info->netlock, flags);
1650 if (info->port.count != 0 || info->netcount != 0) {
1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658 /* claim resources and init adapter */
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
1666 /* assert RTS and DTR, apply hardware settings */
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1668 program_hw(info);
1669
1670 /* enable network layer transmit */
1671 dev->trans_start = jiffies;
1672 netif_start_queue(dev);
1673
1674 /* inform generic HDLC layer of current DCD status */
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1682 return 0;
1683}
1684
1685/**
1686 * called by network layer when interface is disabled
1687 * shutdown hardware and release resources
1688 *
1689 * dev pointer to network device structure
1690 *
1691 * returns 0 if success, otherwise error code
1692 */
1693static int hdlcdev_close(struct net_device *dev)
1694{
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703 /* shutdown adapter and release resources */
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713}
1714
1715/**
1716 * called by network layer to process IOCTL call to network device
1717 *
1718 * dev pointer to network device structure
1719 * ifr pointer to network interface request structure
1720 * cmd IOCTL command code
1721 *
1722 * returns 0 if success, otherwise error code
1723 */
1724static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725{
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735 /* return error if TTY interface open */
1736 if (info->port.count)
1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE: /* return current sync_serial_settings */
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size; /* data size wanted */
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
1756 memset(&new_line, 0, sizeof(new_line));
1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809 /* if network interface up, reprogram hardware */
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817}
1818
1819/**
1820 * called by network layer when transmit timeout is detected
1821 *
1822 * dev pointer to network device structure
1823 */
1824static void hdlcdev_tx_timeout(struct net_device *dev)
1825{
1826 SLMP_INFO *info = dev_to_port(dev);
1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840}
1841
1842/**
1843 * called by device driver when transmit completes
1844 * reenable network layer transmit if stopped
1845 *
1846 * info pointer to device instance information
1847 */
1848static void hdlcdev_tx_done(SLMP_INFO *info)
1849{
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852}
1853
1854/**
1855 * called by device driver when frame received
1856 * pass frame to network layer
1857 *
1858 * info pointer to device instance information
1859 * buf pointer to buffer contianing frame data
1860 * size count of data bytes in buf
1861 */
1862static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863{
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1874 return;
1875 }
1876
1877 memcpy(skb_put(skb, size), buf, size);
1878
1879 skb->protocol = hdlc_type_trans(skb, dev);
1880
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1883
1884 netif_rx(skb);
1885}
1886
1887static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_change_mtu = hdlc_change_mtu,
1891 .ndo_start_xmit = hdlc_start_xmit,
1892 .ndo_do_ioctl = hdlcdev_ioctl,
1893 .ndo_tx_timeout = hdlcdev_tx_timeout,
1894};
1895
1896/**
1897 * called by device driver when adding device instance
1898 * do generic HDLC initialization
1899 *
1900 * info pointer to device instance information
1901 *
1902 * returns 0 if success, otherwise error code
1903 */
1904static int hdlcdev_init(SLMP_INFO *info)
1905{
1906 int rc;
1907 struct net_device *dev;
1908 hdlc_device *hdlc;
1909
1910 /* allocate and initialize network and HDLC layer objects */
1911
1912 dev = alloc_hdlcdev(info);
1913 if (!dev) {
1914 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1915 return -ENOMEM;
1916 }
1917
1918 /* for network layer reporting purposes only */
1919 dev->mem_start = info->phys_sca_base;
1920 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1921 dev->irq = info->irq_level;
1922
1923 /* network layer callbacks and settings */
1924 dev->netdev_ops = &hdlcdev_ops;
1925 dev->watchdog_timeo = 10 * HZ;
1926 dev->tx_queue_len = 50;
1927
1928 /* generic HDLC layer callbacks and settings */
1929 hdlc = dev_to_hdlc(dev);
1930 hdlc->attach = hdlcdev_attach;
1931 hdlc->xmit = hdlcdev_xmit;
1932
1933 /* register objects with HDLC layer */
1934 rc = register_hdlc_device(dev);
1935 if (rc) {
1936 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1937 free_netdev(dev);
1938 return rc;
1939 }
1940
1941 info->netdev = dev;
1942 return 0;
1943}
1944
1945/**
1946 * called by device driver when removing device instance
1947 * do generic HDLC cleanup
1948 *
1949 * info pointer to device instance information
1950 */
1951static void hdlcdev_exit(SLMP_INFO *info)
1952{
1953 unregister_hdlc_device(info->netdev);
1954 free_netdev(info->netdev);
1955 info->netdev = NULL;
1956}
1957
1958#endif /* CONFIG_HDLC */
1959
1960
1961/* Return next bottom half action to perform.
1962 * Return Value: BH action code or 0 if nothing to do.
1963 */
1964static int bh_action(SLMP_INFO *info)
1965{
1966 unsigned long flags;
1967 int rc = 0;
1968
1969 spin_lock_irqsave(&info->lock,flags);
1970
1971 if (info->pending_bh & BH_RECEIVE) {
1972 info->pending_bh &= ~BH_RECEIVE;
1973 rc = BH_RECEIVE;
1974 } else if (info->pending_bh & BH_TRANSMIT) {
1975 info->pending_bh &= ~BH_TRANSMIT;
1976 rc = BH_TRANSMIT;
1977 } else if (info->pending_bh & BH_STATUS) {
1978 info->pending_bh &= ~BH_STATUS;
1979 rc = BH_STATUS;
1980 }
1981
1982 if (!rc) {
1983 /* Mark BH routine as complete */
1984 info->bh_running = false;
1985 info->bh_requested = false;
1986 }
1987
1988 spin_unlock_irqrestore(&info->lock,flags);
1989
1990 return rc;
1991}
1992
1993/* Perform bottom half processing of work items queued by ISR.
1994 */
1995static void bh_handler(struct work_struct *work)
1996{
1997 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1998 int action;
1999
2000 if ( debug_level >= DEBUG_LEVEL_BH )
2001 printk( "%s(%d):%s bh_handler() entry\n",
2002 __FILE__,__LINE__,info->device_name);
2003
2004 info->bh_running = true;
2005
2006 while((action = bh_action(info)) != 0) {
2007
2008 /* Process work item */
2009 if ( debug_level >= DEBUG_LEVEL_BH )
2010 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2011 __FILE__,__LINE__,info->device_name, action);
2012
2013 switch (action) {
2014
2015 case BH_RECEIVE:
2016 bh_receive(info);
2017 break;
2018 case BH_TRANSMIT:
2019 bh_transmit(info);
2020 break;
2021 case BH_STATUS:
2022 bh_status(info);
2023 break;
2024 default:
2025 /* unknown work item ID */
2026 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2027 __FILE__,__LINE__,info->device_name,action);
2028 break;
2029 }
2030 }
2031
2032 if ( debug_level >= DEBUG_LEVEL_BH )
2033 printk( "%s(%d):%s bh_handler() exit\n",
2034 __FILE__,__LINE__,info->device_name);
2035}
2036
2037static void bh_receive(SLMP_INFO *info)
2038{
2039 if ( debug_level >= DEBUG_LEVEL_BH )
2040 printk( "%s(%d):%s bh_receive()\n",
2041 __FILE__,__LINE__,info->device_name);
2042
2043 while( rx_get_frame(info) );
2044}
2045
2046static void bh_transmit(SLMP_INFO *info)
2047{
2048 struct tty_struct *tty = info->port.tty;
2049
2050 if ( debug_level >= DEBUG_LEVEL_BH )
2051 printk( "%s(%d):%s bh_transmit() entry\n",
2052 __FILE__,__LINE__,info->device_name);
2053
2054 if (tty)
2055 tty_wakeup(tty);
2056}
2057
2058static void bh_status(SLMP_INFO *info)
2059{
2060 if ( debug_level >= DEBUG_LEVEL_BH )
2061 printk( "%s(%d):%s bh_status() entry\n",
2062 __FILE__,__LINE__,info->device_name);
2063
2064 info->ri_chkcount = 0;
2065 info->dsr_chkcount = 0;
2066 info->dcd_chkcount = 0;
2067 info->cts_chkcount = 0;
2068}
2069
2070static void isr_timer(SLMP_INFO * info)
2071{
2072 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2073
2074 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2075 write_reg(info, IER2, 0);
2076
2077 /* TMCS, Timer Control/Status Register
2078 *
2079 * 07 CMF, Compare match flag (read only) 1=match
2080 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2081 * 05 Reserved, must be 0
2082 * 04 TME, Timer Enable
2083 * 03..00 Reserved, must be 0
2084 *
2085 * 0000 0000
2086 */
2087 write_reg(info, (unsigned char)(timer + TMCS), 0);
2088
2089 info->irq_occurred = true;
2090
2091 if ( debug_level >= DEBUG_LEVEL_ISR )
2092 printk("%s(%d):%s isr_timer()\n",
2093 __FILE__,__LINE__,info->device_name);
2094}
2095
2096static void isr_rxint(SLMP_INFO * info)
2097{
2098 struct tty_struct *tty = info->port.tty;
2099 struct mgsl_icount *icount = &info->icount;
2100 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2101 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2102
2103 /* clear status bits */
2104 if (status)
2105 write_reg(info, SR1, status);
2106
2107 if (status2)
2108 write_reg(info, SR2, status2);
2109
2110 if ( debug_level >= DEBUG_LEVEL_ISR )
2111 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2112 __FILE__,__LINE__,info->device_name,status,status2);
2113
2114 if (info->params.mode == MGSL_MODE_ASYNC) {
2115 if (status & BRKD) {
2116 icount->brk++;
2117
2118 /* process break detection if tty control
2119 * is not set to ignore it
2120 */
2121 if (!(status & info->ignore_status_mask1)) {
2122 if (info->read_status_mask1 & BRKD) {
2123 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2124 if (tty && (info->port.flags & ASYNC_SAK))
2125 do_SAK(tty);
2126 }
2127 }
2128 }
2129 }
2130 else {
2131 if (status & (FLGD|IDLD)) {
2132 if (status & FLGD)
2133 info->icount.exithunt++;
2134 else if (status & IDLD)
2135 info->icount.rxidle++;
2136 wake_up_interruptible(&info->event_wait_q);
2137 }
2138 }
2139
2140 if (status & CDCD) {
2141 /* simulate a common modem status change interrupt
2142 * for our handler
2143 */
2144 get_signals( info );
2145 isr_io_pin(info,
2146 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2147 }
2148}
2149
2150/*
2151 * handle async rx data interrupts
2152 */
2153static void isr_rxrdy(SLMP_INFO * info)
2154{
2155 u16 status;
2156 unsigned char DataByte;
2157 struct mgsl_icount *icount = &info->icount;
2158
2159 if ( debug_level >= DEBUG_LEVEL_ISR )
2160 printk("%s(%d):%s isr_rxrdy\n",
2161 __FILE__,__LINE__,info->device_name);
2162
2163 while((status = read_reg(info,CST0)) & BIT0)
2164 {
2165 int flag = 0;
2166 bool over = false;
2167 DataByte = read_reg(info,TRB);
2168
2169 icount->rx++;
2170
2171 if ( status & (PE + FRME + OVRN) ) {
2172 printk("%s(%d):%s rxerr=%04X\n",
2173 __FILE__,__LINE__,info->device_name,status);
2174
2175 /* update error statistics */
2176 if (status & PE)
2177 icount->parity++;
2178 else if (status & FRME)
2179 icount->frame++;
2180 else if (status & OVRN)
2181 icount->overrun++;
2182
2183 /* discard char if tty control flags say so */
2184 if (status & info->ignore_status_mask2)
2185 continue;
2186
2187 status &= info->read_status_mask2;
2188
2189 if (status & PE)
2190 flag = TTY_PARITY;
2191 else if (status & FRME)
2192 flag = TTY_FRAME;
2193 if (status & OVRN) {
2194 /* Overrun is special, since it's
2195 * reported immediately, and doesn't
2196 * affect the current character
2197 */
2198 over = true;
2199 }
2200 } /* end of if (error) */
2201
2202 tty_insert_flip_char(&info->port, DataByte, flag);
2203 if (over)
2204 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2205 }
2206
2207 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2208 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2209 __FILE__,__LINE__,info->device_name,
2210 icount->rx,icount->brk,icount->parity,
2211 icount->frame,icount->overrun);
2212 }
2213
2214 tty_flip_buffer_push(&info->port);
2215}
2216
2217static void isr_txeom(SLMP_INFO * info, unsigned char status)
2218{
2219 if ( debug_level >= DEBUG_LEVEL_ISR )
2220 printk("%s(%d):%s isr_txeom status=%02x\n",
2221 __FILE__,__LINE__,info->device_name,status);
2222
2223 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2224 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2225 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2226
2227 if (status & UDRN) {
2228 write_reg(info, CMD, TXRESET);
2229 write_reg(info, CMD, TXENABLE);
2230 } else
2231 write_reg(info, CMD, TXBUFCLR);
2232
2233 /* disable and clear tx interrupts */
2234 info->ie0_value &= ~TXRDYE;
2235 info->ie1_value &= ~(IDLE + UDRN);
2236 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2237 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2238
2239 if ( info->tx_active ) {
2240 if (info->params.mode != MGSL_MODE_ASYNC) {
2241 if (status & UDRN)
2242 info->icount.txunder++;
2243 else if (status & IDLE)
2244 info->icount.txok++;
2245 }
2246
2247 info->tx_active = false;
2248 info->tx_count = info->tx_put = info->tx_get = 0;
2249
2250 del_timer(&info->tx_timer);
2251
2252 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2253 info->serial_signals &= ~SerialSignal_RTS;
2254 info->drop_rts_on_tx_done = false;
2255 set_signals(info);
2256 }
2257
2258#if SYNCLINK_GENERIC_HDLC
2259 if (info->netcount)
2260 hdlcdev_tx_done(info);
2261 else
2262#endif
2263 {
2264 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2265 tx_stop(info);
2266 return;
2267 }
2268 info->pending_bh |= BH_TRANSMIT;
2269 }
2270 }
2271}
2272
2273
2274/*
2275 * handle tx status interrupts
2276 */
2277static void isr_txint(SLMP_INFO * info)
2278{
2279 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2280
2281 /* clear status bits */
2282 write_reg(info, SR1, status);
2283
2284 if ( debug_level >= DEBUG_LEVEL_ISR )
2285 printk("%s(%d):%s isr_txint status=%02x\n",
2286 __FILE__,__LINE__,info->device_name,status);
2287
2288 if (status & (UDRN + IDLE))
2289 isr_txeom(info, status);
2290
2291 if (status & CCTS) {
2292 /* simulate a common modem status change interrupt
2293 * for our handler
2294 */
2295 get_signals( info );
2296 isr_io_pin(info,
2297 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2298
2299 }
2300}
2301
2302/*
2303 * handle async tx data interrupts
2304 */
2305static void isr_txrdy(SLMP_INFO * info)
2306{
2307 if ( debug_level >= DEBUG_LEVEL_ISR )
2308 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2309 __FILE__,__LINE__,info->device_name,info->tx_count);
2310
2311 if (info->params.mode != MGSL_MODE_ASYNC) {
2312 /* disable TXRDY IRQ, enable IDLE IRQ */
2313 info->ie0_value &= ~TXRDYE;
2314 info->ie1_value |= IDLE;
2315 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2316 return;
2317 }
2318
2319 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2320 tx_stop(info);
2321 return;
2322 }
2323
2324 if ( info->tx_count )
2325 tx_load_fifo( info );
2326 else {
2327 info->tx_active = false;
2328 info->ie0_value &= ~TXRDYE;
2329 write_reg(info, IE0, info->ie0_value);
2330 }
2331
2332 if (info->tx_count < WAKEUP_CHARS)
2333 info->pending_bh |= BH_TRANSMIT;
2334}
2335
2336static void isr_rxdmaok(SLMP_INFO * info)
2337{
2338 /* BIT7 = EOT (end of transfer)
2339 * BIT6 = EOM (end of message/frame)
2340 */
2341 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2342
2343 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2344 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2345
2346 if ( debug_level >= DEBUG_LEVEL_ISR )
2347 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2348 __FILE__,__LINE__,info->device_name,status);
2349
2350 info->pending_bh |= BH_RECEIVE;
2351}
2352
2353static void isr_rxdmaerror(SLMP_INFO * info)
2354{
2355 /* BIT5 = BOF (buffer overflow)
2356 * BIT4 = COF (counter overflow)
2357 */
2358 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2359
2360 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2361 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2362
2363 if ( debug_level >= DEBUG_LEVEL_ISR )
2364 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2365 __FILE__,__LINE__,info->device_name,status);
2366
2367 info->rx_overflow = true;
2368 info->pending_bh |= BH_RECEIVE;
2369}
2370
2371static void isr_txdmaok(SLMP_INFO * info)
2372{
2373 unsigned char status_reg1 = read_reg(info, SR1);
2374
2375 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2376 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2377 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2378
2379 if ( debug_level >= DEBUG_LEVEL_ISR )
2380 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2381 __FILE__,__LINE__,info->device_name,status_reg1);
2382
2383 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2384 write_reg16(info, TRC0, 0);
2385 info->ie0_value |= TXRDYE;
2386 write_reg(info, IE0, info->ie0_value);
2387}
2388
2389static void isr_txdmaerror(SLMP_INFO * info)
2390{
2391 /* BIT5 = BOF (buffer overflow)
2392 * BIT4 = COF (counter overflow)
2393 */
2394 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2395
2396 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2397 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2398
2399 if ( debug_level >= DEBUG_LEVEL_ISR )
2400 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2401 __FILE__,__LINE__,info->device_name,status);
2402}
2403
2404/* handle input serial signal changes
2405 */
2406static void isr_io_pin( SLMP_INFO *info, u16 status )
2407{
2408 struct mgsl_icount *icount;
2409
2410 if ( debug_level >= DEBUG_LEVEL_ISR )
2411 printk("%s(%d):isr_io_pin status=%04X\n",
2412 __FILE__,__LINE__,status);
2413
2414 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2415 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2416 icount = &info->icount;
2417 /* update input line counters */
2418 if (status & MISCSTATUS_RI_LATCHED) {
2419 icount->rng++;
2420 if ( status & SerialSignal_RI )
2421 info->input_signal_events.ri_up++;
2422 else
2423 info->input_signal_events.ri_down++;
2424 }
2425 if (status & MISCSTATUS_DSR_LATCHED) {
2426 icount->dsr++;
2427 if ( status & SerialSignal_DSR )
2428 info->input_signal_events.dsr_up++;
2429 else
2430 info->input_signal_events.dsr_down++;
2431 }
2432 if (status & MISCSTATUS_DCD_LATCHED) {
2433 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2434 info->ie1_value &= ~CDCD;
2435 write_reg(info, IE1, info->ie1_value);
2436 }
2437 icount->dcd++;
2438 if (status & SerialSignal_DCD) {
2439 info->input_signal_events.dcd_up++;
2440 } else
2441 info->input_signal_events.dcd_down++;
2442#if SYNCLINK_GENERIC_HDLC
2443 if (info->netcount) {
2444 if (status & SerialSignal_DCD)
2445 netif_carrier_on(info->netdev);
2446 else
2447 netif_carrier_off(info->netdev);
2448 }
2449#endif
2450 }
2451 if (status & MISCSTATUS_CTS_LATCHED)
2452 {
2453 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2454 info->ie1_value &= ~CCTS;
2455 write_reg(info, IE1, info->ie1_value);
2456 }
2457 icount->cts++;
2458 if ( status & SerialSignal_CTS )
2459 info->input_signal_events.cts_up++;
2460 else
2461 info->input_signal_events.cts_down++;
2462 }
2463 wake_up_interruptible(&info->status_event_wait_q);
2464 wake_up_interruptible(&info->event_wait_q);
2465
2466 if ( (info->port.flags & ASYNC_CHECK_CD) &&
2467 (status & MISCSTATUS_DCD_LATCHED) ) {
2468 if ( debug_level >= DEBUG_LEVEL_ISR )
2469 printk("%s CD now %s...", info->device_name,
2470 (status & SerialSignal_DCD) ? "on" : "off");
2471 if (status & SerialSignal_DCD)
2472 wake_up_interruptible(&info->port.open_wait);
2473 else {
2474 if ( debug_level >= DEBUG_LEVEL_ISR )
2475 printk("doing serial hangup...");
2476 if (info->port.tty)
2477 tty_hangup(info->port.tty);
2478 }
2479 }
2480
2481 if (tty_port_cts_enabled(&info->port) &&
2482 (status & MISCSTATUS_CTS_LATCHED) ) {
2483 if ( info->port.tty ) {
2484 if (info->port.tty->hw_stopped) {
2485 if (status & SerialSignal_CTS) {
2486 if ( debug_level >= DEBUG_LEVEL_ISR )
2487 printk("CTS tx start...");
2488 info->port.tty->hw_stopped = 0;
2489 tx_start(info);
2490 info->pending_bh |= BH_TRANSMIT;
2491 return;
2492 }
2493 } else {
2494 if (!(status & SerialSignal_CTS)) {
2495 if ( debug_level >= DEBUG_LEVEL_ISR )
2496 printk("CTS tx stop...");
2497 info->port.tty->hw_stopped = 1;
2498 tx_stop(info);
2499 }
2500 }
2501 }
2502 }
2503 }
2504
2505 info->pending_bh |= BH_STATUS;
2506}
2507
2508/* Interrupt service routine entry point.
2509 *
2510 * Arguments:
2511 * irq interrupt number that caused interrupt
2512 * dev_id device ID supplied during interrupt registration
2513 * regs interrupted processor context
2514 */
2515static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2516{
2517 SLMP_INFO *info = dev_id;
2518 unsigned char status, status0, status1=0;
2519 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2520 unsigned char timerstatus0, timerstatus1=0;
2521 unsigned char shift;
2522 unsigned int i;
2523 unsigned short tmp;
2524
2525 if ( debug_level >= DEBUG_LEVEL_ISR )
2526 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2527 __FILE__, __LINE__, info->irq_level);
2528
2529 spin_lock(&info->lock);
2530
2531 for(;;) {
2532
2533 /* get status for SCA0 (ports 0-1) */
2534 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2535 status0 = (unsigned char)tmp;
2536 dmastatus0 = (unsigned char)(tmp>>8);
2537 timerstatus0 = read_reg(info, ISR2);
2538
2539 if ( debug_level >= DEBUG_LEVEL_ISR )
2540 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2541 __FILE__, __LINE__, info->device_name,
2542 status0, dmastatus0, timerstatus0);
2543
2544 if (info->port_count == 4) {
2545 /* get status for SCA1 (ports 2-3) */
2546 tmp = read_reg16(info->port_array[2], ISR0);
2547 status1 = (unsigned char)tmp;
2548 dmastatus1 = (unsigned char)(tmp>>8);
2549 timerstatus1 = read_reg(info->port_array[2], ISR2);
2550
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2553 __FILE__,__LINE__,info->device_name,
2554 status1,dmastatus1,timerstatus1);
2555 }
2556
2557 if (!status0 && !dmastatus0 && !timerstatus0 &&
2558 !status1 && !dmastatus1 && !timerstatus1)
2559 break;
2560
2561 for(i=0; i < info->port_count ; i++) {
2562 if (info->port_array[i] == NULL)
2563 continue;
2564 if (i < 2) {
2565 status = status0;
2566 dmastatus = dmastatus0;
2567 } else {
2568 status = status1;
2569 dmastatus = dmastatus1;
2570 }
2571
2572 shift = i & 1 ? 4 :0;
2573
2574 if (status & BIT0 << shift)
2575 isr_rxrdy(info->port_array[i]);
2576 if (status & BIT1 << shift)
2577 isr_txrdy(info->port_array[i]);
2578 if (status & BIT2 << shift)
2579 isr_rxint(info->port_array[i]);
2580 if (status & BIT3 << shift)
2581 isr_txint(info->port_array[i]);
2582
2583 if (dmastatus & BIT0 << shift)
2584 isr_rxdmaerror(info->port_array[i]);
2585 if (dmastatus & BIT1 << shift)
2586 isr_rxdmaok(info->port_array[i]);
2587 if (dmastatus & BIT2 << shift)
2588 isr_txdmaerror(info->port_array[i]);
2589 if (dmastatus & BIT3 << shift)
2590 isr_txdmaok(info->port_array[i]);
2591 }
2592
2593 if (timerstatus0 & (BIT5 | BIT4))
2594 isr_timer(info->port_array[0]);
2595 if (timerstatus0 & (BIT7 | BIT6))
2596 isr_timer(info->port_array[1]);
2597 if (timerstatus1 & (BIT5 | BIT4))
2598 isr_timer(info->port_array[2]);
2599 if (timerstatus1 & (BIT7 | BIT6))
2600 isr_timer(info->port_array[3]);
2601 }
2602
2603 for(i=0; i < info->port_count ; i++) {
2604 SLMP_INFO * port = info->port_array[i];
2605
2606 /* Request bottom half processing if there's something
2607 * for it to do and the bh is not already running.
2608 *
2609 * Note: startup adapter diags require interrupts.
2610 * do not request bottom half processing if the
2611 * device is not open in a normal mode.
2612 */
2613 if ( port && (port->port.count || port->netcount) &&
2614 port->pending_bh && !port->bh_running &&
2615 !port->bh_requested ) {
2616 if ( debug_level >= DEBUG_LEVEL_ISR )
2617 printk("%s(%d):%s queueing bh task.\n",
2618 __FILE__,__LINE__,port->device_name);
2619 schedule_work(&port->task);
2620 port->bh_requested = true;
2621 }
2622 }
2623
2624 spin_unlock(&info->lock);
2625
2626 if ( debug_level >= DEBUG_LEVEL_ISR )
2627 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2628 __FILE__, __LINE__, info->irq_level);
2629 return IRQ_HANDLED;
2630}
2631
2632/* Initialize and start device.
2633 */
2634static int startup(SLMP_INFO * info)
2635{
2636 if ( debug_level >= DEBUG_LEVEL_INFO )
2637 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2638
2639 if (info->port.flags & ASYNC_INITIALIZED)
2640 return 0;
2641
2642 if (!info->tx_buf) {
2643 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2644 if (!info->tx_buf) {
2645 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2646 __FILE__,__LINE__,info->device_name);
2647 return -ENOMEM;
2648 }
2649 }
2650
2651 info->pending_bh = 0;
2652
2653 memset(&info->icount, 0, sizeof(info->icount));
2654
2655 /* program hardware for current parameters */
2656 reset_port(info);
2657
2658 change_params(info);
2659
2660 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2661
2662 if (info->port.tty)
2663 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2664
2665 info->port.flags |= ASYNC_INITIALIZED;
2666
2667 return 0;
2668}
2669
2670/* Called by close() and hangup() to shutdown hardware
2671 */
2672static void shutdown(SLMP_INFO * info)
2673{
2674 unsigned long flags;
2675
2676 if (!(info->port.flags & ASYNC_INITIALIZED))
2677 return;
2678
2679 if (debug_level >= DEBUG_LEVEL_INFO)
2680 printk("%s(%d):%s synclinkmp_shutdown()\n",
2681 __FILE__,__LINE__, info->device_name );
2682
2683 /* clear status wait queue because status changes */
2684 /* can't happen after shutting down the hardware */
2685 wake_up_interruptible(&info->status_event_wait_q);
2686 wake_up_interruptible(&info->event_wait_q);
2687
2688 del_timer(&info->tx_timer);
2689 del_timer(&info->status_timer);
2690
2691 kfree(info->tx_buf);
2692 info->tx_buf = NULL;
2693
2694 spin_lock_irqsave(&info->lock,flags);
2695
2696 reset_port(info);
2697
2698 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2699 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2700 set_signals(info);
2701 }
2702
2703 spin_unlock_irqrestore(&info->lock,flags);
2704
2705 if (info->port.tty)
2706 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2707
2708 info->port.flags &= ~ASYNC_INITIALIZED;
2709}
2710
2711static void program_hw(SLMP_INFO *info)
2712{
2713 unsigned long flags;
2714
2715 spin_lock_irqsave(&info->lock,flags);
2716
2717 rx_stop(info);
2718 tx_stop(info);
2719
2720 info->tx_count = info->tx_put = info->tx_get = 0;
2721
2722 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2723 hdlc_mode(info);
2724 else
2725 async_mode(info);
2726
2727 set_signals(info);
2728
2729 info->dcd_chkcount = 0;
2730 info->cts_chkcount = 0;
2731 info->ri_chkcount = 0;
2732 info->dsr_chkcount = 0;
2733
2734 info->ie1_value |= (CDCD|CCTS);
2735 write_reg(info, IE1, info->ie1_value);
2736
2737 get_signals(info);
2738
2739 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2740 rx_start(info);
2741
2742 spin_unlock_irqrestore(&info->lock,flags);
2743}
2744
2745/* Reconfigure adapter based on new parameters
2746 */
2747static void change_params(SLMP_INFO *info)
2748{
2749 unsigned cflag;
2750 int bits_per_char;
2751
2752 if (!info->port.tty)
2753 return;
2754
2755 if (debug_level >= DEBUG_LEVEL_INFO)
2756 printk("%s(%d):%s change_params()\n",
2757 __FILE__,__LINE__, info->device_name );
2758
2759 cflag = info->port.tty->termios.c_cflag;
2760
2761 /* if B0 rate (hangup) specified then negate RTS and DTR */
2762 /* otherwise assert RTS and DTR */
2763 if (cflag & CBAUD)
2764 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2765 else
2766 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2767
2768 /* byte size and parity */
2769
2770 switch (cflag & CSIZE) {
2771 case CS5: info->params.data_bits = 5; break;
2772 case CS6: info->params.data_bits = 6; break;
2773 case CS7: info->params.data_bits = 7; break;
2774 case CS8: info->params.data_bits = 8; break;
2775 /* Never happens, but GCC is too dumb to figure it out */
2776 default: info->params.data_bits = 7; break;
2777 }
2778
2779 if (cflag & CSTOPB)
2780 info->params.stop_bits = 2;
2781 else
2782 info->params.stop_bits = 1;
2783
2784 info->params.parity = ASYNC_PARITY_NONE;
2785 if (cflag & PARENB) {
2786 if (cflag & PARODD)
2787 info->params.parity = ASYNC_PARITY_ODD;
2788 else
2789 info->params.parity = ASYNC_PARITY_EVEN;
2790#ifdef CMSPAR
2791 if (cflag & CMSPAR)
2792 info->params.parity = ASYNC_PARITY_SPACE;
2793#endif
2794 }
2795
2796 /* calculate number of jiffies to transmit a full
2797 * FIFO (32 bytes) at specified data rate
2798 */
2799 bits_per_char = info->params.data_bits +
2800 info->params.stop_bits + 1;
2801
2802 /* if port data rate is set to 460800 or less then
2803 * allow tty settings to override, otherwise keep the
2804 * current data rate.
2805 */
2806 if (info->params.data_rate <= 460800) {
2807 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2808 }
2809
2810 if ( info->params.data_rate ) {
2811 info->timeout = (32*HZ*bits_per_char) /
2812 info->params.data_rate;
2813 }
2814 info->timeout += HZ/50; /* Add .02 seconds of slop */
2815
2816 if (cflag & CRTSCTS)
2817 info->port.flags |= ASYNC_CTS_FLOW;
2818 else
2819 info->port.flags &= ~ASYNC_CTS_FLOW;
2820
2821 if (cflag & CLOCAL)
2822 info->port.flags &= ~ASYNC_CHECK_CD;
2823 else
2824 info->port.flags |= ASYNC_CHECK_CD;
2825
2826 /* process tty input control flags */
2827
2828 info->read_status_mask2 = OVRN;
2829 if (I_INPCK(info->port.tty))
2830 info->read_status_mask2 |= PE | FRME;
2831 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2832 info->read_status_mask1 |= BRKD;
2833 if (I_IGNPAR(info->port.tty))
2834 info->ignore_status_mask2 |= PE | FRME;
2835 if (I_IGNBRK(info->port.tty)) {
2836 info->ignore_status_mask1 |= BRKD;
2837 /* If ignoring parity and break indicators, ignore
2838 * overruns too. (For real raw support).
2839 */
2840 if (I_IGNPAR(info->port.tty))
2841 info->ignore_status_mask2 |= OVRN;
2842 }
2843
2844 program_hw(info);
2845}
2846
2847static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2848{
2849 int err;
2850
2851 if (debug_level >= DEBUG_LEVEL_INFO)
2852 printk("%s(%d):%s get_params()\n",
2853 __FILE__,__LINE__, info->device_name);
2854
2855 if (!user_icount) {
2856 memset(&info->icount, 0, sizeof(info->icount));
2857 } else {
2858 mutex_lock(&info->port.mutex);
2859 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2860 mutex_unlock(&info->port.mutex);
2861 if (err)
2862 return -EFAULT;
2863 }
2864
2865 return 0;
2866}
2867
2868static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2869{
2870 int err;
2871 if (debug_level >= DEBUG_LEVEL_INFO)
2872 printk("%s(%d):%s get_params()\n",
2873 __FILE__,__LINE__, info->device_name);
2874
2875 mutex_lock(&info->port.mutex);
2876 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2877 mutex_unlock(&info->port.mutex);
2878 if (err) {
2879 if ( debug_level >= DEBUG_LEVEL_INFO )
2880 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2881 __FILE__,__LINE__,info->device_name);
2882 return -EFAULT;
2883 }
2884
2885 return 0;
2886}
2887
2888static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2889{
2890 unsigned long flags;
2891 MGSL_PARAMS tmp_params;
2892 int err;
2893
2894 if (debug_level >= DEBUG_LEVEL_INFO)
2895 printk("%s(%d):%s set_params\n",
2896 __FILE__,__LINE__,info->device_name );
2897 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2898 if (err) {
2899 if ( debug_level >= DEBUG_LEVEL_INFO )
2900 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2901 __FILE__,__LINE__,info->device_name);
2902 return -EFAULT;
2903 }
2904
2905 mutex_lock(&info->port.mutex);
2906 spin_lock_irqsave(&info->lock,flags);
2907 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2908 spin_unlock_irqrestore(&info->lock,flags);
2909
2910 change_params(info);
2911 mutex_unlock(&info->port.mutex);
2912
2913 return 0;
2914}
2915
2916static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2917{
2918 int err;
2919
2920 if (debug_level >= DEBUG_LEVEL_INFO)
2921 printk("%s(%d):%s get_txidle()=%d\n",
2922 __FILE__,__LINE__, info->device_name, info->idle_mode);
2923
2924 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2925 if (err) {
2926 if ( debug_level >= DEBUG_LEVEL_INFO )
2927 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2928 __FILE__,__LINE__,info->device_name);
2929 return -EFAULT;
2930 }
2931
2932 return 0;
2933}
2934
2935static int set_txidle(SLMP_INFO * info, int idle_mode)
2936{
2937 unsigned long flags;
2938
2939 if (debug_level >= DEBUG_LEVEL_INFO)
2940 printk("%s(%d):%s set_txidle(%d)\n",
2941 __FILE__,__LINE__,info->device_name, idle_mode );
2942
2943 spin_lock_irqsave(&info->lock,flags);
2944 info->idle_mode = idle_mode;
2945 tx_set_idle( info );
2946 spin_unlock_irqrestore(&info->lock,flags);
2947 return 0;
2948}
2949
2950static int tx_enable(SLMP_INFO * info, int enable)
2951{
2952 unsigned long flags;
2953
2954 if (debug_level >= DEBUG_LEVEL_INFO)
2955 printk("%s(%d):%s tx_enable(%d)\n",
2956 __FILE__,__LINE__,info->device_name, enable);
2957
2958 spin_lock_irqsave(&info->lock,flags);
2959 if ( enable ) {
2960 if ( !info->tx_enabled ) {
2961 tx_start(info);
2962 }
2963 } else {
2964 if ( info->tx_enabled )
2965 tx_stop(info);
2966 }
2967 spin_unlock_irqrestore(&info->lock,flags);
2968 return 0;
2969}
2970
2971/* abort send HDLC frame
2972 */
2973static int tx_abort(SLMP_INFO * info)
2974{
2975 unsigned long flags;
2976
2977 if (debug_level >= DEBUG_LEVEL_INFO)
2978 printk("%s(%d):%s tx_abort()\n",
2979 __FILE__,__LINE__,info->device_name);
2980
2981 spin_lock_irqsave(&info->lock,flags);
2982 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2983 info->ie1_value &= ~UDRN;
2984 info->ie1_value |= IDLE;
2985 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2986 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2987
2988 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2989 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2990
2991 write_reg(info, CMD, TXABORT);
2992 }
2993 spin_unlock_irqrestore(&info->lock,flags);
2994 return 0;
2995}
2996
2997static int rx_enable(SLMP_INFO * info, int enable)
2998{
2999 unsigned long flags;
3000
3001 if (debug_level >= DEBUG_LEVEL_INFO)
3002 printk("%s(%d):%s rx_enable(%d)\n",
3003 __FILE__,__LINE__,info->device_name,enable);
3004
3005 spin_lock_irqsave(&info->lock,flags);
3006 if ( enable ) {
3007 if ( !info->rx_enabled )
3008 rx_start(info);
3009 } else {
3010 if ( info->rx_enabled )
3011 rx_stop(info);
3012 }
3013 spin_unlock_irqrestore(&info->lock,flags);
3014 return 0;
3015}
3016
3017/* wait for specified event to occur
3018 */
3019static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3020{
3021 unsigned long flags;
3022 int s;
3023 int rc=0;
3024 struct mgsl_icount cprev, cnow;
3025 int events;
3026 int mask;
3027 struct _input_signal_events oldsigs, newsigs;
3028 DECLARE_WAITQUEUE(wait, current);
3029
3030 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3031 if (rc) {
3032 return -EFAULT;
3033 }
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3037 __FILE__,__LINE__,info->device_name,mask);
3038
3039 spin_lock_irqsave(&info->lock,flags);
3040
3041 /* return immediately if state matches requested events */
3042 get_signals(info);
3043 s = info->serial_signals;
3044
3045 events = mask &
3046 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3047 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3048 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3049 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3050 if (events) {
3051 spin_unlock_irqrestore(&info->lock,flags);
3052 goto exit;
3053 }
3054
3055 /* save current irq counts */
3056 cprev = info->icount;
3057 oldsigs = info->input_signal_events;
3058
3059 /* enable hunt and idle irqs if needed */
3060 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3061 unsigned char oldval = info->ie1_value;
3062 unsigned char newval = oldval +
3063 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3064 (mask & MgslEvent_IdleReceived ? IDLD:0);
3065 if ( oldval != newval ) {
3066 info->ie1_value = newval;
3067 write_reg(info, IE1, info->ie1_value);
3068 }
3069 }
3070
3071 set_current_state(TASK_INTERRUPTIBLE);
3072 add_wait_queue(&info->event_wait_q, &wait);
3073
3074 spin_unlock_irqrestore(&info->lock,flags);
3075
3076 for(;;) {
3077 schedule();
3078 if (signal_pending(current)) {
3079 rc = -ERESTARTSYS;
3080 break;
3081 }
3082
3083 /* get current irq counts */
3084 spin_lock_irqsave(&info->lock,flags);
3085 cnow = info->icount;
3086 newsigs = info->input_signal_events;
3087 set_current_state(TASK_INTERRUPTIBLE);
3088 spin_unlock_irqrestore(&info->lock,flags);
3089
3090 /* if no change, wait aborted for some reason */
3091 if (newsigs.dsr_up == oldsigs.dsr_up &&
3092 newsigs.dsr_down == oldsigs.dsr_down &&
3093 newsigs.dcd_up == oldsigs.dcd_up &&
3094 newsigs.dcd_down == oldsigs.dcd_down &&
3095 newsigs.cts_up == oldsigs.cts_up &&
3096 newsigs.cts_down == oldsigs.cts_down &&
3097 newsigs.ri_up == oldsigs.ri_up &&
3098 newsigs.ri_down == oldsigs.ri_down &&
3099 cnow.exithunt == cprev.exithunt &&
3100 cnow.rxidle == cprev.rxidle) {
3101 rc = -EIO;
3102 break;
3103 }
3104
3105 events = mask &
3106 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3107 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3108 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3109 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3110 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3111 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3112 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3113 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3114 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3115 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3116 if (events)
3117 break;
3118
3119 cprev = cnow;
3120 oldsigs = newsigs;
3121 }
3122
3123 remove_wait_queue(&info->event_wait_q, &wait);
3124 set_current_state(TASK_RUNNING);
3125
3126
3127 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3128 spin_lock_irqsave(&info->lock,flags);
3129 if (!waitqueue_active(&info->event_wait_q)) {
3130 /* disable enable exit hunt mode/idle rcvd IRQs */
3131 info->ie1_value &= ~(FLGD|IDLD);
3132 write_reg(info, IE1, info->ie1_value);
3133 }
3134 spin_unlock_irqrestore(&info->lock,flags);
3135 }
3136exit:
3137 if ( rc == 0 )
3138 PUT_USER(rc, events, mask_ptr);
3139
3140 return rc;
3141}
3142
3143static int modem_input_wait(SLMP_INFO *info,int arg)
3144{
3145 unsigned long flags;
3146 int rc;
3147 struct mgsl_icount cprev, cnow;
3148 DECLARE_WAITQUEUE(wait, current);
3149
3150 /* save current irq counts */
3151 spin_lock_irqsave(&info->lock,flags);
3152 cprev = info->icount;
3153 add_wait_queue(&info->status_event_wait_q, &wait);
3154 set_current_state(TASK_INTERRUPTIBLE);
3155 spin_unlock_irqrestore(&info->lock,flags);
3156
3157 for(;;) {
3158 schedule();
3159 if (signal_pending(current)) {
3160 rc = -ERESTARTSYS;
3161 break;
3162 }
3163
3164 /* get new irq counts */
3165 spin_lock_irqsave(&info->lock,flags);
3166 cnow = info->icount;
3167 set_current_state(TASK_INTERRUPTIBLE);
3168 spin_unlock_irqrestore(&info->lock,flags);
3169
3170 /* if no change, wait aborted for some reason */
3171 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3172 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3173 rc = -EIO;
3174 break;
3175 }
3176
3177 /* check for change in caller specified modem input */
3178 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3179 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3180 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3181 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3182 rc = 0;
3183 break;
3184 }
3185
3186 cprev = cnow;
3187 }
3188 remove_wait_queue(&info->status_event_wait_q, &wait);
3189 set_current_state(TASK_RUNNING);
3190 return rc;
3191}
3192
3193/* return the state of the serial control and status signals
3194 */
3195static int tiocmget(struct tty_struct *tty)
3196{
3197 SLMP_INFO *info = tty->driver_data;
3198 unsigned int result;
3199 unsigned long flags;
3200
3201 spin_lock_irqsave(&info->lock,flags);
3202 get_signals(info);
3203 spin_unlock_irqrestore(&info->lock,flags);
3204
3205 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3206 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3207 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3208 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3209 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3210 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3211
3212 if (debug_level >= DEBUG_LEVEL_INFO)
3213 printk("%s(%d):%s tiocmget() value=%08X\n",
3214 __FILE__,__LINE__, info->device_name, result );
3215 return result;
3216}
3217
3218/* set modem control signals (DTR/RTS)
3219 */
3220static int tiocmset(struct tty_struct *tty,
3221 unsigned int set, unsigned int clear)
3222{
3223 SLMP_INFO *info = tty->driver_data;
3224 unsigned long flags;
3225
3226 if (debug_level >= DEBUG_LEVEL_INFO)
3227 printk("%s(%d):%s tiocmset(%x,%x)\n",
3228 __FILE__,__LINE__,info->device_name, set, clear);
3229
3230 if (set & TIOCM_RTS)
3231 info->serial_signals |= SerialSignal_RTS;
3232 if (set & TIOCM_DTR)
3233 info->serial_signals |= SerialSignal_DTR;
3234 if (clear & TIOCM_RTS)
3235 info->serial_signals &= ~SerialSignal_RTS;
3236 if (clear & TIOCM_DTR)
3237 info->serial_signals &= ~SerialSignal_DTR;
3238
3239 spin_lock_irqsave(&info->lock,flags);
3240 set_signals(info);
3241 spin_unlock_irqrestore(&info->lock,flags);
3242
3243 return 0;
3244}
3245
3246static int carrier_raised(struct tty_port *port)
3247{
3248 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3249 unsigned long flags;
3250
3251 spin_lock_irqsave(&info->lock,flags);
3252 get_signals(info);
3253 spin_unlock_irqrestore(&info->lock,flags);
3254
3255 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3256}
3257
3258static void dtr_rts(struct tty_port *port, int on)
3259{
3260 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3261 unsigned long flags;
3262
3263 spin_lock_irqsave(&info->lock,flags);
3264 if (on)
3265 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3266 else
3267 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3268 set_signals(info);
3269 spin_unlock_irqrestore(&info->lock,flags);
3270}
3271
3272/* Block the current process until the specified port is ready to open.
3273 */
3274static int block_til_ready(struct tty_struct *tty, struct file *filp,
3275 SLMP_INFO *info)
3276{
3277 DECLARE_WAITQUEUE(wait, current);
3278 int retval;
3279 bool do_clocal = false;
3280 unsigned long flags;
3281 int cd;
3282 struct tty_port *port = &info->port;
3283
3284 if (debug_level >= DEBUG_LEVEL_INFO)
3285 printk("%s(%d):%s block_til_ready()\n",
3286 __FILE__,__LINE__, tty->driver->name );
3287
3288 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3289 /* nonblock mode is set or port is not enabled */
3290 /* just verify that callout device is not active */
3291 port->flags |= ASYNC_NORMAL_ACTIVE;
3292 return 0;
3293 }
3294
3295 if (C_CLOCAL(tty))
3296 do_clocal = true;
3297
3298 /* Wait for carrier detect and the line to become
3299 * free (i.e., not in use by the callout). While we are in
3300 * this loop, port->count is dropped by one, so that
3301 * close() knows when to free things. We restore it upon
3302 * exit, either normal or abnormal.
3303 */
3304
3305 retval = 0;
3306 add_wait_queue(&port->open_wait, &wait);
3307
3308 if (debug_level >= DEBUG_LEVEL_INFO)
3309 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3310 __FILE__,__LINE__, tty->driver->name, port->count );
3311
3312 spin_lock_irqsave(&info->lock, flags);
3313 port->count--;
3314 spin_unlock_irqrestore(&info->lock, flags);
3315 port->blocked_open++;
3316
3317 while (1) {
3318 if (C_BAUD(tty) && test_bit(ASYNCB_INITIALIZED, &port->flags))
3319 tty_port_raise_dtr_rts(port);
3320
3321 set_current_state(TASK_INTERRUPTIBLE);
3322
3323 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3324 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3325 -EAGAIN : -ERESTARTSYS;
3326 break;
3327 }
3328
3329 cd = tty_port_carrier_raised(port);
3330 if (do_clocal || cd)
3331 break;
3332
3333 if (signal_pending(current)) {
3334 retval = -ERESTARTSYS;
3335 break;
3336 }
3337
3338 if (debug_level >= DEBUG_LEVEL_INFO)
3339 printk("%s(%d):%s block_til_ready() count=%d\n",
3340 __FILE__,__LINE__, tty->driver->name, port->count );
3341
3342 tty_unlock(tty);
3343 schedule();
3344 tty_lock(tty);
3345 }
3346
3347 set_current_state(TASK_RUNNING);
3348 remove_wait_queue(&port->open_wait, &wait);
3349 if (!tty_hung_up_p(filp))
3350 port->count++;
3351 port->blocked_open--;
3352
3353 if (debug_level >= DEBUG_LEVEL_INFO)
3354 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3355 __FILE__,__LINE__, tty->driver->name, port->count );
3356
3357 if (!retval)
3358 port->flags |= ASYNC_NORMAL_ACTIVE;
3359
3360 return retval;
3361}
3362
3363static int alloc_dma_bufs(SLMP_INFO *info)
3364{
3365 unsigned short BuffersPerFrame;
3366 unsigned short BufferCount;
3367
3368 // Force allocation to start at 64K boundary for each port.
3369 // This is necessary because *all* buffer descriptors for a port
3370 // *must* be in the same 64K block. All descriptors on a port
3371 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3372 // into the CBP register.
3373 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3374
3375 /* Calculate the number of DMA buffers necessary to hold the */
3376 /* largest allowable frame size. Note: If the max frame size is */
3377 /* not an even multiple of the DMA buffer size then we need to */
3378 /* round the buffer count per frame up one. */
3379
3380 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3381 if ( info->max_frame_size % SCABUFSIZE )
3382 BuffersPerFrame++;
3383
3384 /* calculate total number of data buffers (SCABUFSIZE) possible
3385 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3386 * for the descriptor list (BUFFERLISTSIZE).
3387 */
3388 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3389
3390 /* limit number of buffers to maximum amount of descriptors */
3391 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3392 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3393
3394 /* use enough buffers to transmit one max size frame */
3395 info->tx_buf_count = BuffersPerFrame + 1;
3396
3397 /* never use more than half the available buffers for transmit */
3398 if (info->tx_buf_count > (BufferCount/2))
3399 info->tx_buf_count = BufferCount/2;
3400
3401 if (info->tx_buf_count > SCAMAXDESC)
3402 info->tx_buf_count = SCAMAXDESC;
3403
3404 /* use remaining buffers for receive */
3405 info->rx_buf_count = BufferCount - info->tx_buf_count;
3406
3407 if (info->rx_buf_count > SCAMAXDESC)
3408 info->rx_buf_count = SCAMAXDESC;
3409
3410 if ( debug_level >= DEBUG_LEVEL_INFO )
3411 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3412 __FILE__,__LINE__, info->device_name,
3413 info->tx_buf_count,info->rx_buf_count);
3414
3415 if ( alloc_buf_list( info ) < 0 ||
3416 alloc_frame_bufs(info,
3417 info->rx_buf_list,
3418 info->rx_buf_list_ex,
3419 info->rx_buf_count) < 0 ||
3420 alloc_frame_bufs(info,
3421 info->tx_buf_list,
3422 info->tx_buf_list_ex,
3423 info->tx_buf_count) < 0 ||
3424 alloc_tmp_rx_buf(info) < 0 ) {
3425 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3426 __FILE__,__LINE__, info->device_name);
3427 return -ENOMEM;
3428 }
3429
3430 rx_reset_buffers( info );
3431
3432 return 0;
3433}
3434
3435/* Allocate DMA buffers for the transmit and receive descriptor lists.
3436 */
3437static int alloc_buf_list(SLMP_INFO *info)
3438{
3439 unsigned int i;
3440
3441 /* build list in adapter shared memory */
3442 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3443 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3444 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3445
3446 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3447
3448 /* Save virtual address pointers to the receive and */
3449 /* transmit buffer lists. (Receive 1st). These pointers will */
3450 /* be used by the processor to access the lists. */
3451 info->rx_buf_list = (SCADESC *)info->buffer_list;
3452
3453 info->tx_buf_list = (SCADESC *)info->buffer_list;
3454 info->tx_buf_list += info->rx_buf_count;
3455
3456 /* Build links for circular buffer entry lists (tx and rx)
3457 *
3458 * Note: links are physical addresses read by the SCA device
3459 * to determine the next buffer entry to use.
3460 */
3461
3462 for ( i = 0; i < info->rx_buf_count; i++ ) {
3463 /* calculate and store physical address of this buffer entry */
3464 info->rx_buf_list_ex[i].phys_entry =
3465 info->buffer_list_phys + (i * SCABUFSIZE);
3466
3467 /* calculate and store physical address of */
3468 /* next entry in cirular list of entries */
3469 info->rx_buf_list[i].next = info->buffer_list_phys;
3470 if ( i < info->rx_buf_count - 1 )
3471 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3472
3473 info->rx_buf_list[i].length = SCABUFSIZE;
3474 }
3475
3476 for ( i = 0; i < info->tx_buf_count; i++ ) {
3477 /* calculate and store physical address of this buffer entry */
3478 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3479 ((info->rx_buf_count + i) * sizeof(SCADESC));
3480
3481 /* calculate and store physical address of */
3482 /* next entry in cirular list of entries */
3483
3484 info->tx_buf_list[i].next = info->buffer_list_phys +
3485 info->rx_buf_count * sizeof(SCADESC);
3486
3487 if ( i < info->tx_buf_count - 1 )
3488 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3489 }
3490
3491 return 0;
3492}
3493
3494/* Allocate the frame DMA buffers used by the specified buffer list.
3495 */
3496static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3497{
3498 int i;
3499 unsigned long phys_addr;
3500
3501 for ( i = 0; i < count; i++ ) {
3502 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3503 phys_addr = info->port_array[0]->last_mem_alloc;
3504 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3505
3506 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3507 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3508 }
3509
3510 return 0;
3511}
3512
3513static void free_dma_bufs(SLMP_INFO *info)
3514{
3515 info->buffer_list = NULL;
3516 info->rx_buf_list = NULL;
3517 info->tx_buf_list = NULL;
3518}
3519
3520/* allocate buffer large enough to hold max_frame_size.
3521 * This buffer is used to pass an assembled frame to the line discipline.
3522 */
3523static int alloc_tmp_rx_buf(SLMP_INFO *info)
3524{
3525 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3526 if (info->tmp_rx_buf == NULL)
3527 return -ENOMEM;
3528 /* unused flag buffer to satisfy receive_buf calling interface */
3529 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3530 if (!info->flag_buf) {
3531 kfree(info->tmp_rx_buf);
3532 info->tmp_rx_buf = NULL;
3533 return -ENOMEM;
3534 }
3535 return 0;
3536}
3537
3538static void free_tmp_rx_buf(SLMP_INFO *info)
3539{
3540 kfree(info->tmp_rx_buf);
3541 info->tmp_rx_buf = NULL;
3542 kfree(info->flag_buf);
3543 info->flag_buf = NULL;
3544}
3545
3546static int claim_resources(SLMP_INFO *info)
3547{
3548 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3549 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3550 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3551 info->init_error = DiagStatus_AddressConflict;
3552 goto errout;
3553 }
3554 else
3555 info->shared_mem_requested = true;
3556
3557 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3558 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3559 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3560 info->init_error = DiagStatus_AddressConflict;
3561 goto errout;
3562 }
3563 else
3564 info->lcr_mem_requested = true;
3565
3566 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3567 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3568 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3569 info->init_error = DiagStatus_AddressConflict;
3570 goto errout;
3571 }
3572 else
3573 info->sca_base_requested = true;
3574
3575 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3576 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3577 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3578 info->init_error = DiagStatus_AddressConflict;
3579 goto errout;
3580 }
3581 else
3582 info->sca_statctrl_requested = true;
3583
3584 info->memory_base = ioremap_nocache(info->phys_memory_base,
3585 SCA_MEM_SIZE);
3586 if (!info->memory_base) {
3587 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3588 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3589 info->init_error = DiagStatus_CantAssignPciResources;
3590 goto errout;
3591 }
3592
3593 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3594 if (!info->lcr_base) {
3595 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3596 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3597 info->init_error = DiagStatus_CantAssignPciResources;
3598 goto errout;
3599 }
3600 info->lcr_base += info->lcr_offset;
3601
3602 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3603 if (!info->sca_base) {
3604 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3605 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3606 info->init_error = DiagStatus_CantAssignPciResources;
3607 goto errout;
3608 }
3609 info->sca_base += info->sca_offset;
3610
3611 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3612 PAGE_SIZE);
3613 if (!info->statctrl_base) {
3614 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3616 info->init_error = DiagStatus_CantAssignPciResources;
3617 goto errout;
3618 }
3619 info->statctrl_base += info->statctrl_offset;
3620
3621 if ( !memory_test(info) ) {
3622 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3623 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3624 info->init_error = DiagStatus_MemoryError;
3625 goto errout;
3626 }
3627
3628 return 0;
3629
3630errout:
3631 release_resources( info );
3632 return -ENODEV;
3633}
3634
3635static void release_resources(SLMP_INFO *info)
3636{
3637 if ( debug_level >= DEBUG_LEVEL_INFO )
3638 printk( "%s(%d):%s release_resources() entry\n",
3639 __FILE__,__LINE__,info->device_name );
3640
3641 if ( info->irq_requested ) {
3642 free_irq(info->irq_level, info);
3643 info->irq_requested = false;
3644 }
3645
3646 if ( info->shared_mem_requested ) {
3647 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3648 info->shared_mem_requested = false;
3649 }
3650 if ( info->lcr_mem_requested ) {
3651 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3652 info->lcr_mem_requested = false;
3653 }
3654 if ( info->sca_base_requested ) {
3655 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3656 info->sca_base_requested = false;
3657 }
3658 if ( info->sca_statctrl_requested ) {
3659 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3660 info->sca_statctrl_requested = false;
3661 }
3662
3663 if (info->memory_base){
3664 iounmap(info->memory_base);
3665 info->memory_base = NULL;
3666 }
3667
3668 if (info->sca_base) {
3669 iounmap(info->sca_base - info->sca_offset);
3670 info->sca_base=NULL;
3671 }
3672
3673 if (info->statctrl_base) {
3674 iounmap(info->statctrl_base - info->statctrl_offset);
3675 info->statctrl_base=NULL;
3676 }
3677
3678 if (info->lcr_base){
3679 iounmap(info->lcr_base - info->lcr_offset);
3680 info->lcr_base = NULL;
3681 }
3682
3683 if ( debug_level >= DEBUG_LEVEL_INFO )
3684 printk( "%s(%d):%s release_resources() exit\n",
3685 __FILE__,__LINE__,info->device_name );
3686}
3687
3688/* Add the specified device instance data structure to the
3689 * global linked list of devices and increment the device count.
3690 */
3691static int add_device(SLMP_INFO *info)
3692{
3693 info->next_device = NULL;
3694 info->line = synclinkmp_device_count;
3695 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3696
3697 if (info->line < MAX_DEVICES) {
3698 if (maxframe[info->line])
3699 info->max_frame_size = maxframe[info->line];
3700 }
3701
3702 synclinkmp_device_count++;
3703
3704 if ( !synclinkmp_device_list )
3705 synclinkmp_device_list = info;
3706 else {
3707 SLMP_INFO *current_dev = synclinkmp_device_list;
3708 while( current_dev->next_device )
3709 current_dev = current_dev->next_device;
3710 current_dev->next_device = info;
3711 }
3712
3713 if ( info->max_frame_size < 4096 )
3714 info->max_frame_size = 4096;
3715 else if ( info->max_frame_size > 65535 )
3716 info->max_frame_size = 65535;
3717
3718 printk( "SyncLink MultiPort %s: "
3719 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3720 info->device_name,
3721 info->phys_sca_base,
3722 info->phys_memory_base,
3723 info->phys_statctrl_base,
3724 info->phys_lcr_base,
3725 info->irq_level,
3726 info->max_frame_size );
3727
3728#if SYNCLINK_GENERIC_HDLC
3729 return hdlcdev_init(info);
3730#else
3731 return 0;
3732#endif
3733}
3734
3735static const struct tty_port_operations port_ops = {
3736 .carrier_raised = carrier_raised,
3737 .dtr_rts = dtr_rts,
3738};
3739
3740/* Allocate and initialize a device instance structure
3741 *
3742 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3743 */
3744static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3745{
3746 SLMP_INFO *info;
3747
3748 info = kzalloc(sizeof(SLMP_INFO),
3749 GFP_KERNEL);
3750
3751 if (!info) {
3752 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3753 __FILE__,__LINE__, adapter_num, port_num);
3754 } else {
3755 tty_port_init(&info->port);
3756 info->port.ops = &port_ops;
3757 info->magic = MGSL_MAGIC;
3758 INIT_WORK(&info->task, bh_handler);
3759 info->max_frame_size = 4096;
3760 info->port.close_delay = 5*HZ/10;
3761 info->port.closing_wait = 30*HZ;
3762 init_waitqueue_head(&info->status_event_wait_q);
3763 init_waitqueue_head(&info->event_wait_q);
3764 spin_lock_init(&info->netlock);
3765 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3766 info->idle_mode = HDLC_TXIDLE_FLAGS;
3767 info->adapter_num = adapter_num;
3768 info->port_num = port_num;
3769
3770 /* Copy configuration info to device instance data */
3771 info->irq_level = pdev->irq;
3772 info->phys_lcr_base = pci_resource_start(pdev,0);
3773 info->phys_sca_base = pci_resource_start(pdev,2);
3774 info->phys_memory_base = pci_resource_start(pdev,3);
3775 info->phys_statctrl_base = pci_resource_start(pdev,4);
3776
3777 /* Because veremap only works on page boundaries we must map
3778 * a larger area than is actually implemented for the LCR
3779 * memory range. We map a full page starting at the page boundary.
3780 */
3781 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3782 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3783
3784 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3785 info->phys_sca_base &= ~(PAGE_SIZE-1);
3786
3787 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3788 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3789
3790 info->bus_type = MGSL_BUS_TYPE_PCI;
3791 info->irq_flags = IRQF_SHARED;
3792
3793 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3794 setup_timer(&info->status_timer, status_timeout,
3795 (unsigned long)info);
3796
3797 /* Store the PCI9050 misc control register value because a flaw
3798 * in the PCI9050 prevents LCR registers from being read if
3799 * BIOS assigns an LCR base address with bit 7 set.
3800 *
3801 * Only the misc control register is accessed for which only
3802 * write access is needed, so set an initial value and change
3803 * bits to the device instance data as we write the value
3804 * to the actual misc control register.
3805 */
3806 info->misc_ctrl_value = 0x087e4546;
3807
3808 /* initial port state is unknown - if startup errors
3809 * occur, init_error will be set to indicate the
3810 * problem. Once the port is fully initialized,
3811 * this value will be set to 0 to indicate the
3812 * port is available.
3813 */
3814 info->init_error = -1;
3815 }
3816
3817 return info;
3818}
3819
3820static int device_init(int adapter_num, struct pci_dev *pdev)
3821{
3822 SLMP_INFO *port_array[SCA_MAX_PORTS];
3823 int port, rc;
3824
3825 /* allocate device instances for up to SCA_MAX_PORTS devices */
3826 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3827 port_array[port] = alloc_dev(adapter_num,port,pdev);
3828 if( port_array[port] == NULL ) {
3829 for (--port; port >= 0; --port) {
3830 tty_port_destroy(&port_array[port]->port);
3831 kfree(port_array[port]);
3832 }
3833 return -ENOMEM;
3834 }
3835 }
3836
3837 /* give copy of port_array to all ports and add to device list */
3838 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3839 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3840 rc = add_device( port_array[port] );
3841 if (rc)
3842 goto err_add;
3843 spin_lock_init(&port_array[port]->lock);
3844 }
3845
3846 /* Allocate and claim adapter resources */
3847 if ( !claim_resources(port_array[0]) ) {
3848
3849 alloc_dma_bufs(port_array[0]);
3850
3851 /* copy resource information from first port to others */
3852 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3853 port_array[port]->lock = port_array[0]->lock;
3854 port_array[port]->irq_level = port_array[0]->irq_level;
3855 port_array[port]->memory_base = port_array[0]->memory_base;
3856 port_array[port]->sca_base = port_array[0]->sca_base;
3857 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3858 port_array[port]->lcr_base = port_array[0]->lcr_base;
3859 alloc_dma_bufs(port_array[port]);
3860 }
3861
3862 rc = request_irq(port_array[0]->irq_level,
3863 synclinkmp_interrupt,
3864 port_array[0]->irq_flags,
3865 port_array[0]->device_name,
3866 port_array[0]);
3867 if ( rc ) {
3868 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3869 __FILE__,__LINE__,
3870 port_array[0]->device_name,
3871 port_array[0]->irq_level );
3872 goto err_irq;
3873 }
3874 port_array[0]->irq_requested = true;
3875 adapter_test(port_array[0]);
3876 }
3877 return 0;
3878err_irq:
3879 release_resources( port_array[0] );
3880err_add:
3881 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3882 tty_port_destroy(&port_array[port]->port);
3883 kfree(port_array[port]);
3884 }
3885 return rc;
3886}
3887
3888static const struct tty_operations ops = {
3889 .install = install,
3890 .open = open,
3891 .close = close,
3892 .write = write,
3893 .put_char = put_char,
3894 .flush_chars = flush_chars,
3895 .write_room = write_room,
3896 .chars_in_buffer = chars_in_buffer,
3897 .flush_buffer = flush_buffer,
3898 .ioctl = ioctl,
3899 .throttle = throttle,
3900 .unthrottle = unthrottle,
3901 .send_xchar = send_xchar,
3902 .break_ctl = set_break,
3903 .wait_until_sent = wait_until_sent,
3904 .set_termios = set_termios,
3905 .stop = tx_hold,
3906 .start = tx_release,
3907 .hangup = hangup,
3908 .tiocmget = tiocmget,
3909 .tiocmset = tiocmset,
3910 .get_icount = get_icount,
3911 .proc_fops = &synclinkmp_proc_fops,
3912};
3913
3914
3915static void synclinkmp_cleanup(void)
3916{
3917 int rc;
3918 SLMP_INFO *info;
3919 SLMP_INFO *tmp;
3920
3921 printk("Unloading %s %s\n", driver_name, driver_version);
3922
3923 if (serial_driver) {
3924 rc = tty_unregister_driver(serial_driver);
3925 if (rc)
3926 printk("%s(%d) failed to unregister tty driver err=%d\n",
3927 __FILE__,__LINE__,rc);
3928 put_tty_driver(serial_driver);
3929 }
3930
3931 /* reset devices */
3932 info = synclinkmp_device_list;
3933 while(info) {
3934 reset_port(info);
3935 info = info->next_device;
3936 }
3937
3938 /* release devices */
3939 info = synclinkmp_device_list;
3940 while(info) {
3941#if SYNCLINK_GENERIC_HDLC
3942 hdlcdev_exit(info);
3943#endif
3944 free_dma_bufs(info);
3945 free_tmp_rx_buf(info);
3946 if ( info->port_num == 0 ) {
3947 if (info->sca_base)
3948 write_reg(info, LPR, 1); /* set low power mode */
3949 release_resources(info);
3950 }
3951 tmp = info;
3952 info = info->next_device;
3953 tty_port_destroy(&tmp->port);
3954 kfree(tmp);
3955 }
3956
3957 pci_unregister_driver(&synclinkmp_pci_driver);
3958}
3959
3960/* Driver initialization entry point.
3961 */
3962
3963static int __init synclinkmp_init(void)
3964{
3965 int rc;
3966
3967 if (break_on_load) {
3968 synclinkmp_get_text_ptr();
3969 BREAKPOINT();
3970 }
3971
3972 printk("%s %s\n", driver_name, driver_version);
3973
3974 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3975 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3976 return rc;
3977 }
3978
3979 serial_driver = alloc_tty_driver(128);
3980 if (!serial_driver) {
3981 rc = -ENOMEM;
3982 goto error;
3983 }
3984
3985 /* Initialize the tty_driver structure */
3986
3987 serial_driver->driver_name = "synclinkmp";
3988 serial_driver->name = "ttySLM";
3989 serial_driver->major = ttymajor;
3990 serial_driver->minor_start = 64;
3991 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3992 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3993 serial_driver->init_termios = tty_std_termios;
3994 serial_driver->init_termios.c_cflag =
3995 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3996 serial_driver->init_termios.c_ispeed = 9600;
3997 serial_driver->init_termios.c_ospeed = 9600;
3998 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3999 tty_set_operations(serial_driver, &ops);
4000 if ((rc = tty_register_driver(serial_driver)) < 0) {
4001 printk("%s(%d):Couldn't register serial driver\n",
4002 __FILE__,__LINE__);
4003 put_tty_driver(serial_driver);
4004 serial_driver = NULL;
4005 goto error;
4006 }
4007
4008 printk("%s %s, tty major#%d\n",
4009 driver_name, driver_version,
4010 serial_driver->major);
4011
4012 return 0;
4013
4014error:
4015 synclinkmp_cleanup();
4016 return rc;
4017}
4018
4019static void __exit synclinkmp_exit(void)
4020{
4021 synclinkmp_cleanup();
4022}
4023
4024module_init(synclinkmp_init);
4025module_exit(synclinkmp_exit);
4026
4027/* Set the port for internal loopback mode.
4028 * The TxCLK and RxCLK signals are generated from the BRG and
4029 * the TxD is looped back to the RxD internally.
4030 */
4031static void enable_loopback(SLMP_INFO *info, int enable)
4032{
4033 if (enable) {
4034 /* MD2 (Mode Register 2)
4035 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4036 */
4037 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4038
4039 /* degate external TxC clock source */
4040 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4041 write_control_reg(info);
4042
4043 /* RXS/TXS (Rx/Tx clock source)
4044 * 07 Reserved, must be 0
4045 * 06..04 Clock Source, 100=BRG
4046 * 03..00 Clock Divisor, 0000=1
4047 */
4048 write_reg(info, RXS, 0x40);
4049 write_reg(info, TXS, 0x40);
4050
4051 } else {
4052 /* MD2 (Mode Register 2)
4053 * 01..00 CNCT<1..0> Channel connection, 0=normal
4054 */
4055 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4056
4057 /* RXS/TXS (Rx/Tx clock source)
4058 * 07 Reserved, must be 0
4059 * 06..04 Clock Source, 000=RxC/TxC Pin
4060 * 03..00 Clock Divisor, 0000=1
4061 */
4062 write_reg(info, RXS, 0x00);
4063 write_reg(info, TXS, 0x00);
4064 }
4065
4066 /* set LinkSpeed if available, otherwise default to 2Mbps */
4067 if (info->params.clock_speed)
4068 set_rate(info, info->params.clock_speed);
4069 else
4070 set_rate(info, 3686400);
4071}
4072
4073/* Set the baud rate register to the desired speed
4074 *
4075 * data_rate data rate of clock in bits per second
4076 * A data rate of 0 disables the AUX clock.
4077 */
4078static void set_rate( SLMP_INFO *info, u32 data_rate )
4079{
4080 u32 TMCValue;
4081 unsigned char BRValue;
4082 u32 Divisor=0;
4083
4084 /* fBRG = fCLK/(TMC * 2^BR)
4085 */
4086 if (data_rate != 0) {
4087 Divisor = 14745600/data_rate;
4088 if (!Divisor)
4089 Divisor = 1;
4090
4091 TMCValue = Divisor;
4092
4093 BRValue = 0;
4094 if (TMCValue != 1 && TMCValue != 2) {
4095 /* BRValue of 0 provides 50/50 duty cycle *only* when
4096 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4097 * 50/50 duty cycle.
4098 */
4099 BRValue = 1;
4100 TMCValue >>= 1;
4101 }
4102
4103 /* while TMCValue is too big for TMC register, divide
4104 * by 2 and increment BR exponent.
4105 */
4106 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4107 TMCValue >>= 1;
4108
4109 write_reg(info, TXS,
4110 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4111 write_reg(info, RXS,
4112 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4113 write_reg(info, TMC, (unsigned char)TMCValue);
4114 }
4115 else {
4116 write_reg(info, TXS,0);
4117 write_reg(info, RXS,0);
4118 write_reg(info, TMC, 0);
4119 }
4120}
4121
4122/* Disable receiver
4123 */
4124static void rx_stop(SLMP_INFO *info)
4125{
4126 if (debug_level >= DEBUG_LEVEL_ISR)
4127 printk("%s(%d):%s rx_stop()\n",
4128 __FILE__,__LINE__, info->device_name );
4129
4130 write_reg(info, CMD, RXRESET);
4131
4132 info->ie0_value &= ~RXRDYE;
4133 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4134
4135 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4136 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4137 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4138
4139 info->rx_enabled = false;
4140 info->rx_overflow = false;
4141}
4142
4143/* enable the receiver
4144 */
4145static void rx_start(SLMP_INFO *info)
4146{
4147 int i;
4148
4149 if (debug_level >= DEBUG_LEVEL_ISR)
4150 printk("%s(%d):%s rx_start()\n",
4151 __FILE__,__LINE__, info->device_name );
4152
4153 write_reg(info, CMD, RXRESET);
4154
4155 if ( info->params.mode == MGSL_MODE_HDLC ) {
4156 /* HDLC, disabe IRQ on rxdata */
4157 info->ie0_value &= ~RXRDYE;
4158 write_reg(info, IE0, info->ie0_value);
4159
4160 /* Reset all Rx DMA buffers and program rx dma */
4161 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4162 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4163
4164 for (i = 0; i < info->rx_buf_count; i++) {
4165 info->rx_buf_list[i].status = 0xff;
4166
4167 // throttle to 4 shared memory writes at a time to prevent
4168 // hogging local bus (keep latency time for DMA requests low).
4169 if (!(i % 4))
4170 read_status_reg(info);
4171 }
4172 info->current_rx_buf = 0;
4173
4174 /* set current/1st descriptor address */
4175 write_reg16(info, RXDMA + CDA,
4176 info->rx_buf_list_ex[0].phys_entry);
4177
4178 /* set new last rx descriptor address */
4179 write_reg16(info, RXDMA + EDA,
4180 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4181
4182 /* set buffer length (shared by all rx dma data buffers) */
4183 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4184
4185 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4186 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4187 } else {
4188 /* async, enable IRQ on rxdata */
4189 info->ie0_value |= RXRDYE;
4190 write_reg(info, IE0, info->ie0_value);
4191 }
4192
4193 write_reg(info, CMD, RXENABLE);
4194
4195 info->rx_overflow = false;
4196 info->rx_enabled = true;
4197}
4198
4199/* Enable the transmitter and send a transmit frame if
4200 * one is loaded in the DMA buffers.
4201 */
4202static void tx_start(SLMP_INFO *info)
4203{
4204 if (debug_level >= DEBUG_LEVEL_ISR)
4205 printk("%s(%d):%s tx_start() tx_count=%d\n",
4206 __FILE__,__LINE__, info->device_name,info->tx_count );
4207
4208 if (!info->tx_enabled ) {
4209 write_reg(info, CMD, TXRESET);
4210 write_reg(info, CMD, TXENABLE);
4211 info->tx_enabled = true;
4212 }
4213
4214 if ( info->tx_count ) {
4215
4216 /* If auto RTS enabled and RTS is inactive, then assert */
4217 /* RTS and set a flag indicating that the driver should */
4218 /* negate RTS when the transmission completes. */
4219
4220 info->drop_rts_on_tx_done = false;
4221
4222 if (info->params.mode != MGSL_MODE_ASYNC) {
4223
4224 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4225 get_signals( info );
4226 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4227 info->serial_signals |= SerialSignal_RTS;
4228 set_signals( info );
4229 info->drop_rts_on_tx_done = true;
4230 }
4231 }
4232
4233 write_reg16(info, TRC0,
4234 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4235
4236 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4237 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4238
4239 /* set TX CDA (current descriptor address) */
4240 write_reg16(info, TXDMA + CDA,
4241 info->tx_buf_list_ex[0].phys_entry);
4242
4243 /* set TX EDA (last descriptor address) */
4244 write_reg16(info, TXDMA + EDA,
4245 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4246
4247 /* enable underrun IRQ */
4248 info->ie1_value &= ~IDLE;
4249 info->ie1_value |= UDRN;
4250 write_reg(info, IE1, info->ie1_value);
4251 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4252
4253 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4254 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4255
4256 mod_timer(&info->tx_timer, jiffies +
4257 msecs_to_jiffies(5000));
4258 }
4259 else {
4260 tx_load_fifo(info);
4261 /* async, enable IRQ on txdata */
4262 info->ie0_value |= TXRDYE;
4263 write_reg(info, IE0, info->ie0_value);
4264 }
4265
4266 info->tx_active = true;
4267 }
4268}
4269
4270/* stop the transmitter and DMA
4271 */
4272static void tx_stop( SLMP_INFO *info )
4273{
4274 if (debug_level >= DEBUG_LEVEL_ISR)
4275 printk("%s(%d):%s tx_stop()\n",
4276 __FILE__,__LINE__, info->device_name );
4277
4278 del_timer(&info->tx_timer);
4279
4280 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4281 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4282
4283 write_reg(info, CMD, TXRESET);
4284
4285 info->ie1_value &= ~(UDRN + IDLE);
4286 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4287 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4288
4289 info->ie0_value &= ~TXRDYE;
4290 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4291
4292 info->tx_enabled = false;
4293 info->tx_active = false;
4294}
4295
4296/* Fill the transmit FIFO until the FIFO is full or
4297 * there is no more data to load.
4298 */
4299static void tx_load_fifo(SLMP_INFO *info)
4300{
4301 u8 TwoBytes[2];
4302
4303 /* do nothing is now tx data available and no XON/XOFF pending */
4304
4305 if ( !info->tx_count && !info->x_char )
4306 return;
4307
4308 /* load the Transmit FIFO until FIFOs full or all data sent */
4309
4310 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4311
4312 /* there is more space in the transmit FIFO and */
4313 /* there is more data in transmit buffer */
4314
4315 if ( (info->tx_count > 1) && !info->x_char ) {
4316 /* write 16-bits */
4317 TwoBytes[0] = info->tx_buf[info->tx_get++];
4318 if (info->tx_get >= info->max_frame_size)
4319 info->tx_get -= info->max_frame_size;
4320 TwoBytes[1] = info->tx_buf[info->tx_get++];
4321 if (info->tx_get >= info->max_frame_size)
4322 info->tx_get -= info->max_frame_size;
4323
4324 write_reg16(info, TRB, *((u16 *)TwoBytes));
4325
4326 info->tx_count -= 2;
4327 info->icount.tx += 2;
4328 } else {
4329 /* only 1 byte left to transmit or 1 FIFO slot left */
4330
4331 if (info->x_char) {
4332 /* transmit pending high priority char */
4333 write_reg(info, TRB, info->x_char);
4334 info->x_char = 0;
4335 } else {
4336 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4337 if (info->tx_get >= info->max_frame_size)
4338 info->tx_get -= info->max_frame_size;
4339 info->tx_count--;
4340 }
4341 info->icount.tx++;
4342 }
4343 }
4344}
4345
4346/* Reset a port to a known state
4347 */
4348static void reset_port(SLMP_INFO *info)
4349{
4350 if (info->sca_base) {
4351
4352 tx_stop(info);
4353 rx_stop(info);
4354
4355 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4356 set_signals(info);
4357
4358 /* disable all port interrupts */
4359 info->ie0_value = 0;
4360 info->ie1_value = 0;
4361 info->ie2_value = 0;
4362 write_reg(info, IE0, info->ie0_value);
4363 write_reg(info, IE1, info->ie1_value);
4364 write_reg(info, IE2, info->ie2_value);
4365
4366 write_reg(info, CMD, CHRESET);
4367 }
4368}
4369
4370/* Reset all the ports to a known state.
4371 */
4372static void reset_adapter(SLMP_INFO *info)
4373{
4374 int i;
4375
4376 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4377 if (info->port_array[i])
4378 reset_port(info->port_array[i]);
4379 }
4380}
4381
4382/* Program port for asynchronous communications.
4383 */
4384static void async_mode(SLMP_INFO *info)
4385{
4386
4387 unsigned char RegValue;
4388
4389 tx_stop(info);
4390 rx_stop(info);
4391
4392 /* MD0, Mode Register 0
4393 *
4394 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4395 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4396 * 03 Reserved, must be 0
4397 * 02 CRCCC, CRC Calculation, 0=disabled
4398 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4399 *
4400 * 0000 0000
4401 */
4402 RegValue = 0x00;
4403 if (info->params.stop_bits != 1)
4404 RegValue |= BIT1;
4405 write_reg(info, MD0, RegValue);
4406
4407 /* MD1, Mode Register 1
4408 *
4409 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4410 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4411 * 03..02 RXCHR<1..0>, rx char size
4412 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4413 *
4414 * 0100 0000
4415 */
4416 RegValue = 0x40;
4417 switch (info->params.data_bits) {
4418 case 7: RegValue |= BIT4 + BIT2; break;
4419 case 6: RegValue |= BIT5 + BIT3; break;
4420 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4421 }
4422 if (info->params.parity != ASYNC_PARITY_NONE) {
4423 RegValue |= BIT1;
4424 if (info->params.parity == ASYNC_PARITY_ODD)
4425 RegValue |= BIT0;
4426 }
4427 write_reg(info, MD1, RegValue);
4428
4429 /* MD2, Mode Register 2
4430 *
4431 * 07..02 Reserved, must be 0
4432 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4433 *
4434 * 0000 0000
4435 */
4436 RegValue = 0x00;
4437 if (info->params.loopback)
4438 RegValue |= (BIT1 + BIT0);
4439 write_reg(info, MD2, RegValue);
4440
4441 /* RXS, Receive clock source
4442 *
4443 * 07 Reserved, must be 0
4444 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4445 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4446 */
4447 RegValue=BIT6;
4448 write_reg(info, RXS, RegValue);
4449
4450 /* TXS, Transmit clock source
4451 *
4452 * 07 Reserved, must be 0
4453 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4454 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4455 */
4456 RegValue=BIT6;
4457 write_reg(info, TXS, RegValue);
4458
4459 /* Control Register
4460 *
4461 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4462 */
4463 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4464 write_control_reg(info);
4465
4466 tx_set_idle(info);
4467
4468 /* RRC Receive Ready Control 0
4469 *
4470 * 07..05 Reserved, must be 0
4471 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4472 */
4473 write_reg(info, RRC, 0x00);
4474
4475 /* TRC0 Transmit Ready Control 0
4476 *
4477 * 07..05 Reserved, must be 0
4478 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4479 */
4480 write_reg(info, TRC0, 0x10);
4481
4482 /* TRC1 Transmit Ready Control 1
4483 *
4484 * 07..05 Reserved, must be 0
4485 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4486 */
4487 write_reg(info, TRC1, 0x1e);
4488
4489 /* CTL, MSCI control register
4490 *
4491 * 07..06 Reserved, set to 0
4492 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4493 * 04 IDLC, idle control, 0=mark 1=idle register
4494 * 03 BRK, break, 0=off 1 =on (async)
4495 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4496 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4497 * 00 RTS, RTS output control, 0=active 1=inactive
4498 *
4499 * 0001 0001
4500 */
4501 RegValue = 0x10;
4502 if (!(info->serial_signals & SerialSignal_RTS))
4503 RegValue |= 0x01;
4504 write_reg(info, CTL, RegValue);
4505
4506 /* enable status interrupts */
4507 info->ie0_value |= TXINTE + RXINTE;
4508 write_reg(info, IE0, info->ie0_value);
4509
4510 /* enable break detect interrupt */
4511 info->ie1_value = BRKD;
4512 write_reg(info, IE1, info->ie1_value);
4513
4514 /* enable rx overrun interrupt */
4515 info->ie2_value = OVRN;
4516 write_reg(info, IE2, info->ie2_value);
4517
4518 set_rate( info, info->params.data_rate * 16 );
4519}
4520
4521/* Program the SCA for HDLC communications.
4522 */
4523static void hdlc_mode(SLMP_INFO *info)
4524{
4525 unsigned char RegValue;
4526 u32 DpllDivisor;
4527
4528 // Can't use DPLL because SCA outputs recovered clock on RxC when
4529 // DPLL mode selected. This causes output contention with RxC receiver.
4530 // Use of DPLL would require external hardware to disable RxC receiver
4531 // when DPLL mode selected.
4532 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4533
4534 /* disable DMA interrupts */
4535 write_reg(info, TXDMA + DIR, 0);
4536 write_reg(info, RXDMA + DIR, 0);
4537
4538 /* MD0, Mode Register 0
4539 *
4540 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4541 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4542 * 03 Reserved, must be 0
4543 * 02 CRCCC, CRC Calculation, 1=enabled
4544 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4545 * 00 CRC0, CRC initial value, 1 = all 1s
4546 *
4547 * 1000 0001
4548 */
4549 RegValue = 0x81;
4550 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4551 RegValue |= BIT4;
4552 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4553 RegValue |= BIT4;
4554 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4555 RegValue |= BIT2 + BIT1;
4556 write_reg(info, MD0, RegValue);
4557
4558 /* MD1, Mode Register 1
4559 *
4560 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4561 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4562 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4563 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4564 *
4565 * 0000 0000
4566 */
4567 RegValue = 0x00;
4568 write_reg(info, MD1, RegValue);
4569
4570 /* MD2, Mode Register 2
4571 *
4572 * 07 NRZFM, 0=NRZ, 1=FM
4573 * 06..05 CODE<1..0> Encoding, 00=NRZ
4574 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4575 * 02 Reserved, must be 0
4576 * 01..00 CNCT<1..0> Channel connection, 0=normal
4577 *
4578 * 0000 0000
4579 */
4580 RegValue = 0x00;
4581 switch(info->params.encoding) {
4582 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4583 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4584 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4585 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4586#if 0
4587 case HDLC_ENCODING_NRZB: /* not supported */
4588 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4589 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4590#endif
4591 }
4592 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4593 DpllDivisor = 16;
4594 RegValue |= BIT3;
4595 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4596 DpllDivisor = 8;
4597 } else {
4598 DpllDivisor = 32;
4599 RegValue |= BIT4;
4600 }
4601 write_reg(info, MD2, RegValue);
4602
4603
4604 /* RXS, Receive clock source
4605 *
4606 * 07 Reserved, must be 0
4607 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4608 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4609 */
4610 RegValue=0;
4611 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4612 RegValue |= BIT6;
4613 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4614 RegValue |= BIT6 + BIT5;
4615 write_reg(info, RXS, RegValue);
4616
4617 /* TXS, Transmit clock source
4618 *
4619 * 07 Reserved, must be 0
4620 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4621 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4622 */
4623 RegValue=0;
4624 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4625 RegValue |= BIT6;
4626 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4627 RegValue |= BIT6 + BIT5;
4628 write_reg(info, TXS, RegValue);
4629
4630 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4631 set_rate(info, info->params.clock_speed * DpllDivisor);
4632 else
4633 set_rate(info, info->params.clock_speed);
4634
4635 /* GPDATA (General Purpose I/O Data Register)
4636 *
4637 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4638 */
4639 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4640 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4641 else
4642 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4643 write_control_reg(info);
4644
4645 /* RRC Receive Ready Control 0
4646 *
4647 * 07..05 Reserved, must be 0
4648 * 04..00 RRC<4..0> Rx FIFO trigger active
4649 */
4650 write_reg(info, RRC, rx_active_fifo_level);
4651
4652 /* TRC0 Transmit Ready Control 0
4653 *
4654 * 07..05 Reserved, must be 0
4655 * 04..00 TRC<4..0> Tx FIFO trigger active
4656 */
4657 write_reg(info, TRC0, tx_active_fifo_level);
4658
4659 /* TRC1 Transmit Ready Control 1
4660 *
4661 * 07..05 Reserved, must be 0
4662 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4663 */
4664 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4665
4666 /* DMR, DMA Mode Register
4667 *
4668 * 07..05 Reserved, must be 0
4669 * 04 TMOD, Transfer Mode: 1=chained-block
4670 * 03 Reserved, must be 0
4671 * 02 NF, Number of Frames: 1=multi-frame
4672 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4673 * 00 Reserved, must be 0
4674 *
4675 * 0001 0100
4676 */
4677 write_reg(info, TXDMA + DMR, 0x14);
4678 write_reg(info, RXDMA + DMR, 0x14);
4679
4680 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4681 write_reg(info, RXDMA + CPB,
4682 (unsigned char)(info->buffer_list_phys >> 16));
4683
4684 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4685 write_reg(info, TXDMA + CPB,
4686 (unsigned char)(info->buffer_list_phys >> 16));
4687
4688 /* enable status interrupts. other code enables/disables
4689 * the individual sources for these two interrupt classes.
4690 */
4691 info->ie0_value |= TXINTE + RXINTE;
4692 write_reg(info, IE0, info->ie0_value);
4693
4694 /* CTL, MSCI control register
4695 *
4696 * 07..06 Reserved, set to 0
4697 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4698 * 04 IDLC, idle control, 0=mark 1=idle register
4699 * 03 BRK, break, 0=off 1 =on (async)
4700 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4701 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4702 * 00 RTS, RTS output control, 0=active 1=inactive
4703 *
4704 * 0001 0001
4705 */
4706 RegValue = 0x10;
4707 if (!(info->serial_signals & SerialSignal_RTS))
4708 RegValue |= 0x01;
4709 write_reg(info, CTL, RegValue);
4710
4711 /* preamble not supported ! */
4712
4713 tx_set_idle(info);
4714 tx_stop(info);
4715 rx_stop(info);
4716
4717 set_rate(info, info->params.clock_speed);
4718
4719 if (info->params.loopback)
4720 enable_loopback(info,1);
4721}
4722
4723/* Set the transmit HDLC idle mode
4724 */
4725static void tx_set_idle(SLMP_INFO *info)
4726{
4727 unsigned char RegValue = 0xff;
4728
4729 /* Map API idle mode to SCA register bits */
4730 switch(info->idle_mode) {
4731 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4732 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4733 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4734 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4735 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4736 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4737 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4738 }
4739
4740 write_reg(info, IDL, RegValue);
4741}
4742
4743/* Query the adapter for the state of the V24 status (input) signals.
4744 */
4745static void get_signals(SLMP_INFO *info)
4746{
4747 u16 status = read_reg(info, SR3);
4748 u16 gpstatus = read_status_reg(info);
4749 u16 testbit;
4750
4751 /* clear all serial signals except RTS and DTR */
4752 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4753
4754 /* set serial signal bits to reflect MISR */
4755
4756 if (!(status & BIT3))
4757 info->serial_signals |= SerialSignal_CTS;
4758
4759 if ( !(status & BIT2))
4760 info->serial_signals |= SerialSignal_DCD;
4761
4762 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4763 if (!(gpstatus & testbit))
4764 info->serial_signals |= SerialSignal_RI;
4765
4766 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4767 if (!(gpstatus & testbit))
4768 info->serial_signals |= SerialSignal_DSR;
4769}
4770
4771/* Set the state of RTS and DTR based on contents of
4772 * serial_signals member of device context.
4773 */
4774static void set_signals(SLMP_INFO *info)
4775{
4776 unsigned char RegValue;
4777 u16 EnableBit;
4778
4779 RegValue = read_reg(info, CTL);
4780 if (info->serial_signals & SerialSignal_RTS)
4781 RegValue &= ~BIT0;
4782 else
4783 RegValue |= BIT0;
4784 write_reg(info, CTL, RegValue);
4785
4786 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4787 EnableBit = BIT1 << (info->port_num*2);
4788 if (info->serial_signals & SerialSignal_DTR)
4789 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4790 else
4791 info->port_array[0]->ctrlreg_value |= EnableBit;
4792 write_control_reg(info);
4793}
4794
4795/*******************/
4796/* DMA Buffer Code */
4797/*******************/
4798
4799/* Set the count for all receive buffers to SCABUFSIZE
4800 * and set the current buffer to the first buffer. This effectively
4801 * makes all buffers free and discards any data in buffers.
4802 */
4803static void rx_reset_buffers(SLMP_INFO *info)
4804{
4805 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4806}
4807
4808/* Free the buffers used by a received frame
4809 *
4810 * info pointer to device instance data
4811 * first index of 1st receive buffer of frame
4812 * last index of last receive buffer of frame
4813 */
4814static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4815{
4816 bool done = false;
4817
4818 while(!done) {
4819 /* reset current buffer for reuse */
4820 info->rx_buf_list[first].status = 0xff;
4821
4822 if (first == last) {
4823 done = true;
4824 /* set new last rx descriptor address */
4825 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4826 }
4827
4828 first++;
4829 if (first == info->rx_buf_count)
4830 first = 0;
4831 }
4832
4833 /* set current buffer to next buffer after last buffer of frame */
4834 info->current_rx_buf = first;
4835}
4836
4837/* Return a received frame from the receive DMA buffers.
4838 * Only frames received without errors are returned.
4839 *
4840 * Return Value: true if frame returned, otherwise false
4841 */
4842static bool rx_get_frame(SLMP_INFO *info)
4843{
4844 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4845 unsigned short status;
4846 unsigned int framesize = 0;
4847 bool ReturnCode = false;
4848 unsigned long flags;
4849 struct tty_struct *tty = info->port.tty;
4850 unsigned char addr_field = 0xff;
4851 SCADESC *desc;
4852 SCADESC_EX *desc_ex;
4853
4854CheckAgain:
4855 /* assume no frame returned, set zero length */
4856 framesize = 0;
4857 addr_field = 0xff;
4858
4859 /*
4860 * current_rx_buf points to the 1st buffer of the next available
4861 * receive frame. To find the last buffer of the frame look for
4862 * a non-zero status field in the buffer entries. (The status
4863 * field is set by the 16C32 after completing a receive frame.
4864 */
4865 StartIndex = EndIndex = info->current_rx_buf;
4866
4867 for ( ;; ) {
4868 desc = &info->rx_buf_list[EndIndex];
4869 desc_ex = &info->rx_buf_list_ex[EndIndex];
4870
4871 if (desc->status == 0xff)
4872 goto Cleanup; /* current desc still in use, no frames available */
4873
4874 if (framesize == 0 && info->params.addr_filter != 0xff)
4875 addr_field = desc_ex->virt_addr[0];
4876
4877 framesize += desc->length;
4878
4879 /* Status != 0 means last buffer of frame */
4880 if (desc->status)
4881 break;
4882
4883 EndIndex++;
4884 if (EndIndex == info->rx_buf_count)
4885 EndIndex = 0;
4886
4887 if (EndIndex == info->current_rx_buf) {
4888 /* all buffers have been 'used' but none mark */
4889 /* the end of a frame. Reset buffers and receiver. */
4890 if ( info->rx_enabled ){
4891 spin_lock_irqsave(&info->lock,flags);
4892 rx_start(info);
4893 spin_unlock_irqrestore(&info->lock,flags);
4894 }
4895 goto Cleanup;
4896 }
4897
4898 }
4899
4900 /* check status of receive frame */
4901
4902 /* frame status is byte stored after frame data
4903 *
4904 * 7 EOM (end of msg), 1 = last buffer of frame
4905 * 6 Short Frame, 1 = short frame
4906 * 5 Abort, 1 = frame aborted
4907 * 4 Residue, 1 = last byte is partial
4908 * 3 Overrun, 1 = overrun occurred during frame reception
4909 * 2 CRC, 1 = CRC error detected
4910 *
4911 */
4912 status = desc->status;
4913
4914 /* ignore CRC bit if not using CRC (bit is undefined) */
4915 /* Note:CRC is not save to data buffer */
4916 if (info->params.crc_type == HDLC_CRC_NONE)
4917 status &= ~BIT2;
4918
4919 if (framesize == 0 ||
4920 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4921 /* discard 0 byte frames, this seems to occur sometime
4922 * when remote is idling flags.
4923 */
4924 rx_free_frame_buffers(info, StartIndex, EndIndex);
4925 goto CheckAgain;
4926 }
4927
4928 if (framesize < 2)
4929 status |= BIT6;
4930
4931 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4932 /* received frame has errors,
4933 * update counts and mark frame size as 0
4934 */
4935 if (status & BIT6)
4936 info->icount.rxshort++;
4937 else if (status & BIT5)
4938 info->icount.rxabort++;
4939 else if (status & BIT3)
4940 info->icount.rxover++;
4941 else
4942 info->icount.rxcrc++;
4943
4944 framesize = 0;
4945#if SYNCLINK_GENERIC_HDLC
4946 {
4947 info->netdev->stats.rx_errors++;
4948 info->netdev->stats.rx_frame_errors++;
4949 }
4950#endif
4951 }
4952
4953 if ( debug_level >= DEBUG_LEVEL_BH )
4954 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4955 __FILE__,__LINE__,info->device_name,status,framesize);
4956
4957 if ( debug_level >= DEBUG_LEVEL_DATA )
4958 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4959 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4960
4961 if (framesize) {
4962 if (framesize > info->max_frame_size)
4963 info->icount.rxlong++;
4964 else {
4965 /* copy dma buffer(s) to contiguous intermediate buffer */
4966 int copy_count = framesize;
4967 int index = StartIndex;
4968 unsigned char *ptmp = info->tmp_rx_buf;
4969 info->tmp_rx_buf_count = framesize;
4970
4971 info->icount.rxok++;
4972
4973 while(copy_count) {
4974 int partial_count = min(copy_count,SCABUFSIZE);
4975 memcpy( ptmp,
4976 info->rx_buf_list_ex[index].virt_addr,
4977 partial_count );
4978 ptmp += partial_count;
4979 copy_count -= partial_count;
4980
4981 if ( ++index == info->rx_buf_count )
4982 index = 0;
4983 }
4984
4985#if SYNCLINK_GENERIC_HDLC
4986 if (info->netcount)
4987 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4988 else
4989#endif
4990 ldisc_receive_buf(tty,info->tmp_rx_buf,
4991 info->flag_buf, framesize);
4992 }
4993 }
4994 /* Free the buffers used by this frame. */
4995 rx_free_frame_buffers( info, StartIndex, EndIndex );
4996
4997 ReturnCode = true;
4998
4999Cleanup:
5000 if ( info->rx_enabled && info->rx_overflow ) {
5001 /* Receiver is enabled, but needs to restarted due to
5002 * rx buffer overflow. If buffers are empty, restart receiver.
5003 */
5004 if (info->rx_buf_list[EndIndex].status == 0xff) {
5005 spin_lock_irqsave(&info->lock,flags);
5006 rx_start(info);
5007 spin_unlock_irqrestore(&info->lock,flags);
5008 }
5009 }
5010
5011 return ReturnCode;
5012}
5013
5014/* load the transmit DMA buffer with data
5015 */
5016static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5017{
5018 unsigned short copy_count;
5019 unsigned int i = 0;
5020 SCADESC *desc;
5021 SCADESC_EX *desc_ex;
5022
5023 if ( debug_level >= DEBUG_LEVEL_DATA )
5024 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5025
5026 /* Copy source buffer to one or more DMA buffers, starting with
5027 * the first transmit dma buffer.
5028 */
5029 for(i=0;;)
5030 {
5031 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5032
5033 desc = &info->tx_buf_list[i];
5034 desc_ex = &info->tx_buf_list_ex[i];
5035
5036 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5037
5038 desc->length = copy_count;
5039 desc->status = 0;
5040
5041 buf += copy_count;
5042 count -= copy_count;
5043
5044 if (!count)
5045 break;
5046
5047 i++;
5048 if (i >= info->tx_buf_count)
5049 i = 0;
5050 }
5051
5052 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5053 info->last_tx_buf = ++i;
5054}
5055
5056static bool register_test(SLMP_INFO *info)
5057{
5058 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5059 static unsigned int count = ARRAY_SIZE(testval);
5060 unsigned int i;
5061 bool rc = true;
5062 unsigned long flags;
5063
5064 spin_lock_irqsave(&info->lock,flags);
5065 reset_port(info);
5066
5067 /* assume failure */
5068 info->init_error = DiagStatus_AddressFailure;
5069
5070 /* Write bit patterns to various registers but do it out of */
5071 /* sync, then read back and verify values. */
5072
5073 for (i = 0 ; i < count ; i++) {
5074 write_reg(info, TMC, testval[i]);
5075 write_reg(info, IDL, testval[(i+1)%count]);
5076 write_reg(info, SA0, testval[(i+2)%count]);
5077 write_reg(info, SA1, testval[(i+3)%count]);
5078
5079 if ( (read_reg(info, TMC) != testval[i]) ||
5080 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5081 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5082 (read_reg(info, SA1) != testval[(i+3)%count]) )
5083 {
5084 rc = false;
5085 break;
5086 }
5087 }
5088
5089 reset_port(info);
5090 spin_unlock_irqrestore(&info->lock,flags);
5091
5092 return rc;
5093}
5094
5095static bool irq_test(SLMP_INFO *info)
5096{
5097 unsigned long timeout;
5098 unsigned long flags;
5099
5100 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5101
5102 spin_lock_irqsave(&info->lock,flags);
5103 reset_port(info);
5104
5105 /* assume failure */
5106 info->init_error = DiagStatus_IrqFailure;
5107 info->irq_occurred = false;
5108
5109 /* setup timer0 on SCA0 to interrupt */
5110
5111 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5112 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5113
5114 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5115 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5116
5117
5118 /* TMCS, Timer Control/Status Register
5119 *
5120 * 07 CMF, Compare match flag (read only) 1=match
5121 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5122 * 05 Reserved, must be 0
5123 * 04 TME, Timer Enable
5124 * 03..00 Reserved, must be 0
5125 *
5126 * 0101 0000
5127 */
5128 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5129
5130 spin_unlock_irqrestore(&info->lock,flags);
5131
5132 timeout=100;
5133 while( timeout-- && !info->irq_occurred ) {
5134 msleep_interruptible(10);
5135 }
5136
5137 spin_lock_irqsave(&info->lock,flags);
5138 reset_port(info);
5139 spin_unlock_irqrestore(&info->lock,flags);
5140
5141 return info->irq_occurred;
5142}
5143
5144/* initialize individual SCA device (2 ports)
5145 */
5146static bool sca_init(SLMP_INFO *info)
5147{
5148 /* set wait controller to single mem partition (low), no wait states */
5149 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5150 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5151 write_reg(info, WCRL, 0); /* wait controller low range */
5152 write_reg(info, WCRM, 0); /* wait controller mid range */
5153 write_reg(info, WCRH, 0); /* wait controller high range */
5154
5155 /* DPCR, DMA Priority Control
5156 *
5157 * 07..05 Not used, must be 0
5158 * 04 BRC, bus release condition: 0=all transfers complete
5159 * 03 CCC, channel change condition: 0=every cycle
5160 * 02..00 PR<2..0>, priority 100=round robin
5161 *
5162 * 00000100 = 0x04
5163 */
5164 write_reg(info, DPCR, dma_priority);
5165
5166 /* DMA Master Enable, BIT7: 1=enable all channels */
5167 write_reg(info, DMER, 0x80);
5168
5169 /* enable all interrupt classes */
5170 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5171 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5172 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5173
5174 /* ITCR, interrupt control register
5175 * 07 IPC, interrupt priority, 0=MSCI->DMA
5176 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5177 * 04 VOS, Vector Output, 0=unmodified vector
5178 * 03..00 Reserved, must be 0
5179 */
5180 write_reg(info, ITCR, 0);
5181
5182 return true;
5183}
5184
5185/* initialize adapter hardware
5186 */
5187static bool init_adapter(SLMP_INFO *info)
5188{
5189 int i;
5190
5191 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5192 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5193 u32 readval;
5194
5195 info->misc_ctrl_value |= BIT30;
5196 *MiscCtrl = info->misc_ctrl_value;
5197
5198 /*
5199 * Force at least 170ns delay before clearing
5200 * reset bit. Each read from LCR takes at least
5201 * 30ns so 10 times for 300ns to be safe.
5202 */
5203 for(i=0;i<10;i++)
5204 readval = *MiscCtrl;
5205
5206 info->misc_ctrl_value &= ~BIT30;
5207 *MiscCtrl = info->misc_ctrl_value;
5208
5209 /* init control reg (all DTRs off, all clksel=input) */
5210 info->ctrlreg_value = 0xaa;
5211 write_control_reg(info);
5212
5213 {
5214 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5215 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5216
5217 switch(read_ahead_count)
5218 {
5219 case 16:
5220 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5221 break;
5222 case 8:
5223 lcr1_brdr_value |= BIT5 + BIT4;
5224 break;
5225 case 4:
5226 lcr1_brdr_value |= BIT5 + BIT3;
5227 break;
5228 case 0:
5229 lcr1_brdr_value |= BIT5;
5230 break;
5231 }
5232
5233 *LCR1BRDR = lcr1_brdr_value;
5234 *MiscCtrl = misc_ctrl_value;
5235 }
5236
5237 sca_init(info->port_array[0]);
5238 sca_init(info->port_array[2]);
5239
5240 return true;
5241}
5242
5243/* Loopback an HDLC frame to test the hardware
5244 * interrupt and DMA functions.
5245 */
5246static bool loopback_test(SLMP_INFO *info)
5247{
5248#define TESTFRAMESIZE 20
5249
5250 unsigned long timeout;
5251 u16 count = TESTFRAMESIZE;
5252 unsigned char buf[TESTFRAMESIZE];
5253 bool rc = false;
5254 unsigned long flags;
5255
5256 struct tty_struct *oldtty = info->port.tty;
5257 u32 speed = info->params.clock_speed;
5258
5259 info->params.clock_speed = 3686400;
5260 info->port.tty = NULL;
5261
5262 /* assume failure */
5263 info->init_error = DiagStatus_DmaFailure;
5264
5265 /* build and send transmit frame */
5266 for (count = 0; count < TESTFRAMESIZE;++count)
5267 buf[count] = (unsigned char)count;
5268
5269 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5270
5271 /* program hardware for HDLC and enabled receiver */
5272 spin_lock_irqsave(&info->lock,flags);
5273 hdlc_mode(info);
5274 enable_loopback(info,1);
5275 rx_start(info);
5276 info->tx_count = count;
5277 tx_load_dma_buffer(info,buf,count);
5278 tx_start(info);
5279 spin_unlock_irqrestore(&info->lock,flags);
5280
5281 /* wait for receive complete */
5282 /* Set a timeout for waiting for interrupt. */
5283 for ( timeout = 100; timeout; --timeout ) {
5284 msleep_interruptible(10);
5285
5286 if (rx_get_frame(info)) {
5287 rc = true;
5288 break;
5289 }
5290 }
5291
5292 /* verify received frame length and contents */
5293 if (rc &&
5294 ( info->tmp_rx_buf_count != count ||
5295 memcmp(buf, info->tmp_rx_buf,count))) {
5296 rc = false;
5297 }
5298
5299 spin_lock_irqsave(&info->lock,flags);
5300 reset_adapter(info);
5301 spin_unlock_irqrestore(&info->lock,flags);
5302
5303 info->params.clock_speed = speed;
5304 info->port.tty = oldtty;
5305
5306 return rc;
5307}
5308
5309/* Perform diagnostics on hardware
5310 */
5311static int adapter_test( SLMP_INFO *info )
5312{
5313 unsigned long flags;
5314 if ( debug_level >= DEBUG_LEVEL_INFO )
5315 printk( "%s(%d):Testing device %s\n",
5316 __FILE__,__LINE__,info->device_name );
5317
5318 spin_lock_irqsave(&info->lock,flags);
5319 init_adapter(info);
5320 spin_unlock_irqrestore(&info->lock,flags);
5321
5322 info->port_array[0]->port_count = 0;
5323
5324 if ( register_test(info->port_array[0]) &&
5325 register_test(info->port_array[1])) {
5326
5327 info->port_array[0]->port_count = 2;
5328
5329 if ( register_test(info->port_array[2]) &&
5330 register_test(info->port_array[3]) )
5331 info->port_array[0]->port_count += 2;
5332 }
5333 else {
5334 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5335 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5336 return -ENODEV;
5337 }
5338
5339 if ( !irq_test(info->port_array[0]) ||
5340 !irq_test(info->port_array[1]) ||
5341 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5342 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5343 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5344 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5345 return -ENODEV;
5346 }
5347
5348 if (!loopback_test(info->port_array[0]) ||
5349 !loopback_test(info->port_array[1]) ||
5350 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5351 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5352 printk( "%s(%d):DMA test failure for device %s\n",
5353 __FILE__,__LINE__,info->device_name);
5354 return -ENODEV;
5355 }
5356
5357 if ( debug_level >= DEBUG_LEVEL_INFO )
5358 printk( "%s(%d):device %s passed diagnostics\n",
5359 __FILE__,__LINE__,info->device_name );
5360
5361 info->port_array[0]->init_error = 0;
5362 info->port_array[1]->init_error = 0;
5363 if ( info->port_count > 2 ) {
5364 info->port_array[2]->init_error = 0;
5365 info->port_array[3]->init_error = 0;
5366 }
5367
5368 return 0;
5369}
5370
5371/* Test the shared memory on a PCI adapter.
5372 */
5373static bool memory_test(SLMP_INFO *info)
5374{
5375 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5376 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5377 unsigned long count = ARRAY_SIZE(testval);
5378 unsigned long i;
5379 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5380 unsigned long * addr = (unsigned long *)info->memory_base;
5381
5382 /* Test data lines with test pattern at one location. */
5383
5384 for ( i = 0 ; i < count ; i++ ) {
5385 *addr = testval[i];
5386 if ( *addr != testval[i] )
5387 return false;
5388 }
5389
5390 /* Test address lines with incrementing pattern over */
5391 /* entire address range. */
5392
5393 for ( i = 0 ; i < limit ; i++ ) {
5394 *addr = i * 4;
5395 addr++;
5396 }
5397
5398 addr = (unsigned long *)info->memory_base;
5399
5400 for ( i = 0 ; i < limit ; i++ ) {
5401 if ( *addr != i * 4 )
5402 return false;
5403 addr++;
5404 }
5405
5406 memset( info->memory_base, 0, SCA_MEM_SIZE );
5407 return true;
5408}
5409
5410/* Load data into PCI adapter shared memory.
5411 *
5412 * The PCI9050 releases control of the local bus
5413 * after completing the current read or write operation.
5414 *
5415 * While the PCI9050 write FIFO not empty, the
5416 * PCI9050 treats all of the writes as a single transaction
5417 * and does not release the bus. This causes DMA latency problems
5418 * at high speeds when copying large data blocks to the shared memory.
5419 *
5420 * This function breaks a write into multiple transations by
5421 * interleaving a read which flushes the write FIFO and 'completes'
5422 * the write transation. This allows any pending DMA request to gain control
5423 * of the local bus in a timely fasion.
5424 */
5425static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5426{
5427 /* A load interval of 16 allows for 4 32-bit writes at */
5428 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5429
5430 unsigned short interval = count / sca_pci_load_interval;
5431 unsigned short i;
5432
5433 for ( i = 0 ; i < interval ; i++ )
5434 {
5435 memcpy(dest, src, sca_pci_load_interval);
5436 read_status_reg(info);
5437 dest += sca_pci_load_interval;
5438 src += sca_pci_load_interval;
5439 }
5440
5441 memcpy(dest, src, count % sca_pci_load_interval);
5442}
5443
5444static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5445{
5446 int i;
5447 int linecount;
5448 if (xmit)
5449 printk("%s tx data:\n",info->device_name);
5450 else
5451 printk("%s rx data:\n",info->device_name);
5452
5453 while(count) {
5454 if (count > 16)
5455 linecount = 16;
5456 else
5457 linecount = count;
5458
5459 for(i=0;i<linecount;i++)
5460 printk("%02X ",(unsigned char)data[i]);
5461 for(;i<17;i++)
5462 printk(" ");
5463 for(i=0;i<linecount;i++) {
5464 if (data[i]>=040 && data[i]<=0176)
5465 printk("%c",data[i]);
5466 else
5467 printk(".");
5468 }
5469 printk("\n");
5470
5471 data += linecount;
5472 count -= linecount;
5473 }
5474} /* end of trace_block() */
5475
5476/* called when HDLC frame times out
5477 * update stats and do tx completion processing
5478 */
5479static void tx_timeout(unsigned long context)
5480{
5481 SLMP_INFO *info = (SLMP_INFO*)context;
5482 unsigned long flags;
5483
5484 if ( debug_level >= DEBUG_LEVEL_INFO )
5485 printk( "%s(%d):%s tx_timeout()\n",
5486 __FILE__,__LINE__,info->device_name);
5487 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5488 info->icount.txtimeout++;
5489 }
5490 spin_lock_irqsave(&info->lock,flags);
5491 info->tx_active = false;
5492 info->tx_count = info->tx_put = info->tx_get = 0;
5493
5494 spin_unlock_irqrestore(&info->lock,flags);
5495
5496#if SYNCLINK_GENERIC_HDLC
5497 if (info->netcount)
5498 hdlcdev_tx_done(info);
5499 else
5500#endif
5501 bh_transmit(info);
5502}
5503
5504/* called to periodically check the DSR/RI modem signal input status
5505 */
5506static void status_timeout(unsigned long context)
5507{
5508 u16 status = 0;
5509 SLMP_INFO *info = (SLMP_INFO*)context;
5510 unsigned long flags;
5511 unsigned char delta;
5512
5513
5514 spin_lock_irqsave(&info->lock,flags);
5515 get_signals(info);
5516 spin_unlock_irqrestore(&info->lock,flags);
5517
5518 /* check for DSR/RI state change */
5519
5520 delta = info->old_signals ^ info->serial_signals;
5521 info->old_signals = info->serial_signals;
5522
5523 if (delta & SerialSignal_DSR)
5524 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5525
5526 if (delta & SerialSignal_RI)
5527 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5528
5529 if (delta & SerialSignal_DCD)
5530 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5531
5532 if (delta & SerialSignal_CTS)
5533 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5534
5535 if (status)
5536 isr_io_pin(info,status);
5537
5538 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5539}
5540
5541
5542/* Register Access Routines -
5543 * All registers are memory mapped
5544 */
5545#define CALC_REGADDR() \
5546 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5547 if (info->port_num > 1) \
5548 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5549 if ( info->port_num & 1) { \
5550 if (Addr > 0x7f) \
5551 RegAddr += 0x40; /* DMA access */ \
5552 else if (Addr > 0x1f && Addr < 0x60) \
5553 RegAddr += 0x20; /* MSCI access */ \
5554 }
5555
5556
5557static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5558{
5559 CALC_REGADDR();
5560 return *RegAddr;
5561}
5562static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5563{
5564 CALC_REGADDR();
5565 *RegAddr = Value;
5566}
5567
5568static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5569{
5570 CALC_REGADDR();
5571 return *((u16 *)RegAddr);
5572}
5573
5574static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5575{
5576 CALC_REGADDR();
5577 *((u16 *)RegAddr) = Value;
5578}
5579
5580static unsigned char read_status_reg(SLMP_INFO * info)
5581{
5582 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5583 return *RegAddr;
5584}
5585
5586static void write_control_reg(SLMP_INFO * info)
5587{
5588 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5589 *RegAddr = info->port_array[0]->ctrlreg_value;
5590}
5591
5592
5593static int synclinkmp_init_one (struct pci_dev *dev,
5594 const struct pci_device_id *ent)
5595{
5596 if (pci_enable_device(dev)) {
5597 printk("error enabling pci device %p\n", dev);
5598 return -EIO;
5599 }
5600 return device_init( ++synclinkmp_adapter_count, dev );
5601}
5602
5603static void synclinkmp_remove_one (struct pci_dev *dev)
5604{
5605}