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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
20#include <linux/etherdevice.h>
21#include <linux/device.h>
22#include <linux/interrupt.h>
23#include <linux/leds.h>
24#include <linux/completion.h>
25
26#include "debug.h"
27#include "common.h"
28
29/*
30 * Header for the ath9k.ko driver core *only* -- hw code nor any other driver
31 * should rely on this file or its contents.
32 */
33
34struct ath_node;
35
36/* Macro to expand scalars to 64-bit objects */
37
38#define ito64(x) (sizeof(x) == 1) ? \
39 (((unsigned long long int)(x)) & (0xff)) : \
40 (sizeof(x) == 2) ? \
41 (((unsigned long long int)(x)) & 0xffff) : \
42 ((sizeof(x) == 4) ? \
43 (((unsigned long long int)(x)) & 0xffffffff) : \
44 (unsigned long long int)(x))
45
46/* increment with wrap-around */
47#define INCR(_l, _sz) do { \
48 (_l)++; \
49 (_l) &= ((_sz) - 1); \
50 } while (0)
51
52/* decrement with wrap-around */
53#define DECR(_l, _sz) do { \
54 (_l)--; \
55 (_l) &= ((_sz) - 1); \
56 } while (0)
57
58#define TSF_TO_TU(_h,_l) \
59 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
60
61#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
62
63struct ath_config {
64 u16 txpowlimit;
65 u8 cabqReadytime;
66};
67
68/*************************/
69/* Descriptor Management */
70/*************************/
71
72#define ATH_TXBUF_RESET(_bf) do { \
73 (_bf)->bf_stale = false; \
74 (_bf)->bf_lastbf = NULL; \
75 (_bf)->bf_next = NULL; \
76 memset(&((_bf)->bf_state), 0, \
77 sizeof(struct ath_buf_state)); \
78 } while (0)
79
80#define ATH_RXBUF_RESET(_bf) do { \
81 (_bf)->bf_stale = false; \
82 } while (0)
83
84/**
85 * enum buffer_type - Buffer type flags
86 *
87 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
88 * @BUF_AGGR: Indicates whether the buffer can be aggregated
89 * (used in aggregation scheduling)
90 * @BUF_XRETRY: To denote excessive retries of the buffer
91 */
92enum buffer_type {
93 BUF_AMPDU = BIT(0),
94 BUF_AGGR = BIT(1),
95 BUF_XRETRY = BIT(2),
96};
97
98#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
99#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
100#define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
101
102#define ATH_TXSTATUS_RING_SIZE 64
103
104#define DS2PHYS(_dd, _ds) \
105 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
106#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
107#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
108
109struct ath_descdma {
110 void *dd_desc;
111 dma_addr_t dd_desc_paddr;
112 u32 dd_desc_len;
113 struct ath_buf *dd_bufptr;
114};
115
116int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
117 struct list_head *head, const char *name,
118 int nbuf, int ndesc, bool is_tx);
119void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
120 struct list_head *head);
121
122/***********/
123/* RX / TX */
124/***********/
125
126#define ATH_RXBUF 512
127#define ATH_TXBUF 512
128#define ATH_TXBUF_RESERVE 5
129#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
130#define ATH_TXMAXTRY 13
131
132#define TID_TO_WME_AC(_tid) \
133 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
134 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
135 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
136 WME_AC_VO)
137
138#define ATH_AGGR_DELIM_SZ 4
139#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
140/* number of delimiters for encryption padding */
141#define ATH_AGGR_ENCRYPTDELIM 10
142/* minimum h/w qdepth to be sustained to maximize aggregation */
143#define ATH_AGGR_MIN_QDEPTH 2
144#define ATH_AMPDU_SUBFRAME_DEFAULT 32
145
146#define IEEE80211_SEQ_SEQ_SHIFT 4
147#define IEEE80211_SEQ_MAX 4096
148#define IEEE80211_WEP_IVLEN 3
149#define IEEE80211_WEP_KIDLEN 1
150#define IEEE80211_WEP_CRCLEN 4
151#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
152 (IEEE80211_WEP_IVLEN + \
153 IEEE80211_WEP_KIDLEN + \
154 IEEE80211_WEP_CRCLEN))
155
156/* return whether a bit at index _n in bitmap _bm is set
157 * _sz is the size of the bitmap */
158#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
159 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
160
161/* return block-ack bitmap index given sequence and starting sequence */
162#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
163
164/* returns delimiter padding required given the packet length */
165#define ATH_AGGR_GET_NDELIM(_len) \
166 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
167 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
168
169#define BAW_WITHIN(_start, _bawsz, _seqno) \
170 ((((_seqno) - (_start)) & 4095) < (_bawsz))
171
172#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
173
174#define ATH_TX_COMPLETE_POLL_INT 1000
175
176enum ATH_AGGR_STATUS {
177 ATH_AGGR_DONE,
178 ATH_AGGR_BAW_CLOSED,
179 ATH_AGGR_LIMITED,
180};
181
182#define ATH_TXFIFO_DEPTH 8
183struct ath_txq {
184 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
185 u32 axq_qnum; /* ath9k hardware queue number */
186 void *axq_link;
187 struct list_head axq_q;
188 spinlock_t axq_lock;
189 u32 axq_depth;
190 u32 axq_ampdu_depth;
191 bool stopped;
192 bool axq_tx_inprogress;
193 struct list_head axq_acq;
194 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
195 u8 txq_headidx;
196 u8 txq_tailidx;
197 int pending_frames;
198};
199
200struct ath_atx_ac {
201 struct ath_txq *txq;
202 int sched;
203 struct list_head list;
204 struct list_head tid_q;
205 bool clear_ps_filter;
206};
207
208struct ath_frame_info {
209 int framelen;
210 u32 keyix;
211 enum ath9k_key_type keytype;
212 u8 retries;
213 u16 seqno;
214};
215
216struct ath_buf_state {
217 u8 bf_type;
218 u8 bfs_paprd;
219 unsigned long bfs_paprd_timestamp;
220 enum ath9k_internal_frame_type bfs_ftype;
221};
222
223struct ath_buf {
224 struct list_head list;
225 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
226 an aggregate) */
227 struct ath_buf *bf_next; /* next subframe in the aggregate */
228 struct sk_buff *bf_mpdu; /* enclosing frame structure */
229 void *bf_desc; /* virtual addr of desc */
230 dma_addr_t bf_daddr; /* physical addr of desc */
231 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
232 bool bf_stale;
233 u16 bf_flags;
234 struct ath_buf_state bf_state;
235};
236
237struct ath_atx_tid {
238 struct list_head list;
239 struct list_head buf_q;
240 struct ath_node *an;
241 struct ath_atx_ac *ac;
242 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
243 u16 seq_start;
244 u16 seq_next;
245 u16 baw_size;
246 int tidno;
247 int baw_head; /* first un-acked tx buffer */
248 int baw_tail; /* next unused tx buffer slot */
249 int sched;
250 int paused;
251 u8 state;
252};
253
254struct ath_node {
255#ifdef CONFIG_ATH9K_DEBUGFS
256 struct list_head list; /* for sc->nodes */
257 struct ieee80211_sta *sta; /* station struct we're part of */
258#endif
259 struct ath_atx_tid tid[WME_NUM_TID];
260 struct ath_atx_ac ac[WME_NUM_AC];
261 int ps_key;
262
263 u16 maxampdu;
264 u8 mpdudensity;
265
266 bool sleeping;
267};
268
269#define AGGR_CLEANUP BIT(1)
270#define AGGR_ADDBA_COMPLETE BIT(2)
271#define AGGR_ADDBA_PROGRESS BIT(3)
272
273struct ath_tx_control {
274 struct ath_txq *txq;
275 struct ath_node *an;
276 int if_id;
277 enum ath9k_internal_frame_type frame_type;
278 u8 paprd;
279};
280
281#define ATH_TX_ERROR 0x01
282#define ATH_TX_XRETRY 0x02
283#define ATH_TX_BAR 0x04
284
285/**
286 * @txq_map: Index is mac80211 queue number. This is
287 * not necessarily the same as the hardware queue number
288 * (axq_qnum).
289 */
290struct ath_tx {
291 u16 seq_no;
292 u32 txqsetup;
293 spinlock_t txbuflock;
294 struct list_head txbuf;
295 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
296 struct ath_descdma txdma;
297 struct ath_txq *txq_map[WME_NUM_AC];
298};
299
300struct ath_rx_edma {
301 struct sk_buff_head rx_fifo;
302 struct sk_buff_head rx_buffers;
303 u32 rx_fifo_hwsize;
304};
305
306struct ath_rx {
307 u8 defant;
308 u8 rxotherant;
309 u32 *rxlink;
310 unsigned int rxfilter;
311 spinlock_t rxbuflock;
312 struct list_head rxbuf;
313 struct ath_descdma rxdma;
314 struct ath_buf *rx_bufptr;
315 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
316
317 struct sk_buff *frag;
318};
319
320int ath_startrecv(struct ath_softc *sc);
321bool ath_stoprecv(struct ath_softc *sc);
322void ath_flushrecv(struct ath_softc *sc);
323u32 ath_calcrxfilter(struct ath_softc *sc);
324int ath_rx_init(struct ath_softc *sc, int nbufs);
325void ath_rx_cleanup(struct ath_softc *sc);
326int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
327struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
328void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
329bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
330void ath_draintxq(struct ath_softc *sc,
331 struct ath_txq *txq, bool retry_tx);
332void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
333void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
334void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
335int ath_tx_init(struct ath_softc *sc, int nbufs);
336void ath_tx_cleanup(struct ath_softc *sc);
337int ath_txq_update(struct ath_softc *sc, int qnum,
338 struct ath9k_tx_queue_info *q);
339int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
340 struct ath_tx_control *txctl);
341void ath_tx_tasklet(struct ath_softc *sc);
342void ath_tx_edma_tasklet(struct ath_softc *sc);
343int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
344 u16 tid, u16 *ssn);
345void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
346void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
347
348void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
349bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
350
351/********/
352/* VIFs */
353/********/
354
355struct ath_vif {
356 int av_bslot;
357 bool is_bslot_active, primary_sta_vif;
358 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
359 struct ath_buf *av_bcbuf;
360};
361
362/*******************/
363/* Beacon Handling */
364/*******************/
365
366/*
367 * Regardless of the number of beacons we stagger, (i.e. regardless of the
368 * number of BSSIDs) if a given beacon does not go out even after waiting this
369 * number of beacon intervals, the game's up.
370 */
371#define BSTUCK_THRESH 9
372#define ATH_BCBUF 4
373#define ATH_DEFAULT_BINTVAL 100 /* TU */
374#define ATH_DEFAULT_BMISS_LIMIT 10
375#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
376
377struct ath_beacon_config {
378 int beacon_interval;
379 u16 listen_interval;
380 u16 dtim_period;
381 u16 bmiss_timeout;
382 u8 dtim_count;
383};
384
385struct ath_beacon {
386 enum {
387 OK, /* no change needed */
388 UPDATE, /* update pending */
389 COMMIT /* beacon sent, commit change */
390 } updateslot; /* slot time update fsm */
391
392 u32 beaconq;
393 u32 bmisscnt;
394 u32 ast_be_xmit;
395 u32 bc_tstamp;
396 struct ieee80211_vif *bslot[ATH_BCBUF];
397 int slottime;
398 int slotupdate;
399 struct ath9k_tx_queue_info beacon_qi;
400 struct ath_descdma bdma;
401 struct ath_txq *cabq;
402 struct list_head bbuf;
403
404 bool tx_processed;
405 bool tx_last;
406};
407
408void ath_beacon_tasklet(unsigned long data);
409void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
410int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
411void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
412int ath_beaconq_config(struct ath_softc *sc);
413void ath_set_beacon(struct ath_softc *sc);
414void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
415
416/*******/
417/* ANI */
418/*******/
419
420#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
421#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
422#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
423#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
424#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
425#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
426#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
427
428#define ATH_PAPRD_TIMEOUT 100 /* msecs */
429
430void ath_hw_check(struct work_struct *work);
431void ath_hw_pll_work(struct work_struct *work);
432void ath_paprd_calibrate(struct work_struct *work);
433void ath_ani_calibrate(unsigned long data);
434void ath_start_ani(struct ath_common *common);
435
436/**********/
437/* BTCOEX */
438/**********/
439
440struct ath_btcoex {
441 bool hw_timer_enabled;
442 spinlock_t btcoex_lock;
443 struct timer_list period_timer; /* Timer for BT period */
444 u32 bt_priority_cnt;
445 unsigned long bt_priority_time;
446 int bt_stomp_type; /* Types of BT stomping */
447 u32 btcoex_no_stomp; /* in usec */
448 u32 btcoex_period; /* in usec */
449 u32 btscan_no_stomp; /* in usec */
450 struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
451};
452
453int ath_init_btcoex_timer(struct ath_softc *sc);
454void ath9k_btcoex_timer_resume(struct ath_softc *sc);
455void ath9k_btcoex_timer_pause(struct ath_softc *sc);
456
457/********************/
458/* LED Control */
459/********************/
460
461#define ATH_LED_PIN_DEF 1
462#define ATH_LED_PIN_9287 8
463#define ATH_LED_PIN_9300 10
464#define ATH_LED_PIN_9485 6
465
466#ifdef CONFIG_MAC80211_LEDS
467void ath_init_leds(struct ath_softc *sc);
468void ath_deinit_leds(struct ath_softc *sc);
469#else
470static inline void ath_init_leds(struct ath_softc *sc)
471{
472}
473
474static inline void ath_deinit_leds(struct ath_softc *sc)
475{
476}
477#endif
478
479
480/* Antenna diversity/combining */
481#define ATH_ANT_RX_CURRENT_SHIFT 4
482#define ATH_ANT_RX_MAIN_SHIFT 2
483#define ATH_ANT_RX_MASK 0x3
484
485#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
486#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
487#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
488#define ATH_ANT_DIV_COMB_INIT_COUNT 95
489#define ATH_ANT_DIV_COMB_MAX_COUNT 100
490#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
491#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
492
493#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
494#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
495#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
496#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
497
498enum ath9k_ant_div_comb_lna_conf {
499 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
500 ATH_ANT_DIV_COMB_LNA2,
501 ATH_ANT_DIV_COMB_LNA1,
502 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
503};
504
505struct ath_ant_comb {
506 u16 count;
507 u16 total_pkt_count;
508 bool scan;
509 bool scan_not_start;
510 int main_total_rssi;
511 int alt_total_rssi;
512 int alt_recv_cnt;
513 int main_recv_cnt;
514 int rssi_lna1;
515 int rssi_lna2;
516 int rssi_add;
517 int rssi_sub;
518 int rssi_first;
519 int rssi_second;
520 int rssi_third;
521 bool alt_good;
522 int quick_scan_cnt;
523 int main_conf;
524 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
525 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
526 int first_bias;
527 int second_bias;
528 bool first_ratio;
529 bool second_ratio;
530 unsigned long scan_start_time;
531};
532
533/********************/
534/* Main driver core */
535/********************/
536
537/*
538 * Default cache line size, in bytes.
539 * Used when PCI device not fully initialized by bootrom/BIOS
540*/
541#define DEFAULT_CACHELINE 32
542#define ATH_REGCLASSIDS_MAX 10
543#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
544#define ATH_MAX_SW_RETRIES 10
545#define ATH_CHAN_MAX 255
546
547#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
548#define ATH_RATE_DUMMY_MARKER 0
549
550#define SC_OP_INVALID BIT(0)
551#define SC_OP_BEACONS BIT(1)
552#define SC_OP_RXAGGR BIT(2)
553#define SC_OP_TXAGGR BIT(3)
554#define SC_OP_OFFCHANNEL BIT(4)
555#define SC_OP_PREAMBLE_SHORT BIT(5)
556#define SC_OP_PROTECT_ENABLE BIT(6)
557#define SC_OP_RXFLUSH BIT(7)
558#define SC_OP_LED_ASSOCIATED BIT(8)
559#define SC_OP_LED_ON BIT(9)
560#define SC_OP_TSF_RESET BIT(11)
561#define SC_OP_BT_PRIORITY_DETECTED BIT(12)
562#define SC_OP_BT_SCAN BIT(13)
563#define SC_OP_ANI_RUN BIT(14)
564#define SC_OP_ENABLE_APM BIT(15)
565#define SC_OP_PRIM_STA_VIF BIT(16)
566
567/* Powersave flags */
568#define PS_WAIT_FOR_BEACON BIT(0)
569#define PS_WAIT_FOR_CAB BIT(1)
570#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
571#define PS_WAIT_FOR_TX_ACK BIT(3)
572#define PS_BEACON_SYNC BIT(4)
573#define PS_TSFOOR_SYNC BIT(5)
574
575struct ath_rate_table;
576
577struct ath9k_vif_iter_data {
578 const u8 *hw_macaddr; /* phy's hardware address, set
579 * before starting iteration for
580 * valid bssid mask.
581 */
582 u8 mask[ETH_ALEN]; /* bssid mask */
583 int naps; /* number of AP vifs */
584 int nmeshes; /* number of mesh vifs */
585 int nstations; /* number of station vifs */
586 int nwds; /* number of WDS vifs */
587 int nadhocs; /* number of adhoc vifs */
588 int nothers; /* number of vifs not specified above. */
589};
590
591struct ath_softc {
592 struct ieee80211_hw *hw;
593 struct device *dev;
594
595 int chan_idx;
596 int chan_is_ht;
597 struct survey_info *cur_survey;
598 struct survey_info survey[ATH9K_NUM_CHANNELS];
599
600 struct tasklet_struct intr_tq;
601 struct tasklet_struct bcon_tasklet;
602 struct ath_hw *sc_ah;
603 void __iomem *mem;
604 int irq;
605 spinlock_t sc_serial_rw;
606 spinlock_t sc_pm_lock;
607 spinlock_t sc_pcu_lock;
608 struct mutex mutex;
609 struct work_struct paprd_work;
610 struct work_struct hw_check_work;
611 struct completion paprd_complete;
612
613 unsigned int hw_busy_count;
614
615 u32 intrstatus;
616 u32 sc_flags; /* SC_OP_* */
617 u16 ps_flags; /* PS_* */
618 u16 curtxpow;
619 bool ps_enabled;
620 bool ps_idle;
621 short nbcnvifs;
622 short nvifs;
623 unsigned long ps_usecount;
624
625 struct ath_config config;
626 struct ath_rx rx;
627 struct ath_tx tx;
628 struct ath_beacon beacon;
629 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
630
631#ifdef CONFIG_MAC80211_LEDS
632 bool led_registered;
633 char led_name[32];
634 struct led_classdev led_cdev;
635#endif
636
637 struct ath9k_hw_cal_data caldata;
638 int last_rssi;
639
640#ifdef CONFIG_ATH9K_DEBUGFS
641 struct ath9k_debug debug;
642 spinlock_t nodes_lock;
643 struct list_head nodes; /* basically, stations */
644 unsigned int tx_complete_poll_work_seen;
645#endif
646 struct ath_beacon_config cur_beacon_conf;
647 struct delayed_work tx_complete_work;
648 struct delayed_work hw_pll_work;
649 struct ath_btcoex btcoex;
650
651 struct ath_descdma txsdma;
652
653 struct ath_ant_comb ant_comb;
654};
655
656void ath9k_tasklet(unsigned long data);
657int ath_reset(struct ath_softc *sc, bool retry_tx);
658int ath_cabq_update(struct ath_softc *);
659
660static inline void ath_read_cachesize(struct ath_common *common, int *csz)
661{
662 common->bus_ops->read_cachesize(common, csz);
663}
664
665extern struct ieee80211_ops ath9k_ops;
666extern int ath9k_modparam_nohwcrypt;
667extern int led_blink;
668extern bool is_ath9k_unloaded;
669
670irqreturn_t ath_isr(int irq, void *dev);
671void ath9k_init_crypto(struct ath_softc *sc);
672int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
673 const struct ath_bus_ops *bus_ops);
674void ath9k_deinit_device(struct ath_softc *sc);
675void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
676
677void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
678bool ath9k_uses_beacons(int type);
679
680#ifdef CONFIG_ATH9K_PCI
681int ath_pci_init(void);
682void ath_pci_exit(void);
683#else
684static inline int ath_pci_init(void) { return 0; };
685static inline void ath_pci_exit(void) {};
686#endif
687
688#ifdef CONFIG_ATH9K_AHB
689int ath_ahb_init(void);
690void ath_ahb_exit(void);
691#else
692static inline int ath_ahb_init(void) { return 0; };
693static inline void ath_ahb_exit(void) {};
694#endif
695
696void ath9k_ps_wakeup(struct ath_softc *sc);
697void ath9k_ps_restore(struct ath_softc *sc);
698
699u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
700
701void ath_start_rfkill_poll(struct ath_softc *sc);
702extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
703void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
704 struct ieee80211_vif *vif,
705 struct ath9k_vif_iter_data *iter_data);
706
707
708#endif /* ATH9K_H */
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef ATH9K_H
18#define ATH9K_H
19
20#include <linux/etherdevice.h>
21#include <linux/device.h>
22#include <linux/interrupt.h>
23#include <linux/leds.h>
24#include <linux/completion.h>
25#include <linux/time.h>
26#include <linux/hw_random.h>
27
28#include "common.h"
29#include "debug.h"
30#include "mci.h"
31#include "dfs.h"
32
33struct ath_node;
34struct ath_vif;
35
36extern struct ieee80211_ops ath9k_ops;
37extern int ath9k_modparam_nohwcrypt;
38extern int ath9k_led_blink;
39extern bool is_ath9k_unloaded;
40extern int ath9k_use_chanctx;
41
42/*************************/
43/* Descriptor Management */
44/*************************/
45
46#define ATH_TXSTATUS_RING_SIZE 512
47
48/* Macro to expand scalars to 64-bit objects */
49#define ito64(x) (sizeof(x) == 1) ? \
50 (((unsigned long long int)(x)) & (0xff)) : \
51 (sizeof(x) == 2) ? \
52 (((unsigned long long int)(x)) & 0xffff) : \
53 ((sizeof(x) == 4) ? \
54 (((unsigned long long int)(x)) & 0xffffffff) : \
55 (unsigned long long int)(x))
56
57#define ATH_TXBUF_RESET(_bf) do { \
58 (_bf)->bf_lastbf = NULL; \
59 (_bf)->bf_next = NULL; \
60 memset(&((_bf)->bf_state), 0, \
61 sizeof(struct ath_buf_state)); \
62 } while (0)
63
64#define DS2PHYS(_dd, _ds) \
65 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
66#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
67#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
68
69struct ath_descdma {
70 void *dd_desc;
71 dma_addr_t dd_desc_paddr;
72 u32 dd_desc_len;
73};
74
75int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
76 struct list_head *head, const char *name,
77 int nbuf, int ndesc, bool is_tx);
78
79/***********/
80/* RX / TX */
81/***********/
82
83#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
84
85/* increment with wrap-around */
86#define INCR(_l, _sz) do { \
87 (_l)++; \
88 (_l) &= ((_sz) - 1); \
89 } while (0)
90
91#define ATH_RXBUF 512
92#define ATH_TXBUF 512
93#define ATH_TXBUF_RESERVE 5
94#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
95#define ATH_TXMAXTRY 13
96#define ATH_MAX_SW_RETRIES 30
97
98#define TID_TO_WME_AC(_tid) \
99 ((((_tid) == 0) || ((_tid) == 3)) ? IEEE80211_AC_BE : \
100 (((_tid) == 1) || ((_tid) == 2)) ? IEEE80211_AC_BK : \
101 (((_tid) == 4) || ((_tid) == 5)) ? IEEE80211_AC_VI : \
102 IEEE80211_AC_VO)
103
104#define ATH_AGGR_DELIM_SZ 4
105#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
106/* number of delimiters for encryption padding */
107#define ATH_AGGR_ENCRYPTDELIM 10
108/* minimum h/w qdepth to be sustained to maximize aggregation */
109#define ATH_AGGR_MIN_QDEPTH 2
110/* minimum h/w qdepth for non-aggregated traffic */
111#define ATH_NON_AGGR_MIN_QDEPTH 8
112#define ATH_TX_COMPLETE_POLL_INT 1000
113#define ATH_TXFIFO_DEPTH 8
114#define ATH_TX_ERROR 0x01
115
116/* Stop tx traffic 1ms before the GO goes away */
117#define ATH_P2P_PS_STOP_TIME 1000
118
119#define IEEE80211_SEQ_SEQ_SHIFT 4
120#define IEEE80211_SEQ_MAX 4096
121#define IEEE80211_WEP_IVLEN 3
122#define IEEE80211_WEP_KIDLEN 1
123#define IEEE80211_WEP_CRCLEN 4
124#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
125 (IEEE80211_WEP_IVLEN + \
126 IEEE80211_WEP_KIDLEN + \
127 IEEE80211_WEP_CRCLEN))
128
129/* return whether a bit at index _n in bitmap _bm is set
130 * _sz is the size of the bitmap */
131#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
132 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
133
134/* return block-ack bitmap index given sequence and starting sequence */
135#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
136
137/* return the seqno for _start + _offset */
138#define ATH_BA_INDEX2SEQ(_seq, _offset) (((_seq) + (_offset)) & (IEEE80211_SEQ_MAX - 1))
139
140/* returns delimiter padding required given the packet length */
141#define ATH_AGGR_GET_NDELIM(_len) \
142 (((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
143 DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
144
145#define BAW_WITHIN(_start, _bawsz, _seqno) \
146 ((((_seqno) - (_start)) & 4095) < (_bawsz))
147
148#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
149
150#define IS_HT_RATE(rate) (rate & 0x80)
151#define IS_CCK_RATE(rate) ((rate >= 0x18) && (rate <= 0x1e))
152#define IS_OFDM_RATE(rate) ((rate >= 0x8) && (rate <= 0xf))
153
154enum {
155 WLAN_RC_PHY_OFDM,
156 WLAN_RC_PHY_CCK,
157};
158
159struct ath_txq {
160 int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
161 u32 axq_qnum; /* ath9k hardware queue number */
162 void *axq_link;
163 struct list_head axq_q;
164 spinlock_t axq_lock;
165 u32 axq_depth;
166 u32 axq_ampdu_depth;
167 bool stopped;
168 bool axq_tx_inprogress;
169 struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
170 u8 txq_headidx;
171 u8 txq_tailidx;
172 int pending_frames;
173 struct sk_buff_head complete_q;
174};
175
176struct ath_frame_info {
177 struct ath_buf *bf;
178 u16 framelen;
179 s8 txq;
180 u8 keyix;
181 u8 rtscts_rate;
182 u8 retries : 7;
183 u8 baw_tracked : 1;
184 u8 tx_power;
185 enum ath9k_key_type keytype:2;
186};
187
188struct ath_rxbuf {
189 struct list_head list;
190 struct sk_buff *bf_mpdu;
191 void *bf_desc;
192 dma_addr_t bf_daddr;
193 dma_addr_t bf_buf_addr;
194};
195
196/**
197 * enum buffer_type - Buffer type flags
198 *
199 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
200 * @BUF_AGGR: Indicates whether the buffer can be aggregated
201 * (used in aggregation scheduling)
202 */
203enum buffer_type {
204 BUF_AMPDU = BIT(0),
205 BUF_AGGR = BIT(1),
206};
207
208#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
209#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
210
211struct ath_buf_state {
212 u8 bf_type;
213 u8 bfs_paprd;
214 u8 ndelim;
215 bool stale;
216 u16 seqno;
217 unsigned long bfs_paprd_timestamp;
218};
219
220struct ath_buf {
221 struct list_head list;
222 struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
223 an aggregate) */
224 struct ath_buf *bf_next; /* next subframe in the aggregate */
225 struct sk_buff *bf_mpdu; /* enclosing frame structure */
226 void *bf_desc; /* virtual addr of desc */
227 dma_addr_t bf_daddr; /* physical addr of desc */
228 dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
229 struct ieee80211_tx_rate rates[4];
230 struct ath_buf_state bf_state;
231};
232
233struct ath_atx_tid {
234 struct list_head list;
235 struct sk_buff_head buf_q;
236 struct sk_buff_head retry_q;
237 struct ath_node *an;
238 struct ath_txq *txq;
239 unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
240 u16 seq_start;
241 u16 seq_next;
242 u16 baw_size;
243 u8 tidno;
244 int baw_head; /* first un-acked tx buffer */
245 int baw_tail; /* next unused tx buffer slot */
246
247 s8 bar_index;
248 bool active;
249 bool clear_ps_filter;
250};
251
252struct ath_node {
253 struct ath_softc *sc;
254 struct ieee80211_sta *sta; /* station struct we're part of */
255 struct ieee80211_vif *vif; /* interface with which we're associated */
256 struct ath_atx_tid tid[IEEE80211_NUM_TIDS];
257
258 u16 maxampdu;
259 u8 mpdudensity;
260 s8 ps_key;
261
262 bool sleeping;
263 bool no_ps_filter;
264
265#ifdef CONFIG_ATH9K_STATION_STATISTICS
266 struct ath_rx_rate_stats rx_rate_stats;
267#endif
268 u8 key_idx[4];
269
270 u32 ackto;
271 struct list_head list;
272};
273
274struct ath_tx_control {
275 struct ath_txq *txq;
276 struct ath_node *an;
277 struct ieee80211_sta *sta;
278 u8 paprd;
279 bool force_channel;
280};
281
282
283/**
284 * @txq_map: Index is mac80211 queue number. This is
285 * not necessarily the same as the hardware queue number
286 * (axq_qnum).
287 */
288struct ath_tx {
289 u32 txqsetup;
290 spinlock_t txbuflock;
291 struct list_head txbuf;
292 struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
293 struct ath_descdma txdma;
294 struct ath_txq *txq_map[IEEE80211_NUM_ACS];
295 struct ath_txq *uapsdq;
296 u32 txq_max_pending[IEEE80211_NUM_ACS];
297 u16 max_aggr_framelen[IEEE80211_NUM_ACS][4][32];
298};
299
300struct ath_rx_edma {
301 struct sk_buff_head rx_fifo;
302 u32 rx_fifo_hwsize;
303};
304
305struct ath_rx {
306 u8 defant;
307 u8 rxotherant;
308 bool discard_next;
309 u32 *rxlink;
310 u32 num_pkts;
311 struct list_head rxbuf;
312 struct ath_descdma rxdma;
313 struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
314
315 struct ath_rxbuf *buf_hold;
316 struct sk_buff *frag;
317
318 u32 ampdu_ref;
319};
320
321/*******************/
322/* Channel Context */
323/*******************/
324
325struct ath_chanctx {
326 struct cfg80211_chan_def chandef;
327 struct list_head vifs;
328 struct list_head acq[IEEE80211_NUM_ACS];
329 int hw_queue_base;
330
331 /* do not dereference, use for comparison only */
332 struct ieee80211_vif *primary_sta;
333
334 struct ath_beacon_config beacon;
335 struct ath9k_hw_cal_data caldata;
336 struct timespec tsf_ts;
337 u64 tsf_val;
338 u32 last_beacon;
339
340 int flush_timeout;
341 u16 txpower;
342 u16 cur_txpower;
343 bool offchannel;
344 bool stopped;
345 bool active;
346 bool assigned;
347 bool switch_after_beacon;
348
349 short nvifs;
350 short nvifs_assigned;
351 unsigned int rxfilter;
352};
353
354enum ath_chanctx_event {
355 ATH_CHANCTX_EVENT_BEACON_PREPARE,
356 ATH_CHANCTX_EVENT_BEACON_SENT,
357 ATH_CHANCTX_EVENT_TSF_TIMER,
358 ATH_CHANCTX_EVENT_BEACON_RECEIVED,
359 ATH_CHANCTX_EVENT_AUTHORIZED,
360 ATH_CHANCTX_EVENT_SWITCH,
361 ATH_CHANCTX_EVENT_ASSIGN,
362 ATH_CHANCTX_EVENT_UNASSIGN,
363 ATH_CHANCTX_EVENT_CHANGE,
364 ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL,
365};
366
367enum ath_chanctx_state {
368 ATH_CHANCTX_STATE_IDLE,
369 ATH_CHANCTX_STATE_WAIT_FOR_BEACON,
370 ATH_CHANCTX_STATE_WAIT_FOR_TIMER,
371 ATH_CHANCTX_STATE_SWITCH,
372 ATH_CHANCTX_STATE_FORCE_ACTIVE,
373};
374
375struct ath_chanctx_sched {
376 bool beacon_pending;
377 bool beacon_adjust;
378 bool offchannel_pending;
379 bool wait_switch;
380 bool force_noa_update;
381 bool extend_absence;
382 bool mgd_prepare_tx;
383 enum ath_chanctx_state state;
384 u8 beacon_miss;
385
386 u32 next_tbtt;
387 u32 switch_start_time;
388 unsigned int offchannel_duration;
389 unsigned int channel_switch_time;
390
391 /* backup, in case the hardware timer fails */
392 struct timer_list timer;
393};
394
395enum ath_offchannel_state {
396 ATH_OFFCHANNEL_IDLE,
397 ATH_OFFCHANNEL_PROBE_SEND,
398 ATH_OFFCHANNEL_PROBE_WAIT,
399 ATH_OFFCHANNEL_SUSPEND,
400 ATH_OFFCHANNEL_ROC_START,
401 ATH_OFFCHANNEL_ROC_WAIT,
402 ATH_OFFCHANNEL_ROC_DONE,
403};
404
405enum ath_roc_complete_reason {
406 ATH_ROC_COMPLETE_EXPIRE,
407 ATH_ROC_COMPLETE_ABORT,
408 ATH_ROC_COMPLETE_CANCEL,
409};
410
411struct ath_offchannel {
412 struct ath_chanctx chan;
413 struct timer_list timer;
414 struct cfg80211_scan_request *scan_req;
415 struct ieee80211_vif *scan_vif;
416 int scan_idx;
417 enum ath_offchannel_state state;
418 struct ieee80211_channel *roc_chan;
419 struct ieee80211_vif *roc_vif;
420 int roc_duration;
421 int duration;
422};
423
424#define case_rtn_string(val) case val: return #val
425
426#define ath_for_each_chanctx(_sc, _ctx) \
427 for (ctx = &sc->chanctx[0]; \
428 ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \
429 ctx++)
430
431void ath_chanctx_init(struct ath_softc *sc);
432void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx,
433 struct cfg80211_chan_def *chandef);
434
435#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
436
437static inline struct ath_chanctx *
438ath_chanctx_get(struct ieee80211_chanctx_conf *ctx)
439{
440 struct ath_chanctx **ptr = (void *) ctx->drv_priv;
441 return *ptr;
442}
443
444bool ath9k_is_chanctx_enabled(void);
445void ath9k_fill_chanctx_ops(void);
446void ath9k_init_channel_context(struct ath_softc *sc);
447void ath9k_offchannel_init(struct ath_softc *sc);
448void ath9k_deinit_channel_context(struct ath_softc *sc);
449int ath9k_init_p2p(struct ath_softc *sc);
450void ath9k_deinit_p2p(struct ath_softc *sc);
451void ath9k_p2p_remove_vif(struct ath_softc *sc,
452 struct ieee80211_vif *vif);
453void ath9k_p2p_beacon_sync(struct ath_softc *sc);
454void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
455 struct ieee80211_vif *vif);
456void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
457 struct sk_buff *skb);
458void ath9k_p2p_ps_timer(void *priv);
459void ath9k_chanctx_wake_queues(struct ath_softc *sc, struct ath_chanctx *ctx);
460void ath9k_chanctx_stop_queues(struct ath_softc *sc, struct ath_chanctx *ctx);
461void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx);
462
463void ath_chanctx_beacon_recv_ev(struct ath_softc *sc,
464 enum ath_chanctx_event ev);
465void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
466 enum ath_chanctx_event ev);
467void ath_chanctx_event(struct ath_softc *sc, struct ieee80211_vif *vif,
468 enum ath_chanctx_event ev);
469void ath_chanctx_set_next(struct ath_softc *sc, bool force);
470void ath_offchannel_next(struct ath_softc *sc);
471void ath_scan_complete(struct ath_softc *sc, bool abort);
472void ath_roc_complete(struct ath_softc *sc,
473 enum ath_roc_complete_reason reason);
474struct ath_chanctx* ath_is_go_chanctx_present(struct ath_softc *sc);
475
476#else
477
478static inline bool ath9k_is_chanctx_enabled(void)
479{
480 return false;
481}
482static inline void ath9k_fill_chanctx_ops(void)
483{
484}
485static inline void ath9k_init_channel_context(struct ath_softc *sc)
486{
487}
488static inline void ath9k_offchannel_init(struct ath_softc *sc)
489{
490}
491static inline void ath9k_deinit_channel_context(struct ath_softc *sc)
492{
493}
494static inline void ath_chanctx_beacon_recv_ev(struct ath_softc *sc,
495 enum ath_chanctx_event ev)
496{
497}
498static inline void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
499 enum ath_chanctx_event ev)
500{
501}
502static inline void ath_chanctx_event(struct ath_softc *sc,
503 struct ieee80211_vif *vif,
504 enum ath_chanctx_event ev)
505{
506}
507static inline int ath9k_init_p2p(struct ath_softc *sc)
508{
509 return 0;
510}
511static inline void ath9k_deinit_p2p(struct ath_softc *sc)
512{
513}
514static inline void ath9k_p2p_remove_vif(struct ath_softc *sc,
515 struct ieee80211_vif *vif)
516{
517}
518static inline void ath9k_p2p_beacon_sync(struct ath_softc *sc)
519{
520}
521static inline void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
522 struct ieee80211_vif *vif)
523{
524}
525static inline void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
526 struct sk_buff *skb)
527{
528}
529static inline void ath9k_p2p_ps_timer(struct ath_softc *sc)
530{
531}
532static inline void ath9k_chanctx_wake_queues(struct ath_softc *sc,
533 struct ath_chanctx *ctx)
534{
535}
536static inline void ath9k_chanctx_stop_queues(struct ath_softc *sc,
537 struct ath_chanctx *ctx)
538{
539}
540static inline void ath_chanctx_check_active(struct ath_softc *sc,
541 struct ath_chanctx *ctx)
542{
543}
544
545#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
546
547void ath_startrecv(struct ath_softc *sc);
548bool ath_stoprecv(struct ath_softc *sc);
549u32 ath_calcrxfilter(struct ath_softc *sc);
550int ath_rx_init(struct ath_softc *sc, int nbufs);
551void ath_rx_cleanup(struct ath_softc *sc);
552int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
553struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
554void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq);
555void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq);
556void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq);
557void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
558bool ath_drain_all_txq(struct ath_softc *sc);
559void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq);
560void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
561void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
562void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
563void ath_txq_schedule_all(struct ath_softc *sc);
564int ath_tx_init(struct ath_softc *sc, int nbufs);
565int ath_txq_update(struct ath_softc *sc, int qnum,
566 struct ath9k_tx_queue_info *q);
567void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
568void ath_assign_seq(struct ath_common *common, struct sk_buff *skb);
569int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
570 struct ath_tx_control *txctl);
571void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
572 struct sk_buff *skb);
573void ath_tx_tasklet(struct ath_softc *sc);
574void ath_tx_edma_tasklet(struct ath_softc *sc);
575int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
576 u16 tid, u16 *ssn);
577void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
578void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
579
580void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
581void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
582 struct ath_node *an);
583void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
584 struct ieee80211_sta *sta,
585 u16 tids, int nframes,
586 enum ieee80211_frame_release_type reason,
587 bool more_data);
588
589/********/
590/* VIFs */
591/********/
592
593#define P2P_DEFAULT_CTWIN 10
594
595struct ath_vif {
596 struct list_head list;
597
598 u16 seq_no;
599
600 /* BSS info */
601 u8 bssid[ETH_ALEN] __aligned(2);
602 u16 aid;
603 bool assoc;
604
605 struct ieee80211_vif *vif;
606 struct ath_node mcast_node;
607 int av_bslot;
608 __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
609 struct ath_buf *av_bcbuf;
610 struct ath_chanctx *chanctx;
611
612 /* P2P Client */
613 struct ieee80211_noa_data noa;
614
615 /* P2P GO */
616 u8 noa_index;
617 u32 offchannel_start;
618 u32 offchannel_duration;
619
620 /* These are used for both periodic and one-shot */
621 u32 noa_start;
622 u32 noa_duration;
623 bool periodic_noa;
624 bool oneshot_noa;
625};
626
627struct ath9k_vif_iter_data {
628 u8 hw_macaddr[ETH_ALEN]; /* address of the first vif */
629 u8 mask[ETH_ALEN]; /* bssid mask */
630 bool has_hw_macaddr;
631 u8 slottime;
632 bool beacons;
633
634 int naps; /* number of AP vifs */
635 int nmeshes; /* number of mesh vifs */
636 int nstations; /* number of station vifs */
637 int nwds; /* number of WDS vifs */
638 int nadhocs; /* number of adhoc vifs */
639 int nocbs; /* number of OCB vifs */
640 struct ieee80211_vif *primary_sta;
641};
642
643void ath9k_calculate_iter_data(struct ath_softc *sc,
644 struct ath_chanctx *ctx,
645 struct ath9k_vif_iter_data *iter_data);
646void ath9k_calculate_summary_state(struct ath_softc *sc,
647 struct ath_chanctx *ctx);
648void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif);
649
650/*******************/
651/* Beacon Handling */
652/*******************/
653
654/*
655 * Regardless of the number of beacons we stagger, (i.e. regardless of the
656 * number of BSSIDs) if a given beacon does not go out even after waiting this
657 * number of beacon intervals, the game's up.
658 */
659#define BSTUCK_THRESH 9
660#define ATH_BCBUF 8
661#define ATH_DEFAULT_BINTVAL 100 /* TU */
662#define ATH_DEFAULT_BMISS_LIMIT 10
663
664#define TSF_TO_TU(_h,_l) \
665 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
666
667struct ath_beacon {
668 enum {
669 OK, /* no change needed */
670 UPDATE, /* update pending */
671 COMMIT /* beacon sent, commit change */
672 } updateslot; /* slot time update fsm */
673
674 u32 beaconq;
675 u32 bmisscnt;
676 struct ieee80211_vif *bslot[ATH_BCBUF];
677 int slottime;
678 int slotupdate;
679 struct ath_descdma bdma;
680 struct ath_txq *cabq;
681 struct list_head bbuf;
682
683 bool tx_processed;
684 bool tx_last;
685};
686
687void ath9k_beacon_tasklet(unsigned long data);
688void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
689 u32 changed);
690void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
691void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
692void ath9k_set_beacon(struct ath_softc *sc);
693bool ath9k_csa_is_finished(struct ath_softc *sc, struct ieee80211_vif *vif);
694void ath9k_csa_update(struct ath_softc *sc);
695
696/*******************/
697/* Link Monitoring */
698/*******************/
699
700#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
701#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
702#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
703#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
704#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
705#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
706#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
707#define ATH_ANI_MAX_SKIP_COUNT 10
708#define ATH_PAPRD_TIMEOUT 100 /* msecs */
709#define ATH_PLL_WORK_INTERVAL 100
710
711void ath_tx_complete_poll_work(struct work_struct *work);
712void ath_reset_work(struct work_struct *work);
713bool ath_hw_check(struct ath_softc *sc);
714void ath_hw_pll_work(struct work_struct *work);
715void ath_paprd_calibrate(struct work_struct *work);
716void ath_ani_calibrate(unsigned long data);
717void ath_start_ani(struct ath_softc *sc);
718void ath_stop_ani(struct ath_softc *sc);
719void ath_check_ani(struct ath_softc *sc);
720int ath_update_survey_stats(struct ath_softc *sc);
721void ath_update_survey_nf(struct ath_softc *sc, int channel);
722void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
723void ath_ps_full_sleep(unsigned long data);
724void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
725 bool sw_pending, bool timeout_override);
726
727/**********/
728/* BTCOEX */
729/**********/
730
731#define ATH_DUMP_BTCOEX(_s, _val) \
732 do { \
733 len += scnprintf(buf + len, size - len, \
734 "%20s : %10d\n", _s, (_val)); \
735 } while (0)
736
737enum bt_op_flags {
738 BT_OP_PRIORITY_DETECTED,
739 BT_OP_SCAN,
740};
741
742struct ath_btcoex {
743 spinlock_t btcoex_lock;
744 struct timer_list period_timer; /* Timer for BT period */
745 struct timer_list no_stomp_timer;
746 u32 bt_priority_cnt;
747 unsigned long bt_priority_time;
748 unsigned long op_flags;
749 int bt_stomp_type; /* Types of BT stomping */
750 u32 btcoex_no_stomp; /* in msec */
751 u32 btcoex_period; /* in msec */
752 u32 btscan_no_stomp; /* in msec */
753 u32 duty_cycle;
754 u32 bt_wait_time;
755 int rssi_count;
756 struct ath_mci_profile mci;
757 u8 stomp_audio;
758};
759
760#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
761int ath9k_init_btcoex(struct ath_softc *sc);
762void ath9k_deinit_btcoex(struct ath_softc *sc);
763void ath9k_start_btcoex(struct ath_softc *sc);
764void ath9k_stop_btcoex(struct ath_softc *sc);
765void ath9k_btcoex_timer_resume(struct ath_softc *sc);
766void ath9k_btcoex_timer_pause(struct ath_softc *sc);
767void ath9k_btcoex_handle_interrupt(struct ath_softc *sc, u32 status);
768u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc, u32 max_4ms_framelen);
769void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc);
770int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size);
771#else
772static inline int ath9k_init_btcoex(struct ath_softc *sc)
773{
774 return 0;
775}
776static inline void ath9k_deinit_btcoex(struct ath_softc *sc)
777{
778}
779static inline void ath9k_start_btcoex(struct ath_softc *sc)
780{
781}
782static inline void ath9k_stop_btcoex(struct ath_softc *sc)
783{
784}
785static inline void ath9k_btcoex_handle_interrupt(struct ath_softc *sc,
786 u32 status)
787{
788}
789static inline u16 ath9k_btcoex_aggr_limit(struct ath_softc *sc,
790 u32 max_4ms_framelen)
791{
792 return 0;
793}
794static inline void ath9k_btcoex_stop_gen_timer(struct ath_softc *sc)
795{
796}
797static inline int ath9k_dump_btcoex(struct ath_softc *sc, u8 *buf, u32 size)
798{
799 return 0;
800}
801#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
802
803/********************/
804/* LED Control */
805/********************/
806
807#define ATH_LED_PIN_DEF 1
808#define ATH_LED_PIN_9287 8
809#define ATH_LED_PIN_9300 10
810#define ATH_LED_PIN_9485 6
811#define ATH_LED_PIN_9462 4
812
813#ifdef CONFIG_MAC80211_LEDS
814void ath_init_leds(struct ath_softc *sc);
815void ath_deinit_leds(struct ath_softc *sc);
816void ath_fill_led_pin(struct ath_softc *sc);
817#else
818static inline void ath_init_leds(struct ath_softc *sc)
819{
820}
821
822static inline void ath_deinit_leds(struct ath_softc *sc)
823{
824}
825static inline void ath_fill_led_pin(struct ath_softc *sc)
826{
827}
828#endif
829
830/************************/
831/* Wake on Wireless LAN */
832/************************/
833
834#ifdef CONFIG_ATH9K_WOW
835void ath9k_init_wow(struct ieee80211_hw *hw);
836void ath9k_deinit_wow(struct ieee80211_hw *hw);
837int ath9k_suspend(struct ieee80211_hw *hw,
838 struct cfg80211_wowlan *wowlan);
839int ath9k_resume(struct ieee80211_hw *hw);
840void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled);
841#else
842static inline void ath9k_init_wow(struct ieee80211_hw *hw)
843{
844}
845static inline void ath9k_deinit_wow(struct ieee80211_hw *hw)
846{
847}
848static inline int ath9k_suspend(struct ieee80211_hw *hw,
849 struct cfg80211_wowlan *wowlan)
850{
851 return 0;
852}
853static inline int ath9k_resume(struct ieee80211_hw *hw)
854{
855 return 0;
856}
857static inline void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
858{
859}
860#endif /* CONFIG_ATH9K_WOW */
861
862/*******************************/
863/* Antenna diversity/combining */
864/*******************************/
865
866#define ATH_ANT_RX_CURRENT_SHIFT 4
867#define ATH_ANT_RX_MAIN_SHIFT 2
868#define ATH_ANT_RX_MASK 0x3
869
870#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
871#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
872#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
873#define ATH_ANT_DIV_COMB_INIT_COUNT 95
874#define ATH_ANT_DIV_COMB_MAX_COUNT 100
875#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
876#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
877#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO_LOW_RSSI 50
878#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2_LOW_RSSI 50
879
880#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
881#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
882#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
883
884struct ath_ant_comb {
885 u16 count;
886 u16 total_pkt_count;
887 bool scan;
888 bool scan_not_start;
889 int main_total_rssi;
890 int alt_total_rssi;
891 int alt_recv_cnt;
892 int main_recv_cnt;
893 int rssi_lna1;
894 int rssi_lna2;
895 int rssi_add;
896 int rssi_sub;
897 int rssi_first;
898 int rssi_second;
899 int rssi_third;
900 int ant_ratio;
901 int ant_ratio2;
902 bool alt_good;
903 int quick_scan_cnt;
904 enum ath9k_ant_div_comb_lna_conf main_conf;
905 enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
906 enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
907 bool first_ratio;
908 bool second_ratio;
909 unsigned long scan_start_time;
910
911 /*
912 * Card-specific config values.
913 */
914 int low_rssi_thresh;
915 int fast_div_bias;
916};
917
918void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs);
919
920/********************/
921/* Main driver core */
922/********************/
923
924#define ATH9K_PCI_CUS198 0x0001
925#define ATH9K_PCI_CUS230 0x0002
926#define ATH9K_PCI_CUS217 0x0004
927#define ATH9K_PCI_CUS252 0x0008
928#define ATH9K_PCI_WOW 0x0010
929#define ATH9K_PCI_BT_ANT_DIV 0x0020
930#define ATH9K_PCI_D3_L1_WAR 0x0040
931#define ATH9K_PCI_AR9565_1ANT 0x0080
932#define ATH9K_PCI_AR9565_2ANT 0x0100
933#define ATH9K_PCI_NO_PLL_PWRSAVE 0x0200
934#define ATH9K_PCI_KILLER 0x0400
935#define ATH9K_PCI_LED_ACT_HI 0x0800
936
937/*
938 * Default cache line size, in bytes.
939 * Used when PCI device not fully initialized by bootrom/BIOS
940*/
941#define DEFAULT_CACHELINE 32
942#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
943#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
944#define MAX_GTT_CNT 5
945
946/* Powersave flags */
947#define PS_WAIT_FOR_BEACON BIT(0)
948#define PS_WAIT_FOR_CAB BIT(1)
949#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
950#define PS_WAIT_FOR_TX_ACK BIT(3)
951#define PS_BEACON_SYNC BIT(4)
952#define PS_WAIT_FOR_ANI BIT(5)
953
954#define ATH9K_NUM_CHANCTX 2 /* supports 2 operating channels */
955
956struct ath_softc {
957 struct ieee80211_hw *hw;
958 struct device *dev;
959
960 struct survey_info *cur_survey;
961 struct survey_info survey[ATH9K_NUM_CHANNELS];
962
963 struct tasklet_struct intr_tq;
964 struct tasklet_struct bcon_tasklet;
965 struct ath_hw *sc_ah;
966 void __iomem *mem;
967 int irq;
968 spinlock_t sc_serial_rw;
969 spinlock_t sc_pm_lock;
970 spinlock_t sc_pcu_lock;
971 struct mutex mutex;
972 struct work_struct paprd_work;
973 struct work_struct hw_reset_work;
974 struct completion paprd_complete;
975 wait_queue_head_t tx_wait;
976
977#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
978 struct work_struct chanctx_work;
979 struct ath_gen_timer *p2p_ps_timer;
980 struct ath_vif *p2p_ps_vif;
981 struct ath_chanctx_sched sched;
982 struct ath_offchannel offchannel;
983 struct ath_chanctx *next_chan;
984 struct completion go_beacon;
985 struct timespec last_event_time;
986#endif
987
988 unsigned long driver_data;
989
990 u8 gtt_cnt;
991 u32 intrstatus;
992 u16 ps_flags; /* PS_* */
993 bool ps_enabled;
994 bool ps_idle;
995 short nbcnvifs;
996 unsigned long ps_usecount;
997
998 struct ath_rx rx;
999 struct ath_tx tx;
1000 struct ath_beacon beacon;
1001
1002 struct cfg80211_chan_def cur_chandef;
1003 struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX];
1004 struct ath_chanctx *cur_chan;
1005 spinlock_t chan_lock;
1006
1007#ifdef CONFIG_MAC80211_LEDS
1008 bool led_registered;
1009 char led_name[32];
1010 struct led_classdev led_cdev;
1011#endif
1012
1013#ifdef CONFIG_ATH9K_DEBUGFS
1014 struct ath9k_debug debug;
1015#endif
1016 struct delayed_work tx_complete_work;
1017 struct delayed_work hw_pll_work;
1018 struct timer_list sleep_timer;
1019
1020#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1021 struct ath_btcoex btcoex;
1022 struct ath_mci_coex mci_coex;
1023 struct work_struct mci_work;
1024#endif
1025
1026 struct ath_descdma txsdma;
1027
1028 struct ath_ant_comb ant_comb;
1029 u8 ant_tx, ant_rx;
1030 struct dfs_pattern_detector *dfs_detector;
1031 u64 dfs_prev_pulse_ts;
1032 u32 wow_enabled;
1033
1034 struct ath_spec_scan_priv spec_priv;
1035
1036 struct ieee80211_vif *tx99_vif;
1037 struct sk_buff *tx99_skb;
1038 bool tx99_state;
1039 s16 tx99_power;
1040
1041#ifdef CONFIG_ATH9K_WOW
1042 u32 wow_intr_before_sleep;
1043 bool force_wow;
1044#endif
1045
1046#ifdef CONFIG_ATH9K_HWRNG
1047 u32 rng_last;
1048 struct task_struct *rng_task;
1049#endif
1050};
1051
1052/********/
1053/* TX99 */
1054/********/
1055
1056#ifdef CONFIG_ATH9K_TX99
1057void ath9k_tx99_init_debug(struct ath_softc *sc);
1058int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
1059 struct ath_tx_control *txctl);
1060#else
1061static inline void ath9k_tx99_init_debug(struct ath_softc *sc)
1062{
1063}
1064static inline int ath9k_tx99_send(struct ath_softc *sc,
1065 struct sk_buff *skb,
1066 struct ath_tx_control *txctl)
1067{
1068 return 0;
1069}
1070#endif /* CONFIG_ATH9K_TX99 */
1071
1072/***************************/
1073/* Random Number Generator */
1074/***************************/
1075#ifdef CONFIG_ATH9K_HWRNG
1076void ath9k_rng_start(struct ath_softc *sc);
1077void ath9k_rng_stop(struct ath_softc *sc);
1078#else
1079static inline void ath9k_rng_start(struct ath_softc *sc)
1080{
1081}
1082
1083static inline void ath9k_rng_stop(struct ath_softc *sc)
1084{
1085}
1086#endif
1087
1088static inline void ath_read_cachesize(struct ath_common *common, int *csz)
1089{
1090 common->bus_ops->read_cachesize(common, csz);
1091}
1092
1093void ath9k_tasklet(unsigned long data);
1094int ath_cabq_update(struct ath_softc *);
1095u8 ath9k_parse_mpdudensity(u8 mpdudensity);
1096irqreturn_t ath_isr(int irq, void *dev);
1097int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan);
1098void ath_cancel_work(struct ath_softc *sc);
1099void ath_restart_work(struct ath_softc *sc);
1100int ath9k_init_device(u16 devid, struct ath_softc *sc,
1101 const struct ath_bus_ops *bus_ops);
1102void ath9k_deinit_device(struct ath_softc *sc);
1103void ath9k_reload_chainmask_settings(struct ath_softc *sc);
1104u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
1105void ath_start_rfkill_poll(struct ath_softc *sc);
1106void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
1107void ath9k_ps_wakeup(struct ath_softc *sc);
1108void ath9k_ps_restore(struct ath_softc *sc);
1109
1110#ifdef CONFIG_ATH9K_PCI
1111int ath_pci_init(void);
1112void ath_pci_exit(void);
1113#else
1114static inline int ath_pci_init(void) { return 0; };
1115static inline void ath_pci_exit(void) {};
1116#endif
1117
1118#ifdef CONFIG_ATH9K_AHB
1119int ath_ahb_init(void);
1120void ath_ahb_exit(void);
1121#else
1122static inline int ath_ahb_init(void) { return 0; };
1123static inline void ath_ahb_exit(void) {};
1124#endif
1125
1126#endif /* ATH9K_H */