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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _RX_DESC_H_
19#define _RX_DESC_H_
20
21enum rx_attention_flags {
22 RX_ATTENTION_FLAGS_FIRST_MPDU = 1 << 0,
23 RX_ATTENTION_FLAGS_LAST_MPDU = 1 << 1,
24 RX_ATTENTION_FLAGS_MCAST_BCAST = 1 << 2,
25 RX_ATTENTION_FLAGS_PEER_IDX_INVALID = 1 << 3,
26 RX_ATTENTION_FLAGS_PEER_IDX_TIMEOUT = 1 << 4,
27 RX_ATTENTION_FLAGS_POWER_MGMT = 1 << 5,
28 RX_ATTENTION_FLAGS_NON_QOS = 1 << 6,
29 RX_ATTENTION_FLAGS_NULL_DATA = 1 << 7,
30 RX_ATTENTION_FLAGS_MGMT_TYPE = 1 << 8,
31 RX_ATTENTION_FLAGS_CTRL_TYPE = 1 << 9,
32 RX_ATTENTION_FLAGS_MORE_DATA = 1 << 10,
33 RX_ATTENTION_FLAGS_EOSP = 1 << 11,
34 RX_ATTENTION_FLAGS_U_APSD_TRIGGER = 1 << 12,
35 RX_ATTENTION_FLAGS_FRAGMENT = 1 << 13,
36 RX_ATTENTION_FLAGS_ORDER = 1 << 14,
37 RX_ATTENTION_FLAGS_CLASSIFICATION = 1 << 15,
38 RX_ATTENTION_FLAGS_OVERFLOW_ERR = 1 << 16,
39 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR = 1 << 17,
40 RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL = 1 << 18,
41 RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL = 1 << 19,
42 RX_ATTENTION_FLAGS_SA_IDX_INVALID = 1 << 20,
43 RX_ATTENTION_FLAGS_DA_IDX_INVALID = 1 << 21,
44 RX_ATTENTION_FLAGS_SA_IDX_TIMEOUT = 1 << 22,
45 RX_ATTENTION_FLAGS_DA_IDX_TIMEOUT = 1 << 23,
46 RX_ATTENTION_FLAGS_ENCRYPT_REQUIRED = 1 << 24,
47 RX_ATTENTION_FLAGS_DIRECTED = 1 << 25,
48 RX_ATTENTION_FLAGS_BUFFER_FRAGMENT = 1 << 26,
49 RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR = 1 << 27,
50 RX_ATTENTION_FLAGS_TKIP_MIC_ERR = 1 << 28,
51 RX_ATTENTION_FLAGS_DECRYPT_ERR = 1 << 29,
52 RX_ATTENTION_FLAGS_FCS_ERR = 1 << 30,
53 RX_ATTENTION_FLAGS_MSDU_DONE = 1 << 31,
54};
55
56struct rx_attention {
57 __le32 flags; /* %RX_ATTENTION_FLAGS_ */
58} __packed;
59
60/*
61 * first_mpdu
62 * Indicates the first MSDU of the PPDU. If both first_mpdu
63 * and last_mpdu are set in the MSDU then this is a not an
64 * A-MPDU frame but a stand alone MPDU. Interior MPDU in an
65 * A-MPDU shall have both first_mpdu and last_mpdu bits set to
66 * 0. The PPDU start status will only be valid when this bit
67 * is set.
68 *
69 * last_mpdu
70 * Indicates the last MSDU of the last MPDU of the PPDU. The
71 * PPDU end status will only be valid when this bit is set.
72 *
73 * mcast_bcast
74 * Multicast / broadcast indicator. Only set when the MAC
75 * address 1 bit 0 is set indicating mcast/bcast and the BSSID
76 * matches one of the 4 BSSID registers. Only set when
77 * first_msdu is set.
78 *
79 * peer_idx_invalid
80 * Indicates no matching entries within the the max search
81 * count. Only set when first_msdu is set.
82 *
83 * peer_idx_timeout
84 * Indicates an unsuccessful search for the peer index due to
85 * timeout. Only set when first_msdu is set.
86 *
87 * power_mgmt
88 * Power management bit set in the 802.11 header. Only set
89 * when first_msdu is set.
90 *
91 * non_qos
92 * Set if packet is not a non-QoS data frame. Only set when
93 * first_msdu is set.
94 *
95 * null_data
96 * Set if frame type indicates either null data or QoS null
97 * data format. Only set when first_msdu is set.
98 *
99 * mgmt_type
100 * Set if packet is a management packet. Only set when
101 * first_msdu is set.
102 *
103 * ctrl_type
104 * Set if packet is a control packet. Only set when first_msdu
105 * is set.
106 *
107 * more_data
108 * Set if more bit in frame control is set. Only set when
109 * first_msdu is set.
110 *
111 * eosp
112 * Set if the EOSP (end of service period) bit in the QoS
113 * control field is set. Only set when first_msdu is set.
114 *
115 * u_apsd_trigger
116 * Set if packet is U-APSD trigger. Key table will have bits
117 * per TID to indicate U-APSD trigger.
118 *
119 * fragment
120 * Indicates that this is an 802.11 fragment frame. This is
121 * set when either the more_frag bit is set in the frame
122 * control or the fragment number is not zero. Only set when
123 * first_msdu is set.
124 *
125 * order
126 * Set if the order bit in the frame control is set. Only set
127 * when first_msdu is set.
128 *
129 * classification
130 * Indicates that this status has a corresponding MSDU that
131 * requires FW processing. The OLE will have classification
132 * ring mask registers which will indicate the ring(s) for
133 * packets and descriptors which need FW attention.
134 *
135 * overflow_err
136 * PCU Receive FIFO does not have enough space to store the
137 * full receive packet. Enough space is reserved in the
138 * receive FIFO for the status is written. This MPDU remaining
139 * packets in the PPDU will be filtered and no Ack response
140 * will be transmitted.
141 *
142 * msdu_length_err
143 * Indicates that the MSDU length from the 802.3 encapsulated
144 * length field extends beyond the MPDU boundary.
145 *
146 * tcp_udp_chksum_fail
147 * Indicates that the computed checksum (tcp_udp_chksum) did
148 * not match the checksum in the TCP/UDP header.
149 *
150 * ip_chksum_fail
151 * Indicates that the computed checksum did not match the
152 * checksum in the IP header.
153 *
154 * sa_idx_invalid
155 * Indicates no matching entry was found in the address search
156 * table for the source MAC address.
157 *
158 * da_idx_invalid
159 * Indicates no matching entry was found in the address search
160 * table for the destination MAC address.
161 *
162 * sa_idx_timeout
163 * Indicates an unsuccessful search for the source MAC address
164 * due to the expiring of the search timer.
165 *
166 * da_idx_timeout
167 * Indicates an unsuccessful search for the destination MAC
168 * address due to the expiring of the search timer.
169 *
170 * encrypt_required
171 * Indicates that this data type frame is not encrypted even if
172 * the policy for this MPDU requires encryption as indicated in
173 * the peer table key type.
174 *
175 * directed
176 * MPDU is a directed packet which means that the RA matched
177 * our STA addresses. In proxySTA it means that the TA matched
178 * an entry in our address search table with the corresponding
179 * 'no_ack' bit is the address search entry cleared.
180 *
181 * buffer_fragment
182 * Indicates that at least one of the rx buffers has been
183 * fragmented. If set the FW should look at the rx_frag_info
184 * descriptor described below.
185 *
186 * mpdu_length_err
187 * Indicates that the MPDU was pre-maturely terminated
188 * resulting in a truncated MPDU. Don't trust the MPDU length
189 * field.
190 *
191 * tkip_mic_err
192 * Indicates that the MPDU Michael integrity check failed
193 *
194 * decrypt_err
195 * Indicates that the MPDU decrypt integrity check failed
196 *
197 * fcs_err
198 * Indicates that the MPDU FCS check failed
199 *
200 * msdu_done
201 * If set indicates that the RX packet data, RX header data, RX
202 * PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
203 * start/end descriptors and RX Attention descriptor are all
204 * valid. This bit must be in the last octet of the
205 * descriptor.
206 */
207
208struct rx_frag_info {
209 u8 ring0_more_count;
210 u8 ring1_more_count;
211 u8 ring2_more_count;
212 u8 ring3_more_count;
213} __packed;
214
215/*
216 * ring0_more_count
217 * Indicates the number of more buffers associated with RX DMA
218 * ring 0. Field is filled in by the RX_DMA.
219 *
220 * ring1_more_count
221 * Indicates the number of more buffers associated with RX DMA
222 * ring 1. Field is filled in by the RX_DMA.
223 *
224 * ring2_more_count
225 * Indicates the number of more buffers associated with RX DMA
226 * ring 2. Field is filled in by the RX_DMA.
227 *
228 * ring3_more_count
229 * Indicates the number of more buffers associated with RX DMA
230 * ring 3. Field is filled in by the RX_DMA.
231 */
232
233enum htt_rx_mpdu_encrypt_type {
234 HTT_RX_MPDU_ENCRYPT_WEP40 = 0,
235 HTT_RX_MPDU_ENCRYPT_WEP104 = 1,
236 HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC = 2,
237 HTT_RX_MPDU_ENCRYPT_WEP128 = 3,
238 HTT_RX_MPDU_ENCRYPT_TKIP_WPA = 4,
239 HTT_RX_MPDU_ENCRYPT_WAPI = 5,
240 HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2 = 6,
241 HTT_RX_MPDU_ENCRYPT_NONE = 7,
242};
243
244#define RX_MPDU_START_INFO0_PEER_IDX_MASK 0x000007ff
245#define RX_MPDU_START_INFO0_PEER_IDX_LSB 0
246#define RX_MPDU_START_INFO0_SEQ_NUM_MASK 0x0fff0000
247#define RX_MPDU_START_INFO0_SEQ_NUM_LSB 16
248#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
249#define RX_MPDU_START_INFO0_ENCRYPT_TYPE_LSB 28
250#define RX_MPDU_START_INFO0_FROM_DS (1 << 11)
251#define RX_MPDU_START_INFO0_TO_DS (1 << 12)
252#define RX_MPDU_START_INFO0_ENCRYPTED (1 << 13)
253#define RX_MPDU_START_INFO0_RETRY (1 << 14)
254#define RX_MPDU_START_INFO0_TXBF_H_INFO (1 << 15)
255
256#define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
257#define RX_MPDU_START_INFO1_TID_LSB 28
258#define RX_MPDU_START_INFO1_DIRECTED (1 << 16)
259
260struct rx_mpdu_start {
261 __le32 info0;
262 union {
263 struct {
264 __le32 pn31_0;
265 __le32 info1; /* %RX_MPDU_START_INFO1_ */
266 } __packed;
267 struct {
268 u8 pn[6];
269 } __packed;
270 } __packed;
271} __packed;
272
273/*
274 * peer_idx
275 * The index of the address search table which associated with
276 * the peer table entry corresponding to this MPDU. Only valid
277 * when first_msdu is set.
278 *
279 * fr_ds
280 * Set if the from DS bit is set in the frame control. Only
281 * valid when first_msdu is set.
282 *
283 * to_ds
284 * Set if the to DS bit is set in the frame control. Only
285 * valid when first_msdu is set.
286 *
287 * encrypted
288 * Protected bit from the frame control. Only valid when
289 * first_msdu is set.
290 *
291 * retry
292 * Retry bit from the frame control. Only valid when
293 * first_msdu is set.
294 *
295 * txbf_h_info
296 * The MPDU data will contain H information. Primarily used
297 * for debug.
298 *
299 * seq_num
300 * The sequence number from the 802.11 header. Only valid when
301 * first_msdu is set.
302 *
303 * encrypt_type
304 * Indicates type of decrypt cipher used (as defined in the
305 * peer table)
306 * 0: WEP40
307 * 1: WEP104
308 * 2: TKIP without MIC
309 * 3: WEP128
310 * 4: TKIP (WPA)
311 * 5: WAPI
312 * 6: AES-CCM (WPA2)
313 * 7: No cipher
314 * Only valid when first_msdu_is set
315 *
316 * pn_31_0
317 * Bits [31:0] of the PN number extracted from the IV field
318 * WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] is
319 * valid.
320 * TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
321 * WEPSeed[1], pn1}. Only pn[47:0] is valid.
322 * AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
323 * pn0}. Only pn[47:0] is valid.
324 * WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
325 * pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}.
326 * The ext_wapi_pn[127:48] in the rx_msdu_misc descriptor and
327 * pn[47:0] are valid.
328 * Only valid when first_msdu is set.
329 *
330 * pn_47_32
331 * Bits [47:32] of the PN number. See description for
332 * pn_31_0. The remaining PN fields are in the rx_msdu_end
333 * descriptor
334 *
335 * pn
336 * Use this field to access the pn without worrying about
337 * byte-order and bitmasking/bitshifting.
338 *
339 * directed
340 * See definition in RX attention descriptor
341 *
342 * reserved_2
343 * Reserved: HW should fill with zero. FW should ignore.
344 *
345 * tid
346 * The TID field in the QoS control field
347 */
348
349#define RX_MPDU_END_INFO0_RESERVED_0_MASK 0x00001fff
350#define RX_MPDU_END_INFO0_RESERVED_0_LSB 0
351#define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
352#define RX_MPDU_END_INFO0_POST_DELIM_CNT_LSB 16
353#define RX_MPDU_END_INFO0_OVERFLOW_ERR (1 << 13)
354#define RX_MPDU_END_INFO0_LAST_MPDU (1 << 14)
355#define RX_MPDU_END_INFO0_POST_DELIM_ERR (1 << 15)
356#define RX_MPDU_END_INFO0_MPDU_LENGTH_ERR (1 << 28)
357#define RX_MPDU_END_INFO0_TKIP_MIC_ERR (1 << 29)
358#define RX_MPDU_END_INFO0_DECRYPT_ERR (1 << 30)
359#define RX_MPDU_END_INFO0_FCS_ERR (1 << 31)
360
361struct rx_mpdu_end {
362 __le32 info0;
363} __packed;
364
365/*
366 * reserved_0
367 * Reserved
368 *
369 * overflow_err
370 * PCU Receive FIFO does not have enough space to store the
371 * full receive packet. Enough space is reserved in the
372 * receive FIFO for the status is written. This MPDU remaining
373 * packets in the PPDU will be filtered and no Ack response
374 * will be transmitted.
375 *
376 * last_mpdu
377 * Indicates that this is the last MPDU of a PPDU.
378 *
379 * post_delim_err
380 * Indicates that a delimiter FCS error occurred after this
381 * MPDU before the next MPDU. Only valid when last_msdu is
382 * set.
383 *
384 * post_delim_cnt
385 * Count of the delimiters after this MPDU. This requires the
386 * last MPDU to be held until all the EOF descriptors have been
387 * received. This may be inefficient in the future when
388 * ML-MIMO is used. Only valid when last_mpdu is set.
389 *
390 * mpdu_length_err
391 * See definition in RX attention descriptor
392 *
393 * tkip_mic_err
394 * See definition in RX attention descriptor
395 *
396 * decrypt_err
397 * See definition in RX attention descriptor
398 *
399 * fcs_err
400 * See definition in RX attention descriptor
401 */
402
403#define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK 0x00003fff
404#define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB 0
405#define RX_MSDU_START_INFO0_IP_OFFSET_MASK 0x000fc000
406#define RX_MSDU_START_INFO0_IP_OFFSET_LSB 14
407#define RX_MSDU_START_INFO0_RING_MASK_MASK 0x00f00000
408#define RX_MSDU_START_INFO0_RING_MASK_LSB 20
409#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
410#define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_LSB 24
411
412#define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK 0x000000ff
413#define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB 0
414#define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK 0x00000300
415#define RX_MSDU_START_INFO1_DECAP_FORMAT_LSB 8
416#define RX_MSDU_START_INFO1_SA_IDX_MASK 0x07ff0000
417#define RX_MSDU_START_INFO1_SA_IDX_LSB 16
418#define RX_MSDU_START_INFO1_IPV4_PROTO (1 << 10)
419#define RX_MSDU_START_INFO1_IPV6_PROTO (1 << 11)
420#define RX_MSDU_START_INFO1_TCP_PROTO (1 << 12)
421#define RX_MSDU_START_INFO1_UDP_PROTO (1 << 13)
422#define RX_MSDU_START_INFO1_IP_FRAG (1 << 14)
423#define RX_MSDU_START_INFO1_TCP_ONLY_ACK (1 << 15)
424
425#define RX_MSDU_START_INFO2_DA_IDX_MASK 0x000007ff
426#define RX_MSDU_START_INFO2_DA_IDX_LSB 0
427#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000
428#define RX_MSDU_START_INFO2_IP_PROTO_FIELD_LSB 16
429#define RX_MSDU_START_INFO2_DA_BCAST_MCAST BIT(11)
430
431/* The decapped header (rx_hdr_status) contains the following:
432 * a) 802.11 header
433 * [padding to 4 bytes]
434 * b) HW crypto parameter
435 * - 0 bytes for no security
436 * - 4 bytes for WEP
437 * - 8 bytes for TKIP, AES
438 * [padding to 4 bytes]
439 * c) A-MSDU subframe header (14 bytes) if appliable
440 * d) LLC/SNAP (RFC1042, 8 bytes)
441 *
442 * In case of A-MSDU only first frame in sequence contains (a) and (b). */
443enum rx_msdu_decap_format {
444 RX_MSDU_DECAP_RAW = 0,
445
446 /* Note: QoS frames are reported as non-QoS. The rx_hdr_status in
447 * htt_rx_desc contains the original decapped 802.11 header. */
448 RX_MSDU_DECAP_NATIVE_WIFI = 1,
449
450 /* Payload contains an ethernet header (struct ethhdr). */
451 RX_MSDU_DECAP_ETHERNET2_DIX = 2,
452
453 /* Payload contains two 48-bit addresses and 2-byte length (14 bytes
454 * total), followed by an RFC1042 header (8 bytes). */
455 RX_MSDU_DECAP_8023_SNAP_LLC = 3
456};
457
458struct rx_msdu_start_common {
459 __le32 info0; /* %RX_MSDU_START_INFO0_ */
460 __le32 flow_id_crc;
461 __le32 info1; /* %RX_MSDU_START_INFO1_ */
462} __packed;
463
464struct rx_msdu_start_qca99x0 {
465 __le32 info2; /* %RX_MSDU_START_INFO2_ */
466} __packed;
467
468struct rx_msdu_start {
469 struct rx_msdu_start_common common;
470 union {
471 struct rx_msdu_start_qca99x0 qca99x0;
472 } __packed;
473} __packed;
474
475/*
476 * msdu_length
477 * MSDU length in bytes after decapsulation. This field is
478 * still valid for MPDU frames without A-MSDU. It still
479 * represents MSDU length after decapsulation
480 *
481 * ip_offset
482 * Indicates the IP offset in bytes from the start of the
483 * packet after decapsulation. Only valid if ipv4_proto or
484 * ipv6_proto is set.
485 *
486 * ring_mask
487 * Indicates the destination RX rings for this MSDU.
488 *
489 * tcp_udp_offset
490 * Indicates the offset in bytes to the start of TCP or UDP
491 * header from the start of the IP header after decapsulation.
492 * Only valid if tcp_prot or udp_prot is set. The value 0
493 * indicates that the offset is longer than 127 bytes.
494 *
495 * reserved_0c
496 * Reserved: HW should fill with zero. FW should ignore.
497 *
498 * flow_id_crc
499 * The flow_id_crc runs CRC32 on the following information:
500 * IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
501 * protocol[7:0]}.
502 * IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
503 * next_header[7:0]}
504 * UDP case: sort_port[15:0], dest_port[15:0]
505 * TCP case: sort_port[15:0], dest_port[15:0],
506 * {header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
507 * {16'b0, urgent_ptr[15:0]}, all options except 32-bit
508 * timestamp.
509 *
510 * msdu_number
511 * Indicates the MSDU number within a MPDU. This value is
512 * reset to zero at the start of each MPDU. If the number of
513 * MSDU exceeds 255 this number will wrap using modulo 256.
514 *
515 * decap_format
516 * Indicates the format after decapsulation:
517 * 0: RAW: No decapsulation
518 * 1: Native WiFi
519 * 2: Ethernet 2 (DIX)
520 * 3: 802.3 (SNAP/LLC)
521 *
522 * ipv4_proto
523 * Set if L2 layer indicates IPv4 protocol.
524 *
525 * ipv6_proto
526 * Set if L2 layer indicates IPv6 protocol.
527 *
528 * tcp_proto
529 * Set if the ipv4_proto or ipv6_proto are set and the IP
530 * protocol indicates TCP.
531 *
532 * udp_proto
533 * Set if the ipv4_proto or ipv6_proto are set and the IP
534 * protocol indicates UDP.
535 *
536 * ip_frag
537 * Indicates that either the IP More frag bit is set or IP frag
538 * number is non-zero. If set indicates that this is a
539 * fragmented IP packet.
540 *
541 * tcp_only_ack
542 * Set if only the TCP Ack bit is set in the TCP flags and if
543 * the TCP payload is 0.
544 *
545 * sa_idx
546 * The offset in the address table which matches the MAC source
547 * address.
548 *
549 * reserved_2b
550 * Reserved: HW should fill with zero. FW should ignore.
551 */
552
553#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
554#define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB 0
555#define RX_MSDU_END_INFO0_FIRST_MSDU (1 << 14)
556#define RX_MSDU_END_INFO0_LAST_MSDU (1 << 15)
557#define RX_MSDU_END_INFO0_PRE_DELIM_ERR (1 << 30)
558#define RX_MSDU_END_INFO0_RESERVED_3B (1 << 31)
559
560struct rx_msdu_end_common {
561 __le16 ip_hdr_cksum;
562 __le16 tcp_hdr_cksum;
563 u8 key_id_octet;
564 u8 classification_filter;
565 u8 wapi_pn[10];
566 __le32 info0;
567} __packed;
568
569#define RX_MSDU_END_INFO1_TCP_FLAG_MASK 0x000001ff
570#define RX_MSDU_END_INFO1_TCP_FLAG_LSB 0
571#define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK 0x00001c00
572#define RX_MSDU_END_INFO1_L3_HDR_PAD_LSB 10
573#define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK 0xffff0000
574#define RX_MSDU_END_INFO1_WINDOW_SIZE_LSB 16
575#define RX_MSDU_END_INFO1_IRO_ELIGIBLE BIT(9)
576
577#define RX_MSDU_END_INFO2_DA_OFFSET_MASK 0x0000003f
578#define RX_MSDU_END_INFO2_DA_OFFSET_LSB 0
579#define RX_MSDU_END_INFO2_SA_OFFSET_MASK 0x00000fc0
580#define RX_MSDU_END_INFO2_SA_OFFSET_LSB 6
581#define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK 0x0003f000
582#define RX_MSDU_END_INFO2_TYPE_OFFSET_LSB 12
583
584struct rx_msdu_end_qca99x0 {
585 __le32 ipv6_crc;
586 __le32 tcp_seq_no;
587 __le32 tcp_ack_no;
588 __le32 info1;
589 __le32 info2;
590} __packed;
591
592struct rx_msdu_end {
593 struct rx_msdu_end_common common;
594 union {
595 struct rx_msdu_end_qca99x0 qca99x0;
596 } __packed;
597} __packed;
598
599/*
600 *ip_hdr_chksum
601 * This can include the IP header checksum or the pseudo header
602 * checksum used by TCP/UDP checksum.
603 *
604 *tcp_udp_chksum
605 * The value of the computed TCP/UDP checksum. A mode bit
606 * selects whether this checksum is the full checksum or the
607 * partial checksum which does not include the pseudo header.
608 *
609 *key_id_octet
610 * The key ID octet from the IV. Only valid when first_msdu is
611 * set.
612 *
613 *classification_filter
614 * Indicates the number classification filter rule
615 *
616 *ext_wapi_pn_63_48
617 * Extension PN (packet number) which is only used by WAPI.
618 * This corresponds to WAPI PN bits [63:48] (pn6 and pn7). The
619 * WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
620 * descriptor.
621 *
622 *ext_wapi_pn_95_64
623 * Extension PN (packet number) which is only used by WAPI.
624 * This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10 and
625 * pn11).
626 *
627 *ext_wapi_pn_127_96
628 * Extension PN (packet number) which is only used by WAPI.
629 * This corresponds to WAPI PN bits [127:96] (pn12, pn13, pn14,
630 * pn15).
631 *
632 *reported_mpdu_length
633 * MPDU length before decapsulation. Only valid when
634 * first_msdu is set. This field is taken directly from the
635 * length field of the A-MPDU delimiter or the preamble length
636 * field for non-A-MPDU frames.
637 *
638 *first_msdu
639 * Indicates the first MSDU of A-MSDU. If both first_msdu and
640 * last_msdu are set in the MSDU then this is a non-aggregated
641 * MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall
642 * have both first_mpdu and last_mpdu bits set to 0.
643 *
644 *last_msdu
645 * Indicates the last MSDU of the A-MSDU. MPDU end status is
646 * only valid when last_msdu is set.
647 *
648 *reserved_3a
649 * Reserved: HW should fill with zero. FW should ignore.
650 *
651 *pre_delim_err
652 * Indicates that the first delimiter had a FCS failure. Only
653 * valid when first_mpdu and first_msdu are set.
654 *
655 *reserved_3b
656 * Reserved: HW should fill with zero. FW should ignore.
657 */
658
659#define RX_PPDU_START_SIG_RATE_SELECT_OFDM 0
660#define RX_PPDU_START_SIG_RATE_SELECT_CCK 1
661
662#define RX_PPDU_START_SIG_RATE_OFDM_48 0
663#define RX_PPDU_START_SIG_RATE_OFDM_24 1
664#define RX_PPDU_START_SIG_RATE_OFDM_12 2
665#define RX_PPDU_START_SIG_RATE_OFDM_6 3
666#define RX_PPDU_START_SIG_RATE_OFDM_54 4
667#define RX_PPDU_START_SIG_RATE_OFDM_36 5
668#define RX_PPDU_START_SIG_RATE_OFDM_18 6
669#define RX_PPDU_START_SIG_RATE_OFDM_9 7
670
671#define RX_PPDU_START_SIG_RATE_CCK_LP_11 0
672#define RX_PPDU_START_SIG_RATE_CCK_LP_5_5 1
673#define RX_PPDU_START_SIG_RATE_CCK_LP_2 2
674#define RX_PPDU_START_SIG_RATE_CCK_LP_1 3
675#define RX_PPDU_START_SIG_RATE_CCK_SP_11 4
676#define RX_PPDU_START_SIG_RATE_CCK_SP_5_5 5
677#define RX_PPDU_START_SIG_RATE_CCK_SP_2 6
678
679#define HTT_RX_PPDU_START_PREAMBLE_LEGACY 0x04
680#define HTT_RX_PPDU_START_PREAMBLE_HT 0x08
681#define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF 0x09
682#define HTT_RX_PPDU_START_PREAMBLE_VHT 0x0C
683#define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
684
685#define RX_PPDU_START_INFO0_IS_GREENFIELD (1 << 0)
686
687#define RX_PPDU_START_INFO1_L_SIG_RATE_MASK 0x0000000f
688#define RX_PPDU_START_INFO1_L_SIG_RATE_LSB 0
689#define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK 0x0001ffe0
690#define RX_PPDU_START_INFO1_L_SIG_LENGTH_LSB 5
691#define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK 0x00fc0000
692#define RX_PPDU_START_INFO1_L_SIG_TAIL_LSB 18
693#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
694#define RX_PPDU_START_INFO1_PREAMBLE_TYPE_LSB 24
695#define RX_PPDU_START_INFO1_L_SIG_RATE_SELECT (1 << 4)
696#define RX_PPDU_START_INFO1_L_SIG_PARITY (1 << 17)
697
698#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
699#define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB 0
700
701#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
702#define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB 0
703#define RX_PPDU_START_INFO3_TXBF_H_INFO (1 << 24)
704
705#define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
706#define RX_PPDU_START_INFO4_VHT_SIG_B_LSB 0
707
708#define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
709#define RX_PPDU_START_INFO5_SERVICE_LSB 0
710
711/* No idea what this flag means. It seems to be always set in rate. */
712#define RX_PPDU_START_RATE_FLAG BIT(3)
713
714enum rx_ppdu_start_rate {
715 RX_PPDU_START_RATE_OFDM_48M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_48M,
716 RX_PPDU_START_RATE_OFDM_24M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_24M,
717 RX_PPDU_START_RATE_OFDM_12M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_12M,
718 RX_PPDU_START_RATE_OFDM_6M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_6M,
719 RX_PPDU_START_RATE_OFDM_54M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_54M,
720 RX_PPDU_START_RATE_OFDM_36M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_36M,
721 RX_PPDU_START_RATE_OFDM_18M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_18M,
722 RX_PPDU_START_RATE_OFDM_9M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_OFDM_9M,
723
724 RX_PPDU_START_RATE_CCK_LP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_11M,
725 RX_PPDU_START_RATE_CCK_LP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_5_5M,
726 RX_PPDU_START_RATE_CCK_LP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_2M,
727 RX_PPDU_START_RATE_CCK_LP_1M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_LP_1M,
728 RX_PPDU_START_RATE_CCK_SP_11M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_11M,
729 RX_PPDU_START_RATE_CCK_SP_5_5M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_5_5M,
730 RX_PPDU_START_RATE_CCK_SP_2M = RX_PPDU_START_RATE_FLAG | ATH10K_HW_RATE_CCK_SP_2M,
731};
732
733struct rx_ppdu_start {
734 struct {
735 u8 pri20_mhz;
736 u8 ext20_mhz;
737 u8 ext40_mhz;
738 u8 ext80_mhz;
739 } rssi_chains[4];
740 u8 rssi_comb;
741 __le16 rsvd0;
742 u8 info0; /* %RX_PPDU_START_INFO0_ */
743 __le32 info1; /* %RX_PPDU_START_INFO1_ */
744 __le32 info2; /* %RX_PPDU_START_INFO2_ */
745 __le32 info3; /* %RX_PPDU_START_INFO3_ */
746 __le32 info4; /* %RX_PPDU_START_INFO4_ */
747 __le32 info5; /* %RX_PPDU_START_INFO5_ */
748} __packed;
749
750/*
751 * rssi_chain0_pri20
752 * RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
753 * Value of 0x80 indicates invalid.
754 *
755 * rssi_chain0_sec20
756 * RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
757 * Value of 0x80 indicates invalid.
758 *
759 * rssi_chain0_sec40
760 * RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
761 * Value of 0x80 indicates invalid.
762 *
763 * rssi_chain0_sec80
764 * RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
765 * Value of 0x80 indicates invalid.
766 *
767 * rssi_chain1_pri20
768 * RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
769 * Value of 0x80 indicates invalid.
770 *
771 * rssi_chain1_sec20
772 * RSSI of RX PPDU on chain 1 of secondary 20 MHz bandwidth.
773 * Value of 0x80 indicates invalid.
774 *
775 * rssi_chain1_sec40
776 * RSSI of RX PPDU on chain 1 of secondary 40 MHz bandwidth.
777 * Value of 0x80 indicates invalid.
778 *
779 * rssi_chain1_sec80
780 * RSSI of RX PPDU on chain 1 of secondary 80 MHz bandwidth.
781 * Value of 0x80 indicates invalid.
782 *
783 * rssi_chain2_pri20
784 * RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
785 * Value of 0x80 indicates invalid.
786 *
787 * rssi_chain2_sec20
788 * RSSI of RX PPDU on chain 2 of secondary 20 MHz bandwidth.
789 * Value of 0x80 indicates invalid.
790 *
791 * rssi_chain2_sec40
792 * RSSI of RX PPDU on chain 2 of secondary 40 MHz bandwidth.
793 * Value of 0x80 indicates invalid.
794 *
795 * rssi_chain2_sec80
796 * RSSI of RX PPDU on chain 2 of secondary 80 MHz bandwidth.
797 * Value of 0x80 indicates invalid.
798 *
799 * rssi_chain3_pri20
800 * RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
801 * Value of 0x80 indicates invalid.
802 *
803 * rssi_chain3_sec20
804 * RSSI of RX PPDU on chain 3 of secondary 20 MHz bandwidth.
805 * Value of 0x80 indicates invalid.
806 *
807 * rssi_chain3_sec40
808 * RSSI of RX PPDU on chain 3 of secondary 40 MHz bandwidth.
809 * Value of 0x80 indicates invalid.
810 *
811 * rssi_chain3_sec80
812 * RSSI of RX PPDU on chain 3 of secondary 80 MHz bandwidth.
813 * Value of 0x80 indicates invalid.
814 *
815 * rssi_comb
816 * The combined RSSI of RX PPDU of all active chains and
817 * bandwidths. Value of 0x80 indicates invalid.
818 *
819 * reserved_4a
820 * Reserved: HW should fill with 0, FW should ignore.
821 *
822 * is_greenfield
823 * Do we really support this?
824 *
825 * reserved_4b
826 * Reserved: HW should fill with 0, FW should ignore.
827 *
828 * l_sig_rate
829 * If l_sig_rate_select is 0:
830 * 0x8: OFDM 48 Mbps
831 * 0x9: OFDM 24 Mbps
832 * 0xA: OFDM 12 Mbps
833 * 0xB: OFDM 6 Mbps
834 * 0xC: OFDM 54 Mbps
835 * 0xD: OFDM 36 Mbps
836 * 0xE: OFDM 18 Mbps
837 * 0xF: OFDM 9 Mbps
838 * If l_sig_rate_select is 1:
839 * 0x8: CCK 11 Mbps long preamble
840 * 0x9: CCK 5.5 Mbps long preamble
841 * 0xA: CCK 2 Mbps long preamble
842 * 0xB: CCK 1 Mbps long preamble
843 * 0xC: CCK 11 Mbps short preamble
844 * 0xD: CCK 5.5 Mbps short preamble
845 * 0xE: CCK 2 Mbps short preamble
846 *
847 * l_sig_rate_select
848 * Legacy signal rate select. If set then l_sig_rate indicates
849 * CCK rates. If clear then l_sig_rate indicates OFDM rates.
850 *
851 * l_sig_length
852 * Length of legacy frame in octets.
853 *
854 * l_sig_parity
855 * Odd parity over l_sig_rate and l_sig_length
856 *
857 * l_sig_tail
858 * Tail bits for Viterbi decoder
859 *
860 * preamble_type
861 * Indicates the type of preamble ahead:
862 * 0x4: Legacy (OFDM/CCK)
863 * 0x8: HT
864 * 0x9: HT with TxBF
865 * 0xC: VHT
866 * 0xD: VHT with TxBF
867 * 0x80 - 0xFF: Reserved for special baseband data types such
868 * as radar and spectral scan.
869 *
870 * ht_sig_vht_sig_a_1
871 * If preamble_type == 0x8 or 0x9
872 * HT-SIG (first 24 bits)
873 * If preamble_type == 0xC or 0xD
874 * VHT-SIG A (first 24 bits)
875 * Else
876 * Reserved
877 *
878 * reserved_6
879 * Reserved: HW should fill with 0, FW should ignore.
880 *
881 * ht_sig_vht_sig_a_2
882 * If preamble_type == 0x8 or 0x9
883 * HT-SIG (last 24 bits)
884 * If preamble_type == 0xC or 0xD
885 * VHT-SIG A (last 24 bits)
886 * Else
887 * Reserved
888 *
889 * txbf_h_info
890 * Indicates that the packet data carries H information which
891 * is used for TxBF debug.
892 *
893 * reserved_7
894 * Reserved: HW should fill with 0, FW should ignore.
895 *
896 * vht_sig_b
897 * WiFi 1.0 and WiFi 2.0 will likely have this field to be all
898 * 0s since the BB does not plan on decoding VHT SIG-B.
899 *
900 * reserved_8
901 * Reserved: HW should fill with 0, FW should ignore.
902 *
903 * service
904 * Service field from BB for OFDM, HT and VHT packets. CCK
905 * packets will have service field of 0.
906 *
907 * reserved_9
908 * Reserved: HW should fill with 0, FW should ignore.
909*/
910
911#define RX_PPDU_END_FLAGS_PHY_ERR (1 << 0)
912#define RX_PPDU_END_FLAGS_RX_LOCATION (1 << 1)
913#define RX_PPDU_END_FLAGS_TXBF_H_INFO (1 << 2)
914
915#define RX_PPDU_END_INFO0_RX_ANTENNA_MASK 0x00ffffff
916#define RX_PPDU_END_INFO0_RX_ANTENNA_LSB 0
917#define RX_PPDU_END_INFO0_FLAGS_TX_HT_VHT_ACK (1 << 24)
918#define RX_PPDU_END_INFO0_BB_CAPTURED_CHANNEL (1 << 25)
919
920#define RX_PPDU_END_INFO1_PEER_IDX_MASK 0x1ffc
921#define RX_PPDU_END_INFO1_PEER_IDX_LSB 2
922#define RX_PPDU_END_INFO1_BB_DATA BIT(0)
923#define RX_PPDU_END_INFO1_PEER_IDX_VALID BIT(1)
924#define RX_PPDU_END_INFO1_PPDU_DONE BIT(15)
925
926struct rx_ppdu_end_common {
927 __le32 evm_p0;
928 __le32 evm_p1;
929 __le32 evm_p2;
930 __le32 evm_p3;
931 __le32 evm_p4;
932 __le32 evm_p5;
933 __le32 evm_p6;
934 __le32 evm_p7;
935 __le32 evm_p8;
936 __le32 evm_p9;
937 __le32 evm_p10;
938 __le32 evm_p11;
939 __le32 evm_p12;
940 __le32 evm_p13;
941 __le32 evm_p14;
942 __le32 evm_p15;
943 __le32 tsf_timestamp;
944 __le32 wb_timestamp;
945} __packed;
946
947struct rx_ppdu_end_qca988x {
948 u8 locationing_timestamp;
949 u8 phy_err_code;
950 __le16 flags; /* %RX_PPDU_END_FLAGS_ */
951 __le32 info0; /* %RX_PPDU_END_INFO0_ */
952 __le16 bb_length;
953 __le16 info1; /* %RX_PPDU_END_INFO1_ */
954} __packed;
955
956#define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
957#define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB 0
958#define RX_PPDU_END_RTT_UNUSED_MASK 0x7f000000
959#define RX_PPDU_END_RTT_UNUSED_LSB 24
960#define RX_PPDU_END_RTT_NORMAL_MODE BIT(31)
961
962struct rx_ppdu_end_qca6174 {
963 u8 locationing_timestamp;
964 u8 phy_err_code;
965 __le16 flags; /* %RX_PPDU_END_FLAGS_ */
966 __le32 info0; /* %RX_PPDU_END_INFO0_ */
967 __le32 rtt; /* %RX_PPDU_END_RTT_ */
968 __le16 bb_length;
969 __le16 info1; /* %RX_PPDU_END_INFO1_ */
970} __packed;
971
972#define RX_PKT_END_INFO0_RX_SUCCESS BIT(0)
973#define RX_PKT_END_INFO0_ERR_TX_INTERRUPT_RX BIT(3)
974#define RX_PKT_END_INFO0_ERR_OFDM_POWER_DROP BIT(4)
975#define RX_PKT_END_INFO0_ERR_OFDM_RESTART BIT(5)
976#define RX_PKT_END_INFO0_ERR_CCK_POWER_DROP BIT(6)
977#define RX_PKT_END_INFO0_ERR_CCK_RESTART BIT(7)
978
979#define RX_LOCATION_INFO_RTT_CORR_VAL_MASK 0x0001ffff
980#define RX_LOCATION_INFO_RTT_CORR_VAL_LSB 0
981#define RX_LOCATION_INFO_FAC_STATUS_MASK 0x000c0000
982#define RX_LOCATION_INFO_FAC_STATUS_LSB 18
983#define RX_LOCATION_INFO_PKT_BW_MASK 0x00700000
984#define RX_LOCATION_INFO_PKT_BW_LSB 20
985#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000
986#define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_LSB 23
987#define RX_LOCATION_INFO_CIR_STATUS BIT(17)
988#define RX_LOCATION_INFO_RTT_MAC_PHY_PHASE BIT(25)
989#define RX_LOCATION_INFO_RTT_TX_DATA_START_X BIT(26)
990#define RX_LOCATION_INFO_HW_IFFT_MODE BIT(30)
991#define RX_LOCATION_INFO_RX_LOCATION_VALID BIT(31)
992
993struct rx_pkt_end {
994 __le32 info0; /* %RX_PKT_END_INFO0_ */
995 __le32 phy_timestamp_1;
996 __le32 phy_timestamp_2;
997 __le32 rx_location_info; /* %RX_LOCATION_INFO_ */
998} __packed;
999
1000enum rx_phy_ppdu_end_info0 {
1001 RX_PHY_PPDU_END_INFO0_ERR_RADAR = BIT(2),
1002 RX_PHY_PPDU_END_INFO0_ERR_RX_ABORT = BIT(3),
1003 RX_PHY_PPDU_END_INFO0_ERR_RX_NAP = BIT(4),
1004 RX_PHY_PPDU_END_INFO0_ERR_OFDM_TIMING = BIT(5),
1005 RX_PHY_PPDU_END_INFO0_ERR_OFDM_PARITY = BIT(6),
1006 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RATE = BIT(7),
1007 RX_PHY_PPDU_END_INFO0_ERR_OFDM_LENGTH = BIT(8),
1008 RX_PHY_PPDU_END_INFO0_ERR_OFDM_RESTART = BIT(9),
1009 RX_PHY_PPDU_END_INFO0_ERR_OFDM_SERVICE = BIT(10),
1010 RX_PHY_PPDU_END_INFO0_ERR_OFDM_POWER_DROP = BIT(11),
1011 RX_PHY_PPDU_END_INFO0_ERR_CCK_BLOCKER = BIT(12),
1012 RX_PHY_PPDU_END_INFO0_ERR_CCK_TIMING = BIT(13),
1013 RX_PHY_PPDU_END_INFO0_ERR_CCK_HEADER_CRC = BIT(14),
1014 RX_PHY_PPDU_END_INFO0_ERR_CCK_RATE = BIT(15),
1015 RX_PHY_PPDU_END_INFO0_ERR_CCK_LENGTH = BIT(16),
1016 RX_PHY_PPDU_END_INFO0_ERR_CCK_RESTART = BIT(17),
1017 RX_PHY_PPDU_END_INFO0_ERR_CCK_SERVICE = BIT(18),
1018 RX_PHY_PPDU_END_INFO0_ERR_CCK_POWER_DROP = BIT(19),
1019 RX_PHY_PPDU_END_INFO0_ERR_HT_CRC = BIT(20),
1020 RX_PHY_PPDU_END_INFO0_ERR_HT_LENGTH = BIT(21),
1021 RX_PHY_PPDU_END_INFO0_ERR_HT_RATE = BIT(22),
1022 RX_PHY_PPDU_END_INFO0_ERR_HT_ZLF = BIT(23),
1023 RX_PHY_PPDU_END_INFO0_ERR_FALSE_RADAR_EXT = BIT(24),
1024 RX_PHY_PPDU_END_INFO0_ERR_GREEN_FIELD = BIT(25),
1025 RX_PHY_PPDU_END_INFO0_ERR_SPECTRAL_SCAN = BIT(26),
1026 RX_PHY_PPDU_END_INFO0_ERR_RX_DYN_BW = BIT(27),
1027 RX_PHY_PPDU_END_INFO0_ERR_LEG_HT_MISMATCH = BIT(28),
1028 RX_PHY_PPDU_END_INFO0_ERR_VHT_CRC = BIT(29),
1029 RX_PHY_PPDU_END_INFO0_ERR_VHT_SIGA = BIT(30),
1030 RX_PHY_PPDU_END_INFO0_ERR_VHT_LSIG = BIT(31),
1031};
1032
1033enum rx_phy_ppdu_end_info1 {
1034 RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP = BIT(0),
1035 RX_PHY_PPDU_END_INFO1_ERR_VHT_NSYM = BIT(1),
1036 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_EXT_SYM = BIT(2),
1037 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID0 = BIT(3),
1038 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID1_62 = BIT(4),
1039 RX_PHY_PPDU_END_INFO1_ERR_VHT_RX_SKIP_ID63 = BIT(5),
1040 RX_PHY_PPDU_END_INFO1_ERR_OFDM_LDPC_DECODER = BIT(6),
1041 RX_PHY_PPDU_END_INFO1_ERR_DEFER_NAP = BIT(7),
1042 RX_PHY_PPDU_END_INFO1_ERR_FDOMAIN_TIMEOUT = BIT(8),
1043 RX_PHY_PPDU_END_INFO1_ERR_LSIG_REL_CHECK = BIT(9),
1044 RX_PHY_PPDU_END_INFO1_ERR_BT_COLLISION = BIT(10),
1045 RX_PHY_PPDU_END_INFO1_ERR_MU_FEEDBACK = BIT(11),
1046 RX_PHY_PPDU_END_INFO1_ERR_TX_INTERRUPT_RX = BIT(12),
1047 RX_PHY_PPDU_END_INFO1_ERR_RX_CBF = BIT(13),
1048};
1049
1050struct rx_phy_ppdu_end {
1051 __le32 info0; /* %RX_PHY_PPDU_END_INFO0_ */
1052 __le32 info1; /* %RX_PHY_PPDU_END_INFO1_ */
1053} __packed;
1054
1055#define RX_PPDU_END_RX_TIMING_OFFSET_MASK 0x00000fff
1056#define RX_PPDU_END_RX_TIMING_OFFSET_LSB 0
1057
1058#define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK 0x00ffffff
1059#define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB 0
1060#define RX_PPDU_END_RX_INFO_TX_HT_VHT_ACK BIT(24)
1061#define RX_PPDU_END_RX_INFO_RX_PKT_END_VALID BIT(25)
1062#define RX_PPDU_END_RX_INFO_RX_PHY_PPDU_END_VALID BIT(26)
1063#define RX_PPDU_END_RX_INFO_RX_TIMING_OFFSET_VALID BIT(27)
1064#define RX_PPDU_END_RX_INFO_BB_CAPTURED_CHANNEL BIT(28)
1065#define RX_PPDU_END_RX_INFO_UNSUPPORTED_MU_NC BIT(29)
1066#define RX_PPDU_END_RX_INFO_OTP_TXBF_DISABLE BIT(30)
1067
1068struct rx_ppdu_end_qca99x0 {
1069 struct rx_pkt_end rx_pkt_end;
1070 struct rx_phy_ppdu_end rx_phy_ppdu_end;
1071 __le32 rx_timing_offset; /* %RX_PPDU_END_RX_TIMING_OFFSET_ */
1072 __le32 rx_info; /* %RX_PPDU_END_RX_INFO_ */
1073 __le16 bb_length;
1074 __le16 info1; /* %RX_PPDU_END_INFO1_ */
1075} __packed;
1076
1077struct rx_ppdu_end {
1078 struct rx_ppdu_end_common common;
1079 union {
1080 struct rx_ppdu_end_qca988x qca988x;
1081 struct rx_ppdu_end_qca6174 qca6174;
1082 struct rx_ppdu_end_qca99x0 qca99x0;
1083 } __packed;
1084} __packed;
1085
1086/*
1087 * evm_p0
1088 * EVM for pilot 0. Contain EVM for streams: 0, 1, 2 and 3.
1089 *
1090 * evm_p1
1091 * EVM for pilot 1. Contain EVM for streams: 0, 1, 2 and 3.
1092 *
1093 * evm_p2
1094 * EVM for pilot 2. Contain EVM for streams: 0, 1, 2 and 3.
1095 *
1096 * evm_p3
1097 * EVM for pilot 3. Contain EVM for streams: 0, 1, 2 and 3.
1098 *
1099 * evm_p4
1100 * EVM for pilot 4. Contain EVM for streams: 0, 1, 2 and 3.
1101 *
1102 * evm_p5
1103 * EVM for pilot 5. Contain EVM for streams: 0, 1, 2 and 3.
1104 *
1105 * evm_p6
1106 * EVM for pilot 6. Contain EVM for streams: 0, 1, 2 and 3.
1107 *
1108 * evm_p7
1109 * EVM for pilot 7. Contain EVM for streams: 0, 1, 2 and 3.
1110 *
1111 * evm_p8
1112 * EVM for pilot 8. Contain EVM for streams: 0, 1, 2 and 3.
1113 *
1114 * evm_p9
1115 * EVM for pilot 9. Contain EVM for streams: 0, 1, 2 and 3.
1116 *
1117 * evm_p10
1118 * EVM for pilot 10. Contain EVM for streams: 0, 1, 2 and 3.
1119 *
1120 * evm_p11
1121 * EVM for pilot 11. Contain EVM for streams: 0, 1, 2 and 3.
1122 *
1123 * evm_p12
1124 * EVM for pilot 12. Contain EVM for streams: 0, 1, 2 and 3.
1125 *
1126 * evm_p13
1127 * EVM for pilot 13. Contain EVM for streams: 0, 1, 2 and 3.
1128 *
1129 * evm_p14
1130 * EVM for pilot 14. Contain EVM for streams: 0, 1, 2 and 3.
1131 *
1132 * evm_p15
1133 * EVM for pilot 15. Contain EVM for streams: 0, 1, 2 and 3.
1134 *
1135 * tsf_timestamp
1136 * Receive TSF timestamp sampled on the rising edge of
1137 * rx_clear. For PHY errors this may be the current TSF when
1138 * phy_error is asserted if the rx_clear does not assert before
1139 * the end of the PHY error.
1140 *
1141 * wb_timestamp
1142 * WLAN/BT timestamp is a 1 usec resolution timestamp which
1143 * does not get updated based on receive beacon like TSF. The
1144 * same rules for capturing tsf_timestamp are used to capture
1145 * the wb_timestamp.
1146 *
1147 * locationing_timestamp
1148 * Timestamp used for locationing. This timestamp is used to
1149 * indicate fractions of usec. For example if the MAC clock is
1150 * running at 80 MHz, the timestamp will increment every 12.5
1151 * nsec. The value starts at 0 and increments to 79 and
1152 * returns to 0 and repeats. This information is valid for
1153 * every PPDU. This information can be used in conjunction
1154 * with wb_timestamp to capture large delta times.
1155 *
1156 * phy_err_code
1157 * See the 1.10.8.1.2 for the list of the PHY error codes.
1158 *
1159 * phy_err
1160 * Indicates a PHY error was detected for this PPDU.
1161 *
1162 * rx_location
1163 * Indicates that location information was requested.
1164 *
1165 * txbf_h_info
1166 * Indicates that the packet data carries H information which
1167 * is used for TxBF debug.
1168 *
1169 * reserved_18
1170 * Reserved: HW should fill with 0, FW should ignore.
1171 *
1172 * rx_antenna
1173 * Receive antenna value
1174 *
1175 * tx_ht_vht_ack
1176 * Indicates that a HT or VHT Ack/BA frame was transmitted in
1177 * response to this receive packet.
1178 *
1179 * bb_captured_channel
1180 * Indicates that the BB has captured a channel dump. FW can
1181 * then read the channel dump memory. This may indicate that
1182 * the channel was captured either based on PCU setting the
1183 * capture_channel bit BB descriptor or FW setting the
1184 * capture_channel mode bit.
1185 *
1186 * reserved_19
1187 * Reserved: HW should fill with 0, FW should ignore.
1188 *
1189 * bb_length
1190 * Indicates the number of bytes of baseband information for
1191 * PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1192 * which indicates that this is not a normal PPDU but rather
1193 * contains baseband debug information.
1194 *
1195 * reserved_20
1196 * Reserved: HW should fill with 0, FW should ignore.
1197 *
1198 * ppdu_done
1199 * PPDU end status is only valid when ppdu_done bit is set.
1200 * Every time HW sets this bit in memory FW/SW must clear this
1201 * bit in memory. FW will initialize all the ppdu_done dword
1202 * to 0.
1203*/
1204
1205#define FW_RX_DESC_INFO0_DISCARD (1 << 0)
1206#define FW_RX_DESC_INFO0_FORWARD (1 << 1)
1207#define FW_RX_DESC_INFO0_INSPECT (1 << 5)
1208#define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1209#define FW_RX_DESC_INFO0_EXT_LSB 6
1210
1211struct fw_rx_desc_base {
1212 u8 info0;
1213} __packed;
1214
1215#endif /* _RX_DESC_H_ */