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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _HTT_H_
19#define _HTT_H_
20
21#include <linux/bug.h>
22#include <linux/interrupt.h>
23#include <linux/dmapool.h>
24#include <linux/hashtable.h>
25#include <net/mac80211.h>
26
27#include "htc.h"
28#include "hw.h"
29#include "rx_desc.h"
30#include "hw.h"
31
32enum htt_dbg_stats_type {
33 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
34 HTT_DBG_STATS_RX_REORDER = 1 << 1,
35 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
36 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
37 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
38 /* bits 5-23 currently reserved */
39
40 HTT_DBG_NUM_STATS /* keep this last */
41};
42
43enum htt_h2t_msg_type { /* host-to-target */
44 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
45 HTT_H2T_MSG_TYPE_TX_FRM = 1,
46 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
47 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
48 HTT_H2T_MSG_TYPE_SYNC = 4,
49 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
50 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
51
52 /* This command is used for sending management frames in HTT < 3.0.
53 * HTT >= 3.0 uses TX_FRM for everything. */
54 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
55 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
56
57 HTT_H2T_NUM_MSGS /* keep this last */
58};
59
60struct htt_cmd_hdr {
61 u8 msg_type;
62} __packed;
63
64struct htt_ver_req {
65 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
66} __packed;
67
68/*
69 * HTT tx MSDU descriptor
70 *
71 * The HTT tx MSDU descriptor is created by the host HTT SW for each
72 * tx MSDU. The HTT tx MSDU descriptor contains the information that
73 * the target firmware needs for the FW's tx processing, particularly
74 * for creating the HW msdu descriptor.
75 * The same HTT tx descriptor is used for HL and LL systems, though
76 * a few fields within the tx descriptor are used only by LL or
77 * only by HL.
78 * The HTT tx descriptor is defined in two manners: by a struct with
79 * bitfields, and by a series of [dword offset, bit mask, bit shift]
80 * definitions.
81 * The target should use the struct def, for simplicitly and clarity,
82 * but the host shall use the bit-mast + bit-shift defs, to be endian-
83 * neutral. Specifically, the host shall use the get/set macros built
84 * around the mask + shift defs.
85 */
86struct htt_data_tx_desc_frag {
87 union {
88 struct double_word_addr {
89 __le32 paddr;
90 __le32 len;
91 } __packed dword_addr;
92 struct triple_word_addr {
93 __le32 paddr_lo;
94 __le16 paddr_hi;
95 __le16 len_16;
96 } __packed tword_addr;
97 } __packed;
98} __packed;
99
100struct htt_msdu_ext_desc {
101 __le32 tso_flag[3];
102 __le16 ip_identification;
103 u8 flags;
104 u8 reserved;
105 struct htt_data_tx_desc_frag frags[6];
106};
107
108#define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
109#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
110#define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
111#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
112#define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
113
114#define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
118 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
119
120enum htt_data_tx_desc_flags0 {
121 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
122 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
123 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
124 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
125 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
126#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
127#define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
128};
129
130enum htt_data_tx_desc_flags1 {
131#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
132#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
133#define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
134#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
135#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
136#define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
137 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
138 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
139 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
140 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
141 HTT_DATA_TX_DESC_FLAGS1_RSVD1 = 1 << 15
142};
143
144enum htt_data_tx_ext_tid {
145 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
146 HTT_DATA_TX_EXT_TID_MGMT = 17,
147 HTT_DATA_TX_EXT_TID_INVALID = 31
148};
149
150#define HTT_INVALID_PEERID 0xFFFF
151
152/*
153 * htt_data_tx_desc - used for data tx path
154 *
155 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
156 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
157 * for special kinds of tids
158 * postponed: only for HL hosts. indicates if this is a resend
159 * (HL hosts manage queues on the host )
160 * more_in_batch: only for HL hosts. indicates if more packets are
161 * pending. this allows target to wait and aggregate
162 * freq: 0 means home channel of given vdev. intended for offchannel
163 */
164struct htt_data_tx_desc {
165 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
166 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
167 __le16 len;
168 __le16 id;
169 __le32 frags_paddr;
170 union {
171 __le32 peerid;
172 struct {
173 __le16 peerid;
174 __le16 freq;
175 } __packed offchan_tx;
176 } __packed;
177 u8 prefetch[0]; /* start of frame, for FW classification engine */
178} __packed;
179
180enum htt_rx_ring_flags {
181 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
182 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
183 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
184 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
185 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
186 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
187 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
188 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
189 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
190 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
191 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
192 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
193 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
194 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
195 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
196 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
197};
198
199#define HTT_RX_RING_SIZE_MIN 128
200#define HTT_RX_RING_SIZE_MAX 2048
201
202struct htt_rx_ring_setup_ring {
203 __le32 fw_idx_shadow_reg_paddr;
204 __le32 rx_ring_base_paddr;
205 __le16 rx_ring_len; /* in 4-byte words */
206 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
207 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
208 __le16 fw_idx_init_val;
209
210 /* the following offsets are in 4-byte units */
211 __le16 mac80211_hdr_offset;
212 __le16 msdu_payload_offset;
213 __le16 ppdu_start_offset;
214 __le16 ppdu_end_offset;
215 __le16 mpdu_start_offset;
216 __le16 mpdu_end_offset;
217 __le16 msdu_start_offset;
218 __le16 msdu_end_offset;
219 __le16 rx_attention_offset;
220 __le16 frag_info_offset;
221} __packed;
222
223struct htt_rx_ring_setup_hdr {
224 u8 num_rings; /* supported values: 1, 2 */
225 __le16 rsvd0;
226} __packed;
227
228struct htt_rx_ring_setup {
229 struct htt_rx_ring_setup_hdr hdr;
230 struct htt_rx_ring_setup_ring rings[0];
231} __packed;
232
233/*
234 * htt_stats_req - request target to send specified statistics
235 *
236 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
237 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
238 * so make sure its little-endian.
239 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
240 * so make sure its little-endian.
241 * @cfg_val: stat_type specific configuration
242 * @stat_type: see %htt_dbg_stats_type
243 * @cookie_lsb: used for confirmation message from target->host
244 * @cookie_msb: ditto as %cookie
245 */
246struct htt_stats_req {
247 u8 upload_types[3];
248 u8 rsvd0;
249 u8 reset_types[3];
250 struct {
251 u8 mpdu_bytes;
252 u8 mpdu_num_msdus;
253 u8 msdu_bytes;
254 } __packed;
255 u8 stat_type;
256 __le32 cookie_lsb;
257 __le32 cookie_msb;
258} __packed;
259
260#define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
261
262/*
263 * htt_oob_sync_req - request out-of-band sync
264 *
265 * The HTT SYNC tells the target to suspend processing of subsequent
266 * HTT host-to-target messages until some other target agent locally
267 * informs the target HTT FW that the current sync counter is equal to
268 * or greater than (in a modulo sense) the sync counter specified in
269 * the SYNC message.
270 *
271 * This allows other host-target components to synchronize their operation
272 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
273 * security key has been downloaded to and activated by the target.
274 * In the absence of any explicit synchronization counter value
275 * specification, the target HTT FW will use zero as the default current
276 * sync value.
277 *
278 * The HTT target FW will suspend its host->target message processing as long
279 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
280 */
281struct htt_oob_sync_req {
282 u8 sync_count;
283 __le16 rsvd0;
284} __packed;
285
286struct htt_aggr_conf {
287 u8 max_num_ampdu_subframes;
288 /* amsdu_subframes is limited by 0x1F mask */
289 u8 max_num_amsdu_subframes;
290} __packed;
291
292#define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
293struct htt_mgmt_tx_desc_qca99x0 {
294 __le32 rate;
295} __packed;
296
297struct htt_mgmt_tx_desc {
298 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
299 __le32 msdu_paddr;
300 __le32 desc_id;
301 __le32 len;
302 __le32 vdev_id;
303 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
304 union {
305 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
306 } __packed;
307} __packed;
308
309enum htt_mgmt_tx_status {
310 HTT_MGMT_TX_STATUS_OK = 0,
311 HTT_MGMT_TX_STATUS_RETRY = 1,
312 HTT_MGMT_TX_STATUS_DROP = 2
313};
314
315/*=== target -> host messages ===============================================*/
316
317enum htt_main_t2h_msg_type {
318 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
319 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
320 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
321 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
322 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
323 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
324 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
325 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
326 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
327 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
328 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
329 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
330 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
331 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
332 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
333 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
334 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
335 HTT_MAIN_T2H_MSG_TYPE_TEST,
336 /* keep this last */
337 HTT_MAIN_T2H_NUM_MSGS
338};
339
340enum htt_10x_t2h_msg_type {
341 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
342 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
343 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
344 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
345 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
346 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
347 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
348 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
349 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
350 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
351 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
352 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
353 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
354 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
355 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
356 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
357 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
358 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
359 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
360 /* keep this last */
361 HTT_10X_T2H_NUM_MSGS
362};
363
364enum htt_tlv_t2h_msg_type {
365 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
366 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
367 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
368 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
369 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
370 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
371 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
372 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
373 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
374 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
375 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
376 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
377 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */
378 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
379 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
380 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
381 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
382 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
383 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
384 /* 0x13 reservd */
385 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
386 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
387 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
388 HTT_TLV_T2H_MSG_TYPE_TEST,
389 /* keep this last */
390 HTT_TLV_T2H_NUM_MSGS
391};
392
393enum htt_10_4_t2h_msg_type {
394 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
395 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
396 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
397 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
398 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
399 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
400 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
401 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
402 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
403 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
404 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
405 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
406 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
407 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
408 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
409 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
410 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
411 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
412 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
413 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
414 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
415 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
416 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
417 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
418 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
419 /* 0x19 to 0x2f are reserved */
420 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
421 /* keep this last */
422 HTT_10_4_T2H_NUM_MSGS
423};
424
425enum htt_t2h_msg_type {
426 HTT_T2H_MSG_TYPE_VERSION_CONF,
427 HTT_T2H_MSG_TYPE_RX_IND,
428 HTT_T2H_MSG_TYPE_RX_FLUSH,
429 HTT_T2H_MSG_TYPE_PEER_MAP,
430 HTT_T2H_MSG_TYPE_PEER_UNMAP,
431 HTT_T2H_MSG_TYPE_RX_ADDBA,
432 HTT_T2H_MSG_TYPE_RX_DELBA,
433 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
434 HTT_T2H_MSG_TYPE_PKTLOG,
435 HTT_T2H_MSG_TYPE_STATS_CONF,
436 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
437 HTT_T2H_MSG_TYPE_SEC_IND,
438 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
439 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
440 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
441 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
442 HTT_T2H_MSG_TYPE_RX_PN_IND,
443 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
444 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
445 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
446 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
447 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
448 HTT_T2H_MSG_TYPE_AGGR_CONF,
449 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
450 HTT_T2H_MSG_TYPE_TEST,
451 HTT_T2H_MSG_TYPE_EN_STATS,
452 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
453 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
454 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
455 /* keep this last */
456 HTT_T2H_NUM_MSGS
457};
458
459/*
460 * htt_resp_hdr - header for target-to-host messages
461 *
462 * msg_type: see htt_t2h_msg_type
463 */
464struct htt_resp_hdr {
465 u8 msg_type;
466} __packed;
467
468#define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
469#define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
470#define HTT_RESP_HDR_MSG_TYPE_LSB 0
471
472/* htt_ver_resp - response sent for htt_ver_req */
473struct htt_ver_resp {
474 u8 minor;
475 u8 major;
476 u8 rsvd0;
477} __packed;
478
479struct htt_mgmt_tx_completion {
480 u8 rsvd0;
481 u8 rsvd1;
482 u8 rsvd2;
483 __le32 desc_id;
484 __le32 status;
485} __packed;
486
487#define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x3F)
488#define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
489#define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 6)
490#define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 7)
491
492#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
493#define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
494#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
495#define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
496#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
497#define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
498#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
499#define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
500#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
501#define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
502
503struct htt_rx_indication_hdr {
504 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */
505 __le16 peer_id;
506 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */
507} __packed;
508
509#define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
510#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
511#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
512#define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
513#define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
514#define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
515
516#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
517#define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
518#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
519#define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
520
521#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
522#define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
523#define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
524#define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
525
526enum htt_rx_legacy_rate {
527 HTT_RX_OFDM_48 = 0,
528 HTT_RX_OFDM_24 = 1,
529 HTT_RX_OFDM_12,
530 HTT_RX_OFDM_6,
531 HTT_RX_OFDM_54,
532 HTT_RX_OFDM_36,
533 HTT_RX_OFDM_18,
534 HTT_RX_OFDM_9,
535
536 /* long preamble */
537 HTT_RX_CCK_11_LP = 0,
538 HTT_RX_CCK_5_5_LP = 1,
539 HTT_RX_CCK_2_LP,
540 HTT_RX_CCK_1_LP,
541 /* short preamble */
542 HTT_RX_CCK_11_SP,
543 HTT_RX_CCK_5_5_SP,
544 HTT_RX_CCK_2_SP
545};
546
547enum htt_rx_legacy_rate_type {
548 HTT_RX_LEGACY_RATE_OFDM = 0,
549 HTT_RX_LEGACY_RATE_CCK
550};
551
552enum htt_rx_preamble_type {
553 HTT_RX_LEGACY = 0x4,
554 HTT_RX_HT = 0x8,
555 HTT_RX_HT_WITH_TXBF = 0x9,
556 HTT_RX_VHT = 0xC,
557 HTT_RX_VHT_WITH_TXBF = 0xD,
558};
559
560/*
561 * Fields: phy_err_valid, phy_err_code, tsf,
562 * usec_timestamp, sub_usec_timestamp
563 * ..are valid only if end_valid == 1.
564 *
565 * Fields: rssi_chains, legacy_rate_type,
566 * legacy_rate_cck, preamble_type, service,
567 * vht_sig_*
568 * ..are valid only if start_valid == 1;
569 */
570struct htt_rx_indication_ppdu {
571 u8 combined_rssi;
572 u8 sub_usec_timestamp;
573 u8 phy_err_code;
574 u8 info0; /* HTT_RX_INDICATION_INFO0_ */
575 struct {
576 u8 pri20_db;
577 u8 ext20_db;
578 u8 ext40_db;
579 u8 ext80_db;
580 } __packed rssi_chains[4];
581 __le32 tsf;
582 __le32 usec_timestamp;
583 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */
584 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */
585} __packed;
586
587enum htt_rx_mpdu_status {
588 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
589 HTT_RX_IND_MPDU_STATUS_OK,
590 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
591 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
592 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
593 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
594 /* only accept EAPOL frames */
595 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
596 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
597 /* Non-data in promiscous mode */
598 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
599 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
600 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
601 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
602 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
603 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
604
605 /*
606 * MISC: discard for unspecified reasons.
607 * Leave this enum value last.
608 */
609 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
610};
611
612struct htt_rx_indication_mpdu_range {
613 u8 mpdu_count;
614 u8 mpdu_range_status; /* %htt_rx_mpdu_status */
615 u8 pad0;
616 u8 pad1;
617} __packed;
618
619struct htt_rx_indication_prefix {
620 __le16 fw_rx_desc_bytes;
621 u8 pad0;
622 u8 pad1;
623};
624
625struct htt_rx_indication {
626 struct htt_rx_indication_hdr hdr;
627 struct htt_rx_indication_ppdu ppdu;
628 struct htt_rx_indication_prefix prefix;
629
630 /*
631 * the following fields are both dynamically sized, so
632 * take care addressing them
633 */
634
635 /* the size of this is %fw_rx_desc_bytes */
636 struct fw_rx_desc_base fw_desc;
637
638 /*
639 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
640 * and has %num_mpdu_ranges elements.
641 */
642 struct htt_rx_indication_mpdu_range mpdu_ranges[0];
643} __packed;
644
645static inline struct htt_rx_indication_mpdu_range *
646 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
647{
648 void *ptr = rx_ind;
649
650 ptr += sizeof(rx_ind->hdr)
651 + sizeof(rx_ind->ppdu)
652 + sizeof(rx_ind->prefix)
653 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
654 return ptr;
655}
656
657enum htt_rx_flush_mpdu_status {
658 HTT_RX_FLUSH_MPDU_DISCARD = 0,
659 HTT_RX_FLUSH_MPDU_REORDER = 1,
660};
661
662/*
663 * htt_rx_flush - discard or reorder given range of mpdus
664 *
665 * Note: host must check if all sequence numbers between
666 * [seq_num_start, seq_num_end-1] are valid.
667 */
668struct htt_rx_flush {
669 __le16 peer_id;
670 u8 tid;
671 u8 rsvd0;
672 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
673 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
674 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
675};
676
677struct htt_rx_peer_map {
678 u8 vdev_id;
679 __le16 peer_id;
680 u8 addr[6];
681 u8 rsvd0;
682 u8 rsvd1;
683} __packed;
684
685struct htt_rx_peer_unmap {
686 u8 rsvd0;
687 __le16 peer_id;
688} __packed;
689
690enum htt_security_types {
691 HTT_SECURITY_NONE,
692 HTT_SECURITY_WEP128,
693 HTT_SECURITY_WEP104,
694 HTT_SECURITY_WEP40,
695 HTT_SECURITY_TKIP,
696 HTT_SECURITY_TKIP_NOMIC,
697 HTT_SECURITY_AES_CCMP,
698 HTT_SECURITY_WAPI,
699
700 HTT_NUM_SECURITY_TYPES /* keep this last! */
701};
702
703enum htt_security_flags {
704#define HTT_SECURITY_TYPE_MASK 0x7F
705#define HTT_SECURITY_TYPE_LSB 0
706 HTT_SECURITY_IS_UNICAST = 1 << 7
707};
708
709struct htt_security_indication {
710 union {
711 /* dont use bitfields; undefined behaviour */
712 u8 flags; /* %htt_security_flags */
713 struct {
714 u8 security_type:7, /* %htt_security_types */
715 is_unicast:1;
716 } __packed;
717 } __packed;
718 __le16 peer_id;
719 u8 michael_key[8];
720 u8 wapi_rsc[16];
721} __packed;
722
723#define HTT_RX_BA_INFO0_TID_MASK 0x000F
724#define HTT_RX_BA_INFO0_TID_LSB 0
725#define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
726#define HTT_RX_BA_INFO0_PEER_ID_LSB 4
727
728struct htt_rx_addba {
729 u8 window_size;
730 __le16 info0; /* %HTT_RX_BA_INFO0_ */
731} __packed;
732
733struct htt_rx_delba {
734 u8 rsvd0;
735 __le16 info0; /* %HTT_RX_BA_INFO0_ */
736} __packed;
737
738enum htt_data_tx_status {
739 HTT_DATA_TX_STATUS_OK = 0,
740 HTT_DATA_TX_STATUS_DISCARD = 1,
741 HTT_DATA_TX_STATUS_NO_ACK = 2,
742 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */
743 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
744};
745
746enum htt_data_tx_flags {
747#define HTT_DATA_TX_STATUS_MASK 0x07
748#define HTT_DATA_TX_STATUS_LSB 0
749#define HTT_DATA_TX_TID_MASK 0x78
750#define HTT_DATA_TX_TID_LSB 3
751 HTT_DATA_TX_TID_INVALID = 1 << 7
752};
753
754#define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
755
756struct htt_data_tx_completion {
757 union {
758 u8 flags;
759 struct {
760 u8 status:3,
761 tid:4,
762 tid_invalid:1;
763 } __packed;
764 } __packed;
765 u8 num_msdus;
766 u8 rsvd0;
767 __le16 msdus[0]; /* variable length based on %num_msdus */
768} __packed;
769
770struct htt_tx_compl_ind_base {
771 u32 hdr;
772 u16 payload[1/*or more*/];
773} __packed;
774
775struct htt_rc_tx_done_params {
776 u32 rate_code;
777 u32 rate_code_flags;
778 u32 flags;
779 u32 num_enqued; /* 1 for non-AMPDU */
780 u32 num_retries;
781 u32 num_failed; /* for AMPDU */
782 u32 ack_rssi;
783 u32 time_stamp;
784 u32 is_probe;
785};
786
787struct htt_rc_update {
788 u8 vdev_id;
789 __le16 peer_id;
790 u8 addr[6];
791 u8 num_elems;
792 u8 rsvd0;
793 struct htt_rc_tx_done_params params[0]; /* variable length %num_elems */
794} __packed;
795
796/* see htt_rx_indication for similar fields and descriptions */
797struct htt_rx_fragment_indication {
798 union {
799 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */
800 struct {
801 u8 ext_tid:5,
802 flush_valid:1;
803 } __packed;
804 } __packed;
805 __le16 peer_id;
806 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */
807 __le16 fw_rx_desc_bytes;
808 __le16 rsvd0;
809
810 u8 fw_msdu_rx_desc[0];
811} __packed;
812
813#define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
814#define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
815#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
816#define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
817
818#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
819#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
820#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
821#define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
822
823struct htt_rx_pn_ind {
824 __le16 peer_id;
825 u8 tid;
826 u8 seqno_start;
827 u8 seqno_end;
828 u8 pn_ie_count;
829 u8 reserved;
830 u8 pn_ies[0];
831} __packed;
832
833struct htt_rx_offload_msdu {
834 __le16 msdu_len;
835 __le16 peer_id;
836 u8 vdev_id;
837 u8 tid;
838 u8 fw_desc;
839 u8 payload[0];
840} __packed;
841
842struct htt_rx_offload_ind {
843 u8 reserved;
844 __le16 msdu_count;
845} __packed;
846
847struct htt_rx_in_ord_msdu_desc {
848 __le32 msdu_paddr;
849 __le16 msdu_len;
850 u8 fw_desc;
851 u8 reserved;
852} __packed;
853
854struct htt_rx_in_ord_ind {
855 u8 info;
856 __le16 peer_id;
857 u8 vdev_id;
858 u8 reserved;
859 __le16 msdu_count;
860 struct htt_rx_in_ord_msdu_desc msdu_descs[0];
861} __packed;
862
863#define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
864#define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
865#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
866#define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
867#define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
868#define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
869
870/*
871 * target -> host test message definition
872 *
873 * The following field definitions describe the format of the test
874 * message sent from the target to the host.
875 * The message consists of a 4-octet header, followed by a variable
876 * number of 32-bit integer values, followed by a variable number
877 * of 8-bit character values.
878 *
879 * |31 16|15 8|7 0|
880 * |-----------------------------------------------------------|
881 * | num chars | num ints | msg type |
882 * |-----------------------------------------------------------|
883 * | int 0 |
884 * |-----------------------------------------------------------|
885 * | int 1 |
886 * |-----------------------------------------------------------|
887 * | ... |
888 * |-----------------------------------------------------------|
889 * | char 3 | char 2 | char 1 | char 0 |
890 * |-----------------------------------------------------------|
891 * | | | ... | char 4 |
892 * |-----------------------------------------------------------|
893 * - MSG_TYPE
894 * Bits 7:0
895 * Purpose: identifies this as a test message
896 * Value: HTT_MSG_TYPE_TEST
897 * - NUM_INTS
898 * Bits 15:8
899 * Purpose: indicate how many 32-bit integers follow the message header
900 * - NUM_CHARS
901 * Bits 31:16
902 * Purpose: indicate how many 8-bit charaters follow the series of integers
903 */
904struct htt_rx_test {
905 u8 num_ints;
906 __le16 num_chars;
907
908 /* payload consists of 2 lists:
909 * a) num_ints * sizeof(__le32)
910 * b) num_chars * sizeof(u8) aligned to 4bytes */
911 u8 payload[0];
912} __packed;
913
914static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
915{
916 return (__le32 *)rx_test->payload;
917}
918
919static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
920{
921 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
922}
923
924/*
925 * target -> host packet log message
926 *
927 * The following field definitions describe the format of the packet log
928 * message sent from the target to the host.
929 * The message consists of a 4-octet header,followed by a variable number
930 * of 32-bit character values.
931 *
932 * |31 24|23 16|15 8|7 0|
933 * |-----------------------------------------------------------|
934 * | | | | msg type |
935 * |-----------------------------------------------------------|
936 * | payload |
937 * |-----------------------------------------------------------|
938 * - MSG_TYPE
939 * Bits 7:0
940 * Purpose: identifies this as a test message
941 * Value: HTT_MSG_TYPE_PACKETLOG
942 */
943struct htt_pktlog_msg {
944 u8 pad[3];
945 u8 payload[0];
946} __packed;
947
948struct htt_dbg_stats_rx_reorder_stats {
949 /* Non QoS MPDUs received */
950 __le32 deliver_non_qos;
951
952 /* MPDUs received in-order */
953 __le32 deliver_in_order;
954
955 /* Flush due to reorder timer expired */
956 __le32 deliver_flush_timeout;
957
958 /* Flush due to move out of window */
959 __le32 deliver_flush_oow;
960
961 /* Flush due to DELBA */
962 __le32 deliver_flush_delba;
963
964 /* MPDUs dropped due to FCS error */
965 __le32 fcs_error;
966
967 /* MPDUs dropped due to monitor mode non-data packet */
968 __le32 mgmt_ctrl;
969
970 /* MPDUs dropped due to invalid peer */
971 __le32 invalid_peer;
972
973 /* MPDUs dropped due to duplication (non aggregation) */
974 __le32 dup_non_aggr;
975
976 /* MPDUs dropped due to processed before */
977 __le32 dup_past;
978
979 /* MPDUs dropped due to duplicate in reorder queue */
980 __le32 dup_in_reorder;
981
982 /* Reorder timeout happened */
983 __le32 reorder_timeout;
984
985 /* invalid bar ssn */
986 __le32 invalid_bar_ssn;
987
988 /* reorder reset due to bar ssn */
989 __le32 ssn_reset;
990};
991
992struct htt_dbg_stats_wal_tx_stats {
993 /* Num HTT cookies queued to dispatch list */
994 __le32 comp_queued;
995
996 /* Num HTT cookies dispatched */
997 __le32 comp_delivered;
998
999 /* Num MSDU queued to WAL */
1000 __le32 msdu_enqued;
1001
1002 /* Num MPDU queue to WAL */
1003 __le32 mpdu_enqued;
1004
1005 /* Num MSDUs dropped by WMM limit */
1006 __le32 wmm_drop;
1007
1008 /* Num Local frames queued */
1009 __le32 local_enqued;
1010
1011 /* Num Local frames done */
1012 __le32 local_freed;
1013
1014 /* Num queued to HW */
1015 __le32 hw_queued;
1016
1017 /* Num PPDU reaped from HW */
1018 __le32 hw_reaped;
1019
1020 /* Num underruns */
1021 __le32 underrun;
1022
1023 /* Num PPDUs cleaned up in TX abort */
1024 __le32 tx_abort;
1025
1026 /* Num MPDUs requed by SW */
1027 __le32 mpdus_requed;
1028
1029 /* excessive retries */
1030 __le32 tx_ko;
1031
1032 /* data hw rate code */
1033 __le32 data_rc;
1034
1035 /* Scheduler self triggers */
1036 __le32 self_triggers;
1037
1038 /* frames dropped due to excessive sw retries */
1039 __le32 sw_retry_failure;
1040
1041 /* illegal rate phy errors */
1042 __le32 illgl_rate_phy_err;
1043
1044 /* wal pdev continous xretry */
1045 __le32 pdev_cont_xretry;
1046
1047 /* wal pdev continous xretry */
1048 __le32 pdev_tx_timeout;
1049
1050 /* wal pdev resets */
1051 __le32 pdev_resets;
1052
1053 __le32 phy_underrun;
1054
1055 /* MPDU is more than txop limit */
1056 __le32 txop_ovf;
1057} __packed;
1058
1059struct htt_dbg_stats_wal_rx_stats {
1060 /* Cnts any change in ring routing mid-ppdu */
1061 __le32 mid_ppdu_route_change;
1062
1063 /* Total number of statuses processed */
1064 __le32 status_rcvd;
1065
1066 /* Extra frags on rings 0-3 */
1067 __le32 r0_frags;
1068 __le32 r1_frags;
1069 __le32 r2_frags;
1070 __le32 r3_frags;
1071
1072 /* MSDUs / MPDUs delivered to HTT */
1073 __le32 htt_msdus;
1074 __le32 htt_mpdus;
1075
1076 /* MSDUs / MPDUs delivered to local stack */
1077 __le32 loc_msdus;
1078 __le32 loc_mpdus;
1079
1080 /* AMSDUs that have more MSDUs than the status ring size */
1081 __le32 oversize_amsdu;
1082
1083 /* Number of PHY errors */
1084 __le32 phy_errs;
1085
1086 /* Number of PHY errors drops */
1087 __le32 phy_err_drop;
1088
1089 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1090 __le32 mpdu_errs;
1091} __packed;
1092
1093struct htt_dbg_stats_wal_peer_stats {
1094 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1095} __packed;
1096
1097struct htt_dbg_stats_wal_pdev_txrx {
1098 struct htt_dbg_stats_wal_tx_stats tx_stats;
1099 struct htt_dbg_stats_wal_rx_stats rx_stats;
1100 struct htt_dbg_stats_wal_peer_stats peer_stats;
1101} __packed;
1102
1103struct htt_dbg_stats_rx_rate_info {
1104 __le32 mcs[10];
1105 __le32 sgi[10];
1106 __le32 nss[4];
1107 __le32 stbc[10];
1108 __le32 bw[3];
1109 __le32 pream[6];
1110 __le32 ldpc;
1111 __le32 txbf;
1112};
1113
1114/*
1115 * htt_dbg_stats_status -
1116 * present - The requested stats have been delivered in full.
1117 * This indicates that either the stats information was contained
1118 * in its entirety within this message, or else this message
1119 * completes the delivery of the requested stats info that was
1120 * partially delivered through earlier STATS_CONF messages.
1121 * partial - The requested stats have been delivered in part.
1122 * One or more subsequent STATS_CONF messages with the same
1123 * cookie value will be sent to deliver the remainder of the
1124 * information.
1125 * error - The requested stats could not be delivered, for example due
1126 * to a shortage of memory to construct a message holding the
1127 * requested stats.
1128 * invalid - The requested stat type is either not recognized, or the
1129 * target is configured to not gather the stats type in question.
1130 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1131 * series_done - This special value indicates that no further stats info
1132 * elements are present within a series of stats info elems
1133 * (within a stats upload confirmation message).
1134 */
1135enum htt_dbg_stats_status {
1136 HTT_DBG_STATS_STATUS_PRESENT = 0,
1137 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1138 HTT_DBG_STATS_STATUS_ERROR = 2,
1139 HTT_DBG_STATS_STATUS_INVALID = 3,
1140 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1141};
1142
1143/*
1144 * target -> host statistics upload
1145 *
1146 * The following field definitions describe the format of the HTT target
1147 * to host stats upload confirmation message.
1148 * The message contains a cookie echoed from the HTT host->target stats
1149 * upload request, which identifies which request the confirmation is
1150 * for, and a series of tag-length-value stats information elements.
1151 * The tag-length header for each stats info element also includes a
1152 * status field, to indicate whether the request for the stat type in
1153 * question was fully met, partially met, unable to be met, or invalid
1154 * (if the stat type in question is disabled in the target).
1155 * A special value of all 1's in this status field is used to indicate
1156 * the end of the series of stats info elements.
1157 *
1158 *
1159 * |31 16|15 8|7 5|4 0|
1160 * |------------------------------------------------------------|
1161 * | reserved | msg type |
1162 * |------------------------------------------------------------|
1163 * | cookie LSBs |
1164 * |------------------------------------------------------------|
1165 * | cookie MSBs |
1166 * |------------------------------------------------------------|
1167 * | stats entry length | reserved | S |stat type|
1168 * |------------------------------------------------------------|
1169 * | |
1170 * | type-specific stats info |
1171 * | |
1172 * |------------------------------------------------------------|
1173 * | stats entry length | reserved | S |stat type|
1174 * |------------------------------------------------------------|
1175 * | |
1176 * | type-specific stats info |
1177 * | |
1178 * |------------------------------------------------------------|
1179 * | n/a | reserved | 111 | n/a |
1180 * |------------------------------------------------------------|
1181 * Header fields:
1182 * - MSG_TYPE
1183 * Bits 7:0
1184 * Purpose: identifies this is a statistics upload confirmation message
1185 * Value: 0x9
1186 * - COOKIE_LSBS
1187 * Bits 31:0
1188 * Purpose: Provide a mechanism to match a target->host stats confirmation
1189 * message with its preceding host->target stats request message.
1190 * Value: LSBs of the opaque cookie specified by the host-side requestor
1191 * - COOKIE_MSBS
1192 * Bits 31:0
1193 * Purpose: Provide a mechanism to match a target->host stats confirmation
1194 * message with its preceding host->target stats request message.
1195 * Value: MSBs of the opaque cookie specified by the host-side requestor
1196 *
1197 * Stats Information Element tag-length header fields:
1198 * - STAT_TYPE
1199 * Bits 4:0
1200 * Purpose: identifies the type of statistics info held in the
1201 * following information element
1202 * Value: htt_dbg_stats_type
1203 * - STATUS
1204 * Bits 7:5
1205 * Purpose: indicate whether the requested stats are present
1206 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1207 * the completion of the stats entry series
1208 * - LENGTH
1209 * Bits 31:16
1210 * Purpose: indicate the stats information size
1211 * Value: This field specifies the number of bytes of stats information
1212 * that follows the element tag-length header.
1213 * It is expected but not required that this length is a multiple of
1214 * 4 bytes. Even if the length is not an integer multiple of 4, the
1215 * subsequent stats entry header will begin on a 4-byte aligned
1216 * boundary.
1217 */
1218
1219#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1220#define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1221#define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1222#define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1223
1224struct htt_stats_conf_item {
1225 union {
1226 u8 info;
1227 struct {
1228 u8 stat_type:5; /* %HTT_DBG_STATS_ */
1229 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
1230 } __packed;
1231 } __packed;
1232 u8 pad;
1233 __le16 length;
1234 u8 payload[0]; /* roundup(length, 4) long */
1235} __packed;
1236
1237struct htt_stats_conf {
1238 u8 pad[3];
1239 __le32 cookie_lsb;
1240 __le32 cookie_msb;
1241
1242 /* each item has variable length! */
1243 struct htt_stats_conf_item items[0];
1244} __packed;
1245
1246static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1247 const struct htt_stats_conf_item *item)
1248{
1249 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1250}
1251
1252/*
1253 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1254 *
1255 * The following field definitions describe the format of the HTT host
1256 * to target frag_desc/msdu_ext bank configuration message.
1257 * The message contains the based address and the min and max id of the
1258 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1259 * MSDU_EXT/FRAG_DESC.
1260 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1261 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1262 * the hardware does the mapping/translation.
1263 *
1264 * Total banks that can be configured is configured to 16.
1265 *
1266 * This should be called before any TX has be initiated by the HTT
1267 *
1268 * |31 16|15 8|7 5|4 0|
1269 * |------------------------------------------------------------|
1270 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1271 * |------------------------------------------------------------|
1272 * | BANK0_BASE_ADDRESS |
1273 * |------------------------------------------------------------|
1274 * | ... |
1275 * |------------------------------------------------------------|
1276 * | BANK15_BASE_ADDRESS |
1277 * |------------------------------------------------------------|
1278 * | BANK0_MAX_ID | BANK0_MIN_ID |
1279 * |------------------------------------------------------------|
1280 * | ... |
1281 * |------------------------------------------------------------|
1282 * | BANK15_MAX_ID | BANK15_MIN_ID |
1283 * |------------------------------------------------------------|
1284 * Header fields:
1285 * - MSG_TYPE
1286 * Bits 7:0
1287 * Value: 0x6
1288 * - BANKx_BASE_ADDRESS
1289 * Bits 31:0
1290 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1291 * bank physical/bus address.
1292 * - BANKx_MIN_ID
1293 * Bits 15:0
1294 * Purpose: Provide a mechanism to specify the min index that needs to
1295 * mapped.
1296 * - BANKx_MAX_ID
1297 * Bits 31:16
1298 * Purpose: Provide a mechanism to specify the max index that needs to
1299 *
1300 */
1301struct htt_frag_desc_bank_id {
1302 __le16 bank_min_id;
1303 __le16 bank_max_id;
1304} __packed;
1305
1306/* real is 16 but it wouldn't fit in the max htt message size
1307 * so we use a conservatively safe value for now */
1308#define HTT_FRAG_DESC_BANK_MAX 4
1309
1310#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1311#define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1312#define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1313#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1314#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1315#define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1316
1317enum htt_q_depth_type {
1318 HTT_Q_DEPTH_TYPE_BYTES = 0,
1319 HTT_Q_DEPTH_TYPE_MSDUS = 1,
1320};
1321
1322#define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1323 TARGET_10_4_NUM_VDEVS)
1324#define HTT_TX_Q_STATE_NUM_TIDS 8
1325#define HTT_TX_Q_STATE_ENTRY_SIZE 1
1326#define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1327
1328/**
1329 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1330 *
1331 * Defines host q state format and behavior. See htt_q_state.
1332 *
1333 * @record_size: Defines the size of each host q entry in bytes. In practice
1334 * however firmware (at least 10.4.3-00191) ignores this host
1335 * configuration value and uses hardcoded value of 1.
1336 * @record_multiplier: This is valid only when q depth type is MSDUs. It
1337 * defines the exponent for the power of 2 multiplication.
1338 */
1339struct htt_q_state_conf {
1340 __le32 paddr;
1341 __le16 num_peers;
1342 __le16 num_tids;
1343 u8 record_size;
1344 u8 record_multiplier;
1345 u8 pad[2];
1346} __packed;
1347
1348struct htt_frag_desc_bank_cfg {
1349 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1350 u8 num_banks;
1351 u8 desc_size;
1352 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1353 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1354 struct htt_q_state_conf q_state;
1355} __packed;
1356
1357#define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1358#define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1359#define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1360#define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1361#define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1362
1363/**
1364 * htt_q_state - shared between host and firmware via DMA
1365 *
1366 * This structure is used for the host to expose it's software queue state to
1367 * firmware so that its rate control can schedule fetch requests for optimized
1368 * performance. This is most notably used for MU-MIMO aggregation when multiple
1369 * MU clients are connected.
1370 *
1371 * @count: Each element defines the host queue depth. When q depth type was
1372 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as:
1373 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and
1374 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as
1375 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 **
1376 * record_multiplier (see htt_q_state_conf).
1377 * @map: Used by firmware to quickly check which host queues are not empty. It
1378 * is a bitmap simply saying.
1379 * @seq: Used by firmware to quickly check if the host queues were updated
1380 * since it last checked.
1381 *
1382 * FIXME: Is the q_state map[] size calculation really correct?
1383 */
1384struct htt_q_state {
1385 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
1386 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
1387 __le32 seq;
1388} __packed;
1389
1390#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1391#define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1392#define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1393#define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1394
1395struct htt_tx_fetch_record {
1396 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */
1397 __le16 num_msdus;
1398 __le32 num_bytes;
1399} __packed;
1400
1401struct htt_tx_fetch_ind {
1402 u8 pad0;
1403 __le16 fetch_seq_num;
1404 __le32 token;
1405 __le16 num_resp_ids;
1406 __le16 num_records;
1407 struct htt_tx_fetch_record records[0];
1408 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
1409} __packed;
1410
1411static inline void *
1412ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind)
1413{
1414 return (void *)&ind->records[le16_to_cpu(ind->num_records)];
1415}
1416
1417struct htt_tx_fetch_resp {
1418 u8 pad0;
1419 __le16 resp_id;
1420 __le16 fetch_seq_num;
1421 __le16 num_records;
1422 __le32 token;
1423 struct htt_tx_fetch_record records[0];
1424} __packed;
1425
1426struct htt_tx_fetch_confirm {
1427 u8 pad0;
1428 __le16 num_resp_ids;
1429 __le32 resp_ids[0];
1430} __packed;
1431
1432enum htt_tx_mode_switch_mode {
1433 HTT_TX_MODE_SWITCH_PUSH = 0,
1434 HTT_TX_MODE_SWITCH_PUSH_PULL = 1,
1435};
1436
1437#define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1438#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1439#define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1440
1441#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1442#define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1443#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1444#define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1445
1446#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1447#define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1448#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1449#define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1450
1451struct htt_tx_mode_switch_record {
1452 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */
1453 __le16 num_max_msdus;
1454} __packed;
1455
1456struct htt_tx_mode_switch_ind {
1457 u8 pad0;
1458 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
1459 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
1460 u8 pad1[2];
1461 struct htt_tx_mode_switch_record records[0];
1462} __packed;
1463
1464union htt_rx_pn_t {
1465 /* WEP: 24-bit PN */
1466 u32 pn24;
1467
1468 /* TKIP or CCMP: 48-bit PN */
1469 u_int64_t pn48;
1470
1471 /* WAPI: 128-bit PN */
1472 u_int64_t pn128[2];
1473};
1474
1475struct htt_cmd {
1476 struct htt_cmd_hdr hdr;
1477 union {
1478 struct htt_ver_req ver_req;
1479 struct htt_mgmt_tx_desc mgmt_tx;
1480 struct htt_data_tx_desc data_tx;
1481 struct htt_rx_ring_setup rx_setup;
1482 struct htt_stats_req stats_req;
1483 struct htt_oob_sync_req oob_sync_req;
1484 struct htt_aggr_conf aggr_conf;
1485 struct htt_frag_desc_bank_cfg frag_desc_bank_cfg;
1486 struct htt_tx_fetch_resp tx_fetch_resp;
1487 };
1488} __packed;
1489
1490struct htt_resp {
1491 struct htt_resp_hdr hdr;
1492 union {
1493 struct htt_ver_resp ver_resp;
1494 struct htt_mgmt_tx_completion mgmt_tx_completion;
1495 struct htt_data_tx_completion data_tx_completion;
1496 struct htt_rx_indication rx_ind;
1497 struct htt_rx_fragment_indication rx_frag_ind;
1498 struct htt_rx_peer_map peer_map;
1499 struct htt_rx_peer_unmap peer_unmap;
1500 struct htt_rx_flush rx_flush;
1501 struct htt_rx_addba rx_addba;
1502 struct htt_rx_delba rx_delba;
1503 struct htt_security_indication security_indication;
1504 struct htt_rc_update rc_update;
1505 struct htt_rx_test rx_test;
1506 struct htt_pktlog_msg pktlog_msg;
1507 struct htt_stats_conf stats_conf;
1508 struct htt_rx_pn_ind rx_pn_ind;
1509 struct htt_rx_offload_ind rx_offload_ind;
1510 struct htt_rx_in_ord_ind rx_in_ord_ind;
1511 struct htt_tx_fetch_ind tx_fetch_ind;
1512 struct htt_tx_fetch_confirm tx_fetch_confirm;
1513 struct htt_tx_mode_switch_ind tx_mode_switch_ind;
1514 };
1515} __packed;
1516
1517/*** host side structures follow ***/
1518
1519struct htt_tx_done {
1520 u32 msdu_id;
1521 bool discard;
1522 bool no_ack;
1523 bool success;
1524};
1525
1526struct htt_peer_map_event {
1527 u8 vdev_id;
1528 u16 peer_id;
1529 u8 addr[ETH_ALEN];
1530};
1531
1532struct htt_peer_unmap_event {
1533 u16 peer_id;
1534};
1535
1536struct ath10k_htt_txbuf {
1537 struct htt_data_tx_desc_frag frags[2];
1538 struct ath10k_htc_hdr htc_hdr;
1539 struct htt_cmd_hdr cmd_hdr;
1540 struct htt_data_tx_desc cmd_tx;
1541} __packed;
1542
1543struct ath10k_htt {
1544 struct ath10k *ar;
1545 enum ath10k_htc_ep_id eid;
1546
1547 u8 target_version_major;
1548 u8 target_version_minor;
1549 struct completion target_version_received;
1550 enum ath10k_fw_htt_op_version op_version;
1551 u8 max_num_amsdu;
1552 u8 max_num_ampdu;
1553
1554 const enum htt_t2h_msg_type *t2h_msg_types;
1555 u32 t2h_msg_types_max;
1556
1557 struct {
1558 /*
1559 * Ring of network buffer objects - This ring is
1560 * used exclusively by the host SW. This ring
1561 * mirrors the dev_addrs_ring that is shared
1562 * between the host SW and the MAC HW. The host SW
1563 * uses this netbufs ring to locate the network
1564 * buffer objects whose data buffers the HW has
1565 * filled.
1566 */
1567 struct sk_buff **netbufs_ring;
1568
1569 /* This is used only with firmware supporting IN_ORD_IND.
1570 *
1571 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1572 * buffer ring from which buffer addresses are copied by the
1573 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1574 * pointing to specific (re-ordered) buffers.
1575 *
1576 * FIXME: With kernel generic hashing functions there's a lot
1577 * of hash collisions for sk_buffs.
1578 */
1579 bool in_ord_rx;
1580 DECLARE_HASHTABLE(skb_table, 4);
1581
1582 /*
1583 * Ring of buffer addresses -
1584 * This ring holds the "physical" device address of the
1585 * rx buffers the host SW provides for the MAC HW to
1586 * fill.
1587 */
1588 __le32 *paddrs_ring;
1589
1590 /*
1591 * Base address of ring, as a "physical" device address
1592 * rather than a CPU address.
1593 */
1594 dma_addr_t base_paddr;
1595
1596 /* how many elems in the ring (power of 2) */
1597 int size;
1598
1599 /* size - 1 */
1600 unsigned size_mask;
1601
1602 /* how many rx buffers to keep in the ring */
1603 int fill_level;
1604
1605 /* how many rx buffers (full+empty) are in the ring */
1606 int fill_cnt;
1607
1608 /*
1609 * alloc_idx - where HTT SW has deposited empty buffers
1610 * This is allocated in consistent mem, so that the FW can
1611 * read this variable, and program the HW's FW_IDX reg with
1612 * the value of this shadow register.
1613 */
1614 struct {
1615 __le32 *vaddr;
1616 dma_addr_t paddr;
1617 } alloc_idx;
1618
1619 /* where HTT SW has processed bufs filled by rx MAC DMA */
1620 struct {
1621 unsigned msdu_payld;
1622 } sw_rd_idx;
1623
1624 /*
1625 * refill_retry_timer - timer triggered when the ring is
1626 * not refilled to the level expected
1627 */
1628 struct timer_list refill_retry_timer;
1629
1630 /* Protects access to all rx ring buffer state variables */
1631 spinlock_t lock;
1632 } rx_ring;
1633
1634 unsigned int prefetch_len;
1635
1636 /* Protects access to pending_tx, num_pending_tx */
1637 spinlock_t tx_lock;
1638 int max_num_pending_tx;
1639 int num_pending_tx;
1640 int num_pending_mgmt_tx;
1641 struct idr pending_tx;
1642 wait_queue_head_t empty_tx_wq;
1643
1644 /* set if host-fw communication goes haywire
1645 * used to avoid further failures */
1646 bool rx_confused;
1647 struct tasklet_struct rx_replenish_task;
1648
1649 /* This is used to group tx/rx completions separately and process them
1650 * in batches to reduce cache stalls */
1651 struct tasklet_struct txrx_compl_task;
1652 struct sk_buff_head tx_compl_q;
1653 struct sk_buff_head rx_compl_q;
1654 struct sk_buff_head rx_in_ord_compl_q;
1655
1656 /* rx_status template */
1657 struct ieee80211_rx_status rx_status;
1658
1659 struct {
1660 dma_addr_t paddr;
1661 struct htt_msdu_ext_desc *vaddr;
1662 } frag_desc;
1663
1664 struct {
1665 dma_addr_t paddr;
1666 struct ath10k_htt_txbuf *vaddr;
1667 } txbuf;
1668
1669 struct {
1670 struct htt_q_state *vaddr;
1671 dma_addr_t paddr;
1672 u16 num_peers;
1673 u16 num_tids;
1674 enum htt_q_depth_type type;
1675 } tx_q_state;
1676};
1677
1678#define RX_HTT_HDR_STATUS_LEN 64
1679
1680/* This structure layout is programmed via rx ring setup
1681 * so that FW knows how to transfer the rx descriptor to the host.
1682 * Buffers like this are placed on the rx ring. */
1683struct htt_rx_desc {
1684 union {
1685 /* This field is filled on the host using the msdu buffer
1686 * from htt_rx_indication */
1687 struct fw_rx_desc_base fw_desc;
1688 u32 pad;
1689 } __packed;
1690 struct {
1691 struct rx_attention attention;
1692 struct rx_frag_info frag_info;
1693 struct rx_mpdu_start mpdu_start;
1694 struct rx_msdu_start msdu_start;
1695 struct rx_msdu_end msdu_end;
1696 struct rx_mpdu_end mpdu_end;
1697 struct rx_ppdu_start ppdu_start;
1698 struct rx_ppdu_end ppdu_end;
1699 } __packed;
1700 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
1701 u8 msdu_payload[0];
1702};
1703
1704#define HTT_RX_DESC_ALIGN 8
1705
1706#define HTT_MAC_ADDR_LEN 6
1707
1708/*
1709 * FIX THIS
1710 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
1711 * rounded up to a cache line size.
1712 */
1713#define HTT_RX_BUF_SIZE 1920
1714#define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
1715
1716/* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
1717 * aggregated traffic more nicely. */
1718#define ATH10K_HTT_MAX_NUM_REFILL 16
1719
1720/*
1721 * DMA_MAP expects the buffer to be an integral number of cache lines.
1722 * Rather than checking the actual cache line size, this code makes a
1723 * conservative estimate of what the cache line size could be.
1724 */
1725#define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
1726#define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
1727
1728/* These values are default in most firmware revisions and apparently are a
1729 * sweet spot performance wise.
1730 */
1731#define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
1732#define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
1733
1734int ath10k_htt_connect(struct ath10k_htt *htt);
1735int ath10k_htt_init(struct ath10k *ar);
1736int ath10k_htt_setup(struct ath10k_htt *htt);
1737
1738int ath10k_htt_tx_alloc(struct ath10k_htt *htt);
1739void ath10k_htt_tx_free(struct ath10k_htt *htt);
1740
1741int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
1742int ath10k_htt_rx_ring_refill(struct ath10k *ar);
1743void ath10k_htt_rx_free(struct ath10k_htt *htt);
1744
1745void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1746void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
1747int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
1748int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie);
1749int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt);
1750int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt);
1751int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
1752 u8 max_subfrms_ampdu,
1753 u8 max_subfrms_amsdu);
1754void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
1755
1756void __ath10k_htt_tx_dec_pending(struct ath10k_htt *htt, bool limit_mgmt_desc);
1757int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
1758void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
1759int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *);
1760int ath10k_htt_tx(struct ath10k_htt *htt,
1761 enum ath10k_hw_txrx_mode txmode,
1762 struct sk_buff *msdu);
1763void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
1764 struct sk_buff *skb);
1765
1766#endif