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1/* QLogic qed NIC Driver
2 * Copyright (c) 2015 QLogic Corporation
3 *
4 * This software is available under the terms of the GNU General Public License
5 * (GPL) Version 2, available from the file COPYING in the main directory of
6 * this source tree.
7 */
8
9#ifndef _QED_H
10#define _QED_H
11
12#include <linux/types.h>
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <linux/firmware.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/mutex.h>
19#include <linux/pci.h>
20#include <linux/slab.h>
21#include <linux/string.h>
22#include <linux/workqueue.h>
23#include <linux/zlib.h>
24#include <linux/hashtable.h>
25#include <linux/qed/qed_if.h>
26#include "qed_hsi.h"
27
28extern const struct qed_common_ops qed_common_ops_pass;
29#define DRV_MODULE_VERSION "8.7.0.0"
30
31#define MAX_HWFNS_PER_DEVICE (4)
32#define NAME_SIZE 16
33#define VER_SIZE 16
34
35/* cau states */
36enum qed_coalescing_mode {
37 QED_COAL_MODE_DISABLE,
38 QED_COAL_MODE_ENABLE
39};
40
41struct qed_eth_cb_ops;
42struct qed_dev_info;
43
44/* helpers */
45static inline u32 qed_db_addr(u32 cid, u32 DEMS)
46{
47 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
48 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
49
50 return db_addr;
51}
52
53#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
54 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
55 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
56
57#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
58
59#define D_TRINE(val, cond1, cond2, true1, true2, def) \
60 (val == (cond1) ? true1 : \
61 (val == (cond2) ? true2 : def))
62
63/* forward */
64struct qed_ptt_pool;
65struct qed_spq;
66struct qed_sb_info;
67struct qed_sb_attn_info;
68struct qed_cxt_mngr;
69struct qed_sb_sp_info;
70struct qed_mcp_info;
71
72struct qed_rt_data {
73 u32 *init_val;
74 bool *b_valid;
75};
76
77/* The PCI personality is not quite synonymous to protocol ID:
78 * 1. All personalities need CORE connections
79 * 2. The Ethernet personality may support also the RoCE protocol
80 */
81enum qed_pci_personality {
82 QED_PCI_ETH,
83 QED_PCI_DEFAULT /* default in shmem */
84};
85
86/* All VFs are symmetric, all counters are PF + all VFs */
87struct qed_qm_iids {
88 u32 cids;
89 u32 vf_cids;
90 u32 tids;
91};
92
93enum QED_RESOURCES {
94 QED_SB,
95 QED_L2_QUEUE,
96 QED_VPORT,
97 QED_RSS_ENG,
98 QED_PQ,
99 QED_RL,
100 QED_MAC,
101 QED_VLAN,
102 QED_ILT,
103 QED_MAX_RESC,
104};
105
106enum QED_FEATURE {
107 QED_PF_L2_QUE,
108 QED_MAX_FEATURES,
109};
110
111enum QED_PORT_MODE {
112 QED_PORT_MODE_DE_2X40G,
113 QED_PORT_MODE_DE_2X50G,
114 QED_PORT_MODE_DE_1X100G,
115 QED_PORT_MODE_DE_4X10G_F,
116 QED_PORT_MODE_DE_4X10G_E,
117 QED_PORT_MODE_DE_4X20G,
118 QED_PORT_MODE_DE_1X40G,
119 QED_PORT_MODE_DE_2X25G,
120 QED_PORT_MODE_DE_1X25G
121};
122
123enum qed_dev_cap {
124 QED_DEV_CAP_ETH,
125};
126
127struct qed_hw_info {
128 /* PCI personality */
129 enum qed_pci_personality personality;
130
131 /* Resource Allocation scheme results */
132 u32 resc_start[QED_MAX_RESC];
133 u32 resc_num[QED_MAX_RESC];
134 u32 feat_num[QED_MAX_FEATURES];
135
136#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
137#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
138#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
139
140 u8 num_tc;
141 u8 offload_tc;
142 u8 non_offload_tc;
143
144 u32 concrete_fid;
145 u16 opaque_fid;
146 u16 ovlan;
147 u32 part_num[4];
148
149 unsigned char hw_mac_addr[ETH_ALEN];
150
151 struct qed_igu_info *p_igu_info;
152
153 u32 port_mode;
154 u32 hw_mode;
155 unsigned long device_capabilities;
156};
157
158struct qed_hw_cid_data {
159 u32 cid;
160 bool b_cid_allocated;
161
162 /* Additional identifiers */
163 u16 opaque_fid;
164 u8 vport_id;
165};
166
167/* maximun size of read/write commands (HW limit) */
168#define DMAE_MAX_RW_SIZE 0x2000
169
170struct qed_dmae_info {
171 /* Mutex for synchronizing access to functions */
172 struct mutex mutex;
173
174 u8 channel;
175
176 dma_addr_t completion_word_phys_addr;
177
178 /* The memory location where the DMAE writes the completion
179 * value when an operation is finished on this context.
180 */
181 u32 *p_completion_word;
182
183 dma_addr_t intermediate_buffer_phys_addr;
184
185 /* An intermediate buffer for DMAE operations that use virtual
186 * addresses - data is DMA'd to/from this buffer and then
187 * memcpy'd to/from the virtual address
188 */
189 u32 *p_intermediate_buffer;
190
191 dma_addr_t dmae_cmd_phys_addr;
192 struct dmae_cmd *p_dmae_cmd;
193};
194
195struct qed_qm_info {
196 struct init_qm_pq_params *qm_pq_params;
197 struct init_qm_vport_params *qm_vport_params;
198 struct init_qm_port_params *qm_port_params;
199 u16 start_pq;
200 u8 start_vport;
201 u8 pure_lb_pq;
202 u8 offload_pq;
203 u8 pure_ack_pq;
204 u8 vf_queues_offset;
205 u16 num_pqs;
206 u16 num_vf_pqs;
207 u8 num_vports;
208 u8 max_phys_tcs_per_port;
209 bool pf_rl_en;
210 bool pf_wfq_en;
211 bool vport_rl_en;
212 bool vport_wfq_en;
213 u8 pf_wfq;
214 u32 pf_rl;
215};
216
217struct storm_stats {
218 u32 address;
219 u32 len;
220};
221
222struct qed_storm_stats {
223 struct storm_stats mstats;
224 struct storm_stats pstats;
225 struct storm_stats tstats;
226 struct storm_stats ustats;
227};
228
229struct qed_fw_data {
230 struct fw_ver_info *fw_ver_info;
231 const u8 *modes_tree_buf;
232 union init_op *init_ops;
233 const u32 *arr_data;
234 u32 init_ops_size;
235};
236
237struct qed_simd_fp_handler {
238 void *token;
239 void (*func)(void *);
240};
241
242struct qed_hwfn {
243 struct qed_dev *cdev;
244 u8 my_id; /* ID inside the PF */
245#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
246 u8 rel_pf_id; /* Relative to engine*/
247 u8 abs_pf_id;
248#define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1)
249 u8 port_id;
250 bool b_active;
251
252 u32 dp_module;
253 u8 dp_level;
254 char name[NAME_SIZE];
255
256 bool first_on_engine;
257 bool hw_init_done;
258
259 /* BAR access */
260 void __iomem *regview;
261 void __iomem *doorbells;
262 u64 db_phys_addr;
263 unsigned long db_size;
264
265 /* PTT pool */
266 struct qed_ptt_pool *p_ptt_pool;
267
268 /* HW info */
269 struct qed_hw_info hw_info;
270
271 /* rt_array (for init-tool) */
272 struct qed_rt_data rt_data;
273
274 /* SPQ */
275 struct qed_spq *p_spq;
276
277 /* EQ */
278 struct qed_eq *p_eq;
279
280 /* Consolidate Q*/
281 struct qed_consq *p_consq;
282
283 /* Slow-Path definitions */
284 struct tasklet_struct *sp_dpc;
285 bool b_sp_dpc_enabled;
286
287 struct qed_ptt *p_main_ptt;
288 struct qed_ptt *p_dpc_ptt;
289
290 struct qed_sb_sp_info *p_sp_sb;
291 struct qed_sb_attn_info *p_sb_attn;
292
293 /* Protocol related */
294 struct qed_pf_params pf_params;
295
296 /* Array of sb_info of all status blocks */
297 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
298 u16 num_sbs;
299
300 struct qed_cxt_mngr *p_cxt_mngr;
301
302 /* Flag indicating whether interrupts are enabled or not*/
303 bool b_int_enabled;
304 bool b_int_requested;
305
306 /* True if the driver requests for the link */
307 bool b_drv_link_init;
308
309 struct qed_mcp_info *mcp_info;
310
311 struct qed_hw_cid_data *p_tx_cids;
312 struct qed_hw_cid_data *p_rx_cids;
313
314 struct qed_dmae_info dmae_info;
315
316 /* QM init */
317 struct qed_qm_info qm_info;
318 struct qed_storm_stats storm_stats;
319
320 /* Buffer for unzipping firmware data */
321 void *unzip_buf;
322
323 struct qed_simd_fp_handler simd_proto_handler[64];
324
325 struct z_stream_s *stream;
326};
327
328struct pci_params {
329 int pm_cap;
330
331 unsigned long mem_start;
332 unsigned long mem_end;
333 unsigned int irq;
334 u8 pf_num;
335};
336
337struct qed_int_param {
338 u32 int_mode;
339 u8 num_vectors;
340 u8 min_msix_cnt; /* for minimal functionality */
341};
342
343struct qed_int_params {
344 struct qed_int_param in;
345 struct qed_int_param out;
346 struct msix_entry *msix_table;
347 bool fp_initialized;
348 u8 fp_msix_base;
349 u8 fp_msix_cnt;
350};
351
352struct qed_dev {
353 u32 dp_module;
354 u8 dp_level;
355 char name[NAME_SIZE];
356
357 u8 type;
358#define QED_DEV_TYPE_BB (0 << 0)
359#define QED_DEV_TYPE_AH BIT(0)
360/* Translate type/revision combo into the proper conditions */
361#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
362#define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \
363 CHIP_REV_IS_A0(dev))
364#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
365 CHIP_REV_IS_B0(dev))
366
367#define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \
368 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2)
369
370 u16 vendor_id;
371 u16 device_id;
372
373 u16 chip_num;
374#define CHIP_NUM_MASK 0xffff
375#define CHIP_NUM_SHIFT 16
376
377 u16 chip_rev;
378#define CHIP_REV_MASK 0xf
379#define CHIP_REV_SHIFT 12
380#define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev)
381#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
382
383 u16 chip_metal;
384#define CHIP_METAL_MASK 0xff
385#define CHIP_METAL_SHIFT 4
386
387 u16 chip_bond_id;
388#define CHIP_BOND_ID_MASK 0xf
389#define CHIP_BOND_ID_SHIFT 0
390
391 u8 num_engines;
392 u8 num_ports_in_engines;
393 u8 num_funcs_in_port;
394
395 u8 path_id;
396 enum qed_mf_mode mf_mode;
397#define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT)
398#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR)
399#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN)
400
401 int pcie_width;
402 int pcie_speed;
403 u8 ver_str[VER_SIZE];
404
405 /* Add MF related configuration */
406 u8 mcp_rev;
407 u8 boot_mode;
408
409 u8 wol;
410
411 u32 int_mode;
412 enum qed_coalescing_mode int_coalescing_mode;
413 u8 rx_coalesce_usecs;
414 u8 tx_coalesce_usecs;
415
416 /* Start Bar offset of first hwfn */
417 void __iomem *regview;
418 void __iomem *doorbells;
419 u64 db_phys_addr;
420 unsigned long db_size;
421
422 /* PCI */
423 u8 cache_shift;
424
425 /* Init */
426 const struct iro *iro_arr;
427#define IRO (p_hwfn->cdev->iro_arr)
428
429 /* HW functions */
430 u8 num_hwfns;
431 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
432
433 u32 drv_type;
434
435 struct qed_eth_stats *reset_stats;
436 struct qed_fw_data *fw_data;
437
438 u32 mcp_nvm_resp;
439
440 /* Linux specific here */
441 struct qede_dev *edev;
442 struct pci_dev *pdev;
443 int msg_enable;
444
445 struct pci_params pci_params;
446
447 struct qed_int_params int_params;
448
449 u8 protocol;
450#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
451
452 /* Callbacks to protocol driver */
453 union {
454 struct qed_common_cb_ops *common;
455 struct qed_eth_cb_ops *eth;
456 } protocol_ops;
457 void *ops_cookie;
458
459 const struct firmware *firmware;
460};
461
462#define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB
463#define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB
464
465/**
466 * @brief qed_concrete_to_sw_fid - get the sw function id from
467 * the concrete value.
468 *
469 * @param concrete_fid
470 *
471 * @return inline u8
472 */
473static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
474 u32 concrete_fid)
475{
476 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
477
478 return pfid;
479}
480
481#define PURE_LB_TC 8
482
483#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
484
485/* Other Linux specific common definitions */
486#define DP_NAME(cdev) ((cdev)->name)
487
488#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
489 (cdev->regview) + \
490 (offset))
491
492#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
493#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
494#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
495
496#define DOORBELL(cdev, db_addr, val) \
497 writel((u32)val, (void __iomem *)((u8 __iomem *)\
498 (cdev->doorbells) + (db_addr)))
499
500/* Prototypes */
501int qed_fill_dev_info(struct qed_dev *cdev,
502 struct qed_dev_info *dev_info);
503void qed_link_update(struct qed_hwfn *hwfn);
504u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
505 u32 input_len, u8 *input_buf,
506 u32 max_size, u8 *unzip_buf);
507
508int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
509
510#define QED_ETH_INTERFACE_VERSION 300
511
512#endif /* _QED_H */