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1/*
2 * drivers/net/ethernet/freescale/gianfar.h
3 *
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
7 *
8 * Author: Andy Fleming
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 *
12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
18 *
19 * Still left to do:
20 * -Add support for module parameters
21 * -Add patch for ethtool phys id
22 */
23#ifndef __GIANFAR_H
24#define __GIANFAR_H
25
26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/errno.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/spinlock.h>
37#include <linux/mm.h>
38#include <linux/mii.h>
39#include <linux/phy.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/uaccess.h>
44#include <linux/module.h>
45#include <linux/crc32.h>
46#include <linux/workqueue.h>
47#include <linux/ethtool.h>
48
49struct ethtool_flow_spec_container {
50 struct ethtool_rx_flow_spec fs;
51 struct list_head list;
52};
53
54struct ethtool_rx_list {
55 struct list_head list;
56 unsigned int count;
57};
58
59/* The maximum number of packets to be handled in one call of gfar_poll */
60#define GFAR_DEV_WEIGHT 64
61
62/* Length for FCB */
63#define GMAC_FCB_LEN 8
64
65/* Length for TxPAL */
66#define GMAC_TXPAL_LEN 16
67
68/* Default padding amount */
69#define DEFAULT_PADDING 2
70
71/* Number of bytes to align the rx bufs to */
72#define RXBUF_ALIGNMENT 64
73
74#define PHY_INIT_TIMEOUT 100000
75
76#define DRV_NAME "gfar-enet"
77extern const char gfar_driver_version[];
78
79/* MAXIMUM NUMBER OF QUEUES SUPPORTED */
80#define MAX_TX_QS 0x8
81#define MAX_RX_QS 0x8
82
83/* MAXIMUM NUMBER OF GROUPS SUPPORTED */
84#define MAXGROUPS 0x2
85
86/* These need to be powers of 2 for this driver */
87#define DEFAULT_TX_RING_SIZE 256
88#define DEFAULT_RX_RING_SIZE 256
89
90#define GFAR_RX_BUFF_ALLOC 16
91
92#define GFAR_RX_MAX_RING_SIZE 256
93#define GFAR_TX_MAX_RING_SIZE 256
94
95#define GFAR_MAX_FIFO_THRESHOLD 511
96#define GFAR_MAX_FIFO_STARVE 511
97#define GFAR_MAX_FIFO_STARVE_OFF 511
98
99#define FBTHR_SHIFT 24
100#define DEFAULT_RX_LFC_THR 16
101#define DEFAULT_LFC_PTVVAL 4
102
103#define GFAR_RXB_SIZE 1536
104#define GFAR_SKBFRAG_SIZE (RXBUF_ALIGNMENT + GFAR_RXB_SIZE \
105 + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
106#define GFAR_RXB_TRUESIZE 2048
107
108#define TX_RING_MOD_MASK(size) (size-1)
109#define RX_RING_MOD_MASK(size) (size-1)
110#define GFAR_JUMBO_FRAME_SIZE 9600
111
112#define DEFAULT_FIFO_TX_THR 0x100
113#define DEFAULT_FIFO_TX_STARVE 0x40
114#define DEFAULT_FIFO_TX_STARVE_OFF 0x80
115#define DEFAULT_BD_STASH 1
116#define DEFAULT_STASH_LENGTH 96
117#define DEFAULT_STASH_INDEX 0
118
119/* The number of Exact Match registers */
120#define GFAR_EM_NUM 15
121
122/* Latency of interface clock in nanoseconds */
123/* Interface clock latency , in this case, means the
124 * time described by a value of 1 in the interrupt
125 * coalescing registers' time fields. Since those fields
126 * refer to the time it takes for 64 clocks to pass, the
127 * latencies are as such:
128 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
129 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
130 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
131 */
132#define GFAR_GBIT_TIME 512
133#define GFAR_100_TIME 2560
134#define GFAR_10_TIME 25600
135
136#define DEFAULT_TX_COALESCE 1
137#define DEFAULT_TXCOUNT 16
138#define DEFAULT_TXTIME 21
139
140#define DEFAULT_RXTIME 21
141
142#define DEFAULT_RX_COALESCE 0
143#define DEFAULT_RXCOUNT 0
144
145#define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
146 | SUPPORTED_10baseT_Full \
147 | SUPPORTED_100baseT_Half \
148 | SUPPORTED_100baseT_Full \
149 | SUPPORTED_Autoneg \
150 | SUPPORTED_MII)
151
152#define GFAR_SUPPORTED_GBIT SUPPORTED_1000baseT_Full
153
154/* TBI register addresses */
155#define MII_TBICON 0x11
156
157/* TBICON register bit fields */
158#define TBICON_CLK_SELECT 0x0020
159
160/* MAC register bits */
161#define MACCFG1_SOFT_RESET 0x80000000
162#define MACCFG1_RESET_RX_MC 0x00080000
163#define MACCFG1_RESET_TX_MC 0x00040000
164#define MACCFG1_RESET_RX_FUN 0x00020000
165#define MACCFG1_RESET_TX_FUN 0x00010000
166#define MACCFG1_LOOPBACK 0x00000100
167#define MACCFG1_RX_FLOW 0x00000020
168#define MACCFG1_TX_FLOW 0x00000010
169#define MACCFG1_SYNCD_RX_EN 0x00000008
170#define MACCFG1_RX_EN 0x00000004
171#define MACCFG1_SYNCD_TX_EN 0x00000002
172#define MACCFG1_TX_EN 0x00000001
173
174#define MACCFG2_INIT_SETTINGS 0x00007205
175#define MACCFG2_FULL_DUPLEX 0x00000001
176#define MACCFG2_IF 0x00000300
177#define MACCFG2_MII 0x00000100
178#define MACCFG2_GMII 0x00000200
179#define MACCFG2_HUGEFRAME 0x00000020
180#define MACCFG2_LENGTHCHECK 0x00000010
181#define MACCFG2_MPEN 0x00000008
182
183#define ECNTRL_FIFM 0x00008000
184#define ECNTRL_INIT_SETTINGS 0x00001000
185#define ECNTRL_TBI_MODE 0x00000020
186#define ECNTRL_REDUCED_MODE 0x00000010
187#define ECNTRL_R100 0x00000008
188#define ECNTRL_REDUCED_MII_MODE 0x00000004
189#define ECNTRL_SGMII_MODE 0x00000002
190
191#define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
192
193#define MINFLR_INIT_SETTINGS 0x00000040
194
195/* Tqueue control */
196#define TQUEUE_EN0 0x00008000
197#define TQUEUE_EN1 0x00004000
198#define TQUEUE_EN2 0x00002000
199#define TQUEUE_EN3 0x00001000
200#define TQUEUE_EN4 0x00000800
201#define TQUEUE_EN5 0x00000400
202#define TQUEUE_EN6 0x00000200
203#define TQUEUE_EN7 0x00000100
204#define TQUEUE_EN_ALL 0x0000FF00
205
206#define TR03WT_WT0_MASK 0xFF000000
207#define TR03WT_WT1_MASK 0x00FF0000
208#define TR03WT_WT2_MASK 0x0000FF00
209#define TR03WT_WT3_MASK 0x000000FF
210
211#define TR47WT_WT4_MASK 0xFF000000
212#define TR47WT_WT5_MASK 0x00FF0000
213#define TR47WT_WT6_MASK 0x0000FF00
214#define TR47WT_WT7_MASK 0x000000FF
215
216/* Rqueue control */
217#define RQUEUE_EX0 0x00800000
218#define RQUEUE_EX1 0x00400000
219#define RQUEUE_EX2 0x00200000
220#define RQUEUE_EX3 0x00100000
221#define RQUEUE_EX4 0x00080000
222#define RQUEUE_EX5 0x00040000
223#define RQUEUE_EX6 0x00020000
224#define RQUEUE_EX7 0x00010000
225#define RQUEUE_EX_ALL 0x00FF0000
226
227#define RQUEUE_EN0 0x00000080
228#define RQUEUE_EN1 0x00000040
229#define RQUEUE_EN2 0x00000020
230#define RQUEUE_EN3 0x00000010
231#define RQUEUE_EN4 0x00000008
232#define RQUEUE_EN5 0x00000004
233#define RQUEUE_EN6 0x00000002
234#define RQUEUE_EN7 0x00000001
235#define RQUEUE_EN_ALL 0x000000FF
236
237/* Init to do tx snooping for buffers and descriptors */
238#define DMACTRL_INIT_SETTINGS 0x000000c3
239#define DMACTRL_GRS 0x00000010
240#define DMACTRL_GTS 0x00000008
241
242#define TSTAT_CLEAR_THALT_ALL 0xFF000000
243#define TSTAT_CLEAR_THALT 0x80000000
244#define TSTAT_CLEAR_THALT0 0x80000000
245#define TSTAT_CLEAR_THALT1 0x40000000
246#define TSTAT_CLEAR_THALT2 0x20000000
247#define TSTAT_CLEAR_THALT3 0x10000000
248#define TSTAT_CLEAR_THALT4 0x08000000
249#define TSTAT_CLEAR_THALT5 0x04000000
250#define TSTAT_CLEAR_THALT6 0x02000000
251#define TSTAT_CLEAR_THALT7 0x01000000
252
253/* Interrupt coalescing macros */
254#define IC_ICEN 0x80000000
255#define IC_ICFT_MASK 0x1fe00000
256#define IC_ICFT_SHIFT 21
257#define mk_ic_icft(x) \
258 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
259#define IC_ICTT_MASK 0x0000ffff
260#define mk_ic_ictt(x) (x&IC_ICTT_MASK)
261
262#define mk_ic_value(count, time) (IC_ICEN | \
263 mk_ic_icft(count) | \
264 mk_ic_ictt(time))
265#define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
266 IC_ICFT_SHIFT)
267#define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
268
269#define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
270#define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
271
272#define skip_bd(bdp, stride, base, ring_size) ({ \
273 typeof(bdp) new_bd = (bdp) + (stride); \
274 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
275
276#define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
277
278#define RCTRL_TS_ENABLE 0x01000000
279#define RCTRL_PAL_MASK 0x001f0000
280#define RCTRL_LFC 0x00004000
281#define RCTRL_VLEX 0x00002000
282#define RCTRL_FILREN 0x00001000
283#define RCTRL_GHTX 0x00000400
284#define RCTRL_IPCSEN 0x00000200
285#define RCTRL_TUCSEN 0x00000100
286#define RCTRL_PRSDEP_MASK 0x000000c0
287#define RCTRL_PRSDEP_INIT 0x000000c0
288#define RCTRL_PRSFM 0x00000020
289#define RCTRL_PROM 0x00000008
290#define RCTRL_EMEN 0x00000002
291#define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
292 RCTRL_TUCSEN | RCTRL_FILREN)
293#define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
294 RCTRL_PRSDEP_INIT)
295#define RCTRL_EXTHASH (RCTRL_GHTX)
296#define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
297#define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
298
299
300#define RSTAT_CLEAR_RHALT 0x00800000
301#define RSTAT_CLEAR_RXF0 0x00000080
302#define RSTAT_RXF_MASK 0x000000ff
303
304#define TCTRL_IPCSEN 0x00004000
305#define TCTRL_TUCSEN 0x00002000
306#define TCTRL_VLINS 0x00001000
307#define TCTRL_THDF 0x00000800
308#define TCTRL_RFCPAUSE 0x00000010
309#define TCTRL_TFCPAUSE 0x00000008
310#define TCTRL_TXSCHED_MASK 0x00000006
311#define TCTRL_TXSCHED_INIT 0x00000000
312/* priority scheduling */
313#define TCTRL_TXSCHED_PRIO 0x00000002
314/* weighted round-robin scheduling (WRRS) */
315#define TCTRL_TXSCHED_WRRS 0x00000004
316/* default WRRS weight and policy setting,
317 * tailored to the tr03wt and tr47wt registers:
318 * equal weight for all Tx Qs, measured in 64byte units
319 */
320#define DEFAULT_WRRS_WEIGHT 0x18181818
321
322#define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
323
324#define IEVENT_INIT_CLEAR 0xffffffff
325#define IEVENT_BABR 0x80000000
326#define IEVENT_RXC 0x40000000
327#define IEVENT_BSY 0x20000000
328#define IEVENT_EBERR 0x10000000
329#define IEVENT_MSRO 0x04000000
330#define IEVENT_GTSC 0x02000000
331#define IEVENT_BABT 0x01000000
332#define IEVENT_TXC 0x00800000
333#define IEVENT_TXE 0x00400000
334#define IEVENT_TXB 0x00200000
335#define IEVENT_TXF 0x00100000
336#define IEVENT_LC 0x00040000
337#define IEVENT_CRL 0x00020000
338#define IEVENT_XFUN 0x00010000
339#define IEVENT_RXB0 0x00008000
340#define IEVENT_MAG 0x00000800
341#define IEVENT_GRSC 0x00000100
342#define IEVENT_RXF0 0x00000080
343#define IEVENT_FGPI 0x00000010
344#define IEVENT_FIR 0x00000008
345#define IEVENT_FIQ 0x00000004
346#define IEVENT_DPE 0x00000002
347#define IEVENT_PERR 0x00000001
348#define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
349#define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
350#define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
351#define IEVENT_ERR_MASK \
352(IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
353 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
354 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
355 | IEVENT_MAG | IEVENT_BABR)
356
357#define IMASK_INIT_CLEAR 0x00000000
358#define IMASK_BABR 0x80000000
359#define IMASK_RXC 0x40000000
360#define IMASK_BSY 0x20000000
361#define IMASK_EBERR 0x10000000
362#define IMASK_MSRO 0x04000000
363#define IMASK_GTSC 0x02000000
364#define IMASK_BABT 0x01000000
365#define IMASK_TXC 0x00800000
366#define IMASK_TXEEN 0x00400000
367#define IMASK_TXBEN 0x00200000
368#define IMASK_TXFEN 0x00100000
369#define IMASK_LC 0x00040000
370#define IMASK_CRL 0x00020000
371#define IMASK_XFUN 0x00010000
372#define IMASK_RXB0 0x00008000
373#define IMASK_MAG 0x00000800
374#define IMASK_GRSC 0x00000100
375#define IMASK_RXFEN0 0x00000080
376#define IMASK_FGPI 0x00000010
377#define IMASK_FIR 0x00000008
378#define IMASK_FIQ 0x00000004
379#define IMASK_DPE 0x00000002
380#define IMASK_PERR 0x00000001
381#define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
382 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
383 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
384 | IMASK_PERR)
385#define IMASK_RX_DEFAULT (IMASK_RXFEN0 | IMASK_BSY)
386#define IMASK_TX_DEFAULT (IMASK_TXFEN | IMASK_TXBEN)
387
388#define IMASK_RX_DISABLED ((~(IMASK_RX_DEFAULT)) & IMASK_DEFAULT)
389#define IMASK_TX_DISABLED ((~(IMASK_TX_DEFAULT)) & IMASK_DEFAULT)
390
391/* Fifo management */
392#define FIFO_TX_THR_MASK 0x01ff
393#define FIFO_TX_STARVE_MASK 0x01ff
394#define FIFO_TX_STARVE_OFF_MASK 0x01ff
395
396/* Attribute fields */
397
398/* This enables rx snooping for buffers and descriptors */
399#define ATTR_BDSTASH 0x00000800
400
401#define ATTR_BUFSTASH 0x00004000
402
403#define ATTR_SNOOPING 0x000000c0
404#define ATTR_INIT_SETTINGS ATTR_SNOOPING
405
406#define ATTRELI_INIT_SETTINGS 0x0
407#define ATTRELI_EL_MASK 0x3fff0000
408#define ATTRELI_EL(x) (x << 16)
409#define ATTRELI_EI_MASK 0x00003fff
410#define ATTRELI_EI(x) (x)
411
412#define BD_LFLAG(flags) ((flags) << 16)
413#define BD_LENGTH_MASK 0x0000ffff
414
415#define FPR_FILER_MASK 0xFFFFFFFF
416#define MAX_FILER_IDX 0xFF
417
418/* This default RIR value directly corresponds
419 * to the 3-bit hash value generated */
420#define DEFAULT_8RXQ_RIR0 0x05397700
421/* Map even hash values to Q0, and odd ones to Q1 */
422#define DEFAULT_2RXQ_RIR0 0x04104100
423
424/* RQFCR register bits */
425#define RQFCR_GPI 0x80000000
426#define RQFCR_HASHTBL_Q 0x00000000
427#define RQFCR_HASHTBL_0 0x00020000
428#define RQFCR_HASHTBL_1 0x00040000
429#define RQFCR_HASHTBL_2 0x00060000
430#define RQFCR_HASHTBL_3 0x00080000
431#define RQFCR_HASH 0x00010000
432#define RQFCR_QUEUE 0x0000FC00
433#define RQFCR_CLE 0x00000200
434#define RQFCR_RJE 0x00000100
435#define RQFCR_AND 0x00000080
436#define RQFCR_CMP_EXACT 0x00000000
437#define RQFCR_CMP_MATCH 0x00000020
438#define RQFCR_CMP_NOEXACT 0x00000040
439#define RQFCR_CMP_NOMATCH 0x00000060
440
441/* RQFCR PID values */
442#define RQFCR_PID_MASK 0x00000000
443#define RQFCR_PID_PARSE 0x00000001
444#define RQFCR_PID_ARB 0x00000002
445#define RQFCR_PID_DAH 0x00000003
446#define RQFCR_PID_DAL 0x00000004
447#define RQFCR_PID_SAH 0x00000005
448#define RQFCR_PID_SAL 0x00000006
449#define RQFCR_PID_ETY 0x00000007
450#define RQFCR_PID_VID 0x00000008
451#define RQFCR_PID_PRI 0x00000009
452#define RQFCR_PID_TOS 0x0000000A
453#define RQFCR_PID_L4P 0x0000000B
454#define RQFCR_PID_DIA 0x0000000C
455#define RQFCR_PID_SIA 0x0000000D
456#define RQFCR_PID_DPT 0x0000000E
457#define RQFCR_PID_SPT 0x0000000F
458
459/* RQFPR when PID is 0x0001 */
460#define RQFPR_HDR_GE_512 0x00200000
461#define RQFPR_LERR 0x00100000
462#define RQFPR_RAR 0x00080000
463#define RQFPR_RARQ 0x00040000
464#define RQFPR_AR 0x00020000
465#define RQFPR_ARQ 0x00010000
466#define RQFPR_EBC 0x00008000
467#define RQFPR_VLN 0x00004000
468#define RQFPR_CFI 0x00002000
469#define RQFPR_JUM 0x00001000
470#define RQFPR_IPF 0x00000800
471#define RQFPR_FIF 0x00000400
472#define RQFPR_IPV4 0x00000200
473#define RQFPR_IPV6 0x00000100
474#define RQFPR_ICC 0x00000080
475#define RQFPR_ICV 0x00000040
476#define RQFPR_TCP 0x00000020
477#define RQFPR_UDP 0x00000010
478#define RQFPR_TUC 0x00000008
479#define RQFPR_TUV 0x00000004
480#define RQFPR_PER 0x00000002
481#define RQFPR_EER 0x00000001
482
483/* TxBD status field bits */
484#define TXBD_READY 0x8000
485#define TXBD_PADCRC 0x4000
486#define TXBD_WRAP 0x2000
487#define TXBD_INTERRUPT 0x1000
488#define TXBD_LAST 0x0800
489#define TXBD_CRC 0x0400
490#define TXBD_DEF 0x0200
491#define TXBD_HUGEFRAME 0x0080
492#define TXBD_LATECOLLISION 0x0080
493#define TXBD_RETRYLIMIT 0x0040
494#define TXBD_RETRYCOUNTMASK 0x003c
495#define TXBD_UNDERRUN 0x0002
496#define TXBD_TOE 0x0002
497
498/* Tx FCB param bits */
499#define TXFCB_VLN 0x80
500#define TXFCB_IP 0x40
501#define TXFCB_IP6 0x20
502#define TXFCB_TUP 0x10
503#define TXFCB_UDP 0x08
504#define TXFCB_CIP 0x04
505#define TXFCB_CTU 0x02
506#define TXFCB_NPH 0x01
507#define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
508
509/* RxBD status field bits */
510#define RXBD_EMPTY 0x8000
511#define RXBD_RO1 0x4000
512#define RXBD_WRAP 0x2000
513#define RXBD_INTERRUPT 0x1000
514#define RXBD_LAST 0x0800
515#define RXBD_FIRST 0x0400
516#define RXBD_MISS 0x0100
517#define RXBD_BROADCAST 0x0080
518#define RXBD_MULTICAST 0x0040
519#define RXBD_LARGE 0x0020
520#define RXBD_NONOCTET 0x0010
521#define RXBD_SHORT 0x0008
522#define RXBD_CRCERR 0x0004
523#define RXBD_OVERRUN 0x0002
524#define RXBD_TRUNCATED 0x0001
525#define RXBD_STATS 0x01ff
526#define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
527 | RXBD_CRCERR | RXBD_OVERRUN \
528 | RXBD_TRUNCATED)
529
530/* Rx FCB status field bits */
531#define RXFCB_VLN 0x8000
532#define RXFCB_IP 0x4000
533#define RXFCB_IP6 0x2000
534#define RXFCB_TUP 0x1000
535#define RXFCB_CIP 0x0800
536#define RXFCB_CTU 0x0400
537#define RXFCB_EIP 0x0200
538#define RXFCB_ETU 0x0100
539#define RXFCB_CSUM_MASK 0x0f00
540#define RXFCB_PERR_MASK 0x000c
541#define RXFCB_PERR_BADL3 0x0008
542
543#define GFAR_INT_NAME_MAX (IFNAMSIZ + 6) /* '_g#_xx' */
544
545#define GFAR_WOL_MAGIC 0x00000001
546#define GFAR_WOL_FILER_UCAST 0x00000002
547
548struct txbd8
549{
550 union {
551 struct {
552 __be16 status; /* Status Fields */
553 __be16 length; /* Buffer length */
554 };
555 __be32 lstatus;
556 };
557 __be32 bufPtr; /* Buffer Pointer */
558};
559
560struct txfcb {
561 u8 flags;
562 u8 ptp; /* Flag to enable tx timestamping */
563 u8 l4os; /* Level 4 Header Offset */
564 u8 l3os; /* Level 3 Header Offset */
565 __be16 phcs; /* Pseudo-header Checksum */
566 __be16 vlctl; /* VLAN control word */
567};
568
569struct rxbd8
570{
571 union {
572 struct {
573 __be16 status; /* Status Fields */
574 __be16 length; /* Buffer Length */
575 };
576 __be32 lstatus;
577 };
578 __be32 bufPtr; /* Buffer Pointer */
579};
580
581struct rxfcb {
582 __be16 flags;
583 u8 rq; /* Receive Queue index */
584 u8 pro; /* Layer 4 Protocol */
585 u16 reserved;
586 __be16 vlctl; /* VLAN control word */
587};
588
589struct gianfar_skb_cb {
590 unsigned int bytes_sent; /* bytes-on-wire (i.e. no FCB) */
591};
592
593#define GFAR_CB(skb) ((struct gianfar_skb_cb *)((skb)->cb))
594
595struct rmon_mib
596{
597 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
598 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
599 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
600 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
601 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
602 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
603 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
604 u32 rbyt; /* 0x.69c - Receive Byte Counter */
605 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
606 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
607 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
608 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
609 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
610 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
611 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
612 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
613 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
614 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
615 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
616 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
617 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
618 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
619 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
620 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
621 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
622 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
623 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
624 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
625 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
626 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
627 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
628 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
629 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
630 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
631 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
632 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
633 u8 res1[4];
634 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
635 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
636 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
637 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
638 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
639 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
640 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
641 u32 car1; /* 0x.730 - Carry Register One */
642 u32 car2; /* 0x.734 - Carry Register Two */
643 u32 cam1; /* 0x.738 - Carry Mask Register One */
644 u32 cam2; /* 0x.73c - Carry Mask Register Two */
645};
646
647struct gfar_extra_stats {
648 atomic64_t rx_alloc_err;
649 atomic64_t rx_large;
650 atomic64_t rx_short;
651 atomic64_t rx_nonoctet;
652 atomic64_t rx_crcerr;
653 atomic64_t rx_overrun;
654 atomic64_t rx_bsy;
655 atomic64_t rx_babr;
656 atomic64_t rx_trunc;
657 atomic64_t eberr;
658 atomic64_t tx_babt;
659 atomic64_t tx_underrun;
660 atomic64_t tx_timeout;
661};
662
663#define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
664#define GFAR_EXTRA_STATS_LEN \
665 (sizeof(struct gfar_extra_stats)/sizeof(atomic64_t))
666
667/* Number of stats exported via ethtool */
668#define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
669
670struct gfar {
671 u32 tsec_id; /* 0x.000 - Controller ID register */
672 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
673 u8 res1[8];
674 u32 ievent; /* 0x.010 - Interrupt Event Register */
675 u32 imask; /* 0x.014 - Interrupt Mask Register */
676 u32 edis; /* 0x.018 - Error Disabled Register */
677 u32 emapg; /* 0x.01c - Group Error mapping register */
678 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
679 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
680 u32 ptv; /* 0x.028 - Pause Time Value Register */
681 u32 dmactrl; /* 0x.02c - DMA Control Register */
682 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
683 u8 res2[28];
684 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
685 register */
686 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
687 register */
688 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
689 register */
690 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
691 shutoff register */
692 u8 res3[44];
693 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
694 u8 res4[8];
695 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
696 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
697 u8 res5[96];
698 u32 tctrl; /* 0x.100 - Transmit Control Register */
699 u32 tstat; /* 0x.104 - Transmit Status Register */
700 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
701 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
702 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
703 u32 tqueue; /* 0x.114 - Transmit queue control register */
704 u8 res7[40];
705 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
706 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
707 u8 res8[52];
708 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
709 u8 res9a[4];
710 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
711 u8 res9b[4];
712 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
713 u8 res9c[4];
714 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
715 u8 res9d[4];
716 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
717 u8 res9e[4];
718 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
719 u8 res9f[4];
720 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
721 u8 res9g[4];
722 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
723 u8 res9h[4];
724 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
725 u8 res9[64];
726 u32 tbaseh; /* 0x.200 - TxBD base address high */
727 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
728 u8 res10a[4];
729 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
730 u8 res10b[4];
731 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
732 u8 res10c[4];
733 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
734 u8 res10d[4];
735 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
736 u8 res10e[4];
737 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
738 u8 res10f[4];
739 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
740 u8 res10g[4];
741 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
742 u8 res10[192];
743 u32 rctrl; /* 0x.300 - Receive Control Register */
744 u32 rstat; /* 0x.304 - Receive Status Register */
745 u8 res12[8];
746 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
747 u32 rqueue; /* 0x.314 - Receive queue control register */
748 u32 rir0; /* 0x.318 - Ring mapping register 0 */
749 u32 rir1; /* 0x.31c - Ring mapping register 1 */
750 u32 rir2; /* 0x.320 - Ring mapping register 2 */
751 u32 rir3; /* 0x.324 - Ring mapping register 3 */
752 u8 res13[8];
753 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
754 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
755 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
756 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
757 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
758 u8 res14[56];
759 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
760 u8 res15a[4];
761 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
762 u8 res15b[4];
763 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
764 u8 res15c[4];
765 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
766 u8 res15d[4];
767 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
768 u8 res15e[4];
769 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
770 u8 res15f[4];
771 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
772 u8 res15g[4];
773 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
774 u8 res15h[4];
775 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
776 u8 res16[64];
777 u32 rbaseh; /* 0x.400 - RxBD base address high */
778 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
779 u8 res17a[4];
780 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
781 u8 res17b[4];
782 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
783 u8 res17c[4];
784 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
785 u8 res17d[4];
786 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
787 u8 res17e[4];
788 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
789 u8 res17f[4];
790 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
791 u8 res17g[4];
792 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
793 u8 res17[192];
794 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
795 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
796 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
797 u32 hafdup; /* 0x.50c - Half Duplex Register */
798 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
799 u8 res18[12];
800 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
801 u32 ifctrl; /* 0x.538 - Interface control register */
802 u32 ifstat; /* 0x.53c - Interface Status Register */
803 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
804 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
805 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
806 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
807 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
808 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
809 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
810 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
811 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
812 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
813 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
814 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
815 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
816 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
817 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
818 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
819 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
820 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
821 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
822 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
823 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
824 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
825 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
826 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
827 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
828 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
829 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
830 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
831 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
832 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
833 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
834 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
835 u8 res20[192];
836 struct rmon_mib rmon; /* 0x.680-0x.73c */
837 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
838 u8 res21[188];
839 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
840 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
841 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
842 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
843 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
844 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
845 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
846 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
847 u8 res22[96];
848 u32 gaddr0; /* 0x.880 - Group address register 0 */
849 u32 gaddr1; /* 0x.884 - Group address register 1 */
850 u32 gaddr2; /* 0x.888 - Group address register 2 */
851 u32 gaddr3; /* 0x.88c - Group address register 3 */
852 u32 gaddr4; /* 0x.890 - Group address register 4 */
853 u32 gaddr5; /* 0x.894 - Group address register 5 */
854 u32 gaddr6; /* 0x.898 - Group address register 6 */
855 u32 gaddr7; /* 0x.89c - Group address register 7 */
856 u8 res23a[352];
857 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
858 u8 res23b[252];
859 u8 res23c[248];
860 u32 attr; /* 0x.bf8 - Attributes Register */
861 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
862 u32 rqprm0; /* 0x.c00 - Receive queue parameters register 0 */
863 u32 rqprm1; /* 0x.c04 - Receive queue parameters register 1 */
864 u32 rqprm2; /* 0x.c08 - Receive queue parameters register 2 */
865 u32 rqprm3; /* 0x.c0c - Receive queue parameters register 3 */
866 u32 rqprm4; /* 0x.c10 - Receive queue parameters register 4 */
867 u32 rqprm5; /* 0x.c14 - Receive queue parameters register 5 */
868 u32 rqprm6; /* 0x.c18 - Receive queue parameters register 6 */
869 u32 rqprm7; /* 0x.c1c - Receive queue parameters register 7 */
870 u8 res24[36];
871 u32 rfbptr0; /* 0x.c44 - Last free RxBD pointer for ring 0 */
872 u8 res24a[4];
873 u32 rfbptr1; /* 0x.c4c - Last free RxBD pointer for ring 1 */
874 u8 res24b[4];
875 u32 rfbptr2; /* 0x.c54 - Last free RxBD pointer for ring 2 */
876 u8 res24c[4];
877 u32 rfbptr3; /* 0x.c5c - Last free RxBD pointer for ring 3 */
878 u8 res24d[4];
879 u32 rfbptr4; /* 0x.c64 - Last free RxBD pointer for ring 4 */
880 u8 res24e[4];
881 u32 rfbptr5; /* 0x.c6c - Last free RxBD pointer for ring 5 */
882 u8 res24f[4];
883 u32 rfbptr6; /* 0x.c74 - Last free RxBD pointer for ring 6 */
884 u8 res24g[4];
885 u32 rfbptr7; /* 0x.c7c - Last free RxBD pointer for ring 7 */
886 u8 res24h[4];
887 u8 res24x[556];
888 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
889 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
890 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
891 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
892 u8 res25[16];
893 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
894 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
895 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
896 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
897 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
898 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
899 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
900 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
901 u8 res26[32];
902 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
903 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
904 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
905 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
906 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
907 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
908 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
909 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
910 u8 res27[208];
911};
912
913/* Flags related to gianfar device features */
914#define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
915#define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
916#define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
917#define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
918#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
919#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
920#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
921#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
922#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
923#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
924#define FSL_GIANFAR_DEV_HAS_TIMER 0x00000800
925#define FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER 0x00001000
926#define FSL_GIANFAR_DEV_HAS_RX_FILER 0x00002000
927
928#if (MAXGROUPS == 2)
929#define DEFAULT_MAPPING 0xAA
930#else
931#define DEFAULT_MAPPING 0xFF
932#endif
933
934#define ISRG_RR0 0x80000000
935#define ISRG_TR0 0x00800000
936
937/* The same driver can operate in two modes */
938/* SQ_SG_MODE: Single Queue Single Group Mode
939 * (Backward compatible mode)
940 * MQ_MG_MODE: Multi Queue Multi Group mode
941 */
942enum {
943 SQ_SG_MODE = 0,
944 MQ_MG_MODE
945};
946
947/* GFAR_SQ_POLLING: Single Queue NAPI polling mode
948 * The driver supports a single pair of RX/Tx queues
949 * per interrupt group (Rx/Tx int line). MQ_MG mode
950 * devices have 2 interrupt groups, so the device will
951 * have a total of 2 Tx and 2 Rx queues in this case.
952 * GFAR_MQ_POLLING: Multi Queue NAPI polling mode
953 * The driver supports all the 8 Rx and Tx HW queues
954 * each queue mapped by the Device Tree to one of
955 * the 2 interrupt groups. This mode implies significant
956 * processing overhead (CPU and controller level).
957 */
958enum gfar_poll_mode {
959 GFAR_SQ_POLLING = 0,
960 GFAR_MQ_POLLING
961};
962
963/*
964 * Per TX queue stats
965 */
966struct tx_q_stats {
967 unsigned long tx_packets;
968 unsigned long tx_bytes;
969};
970
971/**
972 * struct gfar_priv_tx_q - per tx queue structure
973 * @txlock: per queue tx spin lock
974 * @tx_skbuff:skb pointers
975 * @skb_curtx: to be used skb pointer
976 * @skb_dirtytx:the last used skb pointer
977 * @stats: bytes/packets stats
978 * @qindex: index of this queue
979 * @dev: back pointer to the dev structure
980 * @grp: back pointer to the group to which this queue belongs
981 * @tx_bd_base: First tx buffer descriptor
982 * @cur_tx: Next free ring entry
983 * @dirty_tx: First buffer in line to be transmitted
984 * @tx_ring_size: Tx ring size
985 * @num_txbdfree: number of free TxBds
986 * @txcoalescing: enable/disable tx coalescing
987 * @txic: transmit interrupt coalescing value
988 * @txcount: coalescing value if based on tx frame count
989 * @txtime: coalescing value if based on time
990 */
991struct gfar_priv_tx_q {
992 /* cacheline 1 */
993 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
994 struct txbd8 *tx_bd_base;
995 struct txbd8 *cur_tx;
996 unsigned int num_txbdfree;
997 unsigned short skb_curtx;
998 unsigned short tx_ring_size;
999 struct tx_q_stats stats;
1000 struct gfar_priv_grp *grp;
1001 /* cacheline 2 */
1002 struct net_device *dev;
1003 struct sk_buff **tx_skbuff;
1004 struct txbd8 *dirty_tx;
1005 unsigned short skb_dirtytx;
1006 unsigned short qindex;
1007 /* Configuration info for the coalescing features */
1008 unsigned int txcoalescing;
1009 unsigned long txic;
1010 dma_addr_t tx_bd_dma_base;
1011};
1012
1013/*
1014 * Per RX queue stats
1015 */
1016struct rx_q_stats {
1017 unsigned long rx_packets;
1018 unsigned long rx_bytes;
1019 unsigned long rx_dropped;
1020};
1021
1022struct gfar_rx_buff {
1023 dma_addr_t dma;
1024 struct page *page;
1025 unsigned int page_offset;
1026};
1027
1028/**
1029 * struct gfar_priv_rx_q - per rx queue structure
1030 * @rx_buff: Array of buffer info metadata structs
1031 * @rx_bd_base: First rx buffer descriptor
1032 * @next_to_use: index of the next buffer to be alloc'd
1033 * @next_to_clean: index of the next buffer to be cleaned
1034 * @qindex: index of this queue
1035 * @ndev: back pointer to net_device
1036 * @rx_ring_size: Rx ring size
1037 * @rxcoalescing: enable/disable rx-coalescing
1038 * @rxic: receive interrupt coalescing vlaue
1039 */
1040
1041struct gfar_priv_rx_q {
1042 struct gfar_rx_buff *rx_buff __aligned(SMP_CACHE_BYTES);
1043 struct rxbd8 *rx_bd_base;
1044 struct net_device *ndev;
1045 struct device *dev;
1046 u16 rx_ring_size;
1047 u16 qindex;
1048 struct gfar_priv_grp *grp;
1049 u16 next_to_clean;
1050 u16 next_to_use;
1051 u16 next_to_alloc;
1052 struct sk_buff *skb;
1053 struct rx_q_stats stats;
1054 u32 __iomem *rfbptr;
1055 unsigned char rxcoalescing;
1056 unsigned long rxic;
1057 dma_addr_t rx_bd_dma_base;
1058};
1059
1060enum gfar_irqinfo_id {
1061 GFAR_TX = 0,
1062 GFAR_RX = 1,
1063 GFAR_ER = 2,
1064 GFAR_NUM_IRQS = 3
1065};
1066
1067struct gfar_irqinfo {
1068 unsigned int irq;
1069 char name[GFAR_INT_NAME_MAX];
1070};
1071
1072/**
1073 * struct gfar_priv_grp - per group structure
1074 * @napi: the napi poll function
1075 * @priv: back pointer to the priv structure
1076 * @regs: the ioremapped register space for this group
1077 * @irqinfo: TX/RX/ER irq data for this group
1078 */
1079
1080struct gfar_priv_grp {
1081 spinlock_t grplock __aligned(SMP_CACHE_BYTES);
1082 struct napi_struct napi_rx;
1083 struct napi_struct napi_tx;
1084 struct gfar __iomem *regs;
1085 struct gfar_priv_tx_q *tx_queue;
1086 struct gfar_priv_rx_q *rx_queue;
1087 unsigned int tstat;
1088 unsigned int rstat;
1089
1090 struct gfar_private *priv;
1091 unsigned long num_tx_queues;
1092 unsigned long tx_bit_map;
1093 unsigned long num_rx_queues;
1094 unsigned long rx_bit_map;
1095
1096 struct gfar_irqinfo *irqinfo[GFAR_NUM_IRQS];
1097};
1098
1099#define gfar_irq(grp, ID) \
1100 ((grp)->irqinfo[GFAR_##ID])
1101
1102enum gfar_errata {
1103 GFAR_ERRATA_74 = 0x01,
1104 GFAR_ERRATA_76 = 0x02,
1105 GFAR_ERRATA_A002 = 0x04,
1106 GFAR_ERRATA_12 = 0x08, /* a.k.a errata eTSEC49 */
1107};
1108
1109enum gfar_dev_state {
1110 GFAR_DOWN = 1,
1111 GFAR_RESETTING
1112};
1113
1114/* Struct stolen almost completely (and shamelessly) from the FCC enet source
1115 * (Ok, that's not so true anymore, but there is a family resemblance)
1116 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
1117 * and tx_bd_base always point to the currently available buffer.
1118 * The dirty_tx tracks the current buffer that is being sent by the
1119 * controller. The cur_tx and dirty_tx are equal under both completely
1120 * empty and completely full conditions. The empty/ready indicator in
1121 * the buffer descriptor determines the actual condition.
1122 */
1123struct gfar_private {
1124 struct device *dev;
1125 struct net_device *ndev;
1126 enum gfar_errata errata;
1127
1128 u16 uses_rxfcb;
1129 u16 padding;
1130 u32 device_flags;
1131
1132 /* HW time stamping enabled flag */
1133 int hwts_rx_en;
1134 int hwts_tx_en;
1135
1136 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
1137 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
1138 struct gfar_priv_grp gfargrp[MAXGROUPS];
1139
1140 unsigned long state;
1141
1142 unsigned short mode;
1143 unsigned short poll_mode;
1144 unsigned int num_tx_queues;
1145 unsigned int num_rx_queues;
1146 unsigned int num_grps;
1147 int tx_actual_en;
1148
1149 /* Network Statistics */
1150 struct gfar_extra_stats extra_stats;
1151
1152 /* PHY stuff */
1153 phy_interface_t interface;
1154 struct device_node *phy_node;
1155 struct device_node *tbi_node;
1156 struct phy_device *phydev;
1157 struct mii_bus *mii_bus;
1158 int oldspeed;
1159 int oldduplex;
1160 int oldlink;
1161
1162 uint32_t msg_enable;
1163
1164 struct work_struct reset_task;
1165
1166 struct platform_device *ofdev;
1167 unsigned char
1168 extended_hash:1,
1169 bd_stash_en:1,
1170 rx_filer_enable:1,
1171 /* Enable priorty based Tx scheduling in Hw */
1172 prio_sched_en:1,
1173 /* Flow control flags */
1174 pause_aneg_en:1,
1175 tx_pause_en:1,
1176 rx_pause_en:1;
1177
1178 /* The total tx and rx ring size for the enabled queues */
1179 unsigned int total_tx_ring_size;
1180 unsigned int total_rx_ring_size;
1181
1182 u32 rqueue;
1183 u32 tqueue;
1184
1185 /* RX per device parameters */
1186 unsigned int rx_stash_size;
1187 unsigned int rx_stash_index;
1188
1189 u32 cur_filer_idx;
1190
1191 /* RX queue filer rule set*/
1192 struct ethtool_rx_list rx_list;
1193 struct mutex rx_queue_access;
1194
1195 /* Hash registers and their width */
1196 u32 __iomem *hash_regs[16];
1197 int hash_width;
1198
1199 /* wake-on-lan settings */
1200 u16 wol_opts;
1201 u16 wol_supported;
1202
1203 /*Filer table*/
1204 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1205 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
1206};
1207
1208
1209static inline int gfar_has_errata(struct gfar_private *priv,
1210 enum gfar_errata err)
1211{
1212 return priv->errata & err;
1213}
1214
1215static inline u32 gfar_read(unsigned __iomem *addr)
1216{
1217 u32 val;
1218 val = ioread32be(addr);
1219 return val;
1220}
1221
1222static inline void gfar_write(unsigned __iomem *addr, u32 val)
1223{
1224 iowrite32be(val, addr);
1225}
1226
1227static inline void gfar_write_filer(struct gfar_private *priv,
1228 unsigned int far, unsigned int fcr, unsigned int fpr)
1229{
1230 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1231
1232 gfar_write(®s->rqfar, far);
1233 gfar_write(®s->rqfcr, fcr);
1234 gfar_write(®s->rqfpr, fpr);
1235}
1236
1237static inline void gfar_read_filer(struct gfar_private *priv,
1238 unsigned int far, unsigned int *fcr, unsigned int *fpr)
1239{
1240 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1241
1242 gfar_write(®s->rqfar, far);
1243 *fcr = gfar_read(®s->rqfcr);
1244 *fpr = gfar_read(®s->rqfpr);
1245}
1246
1247static inline void gfar_write_isrg(struct gfar_private *priv)
1248{
1249 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1250 u32 __iomem *baddr = ®s->isrg0;
1251 u32 isrg = 0;
1252 int grp_idx, i;
1253
1254 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1255 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1256
1257 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1258 isrg |= (ISRG_RR0 >> i);
1259 }
1260
1261 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1262 isrg |= (ISRG_TR0 >> i);
1263 }
1264
1265 gfar_write(baddr, isrg);
1266
1267 baddr++;
1268 isrg = 0;
1269 }
1270}
1271
1272static inline int gfar_is_dma_stopped(struct gfar_private *priv)
1273{
1274 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1275
1276 return ((gfar_read(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC)) ==
1277 (IEVENT_GRSC | IEVENT_GTSC));
1278}
1279
1280static inline int gfar_is_rx_dma_stopped(struct gfar_private *priv)
1281{
1282 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1283
1284 return gfar_read(®s->ievent) & IEVENT_GRSC;
1285}
1286
1287static inline void gfar_wmb(void)
1288{
1289#if defined(CONFIG_PPC)
1290 /* The powerpc-specific eieio() is used, as wmb() has too strong
1291 * semantics (it requires synchronization between cacheable and
1292 * uncacheable mappings, which eieio() doesn't provide and which we
1293 * don't need), thus requiring a more expensive sync instruction. At
1294 * some point, the set of architecture-independent barrier functions
1295 * should be expanded to include weaker barriers.
1296 */
1297 eieio();
1298#else
1299 wmb(); /* order write acesses for BD (or FCB) fields */
1300#endif
1301}
1302
1303static inline void gfar_clear_txbd_status(struct txbd8 *bdp)
1304{
1305 u32 lstatus = be32_to_cpu(bdp->lstatus);
1306
1307 lstatus &= BD_LFLAG(TXBD_WRAP);
1308 bdp->lstatus = cpu_to_be32(lstatus);
1309}
1310
1311static inline int gfar_rxbd_unused(struct gfar_priv_rx_q *rxq)
1312{
1313 if (rxq->next_to_clean > rxq->next_to_use)
1314 return rxq->next_to_clean - rxq->next_to_use - 1;
1315
1316 return rxq->rx_ring_size + rxq->next_to_clean - rxq->next_to_use - 1;
1317}
1318
1319static inline u32 gfar_rxbd_dma_lastfree(struct gfar_priv_rx_q *rxq)
1320{
1321 struct rxbd8 *bdp;
1322 u32 bdp_dma;
1323 int i;
1324
1325 i = rxq->next_to_use ? rxq->next_to_use - 1 : rxq->rx_ring_size - 1;
1326 bdp = &rxq->rx_bd_base[i];
1327 bdp_dma = lower_32_bits(rxq->rx_bd_dma_base);
1328 bdp_dma += (uintptr_t)bdp - (uintptr_t)rxq->rx_bd_base;
1329
1330 return bdp_dma;
1331}
1332
1333irqreturn_t gfar_receive(int irq, void *dev_id);
1334int startup_gfar(struct net_device *dev);
1335void stop_gfar(struct net_device *dev);
1336void reset_gfar(struct net_device *dev);
1337void gfar_mac_reset(struct gfar_private *priv);
1338void gfar_halt(struct gfar_private *priv);
1339void gfar_start(struct gfar_private *priv);
1340void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1341 u32 regnum, u32 read);
1342void gfar_configure_coalescing_all(struct gfar_private *priv);
1343int gfar_set_features(struct net_device *dev, netdev_features_t features);
1344
1345extern const struct ethtool_ops gfar_ethtool_ops;
1346
1347#define MAX_FILER_CACHE_IDX (2*(MAX_FILER_IDX))
1348
1349#define RQFCR_PID_PRI_MASK 0xFFFFFFF8
1350#define RQFCR_PID_L4P_MASK 0xFFFFFF00
1351#define RQFCR_PID_VID_MASK 0xFFFFF000
1352#define RQFCR_PID_PORT_MASK 0xFFFF0000
1353#define RQFCR_PID_MAC_MASK 0xFF000000
1354
1355struct gfar_mask_entry {
1356 unsigned int mask; /* The mask value which is valid form start to end */
1357 unsigned int start;
1358 unsigned int end;
1359 unsigned int block; /* Same block values indicate depended entries */
1360};
1361
1362/* Represents a receive filer table entry */
1363struct gfar_filer_entry {
1364 u32 ctrl;
1365 u32 prop;
1366};
1367
1368
1369/* The 20 additional entries are a shadow for one extra element */
1370struct filer_table {
1371 u32 index;
1372 struct gfar_filer_entry fe[MAX_FILER_CACHE_IDX + 20];
1373};
1374
1375/* The gianfar_ptp module will set this variable */
1376extern int gfar_phc_index;
1377
1378#endif /* __GIANFAR_H */