1/*
  2 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
  3 *
  4 * Registers and bits definitions of ARC EMAC
  5 */
  6
  7#ifndef ARC_EMAC_H
  8#define ARC_EMAC_H
  9
 10#include <linux/device.h>
 11#include <linux/dma-mapping.h>
 12#include <linux/netdevice.h>
 13#include <linux/phy.h>
 14#include <linux/clk.h>
 15
 16/* STATUS and ENABLE Register bit masks */
 17#define TXINT_MASK	(1 << 0)	/* Transmit interrupt */
 18#define RXINT_MASK	(1 << 1)	/* Receive interrupt */
 19#define ERR_MASK	(1 << 2)	/* Error interrupt */
 20#define TXCH_MASK	(1 << 3)	/* Transmit chaining error interrupt */
 21#define MSER_MASK	(1 << 4)	/* Missed packet counter error */
 22#define RXCR_MASK	(1 << 8)	/* RXCRCERR counter rolled over  */
 23#define RXFR_MASK	(1 << 9)	/* RXFRAMEERR counter rolled over */
 24#define RXFL_MASK	(1 << 10)	/* RXOFLOWERR counter rolled over */
 25#define MDIO_MASK	(1 << 12)	/* MDIO complete interrupt */
 26#define TXPL_MASK	(1 << 31)	/* Force polling of BD by EMAC */
 27
 28/* CONTROL Register bit masks */
 29#define EN_MASK		(1 << 0)	/* VMAC enable */
 30#define TXRN_MASK	(1 << 3)	/* TX enable */
 31#define RXRN_MASK	(1 << 4)	/* RX enable */
 32#define DSBC_MASK	(1 << 8)	/* Disable receive broadcast */
 33#define ENFL_MASK	(1 << 10)	/* Enable Full-duplex */
 34#define PROM_MASK	(1 << 11)	/* Promiscuous mode */
 35
 36/* Buffer descriptor INFO bit masks */
 37#define OWN_MASK	(1 << 31)	/* 0-CPU or 1-EMAC owns buffer */
 38#define FIRST_MASK	(1 << 16)	/* First buffer in chain */
 39#define LAST_MASK	(1 << 17)	/* Last buffer in chain */
 40#define LEN_MASK	0x000007FF	/* last 11 bits */
 41#define CRLS		(1 << 21)
 42#define DEFR		(1 << 22)
 43#define DROP		(1 << 23)
 44#define RTRY		(1 << 24)
 45#define LTCL		(1 << 28)
 46#define UFLO		(1 << 29)
 47
 48#define FOR_EMAC	OWN_MASK
 49#define FOR_CPU		0
 50
 51/* ARC EMAC register set combines entries for MAC and MDIO */
 52enum {
 53	R_ID = 0,
 54	R_STATUS,
 55	R_ENABLE,
 56	R_CTRL,
 57	R_POLLRATE,
 58	R_RXERR,
 59	R_MISS,
 60	R_TX_RING,
 61	R_RX_RING,
 62	R_ADDRL,
 63	R_ADDRH,
 64	R_LAFL,
 65	R_LAFH,
 66	R_MDIO,
 67};
 68
 69#define TX_TIMEOUT		(400 * HZ / 1000) /* Transmission timeout */
 70
 71#define ARC_EMAC_NAPI_WEIGHT	40		/* Workload for NAPI */
 72
 73#define EMAC_BUFFER_SIZE	1536		/* EMAC buffer size */
 74
 75/**
 76 * struct arc_emac_bd - EMAC buffer descriptor (BD).
 77 *
 78 * @info:	Contains status information on the buffer itself.
 79 * @data:	32-bit byte addressable pointer to the packet data.
 80 */
 81struct arc_emac_bd {
 82	__le32 info;
 83	dma_addr_t data;
 84};
 85
 86/* Number of Rx/Tx BD's */
 87#define RX_BD_NUM	128
 88#define TX_BD_NUM	128
 89
 90#define RX_RING_SZ	(RX_BD_NUM * sizeof(struct arc_emac_bd))
 91#define TX_RING_SZ	(TX_BD_NUM * sizeof(struct arc_emac_bd))
 92
 93/**
 94 * struct buffer_state - Stores Rx/Tx buffer state.
 95 * @sk_buff:	Pointer to socket buffer.
 96 * @addr:	Start address of DMA-mapped memory region.
 97 * @len:	Length of DMA-mapped memory region.
 98 */
 99struct buffer_state {
100	struct sk_buff *skb;
101	DEFINE_DMA_UNMAP_ADDR(addr);
102	DEFINE_DMA_UNMAP_LEN(len);
103};
104
105struct arc_emac_mdio_bus_data {
106	struct gpio_desc *reset_gpio;
107	int msec;
108};
109
110/**
111 * struct arc_emac_priv - Storage of EMAC's private information.
112 * @dev:	Pointer to the current device.
113 * @phy_dev:	Pointer to attached PHY device.
114 * @bus:	Pointer to the current MII bus.
115 * @regs:	Base address of EMAC memory-mapped control registers.
116 * @napi:	Structure for NAPI.
117 * @rxbd:	Pointer to Rx BD ring.
118 * @txbd:	Pointer to Tx BD ring.
119 * @rxbd_dma:	DMA handle for Rx BD ring.
120 * @txbd_dma:	DMA handle for Tx BD ring.
121 * @rx_buff:	Storage for Rx buffers states.
122 * @tx_buff:	Storage for Tx buffers states.
123 * @txbd_curr:	Index of Tx BD to use on the next "ndo_start_xmit".
124 * @txbd_dirty:	Index of Tx BD to free on the next Tx interrupt.
125 * @last_rx_bd:	Index of the last Rx BD we've got from EMAC.
126 * @link:	PHY's last seen link state.
127 * @duplex:	PHY's last set duplex mode.
128 * @speed:	PHY's last set speed.
129 */
130struct arc_emac_priv {
131	const char *drv_name;
132	const char *drv_version;
133	void (*set_mac_speed)(void *priv, unsigned int speed);
134
135	/* Devices */
136	struct device *dev;
137	struct phy_device *phy_dev;
138	struct mii_bus *bus;
139	struct arc_emac_mdio_bus_data bus_data;
140
141	void __iomem *regs;
142	struct clk *clk;
143
144	struct napi_struct napi;
145
146	struct arc_emac_bd *rxbd;
147	struct arc_emac_bd *txbd;
148
149	dma_addr_t rxbd_dma;
150	dma_addr_t txbd_dma;
151
152	struct buffer_state rx_buff[RX_BD_NUM];
153	struct buffer_state tx_buff[TX_BD_NUM];
154	unsigned int txbd_curr;
155	unsigned int txbd_dirty;
156
157	unsigned int last_rx_bd;
158
159	unsigned int link;
160	unsigned int duplex;
161	unsigned int speed;
162};
163
164/**
165 * arc_reg_set - Sets EMAC register with provided value.
166 * @priv:	Pointer to ARC EMAC private data structure.
167 * @reg:	Register offset from base address.
168 * @value:	Value to set in register.
169 */
170static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
171{
172	iowrite32(value, priv->regs + reg * sizeof(int));
173}
174
175/**
176 * arc_reg_get - Gets value of specified EMAC register.
177 * @priv:	Pointer to ARC EMAC private data structure.
178 * @reg:	Register offset from base address.
179 *
180 * returns:	Value of requested register.
181 */
182static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
183{
184	return ioread32(priv->regs + reg * sizeof(int));
185}
186
187/**
188 * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
189 * @priv:	Pointer to ARC EMAC private data structure.
190 * @reg:	Register offset from base address.
191 * @mask:	Mask to apply to specified register.
192 *
193 * This function reads initial register value, then applies provided mask
194 * to it and then writes register back.
195 */
196static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
197{
198	unsigned int value = arc_reg_get(priv, reg);
199
200	arc_reg_set(priv, reg, value | mask);
201}
202
203/**
204 * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
205 * @priv:	Pointer to ARC EMAC private data structure.
206 * @reg:	Register offset from base address.
207 * @mask:	Mask to apply to specified register.
208 *
209 * This function reads initial register value, then applies provided mask
210 * to it and then writes register back.
211 */
212static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
213{
214	unsigned int value = arc_reg_get(priv, reg);
215
216	arc_reg_set(priv, reg, value & ~mask);
217}
218
219int arc_mdio_probe(struct arc_emac_priv *priv);
220int arc_mdio_remove(struct arc_emac_priv *priv);
221int arc_emac_probe(struct net_device *ndev, int interface);
222int arc_emac_remove(struct net_device *ndev);
223
224#endif /* ARC_EMAC_H */