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1/*
2 *
3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2013-2014, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 */
16
17#include <linux/pci.h>
18#include <linux/jiffies.h>
19#include <linux/ktime.h>
20#include <linux/delay.h>
21#include <linux/kthread.h>
22#include <linux/irqreturn.h>
23
24#include <linux/mei.h>
25
26#include "mei_dev.h"
27#include "hw-txe.h"
28#include "client.h"
29#include "hbm.h"
30
31#include "mei-trace.h"
32
33
34/**
35 * mei_txe_reg_read - Reads 32bit data from the txe device
36 *
37 * @base_addr: registers base address
38 * @offset: register offset
39 *
40 * Return: register value
41 */
42static inline u32 mei_txe_reg_read(void __iomem *base_addr,
43 unsigned long offset)
44{
45 return ioread32(base_addr + offset);
46}
47
48/**
49 * mei_txe_reg_write - Writes 32bit data to the txe device
50 *
51 * @base_addr: registers base address
52 * @offset: register offset
53 * @value: the value to write
54 */
55static inline void mei_txe_reg_write(void __iomem *base_addr,
56 unsigned long offset, u32 value)
57{
58 iowrite32(value, base_addr + offset);
59}
60
61/**
62 * mei_txe_sec_reg_read_silent - Reads 32bit data from the SeC BAR
63 *
64 * @hw: the txe hardware structure
65 * @offset: register offset
66 *
67 * Doesn't check for aliveness while Reads 32bit data from the SeC BAR
68 *
69 * Return: register value
70 */
71static inline u32 mei_txe_sec_reg_read_silent(struct mei_txe_hw *hw,
72 unsigned long offset)
73{
74 return mei_txe_reg_read(hw->mem_addr[SEC_BAR], offset);
75}
76
77/**
78 * mei_txe_sec_reg_read - Reads 32bit data from the SeC BAR
79 *
80 * @hw: the txe hardware structure
81 * @offset: register offset
82 *
83 * Reads 32bit data from the SeC BAR and shout loud if aliveness is not set
84 *
85 * Return: register value
86 */
87static inline u32 mei_txe_sec_reg_read(struct mei_txe_hw *hw,
88 unsigned long offset)
89{
90 WARN(!hw->aliveness, "sec read: aliveness not asserted\n");
91 return mei_txe_sec_reg_read_silent(hw, offset);
92}
93/**
94 * mei_txe_sec_reg_write_silent - Writes 32bit data to the SeC BAR
95 * doesn't check for aliveness
96 *
97 * @hw: the txe hardware structure
98 * @offset: register offset
99 * @value: value to write
100 *
101 * Doesn't check for aliveness while writes 32bit data from to the SeC BAR
102 */
103static inline void mei_txe_sec_reg_write_silent(struct mei_txe_hw *hw,
104 unsigned long offset, u32 value)
105{
106 mei_txe_reg_write(hw->mem_addr[SEC_BAR], offset, value);
107}
108
109/**
110 * mei_txe_sec_reg_write - Writes 32bit data to the SeC BAR
111 *
112 * @hw: the txe hardware structure
113 * @offset: register offset
114 * @value: value to write
115 *
116 * Writes 32bit data from the SeC BAR and shout loud if aliveness is not set
117 */
118static inline void mei_txe_sec_reg_write(struct mei_txe_hw *hw,
119 unsigned long offset, u32 value)
120{
121 WARN(!hw->aliveness, "sec write: aliveness not asserted\n");
122 mei_txe_sec_reg_write_silent(hw, offset, value);
123}
124/**
125 * mei_txe_br_reg_read - Reads 32bit data from the Bridge BAR
126 *
127 * @hw: the txe hardware structure
128 * @offset: offset from which to read the data
129 *
130 * Return: the byte read.
131 */
132static inline u32 mei_txe_br_reg_read(struct mei_txe_hw *hw,
133 unsigned long offset)
134{
135 return mei_txe_reg_read(hw->mem_addr[BRIDGE_BAR], offset);
136}
137
138/**
139 * mei_txe_br_reg_write - Writes 32bit data to the Bridge BAR
140 *
141 * @hw: the txe hardware structure
142 * @offset: offset from which to write the data
143 * @value: the byte to write
144 */
145static inline void mei_txe_br_reg_write(struct mei_txe_hw *hw,
146 unsigned long offset, u32 value)
147{
148 mei_txe_reg_write(hw->mem_addr[BRIDGE_BAR], offset, value);
149}
150
151/**
152 * mei_txe_aliveness_set - request for aliveness change
153 *
154 * @dev: the device structure
155 * @req: requested aliveness value
156 *
157 * Request for aliveness change and returns true if the change is
158 * really needed and false if aliveness is already
159 * in the requested state
160 *
161 * Locking: called under "dev->device_lock" lock
162 *
163 * Return: true if request was send
164 */
165static bool mei_txe_aliveness_set(struct mei_device *dev, u32 req)
166{
167
168 struct mei_txe_hw *hw = to_txe_hw(dev);
169 bool do_req = hw->aliveness != req;
170
171 dev_dbg(dev->dev, "Aliveness current=%d request=%d\n",
172 hw->aliveness, req);
173 if (do_req) {
174 dev->pg_event = MEI_PG_EVENT_WAIT;
175 mei_txe_br_reg_write(hw, SICR_HOST_ALIVENESS_REQ_REG, req);
176 }
177 return do_req;
178}
179
180
181/**
182 * mei_txe_aliveness_req_get - get aliveness requested register value
183 *
184 * @dev: the device structure
185 *
186 * Extract HICR_HOST_ALIVENESS_RESP_ACK bit from
187 * from HICR_HOST_ALIVENESS_REQ register value
188 *
189 * Return: SICR_HOST_ALIVENESS_REQ_REQUESTED bit value
190 */
191static u32 mei_txe_aliveness_req_get(struct mei_device *dev)
192{
193 struct mei_txe_hw *hw = to_txe_hw(dev);
194 u32 reg;
195
196 reg = mei_txe_br_reg_read(hw, SICR_HOST_ALIVENESS_REQ_REG);
197 return reg & SICR_HOST_ALIVENESS_REQ_REQUESTED;
198}
199
200/**
201 * mei_txe_aliveness_get - get aliveness response register value
202 *
203 * @dev: the device structure
204 *
205 * Return: HICR_HOST_ALIVENESS_RESP_ACK bit from HICR_HOST_ALIVENESS_RESP
206 * register
207 */
208static u32 mei_txe_aliveness_get(struct mei_device *dev)
209{
210 struct mei_txe_hw *hw = to_txe_hw(dev);
211 u32 reg;
212
213 reg = mei_txe_br_reg_read(hw, HICR_HOST_ALIVENESS_RESP_REG);
214 return reg & HICR_HOST_ALIVENESS_RESP_ACK;
215}
216
217/**
218 * mei_txe_aliveness_poll - waits for aliveness to settle
219 *
220 * @dev: the device structure
221 * @expected: expected aliveness value
222 *
223 * Polls for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
224 *
225 * Return: 0 if the expected value was received, -ETIME otherwise
226 */
227static int mei_txe_aliveness_poll(struct mei_device *dev, u32 expected)
228{
229 struct mei_txe_hw *hw = to_txe_hw(dev);
230 ktime_t stop, start;
231
232 start = ktime_get();
233 stop = ktime_add(start, ms_to_ktime(SEC_ALIVENESS_WAIT_TIMEOUT));
234 do {
235 hw->aliveness = mei_txe_aliveness_get(dev);
236 if (hw->aliveness == expected) {
237 dev->pg_event = MEI_PG_EVENT_IDLE;
238 dev_dbg(dev->dev, "aliveness settled after %lld usecs\n",
239 ktime_to_us(ktime_sub(ktime_get(), start)));
240 return 0;
241 }
242 usleep_range(20, 50);
243 } while (ktime_before(ktime_get(), stop));
244
245 dev->pg_event = MEI_PG_EVENT_IDLE;
246 dev_err(dev->dev, "aliveness timed out\n");
247 return -ETIME;
248}
249
250/**
251 * mei_txe_aliveness_wait - waits for aliveness to settle
252 *
253 * @dev: the device structure
254 * @expected: expected aliveness value
255 *
256 * Waits for HICR_HOST_ALIVENESS_RESP.ALIVENESS_RESP to be set
257 *
258 * Return: 0 on success and < 0 otherwise
259 */
260static int mei_txe_aliveness_wait(struct mei_device *dev, u32 expected)
261{
262 struct mei_txe_hw *hw = to_txe_hw(dev);
263 const unsigned long timeout =
264 msecs_to_jiffies(SEC_ALIVENESS_WAIT_TIMEOUT);
265 long err;
266 int ret;
267
268 hw->aliveness = mei_txe_aliveness_get(dev);
269 if (hw->aliveness == expected)
270 return 0;
271
272 mutex_unlock(&dev->device_lock);
273 err = wait_event_timeout(hw->wait_aliveness_resp,
274 dev->pg_event == MEI_PG_EVENT_RECEIVED, timeout);
275 mutex_lock(&dev->device_lock);
276
277 hw->aliveness = mei_txe_aliveness_get(dev);
278 ret = hw->aliveness == expected ? 0 : -ETIME;
279
280 if (ret)
281 dev_warn(dev->dev, "aliveness timed out = %ld aliveness = %d event = %d\n",
282 err, hw->aliveness, dev->pg_event);
283 else
284 dev_dbg(dev->dev, "aliveness settled after = %d msec aliveness = %d event = %d\n",
285 jiffies_to_msecs(timeout - err),
286 hw->aliveness, dev->pg_event);
287
288 dev->pg_event = MEI_PG_EVENT_IDLE;
289 return ret;
290}
291
292/**
293 * mei_txe_aliveness_set_sync - sets an wait for aliveness to complete
294 *
295 * @dev: the device structure
296 * @req: requested aliveness value
297 *
298 * Return: 0 on success and < 0 otherwise
299 */
300int mei_txe_aliveness_set_sync(struct mei_device *dev, u32 req)
301{
302 if (mei_txe_aliveness_set(dev, req))
303 return mei_txe_aliveness_wait(dev, req);
304 return 0;
305}
306
307/**
308 * mei_txe_pg_in_transition - is device now in pg transition
309 *
310 * @dev: the device structure
311 *
312 * Return: true if in pg transition, false otherwise
313 */
314static bool mei_txe_pg_in_transition(struct mei_device *dev)
315{
316 return dev->pg_event == MEI_PG_EVENT_WAIT;
317}
318
319/**
320 * mei_txe_pg_is_enabled - detect if PG is supported by HW
321 *
322 * @dev: the device structure
323 *
324 * Return: true is pg supported, false otherwise
325 */
326static bool mei_txe_pg_is_enabled(struct mei_device *dev)
327{
328 return true;
329}
330
331/**
332 * mei_txe_pg_state - translate aliveness register value
333 * to the mei power gating state
334 *
335 * @dev: the device structure
336 *
337 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
338 */
339static inline enum mei_pg_state mei_txe_pg_state(struct mei_device *dev)
340{
341 struct mei_txe_hw *hw = to_txe_hw(dev);
342
343 return hw->aliveness ? MEI_PG_OFF : MEI_PG_ON;
344}
345
346/**
347 * mei_txe_input_ready_interrupt_enable - sets the Input Ready Interrupt
348 *
349 * @dev: the device structure
350 */
351static void mei_txe_input_ready_interrupt_enable(struct mei_device *dev)
352{
353 struct mei_txe_hw *hw = to_txe_hw(dev);
354 u32 hintmsk;
355 /* Enable the SEC_IPC_HOST_INT_MASK_IN_RDY interrupt */
356 hintmsk = mei_txe_sec_reg_read(hw, SEC_IPC_HOST_INT_MASK_REG);
357 hintmsk |= SEC_IPC_HOST_INT_MASK_IN_RDY;
358 mei_txe_sec_reg_write(hw, SEC_IPC_HOST_INT_MASK_REG, hintmsk);
359}
360
361/**
362 * mei_txe_input_doorbell_set - sets bit 0 in
363 * SEC_IPC_INPUT_DOORBELL.IPC_INPUT_DOORBELL.
364 *
365 * @hw: the txe hardware structure
366 */
367static void mei_txe_input_doorbell_set(struct mei_txe_hw *hw)
368{
369 /* Clear the interrupt cause */
370 clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause);
371 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_DOORBELL_REG, 1);
372}
373
374/**
375 * mei_txe_output_ready_set - Sets the SICR_SEC_IPC_OUTPUT_STATUS bit to 1
376 *
377 * @hw: the txe hardware structure
378 */
379static void mei_txe_output_ready_set(struct mei_txe_hw *hw)
380{
381 mei_txe_br_reg_write(hw,
382 SICR_SEC_IPC_OUTPUT_STATUS_REG,
383 SEC_IPC_OUTPUT_STATUS_RDY);
384}
385
386/**
387 * mei_txe_is_input_ready - check if TXE is ready for receiving data
388 *
389 * @dev: the device structure
390 *
391 * Return: true if INPUT STATUS READY bit is set
392 */
393static bool mei_txe_is_input_ready(struct mei_device *dev)
394{
395 struct mei_txe_hw *hw = to_txe_hw(dev);
396 u32 status;
397
398 status = mei_txe_sec_reg_read(hw, SEC_IPC_INPUT_STATUS_REG);
399 return !!(SEC_IPC_INPUT_STATUS_RDY & status);
400}
401
402/**
403 * mei_txe_intr_clear - clear all interrupts
404 *
405 * @dev: the device structure
406 */
407static inline void mei_txe_intr_clear(struct mei_device *dev)
408{
409 struct mei_txe_hw *hw = to_txe_hw(dev);
410
411 mei_txe_sec_reg_write_silent(hw, SEC_IPC_HOST_INT_STATUS_REG,
412 SEC_IPC_HOST_INT_STATUS_PENDING);
413 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_STS_MSK);
414 mei_txe_br_reg_write(hw, HHISR_REG, IPC_HHIER_MSK);
415}
416
417/**
418 * mei_txe_intr_disable - disable all interrupts
419 *
420 * @dev: the device structure
421 */
422static void mei_txe_intr_disable(struct mei_device *dev)
423{
424 struct mei_txe_hw *hw = to_txe_hw(dev);
425
426 mei_txe_br_reg_write(hw, HHIER_REG, 0);
427 mei_txe_br_reg_write(hw, HIER_REG, 0);
428}
429/**
430 * mei_txe_intr_enable - enable all interrupts
431 *
432 * @dev: the device structure
433 */
434static void mei_txe_intr_enable(struct mei_device *dev)
435{
436 struct mei_txe_hw *hw = to_txe_hw(dev);
437
438 mei_txe_br_reg_write(hw, HHIER_REG, IPC_HHIER_MSK);
439 mei_txe_br_reg_write(hw, HIER_REG, HIER_INT_EN_MSK);
440}
441
442/**
443 * mei_txe_pending_interrupts - check if there are pending interrupts
444 * only Aliveness, Input ready, and output doorbell are of relevance
445 *
446 * @dev: the device structure
447 *
448 * Checks if there are pending interrupts
449 * only Aliveness, Readiness, Input ready, and Output doorbell are relevant
450 *
451 * Return: true if there are pending interrupts
452 */
453static bool mei_txe_pending_interrupts(struct mei_device *dev)
454{
455
456 struct mei_txe_hw *hw = to_txe_hw(dev);
457 bool ret = (hw->intr_cause & (TXE_INTR_READINESS |
458 TXE_INTR_ALIVENESS |
459 TXE_INTR_IN_READY |
460 TXE_INTR_OUT_DB));
461
462 if (ret) {
463 dev_dbg(dev->dev,
464 "Pending Interrupts InReady=%01d Readiness=%01d, Aliveness=%01d, OutDoor=%01d\n",
465 !!(hw->intr_cause & TXE_INTR_IN_READY),
466 !!(hw->intr_cause & TXE_INTR_READINESS),
467 !!(hw->intr_cause & TXE_INTR_ALIVENESS),
468 !!(hw->intr_cause & TXE_INTR_OUT_DB));
469 }
470 return ret;
471}
472
473/**
474 * mei_txe_input_payload_write - write a dword to the host buffer
475 * at offset idx
476 *
477 * @dev: the device structure
478 * @idx: index in the host buffer
479 * @value: value
480 */
481static void mei_txe_input_payload_write(struct mei_device *dev,
482 unsigned long idx, u32 value)
483{
484 struct mei_txe_hw *hw = to_txe_hw(dev);
485
486 mei_txe_sec_reg_write(hw, SEC_IPC_INPUT_PAYLOAD_REG +
487 (idx * sizeof(u32)), value);
488}
489
490/**
491 * mei_txe_out_data_read - read dword from the device buffer
492 * at offset idx
493 *
494 * @dev: the device structure
495 * @idx: index in the device buffer
496 *
497 * Return: register value at index
498 */
499static u32 mei_txe_out_data_read(const struct mei_device *dev,
500 unsigned long idx)
501{
502 struct mei_txe_hw *hw = to_txe_hw(dev);
503
504 return mei_txe_br_reg_read(hw,
505 BRIDGE_IPC_OUTPUT_PAYLOAD_REG + (idx * sizeof(u32)));
506}
507
508/* Readiness */
509
510/**
511 * mei_txe_readiness_set_host_rdy - set host readiness bit
512 *
513 * @dev: the device structure
514 */
515static void mei_txe_readiness_set_host_rdy(struct mei_device *dev)
516{
517 struct mei_txe_hw *hw = to_txe_hw(dev);
518
519 mei_txe_br_reg_write(hw,
520 SICR_HOST_IPC_READINESS_REQ_REG,
521 SICR_HOST_IPC_READINESS_HOST_RDY);
522}
523
524/**
525 * mei_txe_readiness_clear - clear host readiness bit
526 *
527 * @dev: the device structure
528 */
529static void mei_txe_readiness_clear(struct mei_device *dev)
530{
531 struct mei_txe_hw *hw = to_txe_hw(dev);
532
533 mei_txe_br_reg_write(hw, SICR_HOST_IPC_READINESS_REQ_REG,
534 SICR_HOST_IPC_READINESS_RDY_CLR);
535}
536/**
537 * mei_txe_readiness_get - Reads and returns
538 * the HICR_SEC_IPC_READINESS register value
539 *
540 * @dev: the device structure
541 *
542 * Return: the HICR_SEC_IPC_READINESS register value
543 */
544static u32 mei_txe_readiness_get(struct mei_device *dev)
545{
546 struct mei_txe_hw *hw = to_txe_hw(dev);
547
548 return mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
549}
550
551
552/**
553 * mei_txe_readiness_is_sec_rdy - check readiness
554 * for HICR_SEC_IPC_READINESS_SEC_RDY
555 *
556 * @readiness: cached readiness state
557 *
558 * Return: true if readiness bit is set
559 */
560static inline bool mei_txe_readiness_is_sec_rdy(u32 readiness)
561{
562 return !!(readiness & HICR_SEC_IPC_READINESS_SEC_RDY);
563}
564
565/**
566 * mei_txe_hw_is_ready - check if the hw is ready
567 *
568 * @dev: the device structure
569 *
570 * Return: true if sec is ready
571 */
572static bool mei_txe_hw_is_ready(struct mei_device *dev)
573{
574 u32 readiness = mei_txe_readiness_get(dev);
575
576 return mei_txe_readiness_is_sec_rdy(readiness);
577}
578
579/**
580 * mei_txe_host_is_ready - check if the host is ready
581 *
582 * @dev: the device structure
583 *
584 * Return: true if host is ready
585 */
586static inline bool mei_txe_host_is_ready(struct mei_device *dev)
587{
588 struct mei_txe_hw *hw = to_txe_hw(dev);
589 u32 reg = mei_txe_br_reg_read(hw, HICR_SEC_IPC_READINESS_REG);
590
591 return !!(reg & HICR_SEC_IPC_READINESS_HOST_RDY);
592}
593
594/**
595 * mei_txe_readiness_wait - wait till readiness settles
596 *
597 * @dev: the device structure
598 *
599 * Return: 0 on success and -ETIME on timeout
600 */
601static int mei_txe_readiness_wait(struct mei_device *dev)
602{
603 if (mei_txe_hw_is_ready(dev))
604 return 0;
605
606 mutex_unlock(&dev->device_lock);
607 wait_event_timeout(dev->wait_hw_ready, dev->recvd_hw_ready,
608 msecs_to_jiffies(SEC_RESET_WAIT_TIMEOUT));
609 mutex_lock(&dev->device_lock);
610 if (!dev->recvd_hw_ready) {
611 dev_err(dev->dev, "wait for readiness failed\n");
612 return -ETIME;
613 }
614
615 dev->recvd_hw_ready = false;
616 return 0;
617}
618
619static const struct mei_fw_status mei_txe_fw_sts = {
620 .count = 2,
621 .status[0] = PCI_CFG_TXE_FW_STS0,
622 .status[1] = PCI_CFG_TXE_FW_STS1
623};
624
625/**
626 * mei_txe_fw_status - read fw status register from pci config space
627 *
628 * @dev: mei device
629 * @fw_status: fw status register values
630 *
631 * Return: 0 on success, error otherwise
632 */
633static int mei_txe_fw_status(struct mei_device *dev,
634 struct mei_fw_status *fw_status)
635{
636 const struct mei_fw_status *fw_src = &mei_txe_fw_sts;
637 struct pci_dev *pdev = to_pci_dev(dev->dev);
638 int ret;
639 int i;
640
641 if (!fw_status)
642 return -EINVAL;
643
644 fw_status->count = fw_src->count;
645 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
646 ret = pci_read_config_dword(pdev, fw_src->status[i],
647 &fw_status->status[i]);
648 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HSF_X",
649 fw_src->status[i],
650 fw_status->status[i]);
651 if (ret)
652 return ret;
653 }
654
655 return 0;
656}
657
658/**
659 * mei_txe_hw_config - configure hardware at the start of the devices
660 *
661 * @dev: the device structure
662 *
663 * Configure hardware at the start of the device should be done only
664 * once at the device probe time
665 */
666static void mei_txe_hw_config(struct mei_device *dev)
667{
668
669 struct mei_txe_hw *hw = to_txe_hw(dev);
670
671 /* Doesn't change in runtime */
672 dev->hbuf_depth = PAYLOAD_SIZE / 4;
673
674 hw->aliveness = mei_txe_aliveness_get(dev);
675 hw->readiness = mei_txe_readiness_get(dev);
676
677 dev_dbg(dev->dev, "aliveness_resp = 0x%08x, readiness = 0x%08x.\n",
678 hw->aliveness, hw->readiness);
679}
680
681
682/**
683 * mei_txe_write - writes a message to device.
684 *
685 * @dev: the device structure
686 * @header: header of message
687 * @buf: message buffer will be written
688 *
689 * Return: 0 if success, <0 - otherwise.
690 */
691
692static int mei_txe_write(struct mei_device *dev,
693 struct mei_msg_hdr *header, unsigned char *buf)
694{
695 struct mei_txe_hw *hw = to_txe_hw(dev);
696 unsigned long rem;
697 unsigned long length;
698 int slots = dev->hbuf_depth;
699 u32 *reg_buf = (u32 *)buf;
700 u32 dw_cnt;
701 int i;
702
703 if (WARN_ON(!header || !buf))
704 return -EINVAL;
705
706 length = header->length;
707
708 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM(header));
709
710 dw_cnt = mei_data2slots(length);
711 if (dw_cnt > slots)
712 return -EMSGSIZE;
713
714 if (WARN(!hw->aliveness, "txe write: aliveness not asserted\n"))
715 return -EAGAIN;
716
717 /* Enable Input Ready Interrupt. */
718 mei_txe_input_ready_interrupt_enable(dev);
719
720 if (!mei_txe_is_input_ready(dev)) {
721 char fw_sts_str[MEI_FW_STATUS_STR_SZ];
722
723 mei_fw_status_str(dev, fw_sts_str, MEI_FW_STATUS_STR_SZ);
724 dev_err(dev->dev, "Input is not ready %s\n", fw_sts_str);
725 return -EAGAIN;
726 }
727
728 mei_txe_input_payload_write(dev, 0, *((u32 *)header));
729
730 for (i = 0; i < length / 4; i++)
731 mei_txe_input_payload_write(dev, i + 1, reg_buf[i]);
732
733 rem = length & 0x3;
734 if (rem > 0) {
735 u32 reg = 0;
736
737 memcpy(®, &buf[length - rem], rem);
738 mei_txe_input_payload_write(dev, i + 1, reg);
739 }
740
741 /* after each write the whole buffer is consumed */
742 hw->slots = 0;
743
744 /* Set Input-Doorbell */
745 mei_txe_input_doorbell_set(hw);
746
747 return 0;
748}
749
750/**
751 * mei_txe_hbuf_max_len - mimics the me hbuf circular buffer
752 *
753 * @dev: the device structure
754 *
755 * Return: the PAYLOAD_SIZE - 4
756 */
757static size_t mei_txe_hbuf_max_len(const struct mei_device *dev)
758{
759 return PAYLOAD_SIZE - sizeof(struct mei_msg_hdr);
760}
761
762/**
763 * mei_txe_hbuf_empty_slots - mimics the me hbuf circular buffer
764 *
765 * @dev: the device structure
766 *
767 * Return: always hbuf_depth
768 */
769static int mei_txe_hbuf_empty_slots(struct mei_device *dev)
770{
771 struct mei_txe_hw *hw = to_txe_hw(dev);
772
773 return hw->slots;
774}
775
776/**
777 * mei_txe_count_full_read_slots - mimics the me device circular buffer
778 *
779 * @dev: the device structure
780 *
781 * Return: always buffer size in dwords count
782 */
783static int mei_txe_count_full_read_slots(struct mei_device *dev)
784{
785 /* read buffers has static size */
786 return PAYLOAD_SIZE / 4;
787}
788
789/**
790 * mei_txe_read_hdr - read message header which is always in 4 first bytes
791 *
792 * @dev: the device structure
793 *
794 * Return: mei message header
795 */
796
797static u32 mei_txe_read_hdr(const struct mei_device *dev)
798{
799 return mei_txe_out_data_read(dev, 0);
800}
801/**
802 * mei_txe_read - reads a message from the txe device.
803 *
804 * @dev: the device structure
805 * @buf: message buffer will be written
806 * @len: message size will be read
807 *
808 * Return: -EINVAL on error wrong argument and 0 on success
809 */
810static int mei_txe_read(struct mei_device *dev,
811 unsigned char *buf, unsigned long len)
812{
813
814 struct mei_txe_hw *hw = to_txe_hw(dev);
815 u32 *reg_buf, reg;
816 u32 rem;
817 u32 i;
818
819 if (WARN_ON(!buf || !len))
820 return -EINVAL;
821
822 reg_buf = (u32 *)buf;
823 rem = len & 0x3;
824
825 dev_dbg(dev->dev, "buffer-length = %lu buf[0]0x%08X\n",
826 len, mei_txe_out_data_read(dev, 0));
827
828 for (i = 0; i < len / 4; i++) {
829 /* skip header: index starts from 1 */
830 reg = mei_txe_out_data_read(dev, i + 1);
831 dev_dbg(dev->dev, "buf[%d] = 0x%08X\n", i, reg);
832 *reg_buf++ = reg;
833 }
834
835 if (rem) {
836 reg = mei_txe_out_data_read(dev, i + 1);
837 memcpy(reg_buf, ®, rem);
838 }
839
840 mei_txe_output_ready_set(hw);
841 return 0;
842}
843
844/**
845 * mei_txe_hw_reset - resets host and fw.
846 *
847 * @dev: the device structure
848 * @intr_enable: if interrupt should be enabled after reset.
849 *
850 * Return: 0 on success and < 0 in case of error
851 */
852static int mei_txe_hw_reset(struct mei_device *dev, bool intr_enable)
853{
854 struct mei_txe_hw *hw = to_txe_hw(dev);
855
856 u32 aliveness_req;
857 /*
858 * read input doorbell to ensure consistency between Bridge and SeC
859 * return value might be garbage return
860 */
861 (void)mei_txe_sec_reg_read_silent(hw, SEC_IPC_INPUT_DOORBELL_REG);
862
863 aliveness_req = mei_txe_aliveness_req_get(dev);
864 hw->aliveness = mei_txe_aliveness_get(dev);
865
866 /* Disable interrupts in this stage we will poll */
867 mei_txe_intr_disable(dev);
868
869 /*
870 * If Aliveness Request and Aliveness Response are not equal then
871 * wait for them to be equal
872 * Since we might have interrupts disabled - poll for it
873 */
874 if (aliveness_req != hw->aliveness)
875 if (mei_txe_aliveness_poll(dev, aliveness_req) < 0) {
876 dev_err(dev->dev, "wait for aliveness settle failed ... bailing out\n");
877 return -EIO;
878 }
879
880 /*
881 * If Aliveness Request and Aliveness Response are set then clear them
882 */
883 if (aliveness_req) {
884 mei_txe_aliveness_set(dev, 0);
885 if (mei_txe_aliveness_poll(dev, 0) < 0) {
886 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
887 return -EIO;
888 }
889 }
890
891 /*
892 * Set readiness RDY_CLR bit
893 */
894 mei_txe_readiness_clear(dev);
895
896 return 0;
897}
898
899/**
900 * mei_txe_hw_start - start the hardware after reset
901 *
902 * @dev: the device structure
903 *
904 * Return: 0 on success an error code otherwise
905 */
906static int mei_txe_hw_start(struct mei_device *dev)
907{
908 struct mei_txe_hw *hw = to_txe_hw(dev);
909 int ret;
910
911 u32 hisr;
912
913 /* bring back interrupts */
914 mei_txe_intr_enable(dev);
915
916 ret = mei_txe_readiness_wait(dev);
917 if (ret < 0) {
918 dev_err(dev->dev, "waiting for readiness failed\n");
919 return ret;
920 }
921
922 /*
923 * If HISR.INT2_STS interrupt status bit is set then clear it.
924 */
925 hisr = mei_txe_br_reg_read(hw, HISR_REG);
926 if (hisr & HISR_INT_2_STS)
927 mei_txe_br_reg_write(hw, HISR_REG, HISR_INT_2_STS);
928
929 /* Clear the interrupt cause of OutputDoorbell */
930 clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause);
931
932 ret = mei_txe_aliveness_set_sync(dev, 1);
933 if (ret < 0) {
934 dev_err(dev->dev, "wait for aliveness failed ... bailing out\n");
935 return ret;
936 }
937
938 /* enable input ready interrupts:
939 * SEC_IPC_HOST_INT_MASK.IPC_INPUT_READY_INT_MASK
940 */
941 mei_txe_input_ready_interrupt_enable(dev);
942
943
944 /* Set the SICR_SEC_IPC_OUTPUT_STATUS.IPC_OUTPUT_READY bit */
945 mei_txe_output_ready_set(hw);
946
947 /* Set bit SICR_HOST_IPC_READINESS.HOST_RDY
948 */
949 mei_txe_readiness_set_host_rdy(dev);
950
951 return 0;
952}
953
954/**
955 * mei_txe_check_and_ack_intrs - translate multi BAR interrupt into
956 * single bit mask and acknowledge the interrupts
957 *
958 * @dev: the device structure
959 * @do_ack: acknowledge interrupts
960 *
961 * Return: true if found interrupts to process.
962 */
963static bool mei_txe_check_and_ack_intrs(struct mei_device *dev, bool do_ack)
964{
965 struct mei_txe_hw *hw = to_txe_hw(dev);
966 u32 hisr;
967 u32 hhisr;
968 u32 ipc_isr;
969 u32 aliveness;
970 bool generated;
971
972 /* read interrupt registers */
973 hhisr = mei_txe_br_reg_read(hw, HHISR_REG);
974 generated = (hhisr & IPC_HHIER_MSK);
975 if (!generated)
976 goto out;
977
978 hisr = mei_txe_br_reg_read(hw, HISR_REG);
979
980 aliveness = mei_txe_aliveness_get(dev);
981 if (hhisr & IPC_HHIER_SEC && aliveness)
982 ipc_isr = mei_txe_sec_reg_read_silent(hw,
983 SEC_IPC_HOST_INT_STATUS_REG);
984 else
985 ipc_isr = 0;
986
987 generated = generated ||
988 (hisr & HISR_INT_STS_MSK) ||
989 (ipc_isr & SEC_IPC_HOST_INT_STATUS_PENDING);
990
991 if (generated && do_ack) {
992 /* Save the interrupt causes */
993 hw->intr_cause |= hisr & HISR_INT_STS_MSK;
994 if (ipc_isr & SEC_IPC_HOST_INT_STATUS_IN_RDY)
995 hw->intr_cause |= TXE_INTR_IN_READY;
996
997
998 mei_txe_intr_disable(dev);
999 /* Clear the interrupts in hierarchy:
1000 * IPC and Bridge, than the High Level */
1001 mei_txe_sec_reg_write_silent(hw,
1002 SEC_IPC_HOST_INT_STATUS_REG, ipc_isr);
1003 mei_txe_br_reg_write(hw, HISR_REG, hisr);
1004 mei_txe_br_reg_write(hw, HHISR_REG, hhisr);
1005 }
1006
1007out:
1008 return generated;
1009}
1010
1011/**
1012 * mei_txe_irq_quick_handler - The ISR of the MEI device
1013 *
1014 * @irq: The irq number
1015 * @dev_id: pointer to the device structure
1016 *
1017 * Return: IRQ_WAKE_THREAD if interrupt is designed for the device
1018 * IRQ_NONE otherwise
1019 */
1020irqreturn_t mei_txe_irq_quick_handler(int irq, void *dev_id)
1021{
1022 struct mei_device *dev = dev_id;
1023
1024 if (mei_txe_check_and_ack_intrs(dev, true))
1025 return IRQ_WAKE_THREAD;
1026 return IRQ_NONE;
1027}
1028
1029
1030/**
1031 * mei_txe_irq_thread_handler - txe interrupt thread
1032 *
1033 * @irq: The irq number
1034 * @dev_id: pointer to the device structure
1035 *
1036 * Return: IRQ_HANDLED
1037 */
1038irqreturn_t mei_txe_irq_thread_handler(int irq, void *dev_id)
1039{
1040 struct mei_device *dev = (struct mei_device *) dev_id;
1041 struct mei_txe_hw *hw = to_txe_hw(dev);
1042 struct mei_cl_cb complete_list;
1043 s32 slots;
1044 int rets = 0;
1045
1046 dev_dbg(dev->dev, "irq thread: Interrupt Registers HHISR|HISR|SEC=%02X|%04X|%02X\n",
1047 mei_txe_br_reg_read(hw, HHISR_REG),
1048 mei_txe_br_reg_read(hw, HISR_REG),
1049 mei_txe_sec_reg_read_silent(hw, SEC_IPC_HOST_INT_STATUS_REG));
1050
1051
1052 /* initialize our complete list */
1053 mutex_lock(&dev->device_lock);
1054 mei_io_list_init(&complete_list);
1055
1056 if (pci_dev_msi_enabled(to_pci_dev(dev->dev)))
1057 mei_txe_check_and_ack_intrs(dev, true);
1058
1059 /* show irq events */
1060 mei_txe_pending_interrupts(dev);
1061
1062 hw->aliveness = mei_txe_aliveness_get(dev);
1063 hw->readiness = mei_txe_readiness_get(dev);
1064
1065 /* Readiness:
1066 * Detection of TXE driver going through reset
1067 * or TXE driver resetting the HECI interface.
1068 */
1069 if (test_and_clear_bit(TXE_INTR_READINESS_BIT, &hw->intr_cause)) {
1070 dev_dbg(dev->dev, "Readiness Interrupt was received...\n");
1071
1072 /* Check if SeC is going through reset */
1073 if (mei_txe_readiness_is_sec_rdy(hw->readiness)) {
1074 dev_dbg(dev->dev, "we need to start the dev.\n");
1075 dev->recvd_hw_ready = true;
1076 } else {
1077 dev->recvd_hw_ready = false;
1078 if (dev->dev_state != MEI_DEV_RESETTING) {
1079
1080 dev_warn(dev->dev, "FW not ready: resetting.\n");
1081 schedule_work(&dev->reset_work);
1082 goto end;
1083
1084 }
1085 }
1086 wake_up(&dev->wait_hw_ready);
1087 }
1088
1089 /************************************************************/
1090 /* Check interrupt cause:
1091 * Aliveness: Detection of SeC acknowledge of host request that
1092 * it remain alive or host cancellation of that request.
1093 */
1094
1095 if (test_and_clear_bit(TXE_INTR_ALIVENESS_BIT, &hw->intr_cause)) {
1096 /* Clear the interrupt cause */
1097 dev_dbg(dev->dev,
1098 "Aliveness Interrupt: Status: %d\n", hw->aliveness);
1099 dev->pg_event = MEI_PG_EVENT_RECEIVED;
1100 if (waitqueue_active(&hw->wait_aliveness_resp))
1101 wake_up(&hw->wait_aliveness_resp);
1102 }
1103
1104
1105 /* Output Doorbell:
1106 * Detection of SeC having sent output to host
1107 */
1108 slots = mei_count_full_read_slots(dev);
1109 if (test_and_clear_bit(TXE_INTR_OUT_DB_BIT, &hw->intr_cause)) {
1110 /* Read from TXE */
1111 rets = mei_irq_read_handler(dev, &complete_list, &slots);
1112 if (rets && dev->dev_state != MEI_DEV_RESETTING) {
1113 dev_err(dev->dev,
1114 "mei_irq_read_handler ret = %d.\n", rets);
1115
1116 schedule_work(&dev->reset_work);
1117 goto end;
1118 }
1119 }
1120 /* Input Ready: Detection if host can write to SeC */
1121 if (test_and_clear_bit(TXE_INTR_IN_READY_BIT, &hw->intr_cause)) {
1122 dev->hbuf_is_ready = true;
1123 hw->slots = dev->hbuf_depth;
1124 }
1125
1126 if (hw->aliveness && dev->hbuf_is_ready) {
1127 /* get the real register value */
1128 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1129 rets = mei_irq_write_handler(dev, &complete_list);
1130 if (rets && rets != -EMSGSIZE)
1131 dev_err(dev->dev, "mei_irq_write_handler ret = %d.\n",
1132 rets);
1133 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1134 }
1135
1136 mei_irq_compl_handler(dev, &complete_list);
1137
1138end:
1139 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1140
1141 mutex_unlock(&dev->device_lock);
1142
1143 mei_enable_interrupts(dev);
1144 return IRQ_HANDLED;
1145}
1146
1147static const struct mei_hw_ops mei_txe_hw_ops = {
1148
1149 .host_is_ready = mei_txe_host_is_ready,
1150
1151 .fw_status = mei_txe_fw_status,
1152 .pg_state = mei_txe_pg_state,
1153
1154 .hw_is_ready = mei_txe_hw_is_ready,
1155 .hw_reset = mei_txe_hw_reset,
1156 .hw_config = mei_txe_hw_config,
1157 .hw_start = mei_txe_hw_start,
1158
1159 .pg_in_transition = mei_txe_pg_in_transition,
1160 .pg_is_enabled = mei_txe_pg_is_enabled,
1161
1162 .intr_clear = mei_txe_intr_clear,
1163 .intr_enable = mei_txe_intr_enable,
1164 .intr_disable = mei_txe_intr_disable,
1165
1166 .hbuf_free_slots = mei_txe_hbuf_empty_slots,
1167 .hbuf_is_ready = mei_txe_is_input_ready,
1168 .hbuf_max_len = mei_txe_hbuf_max_len,
1169
1170 .write = mei_txe_write,
1171
1172 .rdbuf_full_slots = mei_txe_count_full_read_slots,
1173 .read_hdr = mei_txe_read_hdr,
1174
1175 .read = mei_txe_read,
1176
1177};
1178
1179/**
1180 * mei_txe_dev_init - allocates and initializes txe hardware specific structure
1181 *
1182 * @pdev: pci device
1183 *
1184 * Return: struct mei_device * on success or NULL
1185 */
1186struct mei_device *mei_txe_dev_init(struct pci_dev *pdev)
1187{
1188 struct mei_device *dev;
1189 struct mei_txe_hw *hw;
1190
1191 dev = kzalloc(sizeof(struct mei_device) +
1192 sizeof(struct mei_txe_hw), GFP_KERNEL);
1193 if (!dev)
1194 return NULL;
1195
1196 mei_device_init(dev, &pdev->dev, &mei_txe_hw_ops);
1197
1198 hw = to_txe_hw(dev);
1199
1200 init_waitqueue_head(&hw->wait_aliveness_resp);
1201
1202 return dev;
1203}
1204
1205/**
1206 * mei_txe_setup_satt2 - SATT2 configuration for DMA support.
1207 *
1208 * @dev: the device structure
1209 * @addr: physical address start of the range
1210 * @range: physical range size
1211 *
1212 * Return: 0 on success an error code otherwise
1213 */
1214int mei_txe_setup_satt2(struct mei_device *dev, phys_addr_t addr, u32 range)
1215{
1216 struct mei_txe_hw *hw = to_txe_hw(dev);
1217
1218 u32 lo32 = lower_32_bits(addr);
1219 u32 hi32 = upper_32_bits(addr);
1220 u32 ctrl;
1221
1222 /* SATT is limited to 36 Bits */
1223 if (hi32 & ~0xF)
1224 return -EINVAL;
1225
1226 /* SATT has to be 16Byte aligned */
1227 if (lo32 & 0xF)
1228 return -EINVAL;
1229
1230 /* SATT range has to be 4Bytes aligned */
1231 if (range & 0x4)
1232 return -EINVAL;
1233
1234 /* SATT is limited to 32 MB range*/
1235 if (range > SATT_RANGE_MAX)
1236 return -EINVAL;
1237
1238 ctrl = SATT2_CTRL_VALID_MSK;
1239 ctrl |= hi32 << SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT;
1240
1241 mei_txe_br_reg_write(hw, SATT2_SAP_SIZE_REG, range);
1242 mei_txe_br_reg_write(hw, SATT2_BRG_BA_LSB_REG, lo32);
1243 mei_txe_br_reg_write(hw, SATT2_CTRL_REG, ctrl);
1244 dev_dbg(dev->dev, "SATT2: SAP_SIZE_OFFSET=0x%08X, BRG_BA_LSB_OFFSET=0x%08X, CTRL_OFFSET=0x%08X\n",
1245 range, lo32, ctrl);
1246
1247 return 0;
1248}