1/* da9063-irq.c: Interrupts support for Dialog DA9063
  2 *
  3 * Copyright 2012 Dialog Semiconductor Ltd.
  4 * Copyright 2013 Philipp Zabel, Pengutronix
  5 *
  6 * Author: Michal Hajduk <michal.hajduk@diasemi.com>
  7 *
  8 *  This program is free software; you can redistribute  it and/or modify it
  9 *  under  the terms of  the GNU General  Public License as published by the
 10 *  Free Software Foundation;  either version 2 of the  License, or (at your
 11 *  option) any later version.
 12 *
 13 */
 14
 15#include <linux/kernel.h>
 16#include <linux/module.h>
 17#include <linux/irq.h>
 18#include <linux/mfd/core.h>
 19#include <linux/interrupt.h>
 20#include <linux/regmap.h>
 21#include <linux/mfd/da9063/core.h>
 22#include <linux/mfd/da9063/pdata.h>
 23
 24#define	DA9063_REG_EVENT_A_OFFSET	0
 25#define	DA9063_REG_EVENT_B_OFFSET	1
 26#define	DA9063_REG_EVENT_C_OFFSET	2
 27#define	DA9063_REG_EVENT_D_OFFSET	3
 28#define EVENTS_BUF_LEN			4
 29
 30static const u8 mask_events_buf[] = { [0 ... (EVENTS_BUF_LEN - 1)] = ~0 };
 31
 32struct da9063_irq_data {
 33	u16 reg;
 34	u8 mask;
 35};
 36
 37static const struct regmap_irq da9063_irqs[] = {
 38	/* DA9063 event A register */
 39	[DA9063_IRQ_ONKEY] = {
 40		.reg_offset = DA9063_REG_EVENT_A_OFFSET,
 41		.mask = DA9063_M_ONKEY,
 42	},
 43	[DA9063_IRQ_ALARM] = {
 44		.reg_offset = DA9063_REG_EVENT_A_OFFSET,
 45		.mask = DA9063_M_ALARM,
 46	},
 47	[DA9063_IRQ_TICK] = {
 48		.reg_offset = DA9063_REG_EVENT_A_OFFSET,
 49		.mask = DA9063_M_TICK,
 50	},
 51	[DA9063_IRQ_ADC_RDY] = {
 52		.reg_offset = DA9063_REG_EVENT_A_OFFSET,
 53		.mask = DA9063_M_ADC_RDY,
 54	},
 55	[DA9063_IRQ_SEQ_RDY] = {
 56		.reg_offset = DA9063_REG_EVENT_A_OFFSET,
 57		.mask = DA9063_M_SEQ_RDY,
 58	},
 59	/* DA9063 event B register */
 60	[DA9063_IRQ_WAKE] = {
 61		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 62		.mask = DA9063_M_WAKE,
 63	},
 64	[DA9063_IRQ_TEMP] = {
 65		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 66		.mask = DA9063_M_TEMP,
 67	},
 68	[DA9063_IRQ_COMP_1V2] = {
 69		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 70		.mask = DA9063_M_COMP_1V2,
 71	},
 72	[DA9063_IRQ_LDO_LIM] = {
 73		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 74		.mask = DA9063_M_LDO_LIM,
 75	},
 76	[DA9063_IRQ_REG_UVOV] = {
 77		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 78		.mask = DA9063_M_UVOV,
 79	},
 80	[DA9063_IRQ_DVC_RDY] = {
 81		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 82		.mask = DA9063_M_DVC_RDY,
 83	},
 84	[DA9063_IRQ_VDD_MON] = {
 85		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 86		.mask = DA9063_M_VDD_MON,
 87	},
 88	[DA9063_IRQ_WARN] = {
 89		.reg_offset = DA9063_REG_EVENT_B_OFFSET,
 90		.mask = DA9063_M_VDD_WARN,
 91	},
 92	/* DA9063 event C register */
 93	[DA9063_IRQ_GPI0] = {
 94		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
 95		.mask = DA9063_M_GPI0,
 96	},
 97	[DA9063_IRQ_GPI1] = {
 98		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
 99		.mask = DA9063_M_GPI1,
100	},
101	[DA9063_IRQ_GPI2] = {
102		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
103		.mask = DA9063_M_GPI2,
104	},
105	[DA9063_IRQ_GPI3] = {
106		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
107		.mask = DA9063_M_GPI3,
108	},
109	[DA9063_IRQ_GPI4] = {
110		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
111		.mask = DA9063_M_GPI4,
112	},
113	[DA9063_IRQ_GPI5] = {
114		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
115		.mask = DA9063_M_GPI5,
116	},
117	[DA9063_IRQ_GPI6] = {
118		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
119		.mask = DA9063_M_GPI6,
120	},
121	[DA9063_IRQ_GPI7] = {
122		.reg_offset = DA9063_REG_EVENT_C_OFFSET,
123		.mask = DA9063_M_GPI7,
124	},
125	/* DA9063 event D register */
126	[DA9063_IRQ_GPI8] = {
127		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
128		.mask = DA9063_M_GPI8,
129	},
130	[DA9063_IRQ_GPI9] = {
131		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
132		.mask = DA9063_M_GPI9,
133	},
134	[DA9063_IRQ_GPI10] = {
135		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
136		.mask = DA9063_M_GPI10,
137	},
138	[DA9063_IRQ_GPI11] = {
139		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
140		.mask = DA9063_M_GPI11,
141	},
142	[DA9063_IRQ_GPI12] = {
143		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
144		.mask = DA9063_M_GPI12,
145	},
146	[DA9063_IRQ_GPI13] = {
147		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
148		.mask = DA9063_M_GPI13,
149	},
150	[DA9063_IRQ_GPI14] = {
151		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
152		.mask = DA9063_M_GPI14,
153	},
154	[DA9063_IRQ_GPI15] = {
155		.reg_offset = DA9063_REG_EVENT_D_OFFSET,
156		.mask = DA9063_M_GPI15,
157	},
158};
159
160static const struct regmap_irq_chip da9063_irq_chip = {
161	.name = "da9063-irq",
162	.irqs = da9063_irqs,
163	.num_irqs = DA9063_NUM_IRQ,
164
165	.num_regs = 4,
166	.status_base = DA9063_REG_EVENT_A,
167	.mask_base = DA9063_REG_IRQ_MASK_A,
168	.ack_base = DA9063_REG_EVENT_A,
169	.init_ack_masked = true,
170};
171
172int da9063_irq_init(struct da9063 *da9063)
173{
174	int ret;
175
176	if (!da9063->chip_irq) {
177		dev_err(da9063->dev, "No IRQ configured\n");
178		return -EINVAL;
179	}
180
181	ret = regmap_add_irq_chip(da9063->regmap, da9063->chip_irq,
182			IRQF_TRIGGER_LOW | IRQF_ONESHOT | IRQF_SHARED,
183			da9063->irq_base, &da9063_irq_chip,
184			&da9063->regmap_irq);
185	if (ret) {
186		dev_err(da9063->dev, "Failed to reguest IRQ %d: %d\n",
187				da9063->chip_irq, ret);
188		return ret;
189	}
190
191	return 0;
192}
193
194void da9063_irq_exit(struct da9063 *da9063)
195{
196	regmap_del_irq_chip(da9063->chip_irq, da9063->regmap_irq);
197}