1/*
  2 * Copyright © 2014 Broadcom
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice (including the next
 12 * paragraph) shall be included in all copies or substantial portions of the
 13 * Software.
 14 *
 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 21 * IN THE SOFTWARE.
 22 */
 23
 24/** DOC: Interrupt management for the V3D engine.
 25 *
 26 * We have an interrupt status register (V3D_INTCTL) which reports
 27 * interrupts, and where writing 1 bits clears those interrupts.
 28 * There are also a pair of interrupt registers
 29 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or
 30 * disables that specific interrupt, and 0s written are ignored
 31 * (reading either one returns the set of enabled interrupts).
 32 *
 33 * When we take a binning flush done interrupt, we need to submit the
 34 * next frame for binning and move the finished frame to the render
 35 * thread.
 36 *
 37 * When we take a render frame interrupt, we need to wake the
 38 * processes waiting for some frame to be done, and get the next frame
 39 * submitted ASAP (so the hardware doesn't sit idle when there's work
 40 * to do).
 41 *
 42 * When we take the binner out of memory interrupt, we need to
 43 * allocate some new memory and pass it to the binner so that the
 44 * current job can make progress.
 45 */
 46
 47#include "vc4_drv.h"
 48#include "vc4_regs.h"
 49
 50#define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \
 51			 V3D_INT_FLDONE | \
 52			 V3D_INT_FRDONE)
 53
 54DECLARE_WAIT_QUEUE_HEAD(render_wait);
 55
 56static void
 57vc4_overflow_mem_work(struct work_struct *work)
 58{
 59	struct vc4_dev *vc4 =
 60		container_of(work, struct vc4_dev, overflow_mem_work);
 61	struct drm_device *dev = vc4->dev;
 62	struct vc4_bo *bo;
 63
 64	bo = vc4_bo_create(dev, 256 * 1024, true);
 65	if (IS_ERR(bo)) {
 66		DRM_ERROR("Couldn't allocate binner overflow mem\n");
 67		return;
 68	}
 69
 70	/* If there's a job executing currently, then our previous
 71	 * overflow allocation is getting used in that job and we need
 72	 * to queue it to be released when the job is done.  But if no
 73	 * job is executing at all, then we can free the old overflow
 74	 * object direcctly.
 75	 *
 76	 * No lock necessary for this pointer since we're the only
 77	 * ones that update the pointer, and our workqueue won't
 78	 * reenter.
 79	 */
 80	if (vc4->overflow_mem) {
 81		struct vc4_exec_info *current_exec;
 82		unsigned long irqflags;
 83
 84		spin_lock_irqsave(&vc4->job_lock, irqflags);
 85		current_exec = vc4_first_bin_job(vc4);
 86		if (current_exec) {
 87			vc4->overflow_mem->seqno = vc4->finished_seqno + 1;
 88			list_add_tail(&vc4->overflow_mem->unref_head,
 89				      &current_exec->unref_list);
 90			vc4->overflow_mem = NULL;
 91		}
 92		spin_unlock_irqrestore(&vc4->job_lock, irqflags);
 93	}
 94
 95	if (vc4->overflow_mem)
 96		drm_gem_object_unreference_unlocked(&vc4->overflow_mem->base.base);
 97	vc4->overflow_mem = bo;
 98
 99	V3D_WRITE(V3D_BPOA, bo->base.paddr);
100	V3D_WRITE(V3D_BPOS, bo->base.base.size);
101	V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM);
102	V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM);
103}
104
105static void
106vc4_irq_finish_bin_job(struct drm_device *dev)
107{
108	struct vc4_dev *vc4 = to_vc4_dev(dev);
109	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
110
111	if (!exec)
112		return;
113
114	vc4_move_job_to_render(dev, exec);
115	vc4_submit_next_bin_job(dev);
116}
117
118static void
119vc4_cancel_bin_job(struct drm_device *dev)
120{
121	struct vc4_dev *vc4 = to_vc4_dev(dev);
122	struct vc4_exec_info *exec = vc4_first_bin_job(vc4);
123
124	if (!exec)
125		return;
126
127	list_move_tail(&exec->head, &vc4->bin_job_list);
128	vc4_submit_next_bin_job(dev);
129}
130
131static void
132vc4_irq_finish_render_job(struct drm_device *dev)
133{
134	struct vc4_dev *vc4 = to_vc4_dev(dev);
135	struct vc4_exec_info *exec = vc4_first_render_job(vc4);
136
137	if (!exec)
138		return;
139
140	vc4->finished_seqno++;
141	list_move_tail(&exec->head, &vc4->job_done_list);
142	vc4_submit_next_render_job(dev);
143
144	wake_up_all(&vc4->job_wait_queue);
145	schedule_work(&vc4->job_done_work);
146}
147
148irqreturn_t
149vc4_irq(int irq, void *arg)
150{
151	struct drm_device *dev = arg;
152	struct vc4_dev *vc4 = to_vc4_dev(dev);
153	uint32_t intctl;
154	irqreturn_t status = IRQ_NONE;
155
156	barrier();
157	intctl = V3D_READ(V3D_INTCTL);
158
159	/* Acknowledge the interrupts we're handling here. The binner
160	 * last flush / render frame done interrupt will be cleared,
161	 * while OUTOMEM will stay high until the underlying cause is
162	 * cleared.
163	 */
164	V3D_WRITE(V3D_INTCTL, intctl);
165
166	if (intctl & V3D_INT_OUTOMEM) {
167		/* Disable OUTOMEM until the work is done. */
168		V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM);
169		schedule_work(&vc4->overflow_mem_work);
170		status = IRQ_HANDLED;
171	}
172
173	if (intctl & V3D_INT_FLDONE) {
174		spin_lock(&vc4->job_lock);
175		vc4_irq_finish_bin_job(dev);
176		spin_unlock(&vc4->job_lock);
177		status = IRQ_HANDLED;
178	}
179
180	if (intctl & V3D_INT_FRDONE) {
181		spin_lock(&vc4->job_lock);
182		vc4_irq_finish_render_job(dev);
183		spin_unlock(&vc4->job_lock);
184		status = IRQ_HANDLED;
185	}
186
187	return status;
188}
189
190void
191vc4_irq_preinstall(struct drm_device *dev)
192{
193	struct vc4_dev *vc4 = to_vc4_dev(dev);
194
195	init_waitqueue_head(&vc4->job_wait_queue);
196	INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work);
197
198	/* Clear any pending interrupts someone might have left around
199	 * for us.
200	 */
201	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
202}
203
204int
205vc4_irq_postinstall(struct drm_device *dev)
206{
207	struct vc4_dev *vc4 = to_vc4_dev(dev);
208
209	/* Enable both the render done and out of memory interrupts. */
210	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
211
212	return 0;
213}
214
215void
216vc4_irq_uninstall(struct drm_device *dev)
217{
218	struct vc4_dev *vc4 = to_vc4_dev(dev);
219
220	/* Disable sending interrupts for our driver's IRQs. */
221	V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS);
222
223	/* Clear any pending interrupts we might have left. */
224	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
225
226	cancel_work_sync(&vc4->overflow_mem_work);
227}
228
229/** Reinitializes interrupt registers when a GPU reset is performed. */
230void vc4_irq_reset(struct drm_device *dev)
231{
232	struct vc4_dev *vc4 = to_vc4_dev(dev);
233	unsigned long irqflags;
234
235	/* Acknowledge any stale IRQs. */
236	V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
237
238	/*
239	 * Turn all our interrupts on.  Binner out of memory is the
240	 * only one we expect to trigger at this point, since we've
241	 * just come from poweron and haven't supplied any overflow
242	 * memory yet.
243	 */
244	V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS);
245
246	spin_lock_irqsave(&vc4->job_lock, irqflags);
247	vc4_cancel_bin_job(dev);
248	vc4_irq_finish_render_job(dev);
249	spin_unlock_irqrestore(&vc4->job_lock, irqflags);
250}