Loading...
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h>
21#include <asm/octeon/pci-octeon.h>
22
23union cvmx_pcie_address {
24 uint64_t u64;
25 struct {
26 uint64_t upper:2; /* Normally 2 for XKPHYS */
27 uint64_t reserved_49_61:13; /* Must be zero */
28 uint64_t io:1; /* 1 for IO space access */
29 uint64_t did:5; /* PCIe DID = 3 */
30 uint64_t subdid:3; /* PCIe SubDID = 1 */
31 uint64_t reserved_36_39:4; /* Must be zero */
32 uint64_t es:2; /* Endian swap = 1 */
33 uint64_t port:2; /* PCIe port 0,1 */
34 uint64_t reserved_29_31:3; /* Must be zero */
35 /*
36 * Selects the type of the configuration request (0 = type 0,
37 * 1 = type 1).
38 */
39 uint64_t ty:1;
40 /* Target bus number sent in the ID in the request. */
41 uint64_t bus:8;
42 /*
43 * Target device number sent in the ID in the
44 * request. Note that Dev must be zero for type 0
45 * configuration requests.
46 */
47 uint64_t dev:5;
48 /* Target function number sent in the ID in the request. */
49 uint64_t func:3;
50 /*
51 * Selects a register in the configuration space of
52 * the target.
53 */
54 uint64_t reg:12;
55 } config;
56 struct {
57 uint64_t upper:2; /* Normally 2 for XKPHYS */
58 uint64_t reserved_49_61:13; /* Must be zero */
59 uint64_t io:1; /* 1 for IO space access */
60 uint64_t did:5; /* PCIe DID = 3 */
61 uint64_t subdid:3; /* PCIe SubDID = 2 */
62 uint64_t reserved_36_39:4; /* Must be zero */
63 uint64_t es:2; /* Endian swap = 1 */
64 uint64_t port:2; /* PCIe port 0,1 */
65 uint64_t address:32; /* PCIe IO address */
66 } io;
67 struct {
68 uint64_t upper:2; /* Normally 2 for XKPHYS */
69 uint64_t reserved_49_61:13; /* Must be zero */
70 uint64_t io:1; /* 1 for IO space access */
71 uint64_t did:5; /* PCIe DID = 3 */
72 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
73 uint64_t reserved_36_39:4; /* Must be zero */
74 uint64_t address:36; /* PCIe Mem address */
75 } mem;
76};
77
78#include <dma-coherence.h>
79
80/**
81 * Return the Core virtual base address for PCIe IO access. IOs are
82 * read/written as an offset from this address.
83 *
84 * @pcie_port: PCIe port the IO is for
85 *
86 * Returns 64bit Octeon IO base address for read/write
87 */
88static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
89{
90 union cvmx_pcie_address pcie_addr;
91 pcie_addr.u64 = 0;
92 pcie_addr.io.upper = 0;
93 pcie_addr.io.io = 1;
94 pcie_addr.io.did = 3;
95 pcie_addr.io.subdid = 2;
96 pcie_addr.io.es = 1;
97 pcie_addr.io.port = pcie_port;
98 return pcie_addr.u64;
99}
100
101/**
102 * Size of the IO address region returned at address
103 * cvmx_pcie_get_io_base_address()
104 *
105 * @pcie_port: PCIe port the IO is for
106 *
107 * Returns Size of the IO window
108 */
109static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
110{
111 return 1ull << 32;
112}
113
114/**
115 * Return the Core virtual base address for PCIe MEM access. Memory is
116 * read/written as an offset from this address.
117 *
118 * @pcie_port: PCIe port the IO is for
119 *
120 * Returns 64bit Octeon IO base address for read/write
121 */
122static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
123{
124 union cvmx_pcie_address pcie_addr;
125 pcie_addr.u64 = 0;
126 pcie_addr.mem.upper = 0;
127 pcie_addr.mem.io = 1;
128 pcie_addr.mem.did = 3;
129 pcie_addr.mem.subdid = 3 + pcie_port;
130 return pcie_addr.u64;
131}
132
133/**
134 * Size of the Mem address region returned at address
135 * cvmx_pcie_get_mem_base_address()
136 *
137 * @pcie_port: PCIe port the IO is for
138 *
139 * Returns Size of the Mem window
140 */
141static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
142{
143 return 1ull << 36;
144}
145
146/**
147 * Read a PCIe config space register indirectly. This is used for
148 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
149 *
150 * @pcie_port: PCIe port to read from
151 * @cfg_offset: Address to read
152 *
153 * Returns Value read
154 */
155static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
156{
157 union cvmx_pescx_cfg_rd pescx_cfg_rd;
158 pescx_cfg_rd.u64 = 0;
159 pescx_cfg_rd.s.addr = cfg_offset;
160 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
161 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
162 return pescx_cfg_rd.s.data;
163}
164
165/**
166 * Write a PCIe config space register indirectly. This is used for
167 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168 *
169 * @pcie_port: PCIe port to write to
170 * @cfg_offset: Address to write
171 * @val: Value to write
172 */
173static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
174 uint32_t val)
175{
176 union cvmx_pescx_cfg_wr pescx_cfg_wr;
177 pescx_cfg_wr.u64 = 0;
178 pescx_cfg_wr.s.addr = cfg_offset;
179 pescx_cfg_wr.s.data = val;
180 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
181}
182
183/**
184 * Build a PCIe config space request address for a device
185 *
186 * @pcie_port: PCIe port to access
187 * @bus: Sub bus
188 * @dev: Device ID
189 * @fn: Device sub function
190 * @reg: Register to access
191 *
192 * Returns 64bit Octeon IO address
193 */
194static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
195 int dev, int fn, int reg)
196{
197 union cvmx_pcie_address pcie_addr;
198 union cvmx_pciercx_cfg006 pciercx_cfg006;
199
200 pciercx_cfg006.u32 =
201 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
202 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
203 return 0;
204
205 pcie_addr.u64 = 0;
206 pcie_addr.config.upper = 2;
207 pcie_addr.config.io = 1;
208 pcie_addr.config.did = 3;
209 pcie_addr.config.subdid = 1;
210 pcie_addr.config.es = 1;
211 pcie_addr.config.port = pcie_port;
212 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
213 pcie_addr.config.bus = bus;
214 pcie_addr.config.dev = dev;
215 pcie_addr.config.func = fn;
216 pcie_addr.config.reg = reg;
217 return pcie_addr.u64;
218}
219
220/**
221 * Read 8bits from a Device's config space
222 *
223 * @pcie_port: PCIe port the device is on
224 * @bus: Sub bus
225 * @dev: Device ID
226 * @fn: Device sub function
227 * @reg: Register to access
228 *
229 * Returns Result of the read
230 */
231static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
232 int fn, int reg)
233{
234 uint64_t address =
235 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
236 if (address)
237 return cvmx_read64_uint8(address);
238 else
239 return 0xff;
240}
241
242/**
243 * Read 16bits from a Device's config space
244 *
245 * @pcie_port: PCIe port the device is on
246 * @bus: Sub bus
247 * @dev: Device ID
248 * @fn: Device sub function
249 * @reg: Register to access
250 *
251 * Returns Result of the read
252 */
253static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
254 int fn, int reg)
255{
256 uint64_t address =
257 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
258 if (address)
259 return le16_to_cpu(cvmx_read64_uint16(address));
260 else
261 return 0xffff;
262}
263
264/**
265 * Read 32bits from a Device's config space
266 *
267 * @pcie_port: PCIe port the device is on
268 * @bus: Sub bus
269 * @dev: Device ID
270 * @fn: Device sub function
271 * @reg: Register to access
272 *
273 * Returns Result of the read
274 */
275static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
276 int fn, int reg)
277{
278 uint64_t address =
279 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
280 if (address)
281 return le32_to_cpu(cvmx_read64_uint32(address));
282 else
283 return 0xffffffff;
284}
285
286/**
287 * Write 8bits to a Device's config space
288 *
289 * @pcie_port: PCIe port the device is on
290 * @bus: Sub bus
291 * @dev: Device ID
292 * @fn: Device sub function
293 * @reg: Register to access
294 * @val: Value to write
295 */
296static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
297 int reg, uint8_t val)
298{
299 uint64_t address =
300 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
301 if (address)
302 cvmx_write64_uint8(address, val);
303}
304
305/**
306 * Write 16bits to a Device's config space
307 *
308 * @pcie_port: PCIe port the device is on
309 * @bus: Sub bus
310 * @dev: Device ID
311 * @fn: Device sub function
312 * @reg: Register to access
313 * @val: Value to write
314 */
315static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
316 int reg, uint16_t val)
317{
318 uint64_t address =
319 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
320 if (address)
321 cvmx_write64_uint16(address, cpu_to_le16(val));
322}
323
324/**
325 * Write 32bits to a Device's config space
326 *
327 * @pcie_port: PCIe port the device is on
328 * @bus: Sub bus
329 * @dev: Device ID
330 * @fn: Device sub function
331 * @reg: Register to access
332 * @val: Value to write
333 */
334static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
335 int reg, uint32_t val)
336{
337 uint64_t address =
338 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
339 if (address)
340 cvmx_write64_uint32(address, cpu_to_le32(val));
341}
342
343/**
344 * Initialize the RC config space CSRs
345 *
346 * @pcie_port: PCIe port to initialize
347 */
348static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
349{
350 union cvmx_pciercx_cfg030 pciercx_cfg030;
351 union cvmx_npei_ctl_status2 npei_ctl_status2;
352 union cvmx_pciercx_cfg070 pciercx_cfg070;
353 union cvmx_pciercx_cfg001 pciercx_cfg001;
354 union cvmx_pciercx_cfg032 pciercx_cfg032;
355 union cvmx_pciercx_cfg006 pciercx_cfg006;
356 union cvmx_pciercx_cfg008 pciercx_cfg008;
357 union cvmx_pciercx_cfg009 pciercx_cfg009;
358 union cvmx_pciercx_cfg010 pciercx_cfg010;
359 union cvmx_pciercx_cfg011 pciercx_cfg011;
360 union cvmx_pciercx_cfg035 pciercx_cfg035;
361 union cvmx_pciercx_cfg075 pciercx_cfg075;
362 union cvmx_pciercx_cfg034 pciercx_cfg034;
363
364 /* Max Payload Size (PCIE*_CFG030[MPS]) */
365 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
366 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
367 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
368 pciercx_cfg030.u32 =
369 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
370 /*
371 * Max payload size = 128 bytes for best Octeon DMA
372 * performance.
373 */
374 pciercx_cfg030.s.mps = 0;
375 /*
376 * Max read request size = 128 bytes for best Octeon DMA
377 * performance.
378 */
379 pciercx_cfg030.s.mrrs = 0;
380 /* Enable relaxed ordering. */
381 pciercx_cfg030.s.ro_en = 1;
382 /* Enable no snoop. */
383 pciercx_cfg030.s.ns_en = 1;
384 /* Correctable error reporting enable. */
385 pciercx_cfg030.s.ce_en = 1;
386 /* Non-fatal error reporting enable. */
387 pciercx_cfg030.s.nfe_en = 1;
388 /* Fatal error reporting enable. */
389 pciercx_cfg030.s.fe_en = 1;
390 /* Unsupported request reporting enable. */
391 pciercx_cfg030.s.ur_en = 1;
392 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
393 pciercx_cfg030.u32);
394
395 /*
396 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
397 * PCIE*_CFG030[MPS]
398 *
399 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
400 * exceed PCIE*_CFG030[MRRS].
401 */
402 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
403 /* Max payload size = 128 bytes for best Octeon DMA performance */
404 npei_ctl_status2.s.mps = 0;
405 /* Max read request size = 128 bytes for best Octeon DMA performance */
406 npei_ctl_status2.s.mrrs = 0;
407 if (pcie_port)
408 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
409 else
410 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
411 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
412
413 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
414 pciercx_cfg070.u32 =
415 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
416 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
417 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
418 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
419 pciercx_cfg070.u32);
420
421 /*
422 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
423 * always be set.
424 *
425 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
426 * Message Enable (PCIE*_CFG001[SEE])
427 */
428 pciercx_cfg001.u32 =
429 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
430 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
431 pciercx_cfg001.s.me = 1; /* Bus master enable. */
432 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
433 pciercx_cfg001.s.see = 1; /* SERR# enable */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
435 pciercx_cfg001.u32);
436
437 /* Advanced Error Recovery Message Enables */
438 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
439 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
440 /* Use CVMX_PCIERCX_CFG067 hardware default */
441 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
442
443 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
444 pciercx_cfg032.u32 =
445 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
446 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
447 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
448 pciercx_cfg032.u32);
449
450 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
451
452 /*
453 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
454 * cvmx_pcie_rc_initialize_link()
455 *
456 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
457 *
458 * We set the primary bus number to 1 so IDT bridges are
459 * happy. They don't like zero.
460 */
461 pciercx_cfg006.u32 = 0;
462 pciercx_cfg006.s.pbnum = 1;
463 pciercx_cfg006.s.sbnum = 1;
464 pciercx_cfg006.s.subbnum = 1;
465 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
466 pciercx_cfg006.u32);
467
468 /*
469 * Memory-mapped I/O BAR (PCIERCn_CFG008)
470 * Most applications should disable the memory-mapped I/O BAR by
471 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
472 */
473 pciercx_cfg008.u32 = 0;
474 pciercx_cfg008.s.mb_addr = 0x100;
475 pciercx_cfg008.s.ml_addr = 0;
476 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
477 pciercx_cfg008.u32);
478
479 /*
480 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
481 * Most applications should disable the prefetchable BAR by setting
482 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
483 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
484 */
485 pciercx_cfg009.u32 =
486 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
487 pciercx_cfg010.u32 =
488 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
489 pciercx_cfg011.u32 =
490 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
491 pciercx_cfg009.s.lmem_base = 0x100;
492 pciercx_cfg009.s.lmem_limit = 0;
493 pciercx_cfg010.s.umem_base = 0x100;
494 pciercx_cfg011.s.umem_limit = 0;
495 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
496 pciercx_cfg009.u32);
497 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
498 pciercx_cfg010.u32);
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
500 pciercx_cfg011.u32);
501
502 /*
503 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
504 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
505 */
506 pciercx_cfg035.u32 =
507 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
508 /* System error on correctable error enable. */
509 pciercx_cfg035.s.secee = 1;
510 /* System error on fatal error enable. */
511 pciercx_cfg035.s.sefee = 1;
512 /* System error on non-fatal error enable. */
513 pciercx_cfg035.s.senfee = 1;
514 /* PME interrupt enable. */
515 pciercx_cfg035.s.pmeie = 1;
516 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
517 pciercx_cfg035.u32);
518
519 /*
520 * Advanced Error Recovery Interrupt Enables
521 * (PCIERCn_CFG075[CERE,NFERE,FERE])
522 */
523 pciercx_cfg075.u32 =
524 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
525 /* Correctable error reporting enable. */
526 pciercx_cfg075.s.cere = 1;
527 /* Non-fatal error reporting enable. */
528 pciercx_cfg075.s.nfere = 1;
529 /* Fatal error reporting enable. */
530 pciercx_cfg075.s.fere = 1;
531 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
532 pciercx_cfg075.u32);
533
534 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
535 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
536 */
537 pciercx_cfg034.u32 =
538 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
539 /* Hot-plug interrupt enable. */
540 pciercx_cfg034.s.hpint_en = 1;
541 /* Data Link Layer state changed enable */
542 pciercx_cfg034.s.dlls_en = 1;
543 /* Command completed interrupt enable. */
544 pciercx_cfg034.s.ccint_en = 1;
545 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
546 pciercx_cfg034.u32);
547}
548
549/**
550 * Initialize a host mode PCIe link. This function takes a PCIe
551 * port from reset to a link up state. Software can then begin
552 * configuring the rest of the link.
553 *
554 * @pcie_port: PCIe port to initialize
555 *
556 * Returns Zero on success
557 */
558static int __cvmx_pcie_rc_initialize_link(int pcie_port)
559{
560 uint64_t start_cycle;
561 union cvmx_pescx_ctl_status pescx_ctl_status;
562 union cvmx_pciercx_cfg452 pciercx_cfg452;
563 union cvmx_pciercx_cfg032 pciercx_cfg032;
564 union cvmx_pciercx_cfg448 pciercx_cfg448;
565
566 /* Set the lane width */
567 pciercx_cfg452.u32 =
568 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
569 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
570 if (pescx_ctl_status.s.qlm_cfg == 0) {
571 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
572 pciercx_cfg452.s.lme = 0xf;
573 } else {
574 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
575 pciercx_cfg452.s.lme = 0x7;
576 }
577 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
578 pciercx_cfg452.u32);
579
580 /*
581 * CN52XX pass 1.x has an errata where length mismatches on UR
582 * responses can cause bus errors on 64bit memory
583 * reads. Turning off length error checking fixes this.
584 */
585 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
586 union cvmx_pciercx_cfg455 pciercx_cfg455;
587 pciercx_cfg455.u32 =
588 cvmx_pcie_cfgx_read(pcie_port,
589 CVMX_PCIERCX_CFG455(pcie_port));
590 pciercx_cfg455.s.m_cpl_len_err = 1;
591 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
592 pciercx_cfg455.u32);
593 }
594
595 /* Lane swap needs to be manually enabled for CN52XX */
596 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
597 pescx_ctl_status.s.lane_swp = 1;
598 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
599 pescx_ctl_status.u64);
600 }
601
602 /* Bring up the link */
603 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
604 pescx_ctl_status.s.lnk_enb = 1;
605 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
606
607 /*
608 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
609 * be disabled.
610 */
611 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
612 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
613
614 /* Wait for the link to come up */
615 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
616 start_cycle = cvmx_get_cycle();
617 do {
618 if (cvmx_get_cycle() - start_cycle >
619 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
620 cvmx_dprintf("PCIe: Port %d link timeout\n",
621 pcie_port);
622 return -1;
623 }
624 cvmx_wait(10000);
625 pciercx_cfg032.u32 =
626 cvmx_pcie_cfgx_read(pcie_port,
627 CVMX_PCIERCX_CFG032(pcie_port));
628 } while (pciercx_cfg032.s.dlla == 0);
629
630 /* Display the link status */
631 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
632 pciercx_cfg032.s.nlw);
633
634 /*
635 * Update the Replay Time Limit. Empirically, some PCIe
636 * devices take a little longer to respond than expected under
637 * load. As a workaround for this we configure the Replay Time
638 * Limit to the value expected for a 512 byte MPS instead of
639 * our actual 256 byte MPS. The numbers below are directly
640 * from the PCIe spec table 3-4.
641 */
642 pciercx_cfg448.u32 =
643 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
644 switch (pciercx_cfg032.s.nlw) {
645 case 1: /* 1 lane */
646 pciercx_cfg448.s.rtl = 1677;
647 break;
648 case 2: /* 2 lanes */
649 pciercx_cfg448.s.rtl = 867;
650 break;
651 case 4: /* 4 lanes */
652 pciercx_cfg448.s.rtl = 462;
653 break;
654 case 8: /* 8 lanes */
655 pciercx_cfg448.s.rtl = 258;
656 break;
657 }
658 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
659 pciercx_cfg448.u32);
660
661 return 0;
662}
663
664/**
665 * Initialize a PCIe port for use in host(RC) mode. It doesn't
666 * enumerate the bus.
667 *
668 * @pcie_port: PCIe port to initialize
669 *
670 * Returns Zero on success
671 */
672static int cvmx_pcie_rc_initialize(int pcie_port)
673{
674 int i;
675 int base;
676 u64 addr_swizzle;
677 union cvmx_ciu_soft_prst ciu_soft_prst;
678 union cvmx_pescx_bist_status pescx_bist_status;
679 union cvmx_pescx_bist_status2 pescx_bist_status2;
680 union cvmx_npei_ctl_status npei_ctl_status;
681 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
682 union cvmx_npei_mem_access_subidx mem_access_subid;
683 union cvmx_npei_dbg_data npei_dbg_data;
684 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
685 union cvmx_npei_bar1_indexx bar1_index;
686
687 /*
688 * Make sure we aren't trying to setup a target mode interface
689 * in host mode.
690 */
691 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
692 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
693 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
694 "on port0, but port0 is not in host mode\n");
695 return -1;
696 }
697
698 /*
699 * Make sure a CN52XX isn't trying to bring up port 1 when it
700 * is disabled.
701 */
702 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
703 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
704 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
705 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
706 "called on port1, but port1 is "
707 "disabled\n");
708 return -1;
709 }
710 }
711
712 /*
713 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
714 * PCIe0, then PCIe1. '1' == round robin.
715 */
716 npei_ctl_status.s.arb = 1;
717 /* Allow up to 0x20 config retries */
718 npei_ctl_status.s.cfg_rtry = 0x20;
719 /*
720 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
721 * don't reset.
722 */
723 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
724 npei_ctl_status.s.p0_ntags = 0x20;
725 npei_ctl_status.s.p1_ntags = 0x20;
726 }
727 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
728
729 /* Bring the PCIe out of reset */
730 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
731 /*
732 * The EBH5200 board swapped the PCIe reset lines on
733 * the board. As a workaround for this bug, we bring
734 * both PCIe ports out of reset at the same time
735 * instead of on separate calls. So for port 0, we
736 * bring both out of reset and do nothing on port 1.
737 */
738 if (pcie_port == 0) {
739 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
740 /*
741 * After a chip reset the PCIe will also be in
742 * reset. If it isn't, most likely someone is
743 * trying to init it again without a proper
744 * PCIe reset.
745 */
746 if (ciu_soft_prst.s.soft_prst == 0) {
747 /* Reset the ports */
748 ciu_soft_prst.s.soft_prst = 1;
749 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
750 ciu_soft_prst.u64);
751 ciu_soft_prst.u64 =
752 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
753 ciu_soft_prst.s.soft_prst = 1;
754 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
755 ciu_soft_prst.u64);
756 /* Wait until pcie resets the ports. */
757 udelay(2000);
758 }
759 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
760 ciu_soft_prst.s.soft_prst = 0;
761 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
762 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
763 ciu_soft_prst.s.soft_prst = 0;
764 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
765 }
766 } else {
767 /*
768 * The normal case: The PCIe ports are completely
769 * separate and can be brought out of reset
770 * independently.
771 */
772 if (pcie_port)
773 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
774 else
775 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
776 /*
777 * After a chip reset the PCIe will also be in
778 * reset. If it isn't, most likely someone is trying
779 * to init it again without a proper PCIe reset.
780 */
781 if (ciu_soft_prst.s.soft_prst == 0) {
782 /* Reset the port */
783 ciu_soft_prst.s.soft_prst = 1;
784 if (pcie_port)
785 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
786 ciu_soft_prst.u64);
787 else
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
789 ciu_soft_prst.u64);
790 /* Wait until pcie resets the ports. */
791 udelay(2000);
792 }
793 if (pcie_port) {
794 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
795 ciu_soft_prst.s.soft_prst = 0;
796 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
797 } else {
798 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
799 ciu_soft_prst.s.soft_prst = 0;
800 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
801 }
802 }
803
804 /*
805 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
806 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
807 * fixed number of cycles.
808 */
809 cvmx_wait(400000);
810
811 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
812 CN52XX, so we only probe it on newer chips */
813 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
814 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
815 /* Clear PCLK_RUN so we can check if the clock is running */
816 pescx_ctl_status2.u64 =
817 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
818 pescx_ctl_status2.s.pclk_run = 1;
819 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
820 pescx_ctl_status2.u64);
821 /*
822 * Now that we cleared PCLK_RUN, wait for it to be set
823 * again telling us the clock is running.
824 */
825 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
826 union cvmx_pescx_ctl_status2,
827 pclk_run, ==, 1, 10000)) {
828 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
829 pcie_port);
830 return -1;
831 }
832 }
833
834 /*
835 * Check and make sure PCIe came out of reset. If it doesn't
836 * the board probably hasn't wired the clocks up and the
837 * interface should be skipped.
838 */
839 pescx_ctl_status2.u64 =
840 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
841 if (pescx_ctl_status2.s.pcierst) {
842 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
843 pcie_port);
844 return -1;
845 }
846
847 /*
848 * Check BIST2 status. If any bits are set skip this interface. This
849 * is an attempt to catch PCIE-813 on pass 1 parts.
850 */
851 pescx_bist_status2.u64 =
852 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
853 if (pescx_bist_status2.u64) {
854 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
855 "port isn't hooked up, skipping.\n",
856 pcie_port);
857 return -1;
858 }
859
860 /* Check BIST status */
861 pescx_bist_status.u64 =
862 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
863 if (pescx_bist_status.u64)
864 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
865 pcie_port, CAST64(pescx_bist_status.u64));
866
867 /* Initialize the config space CSRs */
868 __cvmx_pcie_rc_initialize_config_space(pcie_port);
869
870 /* Bring the link up */
871 if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
872 cvmx_dprintf
873 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
874 return -1;
875 }
876
877 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
878 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
879 /* Allow 16 words to combine */
880 npei_mem_access_ctl.s.max_word = 0;
881 /* Wait up to 127 cycles for more data */
882 npei_mem_access_ctl.s.timer = 127;
883 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
884
885 /* Setup Mem access SubDIDs */
886 mem_access_subid.u64 = 0;
887 /* Port the request is sent to. */
888 mem_access_subid.s.port = pcie_port;
889 /* Due to an errata on pass 1 chips, no merging is allowed. */
890 mem_access_subid.s.nmerge = 1;
891 /* Endian-swap for Reads. */
892 mem_access_subid.s.esr = 1;
893 /* Endian-swap for Writes. */
894 mem_access_subid.s.esw = 1;
895 /* No Snoop for Reads. */
896 mem_access_subid.s.nsr = 1;
897 /* No Snoop for Writes. */
898 mem_access_subid.s.nsw = 1;
899 /* Disable Relaxed Ordering for Reads. */
900 mem_access_subid.s.ror = 0;
901 /* Disable Relaxed Ordering for Writes. */
902 mem_access_subid.s.row = 0;
903 /* PCIe Address Bits <63:34>. */
904 mem_access_subid.s.ba = 0;
905
906 /*
907 * Setup mem access 12-15 for port 0, 16-19 for port 1,
908 * supplying 36 bits of address space.
909 */
910 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
911 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
912 mem_access_subid.u64);
913 /* Set each SUBID to extend the addressable range */
914 mem_access_subid.s.ba += 1;
915 }
916
917 /*
918 * Disable the peer to peer forwarding register. This must be
919 * setup by the OS after it enumerates the bus and assigns
920 * addresses to the PCIe busses.
921 */
922 for (i = 0; i < 4; i++) {
923 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
924 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
925 }
926
927 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
928 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
929
930 /* BAR1 follows BAR2 with a gap. */
931 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
932
933 bar1_index.u32 = 0;
934 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
935 bar1_index.s.ca = 1; /* Not Cached */
936 bar1_index.s.end_swp = 1; /* Endian Swap mode */
937 bar1_index.s.addr_v = 1; /* Valid entry */
938
939 base = pcie_port ? 16 : 0;
940
941 /* Big endian swizzle for 32-bit PEXP_NCB register. */
942#ifdef __MIPSEB__
943 addr_swizzle = 4;
944#else
945 addr_swizzle = 0;
946#endif
947 for (i = 0; i < 16; i++) {
948 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
949 bar1_index.u32);
950 base++;
951 /* 256MB / 16 >> 22 == 4 */
952 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
953 }
954
955 /*
956 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
957 * precedence where they overlap. It also overlaps with the
958 * device addresses, so make sure the peer to peer forwarding
959 * is set right.
960 */
961 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
962
963 /*
964 * Setup BAR2 attributes
965 *
966 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
967 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
968 * - WAIT_COM=0 will likely work for all applications.
969 *
970 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
971 */
972 if (pcie_port) {
973 union cvmx_npei_ctl_port1 npei_ctl_port;
974 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
975 npei_ctl_port.s.bar2_enb = 1;
976 npei_ctl_port.s.bar2_esx = 1;
977 npei_ctl_port.s.bar2_cax = 0;
978 npei_ctl_port.s.ptlp_ro = 1;
979 npei_ctl_port.s.ctlp_ro = 1;
980 npei_ctl_port.s.wait_com = 0;
981 npei_ctl_port.s.waitl_com = 0;
982 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
983 } else {
984 union cvmx_npei_ctl_port0 npei_ctl_port;
985 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
986 npei_ctl_port.s.bar2_enb = 1;
987 npei_ctl_port.s.bar2_esx = 1;
988 npei_ctl_port.s.bar2_cax = 0;
989 npei_ctl_port.s.ptlp_ro = 1;
990 npei_ctl_port.s.ctlp_ro = 1;
991 npei_ctl_port.s.wait_com = 0;
992 npei_ctl_port.s.waitl_com = 0;
993 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
994 }
995 return 0;
996}
997
998
999/* Above was cvmx-pcie.c, below original pcie.c */
1000
1001
1002/**
1003 * Map a PCI device to the appropriate interrupt line
1004 *
1005 * @dev: The Linux PCI device structure for the device to map
1006 * @slot: The slot number for this device on __BUS 0__. Linux
1007 * enumerates through all the bridges and figures out the
1008 * slot on Bus 0 where this device eventually hooks to.
1009 * @pin: The PCI interrupt pin read from the device, then swizzled
1010 * as it goes through each bridge.
1011 * Returns Interrupt number for the device
1012 */
1013int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1014 u8 slot, u8 pin)
1015{
1016 /*
1017 * The EBH5600 board with the PCI to PCIe bridge mistakenly
1018 * wires the first slot for both device id 2 and interrupt
1019 * A. According to the PCI spec, device id 2 should be C. The
1020 * following kludge attempts to fix this.
1021 */
1022 if (strstr(octeon_board_type_string(), "EBH5600") &&
1023 dev->bus && dev->bus->parent) {
1024 /*
1025 * Iterate all the way up the device chain and find
1026 * the root bus.
1027 */
1028 while (dev->bus && dev->bus->parent)
1029 dev = to_pci_dev(dev->bus->bridge);
1030 /* If the root bus is number 0 and the PEX 8114 is the
1031 * root, assume we are behind the miswired bus. We
1032 * need to correct the swizzle level by two. Yuck.
1033 */
1034 if ((dev->bus->number == 0) &&
1035 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1036 /*
1037 * The pin field is one based, not zero. We
1038 * need to swizzle it by minus two.
1039 */
1040 pin = ((pin - 3) & 3) + 1;
1041 }
1042 }
1043 /*
1044 * The -1 is because pin starts with one, not zero. It might
1045 * be that this equation needs to include the slot number, but
1046 * I don't have hardware to check that against.
1047 */
1048 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1049}
1050
1051/**
1052 * Read a value from configuration space
1053 *
1054 * @bus:
1055 * @devfn:
1056 * @reg:
1057 * @size:
1058 * @val:
1059 * Returns
1060 */
1061static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1062 unsigned int devfn, int reg, int size,
1063 u32 *val)
1064{
1065 union octeon_cvmemctl cvmmemctl;
1066 union octeon_cvmemctl cvmmemctl_save;
1067 int bus_number = bus->number;
1068
1069 /*
1070 * For the top level bus make sure our hardware bus number
1071 * matches the software one.
1072 */
1073 if (bus->parent == NULL) {
1074 union cvmx_pciercx_cfg006 pciercx_cfg006;
1075 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1076 CVMX_PCIERCX_CFG006(pcie_port));
1077 if (pciercx_cfg006.s.pbnum != bus_number) {
1078 pciercx_cfg006.s.pbnum = bus_number;
1079 pciercx_cfg006.s.sbnum = bus_number;
1080 pciercx_cfg006.s.subbnum = bus_number;
1081 cvmx_pcie_cfgx_write(pcie_port,
1082 CVMX_PCIERCX_CFG006(pcie_port),
1083 pciercx_cfg006.u32);
1084 }
1085 }
1086
1087 /*
1088 * PCIe only has a single device connected to Octeon. It is
1089 * always device ID 0. Don't bother doing reads for other
1090 * device IDs on the first segment.
1091 */
1092 if ((bus->parent == NULL) && (devfn >> 3 != 0))
1093 return PCIBIOS_FUNC_NOT_SUPPORTED;
1094
1095 /*
1096 * The following is a workaround for the CN57XX, CN56XX,
1097 * CN55XX, and CN54XX errata with PCIe config reads from non
1098 * existent devices. These chips will hang the PCIe link if a
1099 * config read is performed that causes a UR response.
1100 */
1101 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1102 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1103 /*
1104 * For our EBH5600 board, port 0 has a bridge with two
1105 * PCI-X slots. We need a new special checks to make
1106 * sure we only probe valid stuff. The PCIe->PCI-X
1107 * bridge only respondes to device ID 0, function
1108 * 0-1
1109 */
1110 if ((bus->parent == NULL) && (devfn >= 2))
1111 return PCIBIOS_FUNC_NOT_SUPPORTED;
1112 /*
1113 * The PCI-X slots are device ID 2,3. Choose one of
1114 * the below "if" blocks based on what is plugged into
1115 * the board.
1116 */
1117#if 1
1118 /* Use this option if you aren't using either slot */
1119 if (bus_number == 1)
1120 return PCIBIOS_FUNC_NOT_SUPPORTED;
1121#elif 0
1122 /*
1123 * Use this option if you are using the first slot but
1124 * not the second.
1125 */
1126 if ((bus_number == 1) && (devfn >> 3 != 2))
1127 return PCIBIOS_FUNC_NOT_SUPPORTED;
1128#elif 0
1129 /*
1130 * Use this option if you are using the second slot
1131 * but not the first.
1132 */
1133 if ((bus_number == 1) && (devfn >> 3 != 3))
1134 return PCIBIOS_FUNC_NOT_SUPPORTED;
1135#elif 0
1136 /* Use this opion if you are using both slots */
1137 if ((bus_number == 1) &&
1138 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1139 return PCIBIOS_FUNC_NOT_SUPPORTED;
1140#endif
1141
1142 /*
1143 * Shorten the DID timeout so bus errors for PCIe
1144 * config reads from non existent devices happen
1145 * faster. This allows us to continue booting even if
1146 * the above "if" checks are wrong. Once one of these
1147 * errors happens, the PCIe port is dead.
1148 */
1149 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1150 cvmmemctl.u64 = cvmmemctl_save.u64;
1151 cvmmemctl.s.didtto = 2;
1152 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1153 }
1154
1155 switch (size) {
1156 case 4:
1157 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1158 devfn >> 3, devfn & 0x7, reg);
1159 break;
1160 case 2:
1161 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1162 devfn >> 3, devfn & 0x7, reg);
1163 break;
1164 case 1:
1165 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
1166 devfn & 0x7, reg);
1167 break;
1168 default:
1169 return PCIBIOS_FUNC_NOT_SUPPORTED;
1170 }
1171
1172 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1173 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1174 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
1175 return PCIBIOS_SUCCESSFUL;
1176}
1177
1178static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1179 int reg, int size, u32 *val)
1180{
1181 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1182}
1183
1184static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1185 int reg, int size, u32 *val)
1186{
1187 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1188}
1189
1190
1191
1192/**
1193 * Write a value to PCI configuration space
1194 *
1195 * @bus:
1196 * @devfn:
1197 * @reg:
1198 * @size:
1199 * @val:
1200 * Returns
1201 */
1202static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1203 unsigned int devfn, int reg,
1204 int size, u32 val)
1205{
1206 int bus_number = bus->number;
1207
1208 switch (size) {
1209 case 4:
1210 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1211 devfn & 0x7, reg, val);
1212 return PCIBIOS_SUCCESSFUL;
1213 case 2:
1214 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1215 devfn & 0x7, reg, val);
1216 return PCIBIOS_SUCCESSFUL;
1217 case 1:
1218 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1219 devfn & 0x7, reg, val);
1220 return PCIBIOS_SUCCESSFUL;
1221 }
1222#if PCI_CONFIG_SPACE_DELAY
1223 udelay(PCI_CONFIG_SPACE_DELAY);
1224#endif
1225 return PCIBIOS_FUNC_NOT_SUPPORTED;
1226}
1227
1228static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1229 int reg, int size, u32 val)
1230{
1231 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1232}
1233
1234static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1235 int reg, int size, u32 val)
1236{
1237 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1238}
1239
1240static struct pci_ops octeon_pcie0_ops = {
1241 octeon_pcie0_read_config,
1242 octeon_pcie0_write_config,
1243};
1244
1245static struct resource octeon_pcie0_mem_resource = {
1246 .name = "Octeon PCIe0 MEM",
1247 .flags = IORESOURCE_MEM,
1248};
1249
1250static struct resource octeon_pcie0_io_resource = {
1251 .name = "Octeon PCIe0 IO",
1252 .flags = IORESOURCE_IO,
1253};
1254
1255static struct pci_controller octeon_pcie0_controller = {
1256 .pci_ops = &octeon_pcie0_ops,
1257 .mem_resource = &octeon_pcie0_mem_resource,
1258 .io_resource = &octeon_pcie0_io_resource,
1259};
1260
1261static struct pci_ops octeon_pcie1_ops = {
1262 octeon_pcie1_read_config,
1263 octeon_pcie1_write_config,
1264};
1265
1266static struct resource octeon_pcie1_mem_resource = {
1267 .name = "Octeon PCIe1 MEM",
1268 .flags = IORESOURCE_MEM,
1269};
1270
1271static struct resource octeon_pcie1_io_resource = {
1272 .name = "Octeon PCIe1 IO",
1273 .flags = IORESOURCE_IO,
1274};
1275
1276static struct pci_controller octeon_pcie1_controller = {
1277 .pci_ops = &octeon_pcie1_ops,
1278 .mem_resource = &octeon_pcie1_mem_resource,
1279 .io_resource = &octeon_pcie1_io_resource,
1280};
1281
1282
1283/**
1284 * Initialize the Octeon PCIe controllers
1285 *
1286 * Returns
1287 */
1288static int __init octeon_pcie_setup(void)
1289{
1290 union cvmx_npei_ctl_status npei_ctl_status;
1291 int result;
1292
1293 /* These chips don't have PCIe */
1294 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1295 return 0;
1296
1297 /* Point pcibios_map_irq() to the PCIe version of it */
1298 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1299
1300 /* Use the PCIe based DMA mappings */
1301 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1302
1303 /*
1304 * PCIe I/O range. It is based on port 0 but includes up until
1305 * port 1's end.
1306 */
1307 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1308 ioport_resource.start = 0;
1309 ioport_resource.end =
1310 cvmx_pcie_get_io_base_address(1) -
1311 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1312
1313 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1314 if (npei_ctl_status.s.host_mode) {
1315 pr_notice("PCIe: Initializing port 0\n");
1316 result = cvmx_pcie_rc_initialize(0);
1317 if (result == 0) {
1318 /* Memory offsets are physical addresses */
1319 octeon_pcie0_controller.mem_offset =
1320 cvmx_pcie_get_mem_base_address(0);
1321 /* IO offsets are Mips virtual addresses */
1322 octeon_pcie0_controller.io_map_base =
1323 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1324 (0));
1325 octeon_pcie0_controller.io_offset = 0;
1326 /*
1327 * To keep things similar to PCI, we start
1328 * device addresses at the same place as PCI
1329 * uisng big bar support. This normally
1330 * translates to 4GB-256MB, which is the same
1331 * as most x86 PCs.
1332 */
1333 octeon_pcie0_controller.mem_resource->start =
1334 cvmx_pcie_get_mem_base_address(0) +
1335 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1336 octeon_pcie0_controller.mem_resource->end =
1337 cvmx_pcie_get_mem_base_address(0) +
1338 cvmx_pcie_get_mem_size(0) - 1;
1339 /*
1340 * Ports must be above 16KB for the ISA bus
1341 * filtering in the PCI-X to PCI bridge.
1342 */
1343 octeon_pcie0_controller.io_resource->start = 4 << 10;
1344 octeon_pcie0_controller.io_resource->end =
1345 cvmx_pcie_get_io_size(0) - 1;
1346 register_pci_controller(&octeon_pcie0_controller);
1347 }
1348 } else {
1349 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1350 }
1351
1352 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1353 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1354 union cvmx_npei_dbg_data npei_dbg_data;
1355 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1356 if (npei_dbg_data.cn52xx.qlm0_link_width)
1357 return 0;
1358 }
1359
1360 pr_notice("PCIe: Initializing port 1\n");
1361 result = cvmx_pcie_rc_initialize(1);
1362 if (result == 0) {
1363 /* Memory offsets are physical addresses */
1364 octeon_pcie1_controller.mem_offset =
1365 cvmx_pcie_get_mem_base_address(1);
1366 /* IO offsets are Mips virtual addresses */
1367 octeon_pcie1_controller.io_map_base =
1368 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1369 octeon_pcie1_controller.io_offset =
1370 cvmx_pcie_get_io_base_address(1) -
1371 cvmx_pcie_get_io_base_address(0);
1372 /*
1373 * To keep things similar to PCI, we start device
1374 * addresses at the same place as PCI uisng big bar
1375 * support. This normally translates to 4GB-256MB,
1376 * which is the same as most x86 PCs.
1377 */
1378 octeon_pcie1_controller.mem_resource->start =
1379 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1380 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1381 octeon_pcie1_controller.mem_resource->end =
1382 cvmx_pcie_get_mem_base_address(1) +
1383 cvmx_pcie_get_mem_size(1) - 1;
1384 /*
1385 * Ports must be above 16KB for the ISA bus filtering
1386 * in the PCI-X to PCI bridge.
1387 */
1388 octeon_pcie1_controller.io_resource->start =
1389 cvmx_pcie_get_io_base_address(1) -
1390 cvmx_pcie_get_io_base_address(0);
1391 octeon_pcie1_controller.io_resource->end =
1392 octeon_pcie1_controller.io_resource->start +
1393 cvmx_pcie_get_io_size(1) - 1;
1394 register_pci_controller(&octeon_pcie1_controller);
1395 }
1396
1397 octeon_pci_dma_init();
1398
1399 return 0;
1400}
1401
1402arch_initcall(octeon_pcie_setup);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008, 2009, 2010, 2011 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include <linux/module.h>
15
16#include <asm/octeon/octeon.h>
17#include <asm/octeon/cvmx-npei-defs.h>
18#include <asm/octeon/cvmx-pciercx-defs.h>
19#include <asm/octeon/cvmx-pescx-defs.h>
20#include <asm/octeon/cvmx-pexp-defs.h>
21#include <asm/octeon/cvmx-pemx-defs.h>
22#include <asm/octeon/cvmx-dpi-defs.h>
23#include <asm/octeon/cvmx-sli-defs.h>
24#include <asm/octeon/cvmx-sriox-defs.h>
25#include <asm/octeon/cvmx-helper-errata.h>
26#include <asm/octeon/pci-octeon.h>
27
28#define MRRS_CN5XXX 0 /* 128 byte Max Read Request Size */
29#define MPS_CN5XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
30#define MRRS_CN6XXX 3 /* 1024 byte Max Read Request Size */
31#define MPS_CN6XXX 0 /* 128 byte Max Packet Size (Limit of most PCs) */
32
33/* Module parameter to disable PCI probing */
34static int pcie_disable;
35module_param(pcie_disable, int, S_IRUGO);
36
37static int enable_pcie_14459_war;
38static int enable_pcie_bus_num_war[2];
39
40union cvmx_pcie_address {
41 uint64_t u64;
42 struct {
43 uint64_t upper:2; /* Normally 2 for XKPHYS */
44 uint64_t reserved_49_61:13; /* Must be zero */
45 uint64_t io:1; /* 1 for IO space access */
46 uint64_t did:5; /* PCIe DID = 3 */
47 uint64_t subdid:3; /* PCIe SubDID = 1 */
48 uint64_t reserved_36_39:4; /* Must be zero */
49 uint64_t es:2; /* Endian swap = 1 */
50 uint64_t port:2; /* PCIe port 0,1 */
51 uint64_t reserved_29_31:3; /* Must be zero */
52 /*
53 * Selects the type of the configuration request (0 = type 0,
54 * 1 = type 1).
55 */
56 uint64_t ty:1;
57 /* Target bus number sent in the ID in the request. */
58 uint64_t bus:8;
59 /*
60 * Target device number sent in the ID in the
61 * request. Note that Dev must be zero for type 0
62 * configuration requests.
63 */
64 uint64_t dev:5;
65 /* Target function number sent in the ID in the request. */
66 uint64_t func:3;
67 /*
68 * Selects a register in the configuration space of
69 * the target.
70 */
71 uint64_t reg:12;
72 } config;
73 struct {
74 uint64_t upper:2; /* Normally 2 for XKPHYS */
75 uint64_t reserved_49_61:13; /* Must be zero */
76 uint64_t io:1; /* 1 for IO space access */
77 uint64_t did:5; /* PCIe DID = 3 */
78 uint64_t subdid:3; /* PCIe SubDID = 2 */
79 uint64_t reserved_36_39:4; /* Must be zero */
80 uint64_t es:2; /* Endian swap = 1 */
81 uint64_t port:2; /* PCIe port 0,1 */
82 uint64_t address:32; /* PCIe IO address */
83 } io;
84 struct {
85 uint64_t upper:2; /* Normally 2 for XKPHYS */
86 uint64_t reserved_49_61:13; /* Must be zero */
87 uint64_t io:1; /* 1 for IO space access */
88 uint64_t did:5; /* PCIe DID = 3 */
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
90 uint64_t reserved_36_39:4; /* Must be zero */
91 uint64_t address:36; /* PCIe Mem address */
92 } mem;
93};
94
95static int cvmx_pcie_rc_initialize(int pcie_port);
96
97#include <dma-coherence.h>
98
99/**
100 * Return the Core virtual base address for PCIe IO access. IOs are
101 * read/written as an offset from this address.
102 *
103 * @pcie_port: PCIe port the IO is for
104 *
105 * Returns 64bit Octeon IO base address for read/write
106 */
107static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
108{
109 union cvmx_pcie_address pcie_addr;
110 pcie_addr.u64 = 0;
111 pcie_addr.io.upper = 0;
112 pcie_addr.io.io = 1;
113 pcie_addr.io.did = 3;
114 pcie_addr.io.subdid = 2;
115 pcie_addr.io.es = 1;
116 pcie_addr.io.port = pcie_port;
117 return pcie_addr.u64;
118}
119
120/**
121 * Size of the IO address region returned at address
122 * cvmx_pcie_get_io_base_address()
123 *
124 * @pcie_port: PCIe port the IO is for
125 *
126 * Returns Size of the IO window
127 */
128static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
129{
130 return 1ull << 32;
131}
132
133/**
134 * Return the Core virtual base address for PCIe MEM access. Memory is
135 * read/written as an offset from this address.
136 *
137 * @pcie_port: PCIe port the IO is for
138 *
139 * Returns 64bit Octeon IO base address for read/write
140 */
141static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
142{
143 union cvmx_pcie_address pcie_addr;
144 pcie_addr.u64 = 0;
145 pcie_addr.mem.upper = 0;
146 pcie_addr.mem.io = 1;
147 pcie_addr.mem.did = 3;
148 pcie_addr.mem.subdid = 3 + pcie_port;
149 return pcie_addr.u64;
150}
151
152/**
153 * Size of the Mem address region returned at address
154 * cvmx_pcie_get_mem_base_address()
155 *
156 * @pcie_port: PCIe port the IO is for
157 *
158 * Returns Size of the Mem window
159 */
160static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
161{
162 return 1ull << 36;
163}
164
165/**
166 * Read a PCIe config space register indirectly. This is used for
167 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
168 *
169 * @pcie_port: PCIe port to read from
170 * @cfg_offset: Address to read
171 *
172 * Returns Value read
173 */
174static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
175{
176 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
177 union cvmx_pescx_cfg_rd pescx_cfg_rd;
178 pescx_cfg_rd.u64 = 0;
179 pescx_cfg_rd.s.addr = cfg_offset;
180 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
181 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
182 return pescx_cfg_rd.s.data;
183 } else {
184 union cvmx_pemx_cfg_rd pemx_cfg_rd;
185 pemx_cfg_rd.u64 = 0;
186 pemx_cfg_rd.s.addr = cfg_offset;
187 cvmx_write_csr(CVMX_PEMX_CFG_RD(pcie_port), pemx_cfg_rd.u64);
188 pemx_cfg_rd.u64 = cvmx_read_csr(CVMX_PEMX_CFG_RD(pcie_port));
189 return pemx_cfg_rd.s.data;
190 }
191}
192
193/**
194 * Write a PCIe config space register indirectly. This is used for
195 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
196 *
197 * @pcie_port: PCIe port to write to
198 * @cfg_offset: Address to write
199 * @val: Value to write
200 */
201static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
202 uint32_t val)
203{
204 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
205 union cvmx_pescx_cfg_wr pescx_cfg_wr;
206 pescx_cfg_wr.u64 = 0;
207 pescx_cfg_wr.s.addr = cfg_offset;
208 pescx_cfg_wr.s.data = val;
209 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
210 } else {
211 union cvmx_pemx_cfg_wr pemx_cfg_wr;
212 pemx_cfg_wr.u64 = 0;
213 pemx_cfg_wr.s.addr = cfg_offset;
214 pemx_cfg_wr.s.data = val;
215 cvmx_write_csr(CVMX_PEMX_CFG_WR(pcie_port), pemx_cfg_wr.u64);
216 }
217}
218
219/**
220 * Build a PCIe config space request address for a device
221 *
222 * @pcie_port: PCIe port to access
223 * @bus: Sub bus
224 * @dev: Device ID
225 * @fn: Device sub function
226 * @reg: Register to access
227 *
228 * Returns 64bit Octeon IO address
229 */
230static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
231 int dev, int fn, int reg)
232{
233 union cvmx_pcie_address pcie_addr;
234 union cvmx_pciercx_cfg006 pciercx_cfg006;
235
236 pciercx_cfg006.u32 =
237 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
238 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
239 return 0;
240
241 pcie_addr.u64 = 0;
242 pcie_addr.config.upper = 2;
243 pcie_addr.config.io = 1;
244 pcie_addr.config.did = 3;
245 pcie_addr.config.subdid = 1;
246 pcie_addr.config.es = 1;
247 pcie_addr.config.port = pcie_port;
248 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
249 pcie_addr.config.bus = bus;
250 pcie_addr.config.dev = dev;
251 pcie_addr.config.func = fn;
252 pcie_addr.config.reg = reg;
253 return pcie_addr.u64;
254}
255
256/**
257 * Read 8bits from a Device's config space
258 *
259 * @pcie_port: PCIe port the device is on
260 * @bus: Sub bus
261 * @dev: Device ID
262 * @fn: Device sub function
263 * @reg: Register to access
264 *
265 * Returns Result of the read
266 */
267static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
268 int fn, int reg)
269{
270 uint64_t address =
271 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
272 if (address)
273 return cvmx_read64_uint8(address);
274 else
275 return 0xff;
276}
277
278/**
279 * Read 16bits from a Device's config space
280 *
281 * @pcie_port: PCIe port the device is on
282 * @bus: Sub bus
283 * @dev: Device ID
284 * @fn: Device sub function
285 * @reg: Register to access
286 *
287 * Returns Result of the read
288 */
289static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
290 int fn, int reg)
291{
292 uint64_t address =
293 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
294 if (address)
295 return le16_to_cpu(cvmx_read64_uint16(address));
296 else
297 return 0xffff;
298}
299
300/**
301 * Read 32bits from a Device's config space
302 *
303 * @pcie_port: PCIe port the device is on
304 * @bus: Sub bus
305 * @dev: Device ID
306 * @fn: Device sub function
307 * @reg: Register to access
308 *
309 * Returns Result of the read
310 */
311static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
312 int fn, int reg)
313{
314 uint64_t address =
315 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
316 if (address)
317 return le32_to_cpu(cvmx_read64_uint32(address));
318 else
319 return 0xffffffff;
320}
321
322/**
323 * Write 8bits to a Device's config space
324 *
325 * @pcie_port: PCIe port the device is on
326 * @bus: Sub bus
327 * @dev: Device ID
328 * @fn: Device sub function
329 * @reg: Register to access
330 * @val: Value to write
331 */
332static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
333 int reg, uint8_t val)
334{
335 uint64_t address =
336 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
337 if (address)
338 cvmx_write64_uint8(address, val);
339}
340
341/**
342 * Write 16bits to a Device's config space
343 *
344 * @pcie_port: PCIe port the device is on
345 * @bus: Sub bus
346 * @dev: Device ID
347 * @fn: Device sub function
348 * @reg: Register to access
349 * @val: Value to write
350 */
351static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
352 int reg, uint16_t val)
353{
354 uint64_t address =
355 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
356 if (address)
357 cvmx_write64_uint16(address, cpu_to_le16(val));
358}
359
360/**
361 * Write 32bits to a Device's config space
362 *
363 * @pcie_port: PCIe port the device is on
364 * @bus: Sub bus
365 * @dev: Device ID
366 * @fn: Device sub function
367 * @reg: Register to access
368 * @val: Value to write
369 */
370static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
371 int reg, uint32_t val)
372{
373 uint64_t address =
374 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
375 if (address)
376 cvmx_write64_uint32(address, cpu_to_le32(val));
377}
378
379/**
380 * Initialize the RC config space CSRs
381 *
382 * @pcie_port: PCIe port to initialize
383 */
384static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
385{
386 union cvmx_pciercx_cfg030 pciercx_cfg030;
387 union cvmx_pciercx_cfg070 pciercx_cfg070;
388 union cvmx_pciercx_cfg001 pciercx_cfg001;
389 union cvmx_pciercx_cfg032 pciercx_cfg032;
390 union cvmx_pciercx_cfg006 pciercx_cfg006;
391 union cvmx_pciercx_cfg008 pciercx_cfg008;
392 union cvmx_pciercx_cfg009 pciercx_cfg009;
393 union cvmx_pciercx_cfg010 pciercx_cfg010;
394 union cvmx_pciercx_cfg011 pciercx_cfg011;
395 union cvmx_pciercx_cfg035 pciercx_cfg035;
396 union cvmx_pciercx_cfg075 pciercx_cfg075;
397 union cvmx_pciercx_cfg034 pciercx_cfg034;
398
399 /* Max Payload Size (PCIE*_CFG030[MPS]) */
400 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
401 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
402 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
403
404 pciercx_cfg030.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
405 if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
406 pciercx_cfg030.s.mps = MPS_CN5XXX;
407 pciercx_cfg030.s.mrrs = MRRS_CN5XXX;
408 } else {
409 pciercx_cfg030.s.mps = MPS_CN6XXX;
410 pciercx_cfg030.s.mrrs = MRRS_CN6XXX;
411 }
412 /*
413 * Enable relaxed order processing. This will allow devices to
414 * affect read response ordering.
415 */
416 pciercx_cfg030.s.ro_en = 1;
417 /* Enable no snoop processing. Not used by Octeon */
418 pciercx_cfg030.s.ns_en = 1;
419 /* Correctable error reporting enable. */
420 pciercx_cfg030.s.ce_en = 1;
421 /* Non-fatal error reporting enable. */
422 pciercx_cfg030.s.nfe_en = 1;
423 /* Fatal error reporting enable. */
424 pciercx_cfg030.s.fe_en = 1;
425 /* Unsupported request reporting enable. */
426 pciercx_cfg030.s.ur_en = 1;
427 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port), pciercx_cfg030.u32);
428
429
430 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
431 union cvmx_npei_ctl_status2 npei_ctl_status2;
432 /*
433 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
434 * PCIE*_CFG030[MPS]. Max Read Request Size
435 * (NPEI_CTL_STATUS2[MRRS]) must not exceed
436 * PCIE*_CFG030[MRRS]
437 */
438 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
439 /* Max payload size = 128 bytes for best Octeon DMA performance */
440 npei_ctl_status2.s.mps = MPS_CN5XXX;
441 /* Max read request size = 128 bytes for best Octeon DMA performance */
442 npei_ctl_status2.s.mrrs = MRRS_CN5XXX;
443 if (pcie_port)
444 npei_ctl_status2.s.c1_b1_s = 3; /* Port1 BAR1 Size 256MB */
445 else
446 npei_ctl_status2.s.c0_b1_s = 3; /* Port0 BAR1 Size 256MB */
447
448 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
449 } else {
450 /*
451 * Max Payload Size (DPI_SLI_PRTX_CFG[MPS]) must match
452 * PCIE*_CFG030[MPS]. Max Read Request Size
453 * (DPI_SLI_PRTX_CFG[MRRS]) must not exceed
454 * PCIE*_CFG030[MRRS].
455 */
456 union cvmx_dpi_sli_prtx_cfg prt_cfg;
457 union cvmx_sli_s2m_portx_ctl sli_s2m_portx_ctl;
458 prt_cfg.u64 = cvmx_read_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port));
459 prt_cfg.s.mps = MPS_CN6XXX;
460 prt_cfg.s.mrrs = MRRS_CN6XXX;
461 /* Max outstanding load request. */
462 prt_cfg.s.molr = 32;
463 cvmx_write_csr(CVMX_DPI_SLI_PRTX_CFG(pcie_port), prt_cfg.u64);
464
465 sli_s2m_portx_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port));
466 sli_s2m_portx_ctl.s.mrrs = MRRS_CN6XXX;
467 cvmx_write_csr(CVMX_PEXP_SLI_S2M_PORTX_CTL(pcie_port), sli_s2m_portx_ctl.u64);
468 }
469
470 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
471 pciercx_cfg070.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
472 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
473 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
474 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port), pciercx_cfg070.u32);
475
476 /*
477 * Access Enables (PCIE*_CFG001[MSAE,ME])
478 * ME and MSAE should always be set.
479 * Interrupt Disable (PCIE*_CFG001[I_DIS])
480 * System Error Message Enable (PCIE*_CFG001[SEE])
481 */
482 pciercx_cfg001.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
483 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
484 pciercx_cfg001.s.me = 1; /* Bus master enable. */
485 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
486 pciercx_cfg001.s.see = 1; /* SERR# enable */
487 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port), pciercx_cfg001.u32);
488
489 /* Advanced Error Recovery Message Enables */
490 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
491 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
492 /* Use CVMX_PCIERCX_CFG067 hardware default */
493 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
494
495
496 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
497 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
498 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
499 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port), pciercx_cfg032.u32);
500
501 /*
502 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
503 * cvmx_pcie_rc_initialize_link()
504 *
505 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
506 *
507 * We set the primary bus number to 1 so IDT bridges are
508 * happy. They don't like zero.
509 */
510 pciercx_cfg006.u32 = 0;
511 pciercx_cfg006.s.pbnum = 1;
512 pciercx_cfg006.s.sbnum = 1;
513 pciercx_cfg006.s.subbnum = 1;
514 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port), pciercx_cfg006.u32);
515
516
517 /*
518 * Memory-mapped I/O BAR (PCIERCn_CFG008)
519 * Most applications should disable the memory-mapped I/O BAR by
520 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
521 */
522 pciercx_cfg008.u32 = 0;
523 pciercx_cfg008.s.mb_addr = 0x100;
524 pciercx_cfg008.s.ml_addr = 0;
525 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port), pciercx_cfg008.u32);
526
527
528 /*
529 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
530 * Most applications should disable the prefetchable BAR by setting
531 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
532 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
533 */
534 pciercx_cfg009.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
535 pciercx_cfg010.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
536 pciercx_cfg011.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
537 pciercx_cfg009.s.lmem_base = 0x100;
538 pciercx_cfg009.s.lmem_limit = 0;
539 pciercx_cfg010.s.umem_base = 0x100;
540 pciercx_cfg011.s.umem_limit = 0;
541 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port), pciercx_cfg009.u32);
542 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port), pciercx_cfg010.u32);
543 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port), pciercx_cfg011.u32);
544
545 /*
546 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
547 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
548 */
549 pciercx_cfg035.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
550 pciercx_cfg035.s.secee = 1; /* System error on correctable error enable. */
551 pciercx_cfg035.s.sefee = 1; /* System error on fatal error enable. */
552 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */
553 pciercx_cfg035.s.pmeie = 1; /* PME interrupt enable. */
554 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port), pciercx_cfg035.u32);
555
556 /*
557 * Advanced Error Recovery Interrupt Enables
558 * (PCIERCn_CFG075[CERE,NFERE,FERE])
559 */
560 pciercx_cfg075.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
561 pciercx_cfg075.s.cere = 1; /* Correctable error reporting enable. */
562 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */
563 pciercx_cfg075.s.fere = 1; /* Fatal error reporting enable. */
564 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port), pciercx_cfg075.u32);
565
566 /*
567 * HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
568 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
569 */
570 pciercx_cfg034.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
571 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */
572 pciercx_cfg034.s.dlls_en = 1; /* Data Link Layer state changed enable */
573 pciercx_cfg034.s.ccint_en = 1; /* Command completed interrupt enable. */
574 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port), pciercx_cfg034.u32);
575}
576
577/**
578 * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
579 * port from reset to a link up state. Software can then begin
580 * configuring the rest of the link.
581 *
582 * @pcie_port: PCIe port to initialize
583 *
584 * Returns Zero on success
585 */
586static int __cvmx_pcie_rc_initialize_link_gen1(int pcie_port)
587{
588 uint64_t start_cycle;
589 union cvmx_pescx_ctl_status pescx_ctl_status;
590 union cvmx_pciercx_cfg452 pciercx_cfg452;
591 union cvmx_pciercx_cfg032 pciercx_cfg032;
592 union cvmx_pciercx_cfg448 pciercx_cfg448;
593
594 /* Set the lane width */
595 pciercx_cfg452.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
596 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
597 if (pescx_ctl_status.s.qlm_cfg == 0)
598 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
599 pciercx_cfg452.s.lme = 0xf;
600 else
601 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
602 pciercx_cfg452.s.lme = 0x7;
603 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port), pciercx_cfg452.u32);
604
605 /*
606 * CN52XX pass 1.x has an errata where length mismatches on UR
607 * responses can cause bus errors on 64bit memory
608 * reads. Turning off length error checking fixes this.
609 */
610 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
611 union cvmx_pciercx_cfg455 pciercx_cfg455;
612 pciercx_cfg455.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG455(pcie_port));
613 pciercx_cfg455.s.m_cpl_len_err = 1;
614 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port), pciercx_cfg455.u32);
615 }
616
617 /* Lane swap needs to be manually enabled for CN52XX */
618 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
619 pescx_ctl_status.s.lane_swp = 1;
620 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
621 }
622
623 /* Bring up the link */
624 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
625 pescx_ctl_status.s.lnk_enb = 1;
626 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
627
628 /*
629 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
630 * be disabled.
631 */
632 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
633 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
634
635 /* Wait for the link to come up */
636 start_cycle = cvmx_get_cycle();
637 do {
638 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) {
639 cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port);
640 return -1;
641 }
642 cvmx_wait(10000);
643 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
644 } while (pciercx_cfg032.s.dlla == 0);
645
646 /* Clear all pending errors */
647 cvmx_write_csr(CVMX_PEXP_NPEI_INT_SUM, cvmx_read_csr(CVMX_PEXP_NPEI_INT_SUM));
648
649 /*
650 * Update the Replay Time Limit. Empirically, some PCIe
651 * devices take a little longer to respond than expected under
652 * load. As a workaround for this we configure the Replay Time
653 * Limit to the value expected for a 512 byte MPS instead of
654 * our actual 256 byte MPS. The numbers below are directly
655 * from the PCIe spec table 3-4.
656 */
657 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
658 switch (pciercx_cfg032.s.nlw) {
659 case 1: /* 1 lane */
660 pciercx_cfg448.s.rtl = 1677;
661 break;
662 case 2: /* 2 lanes */
663 pciercx_cfg448.s.rtl = 867;
664 break;
665 case 4: /* 4 lanes */
666 pciercx_cfg448.s.rtl = 462;
667 break;
668 case 8: /* 8 lanes */
669 pciercx_cfg448.s.rtl = 258;
670 break;
671 }
672 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
673
674 return 0;
675}
676
677static void __cvmx_increment_ba(union cvmx_sli_mem_access_subidx *pmas)
678{
679 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
680 pmas->cn68xx.ba++;
681 else
682 pmas->cn63xx.ba++;
683}
684
685/**
686 * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
687 * enumerate the bus.
688 *
689 * @pcie_port: PCIe port to initialize
690 *
691 * Returns Zero on success
692 */
693static int __cvmx_pcie_rc_initialize_gen1(int pcie_port)
694{
695 int i;
696 int base;
697 u64 addr_swizzle;
698 union cvmx_ciu_soft_prst ciu_soft_prst;
699 union cvmx_pescx_bist_status pescx_bist_status;
700 union cvmx_pescx_bist_status2 pescx_bist_status2;
701 union cvmx_npei_ctl_status npei_ctl_status;
702 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
703 union cvmx_npei_mem_access_subidx mem_access_subid;
704 union cvmx_npei_dbg_data npei_dbg_data;
705 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
706 union cvmx_pciercx_cfg032 pciercx_cfg032;
707 union cvmx_npei_bar1_indexx bar1_index;
708
709retry:
710 /*
711 * Make sure we aren't trying to setup a target mode interface
712 * in host mode.
713 */
714 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
715 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
716 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port);
717 return -1;
718 }
719
720 /*
721 * Make sure a CN52XX isn't trying to bring up port 1 when it
722 * is disabled.
723 */
724 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
725 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
726 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
727 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n");
728 return -1;
729 }
730 }
731
732 /*
733 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
734 * PCIe0, then PCIe1. '1' == round robin.
735 */
736 npei_ctl_status.s.arb = 1;
737 /* Allow up to 0x20 config retries */
738 npei_ctl_status.s.cfg_rtry = 0x20;
739 /*
740 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
741 * don't reset.
742 */
743 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
744 npei_ctl_status.s.p0_ntags = 0x20;
745 npei_ctl_status.s.p1_ntags = 0x20;
746 }
747 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
748
749 /* Bring the PCIe out of reset */
750 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
751 /*
752 * The EBH5200 board swapped the PCIe reset lines on
753 * the board. As a workaround for this bug, we bring
754 * both PCIe ports out of reset at the same time
755 * instead of on separate calls. So for port 0, we
756 * bring both out of reset and do nothing on port 1
757 */
758 if (pcie_port == 0) {
759 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
760 /*
761 * After a chip reset the PCIe will also be in
762 * reset. If it isn't, most likely someone is
763 * trying to init it again without a proper
764 * PCIe reset.
765 */
766 if (ciu_soft_prst.s.soft_prst == 0) {
767 /* Reset the ports */
768 ciu_soft_prst.s.soft_prst = 1;
769 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
770 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
771 ciu_soft_prst.s.soft_prst = 1;
772 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
773 /* Wait until pcie resets the ports. */
774 udelay(2000);
775 }
776 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
777 ciu_soft_prst.s.soft_prst = 0;
778 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
779 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
780 ciu_soft_prst.s.soft_prst = 0;
781 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
782 }
783 } else {
784 /*
785 * The normal case: The PCIe ports are completely
786 * separate and can be brought out of reset
787 * independently.
788 */
789 if (pcie_port)
790 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
791 else
792 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
793 /*
794 * After a chip reset the PCIe will also be in
795 * reset. If it isn't, most likely someone is trying
796 * to init it again without a proper PCIe reset.
797 */
798 if (ciu_soft_prst.s.soft_prst == 0) {
799 /* Reset the port */
800 ciu_soft_prst.s.soft_prst = 1;
801 if (pcie_port)
802 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
803 else
804 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
805 /* Wait until pcie resets the ports. */
806 udelay(2000);
807 }
808 if (pcie_port) {
809 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
810 ciu_soft_prst.s.soft_prst = 0;
811 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
812 } else {
813 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
814 ciu_soft_prst.s.soft_prst = 0;
815 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
816 }
817 }
818
819 /*
820 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
821 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
822 * fixed number of cycles.
823 */
824 cvmx_wait(400000);
825
826 /*
827 * PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of
828 * CN56XX and CN52XX, so we only probe it on newer chips
829 */
830 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
831 /* Clear PCLK_RUN so we can check if the clock is running */
832 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
833 pescx_ctl_status2.s.pclk_run = 1;
834 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port), pescx_ctl_status2.u64);
835 /* Now that we cleared PCLK_RUN, wait for it to be set
836 * again telling us the clock is running
837 */
838 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
839 union cvmx_pescx_ctl_status2, pclk_run, ==, 1, 10000)) {
840 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port);
841 return -1;
842 }
843 }
844
845 /*
846 * Check and make sure PCIe came out of reset. If it doesn't
847 * the board probably hasn't wired the clocks up and the
848 * interface should be skipped.
849 */
850 pescx_ctl_status2.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
851 if (pescx_ctl_status2.s.pcierst) {
852 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
853 return -1;
854 }
855
856 /*
857 * Check BIST2 status. If any bits are set skip this
858 * interface. This is an attempt to catch PCIE-813 on pass 1
859 * parts.
860 */
861 pescx_bist_status2.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
862 if (pescx_bist_status2.u64) {
863 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n",
864 pcie_port);
865 return -1;
866 }
867
868 /* Check BIST status */
869 pescx_bist_status.u64 = cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
870 if (pescx_bist_status.u64)
871 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
872 pcie_port, CAST64(pescx_bist_status.u64));
873
874 /* Initialize the config space CSRs */
875 __cvmx_pcie_rc_initialize_config_space(pcie_port);
876
877 /* Bring the link up */
878 if (__cvmx_pcie_rc_initialize_link_gen1(pcie_port)) {
879 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n",
880 pcie_port);
881 return -1;
882 }
883
884 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
885 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
886 npei_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
887 npei_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
888 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
889
890 /* Setup Mem access SubDIDs */
891 mem_access_subid.u64 = 0;
892 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
893 mem_access_subid.s.nmerge = 1; /* Due to an errata on pass 1 chips, no merging is allowed. */
894 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
895 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
896 mem_access_subid.s.nsr = 0; /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
897 mem_access_subid.s.nsw = 0; /* Enable Snoop for Writes. */
898 mem_access_subid.s.ror = 0; /* Disable Relaxed Ordering for Reads. */
899 mem_access_subid.s.row = 0; /* Disable Relaxed Ordering for Writes. */
900 mem_access_subid.s.ba = 0; /* PCIe Adddress Bits <63:34>. */
901
902 /*
903 * Setup mem access 12-15 for port 0, 16-19 for port 1,
904 * supplying 36 bits of address space.
905 */
906 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
907 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
908 mem_access_subid.s.ba += 1; /* Set each SUBID to extend the addressable range */
909 }
910
911 /*
912 * Disable the peer to peer forwarding register. This must be
913 * setup by the OS after it enumerates the bus and assigns
914 * addresses to the PCIe busses.
915 */
916 for (i = 0; i < 4; i++) {
917 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
918 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
919 }
920
921 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
922 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
923
924 /* BAR1 follows BAR2 with a gap so it has the same address as for gen2. */
925 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
926
927 bar1_index.u32 = 0;
928 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
929 bar1_index.s.ca = 1; /* Not Cached */
930 bar1_index.s.end_swp = 1; /* Endian Swap mode */
931 bar1_index.s.addr_v = 1; /* Valid entry */
932
933 base = pcie_port ? 16 : 0;
934
935 /* Big endian swizzle for 32-bit PEXP_NCB register. */
936#ifdef __MIPSEB__
937 addr_swizzle = 4;
938#else
939 addr_swizzle = 0;
940#endif
941 for (i = 0; i < 16; i++) {
942 cvmx_write64_uint32((CVMX_PEXP_NPEI_BAR1_INDEXX(base) ^ addr_swizzle),
943 bar1_index.u32);
944 base++;
945 /* 256MB / 16 >> 22 == 4 */
946 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
947 }
948
949 /*
950 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
951 * precedence where they overlap. It also overlaps with the
952 * device addresses, so make sure the peer to peer forwarding
953 * is set right.
954 */
955 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
956
957 /*
958 * Setup BAR2 attributes
959 *
960 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
961 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
962 * - WAIT_COM=0 will likely work for all applications.
963 *
964 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
965 */
966 if (pcie_port) {
967 union cvmx_npei_ctl_port1 npei_ctl_port;
968 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
969 npei_ctl_port.s.bar2_enb = 1;
970 npei_ctl_port.s.bar2_esx = 1;
971 npei_ctl_port.s.bar2_cax = 0;
972 npei_ctl_port.s.ptlp_ro = 1;
973 npei_ctl_port.s.ctlp_ro = 1;
974 npei_ctl_port.s.wait_com = 0;
975 npei_ctl_port.s.waitl_com = 0;
976 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
977 } else {
978 union cvmx_npei_ctl_port0 npei_ctl_port;
979 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
980 npei_ctl_port.s.bar2_enb = 1;
981 npei_ctl_port.s.bar2_esx = 1;
982 npei_ctl_port.s.bar2_cax = 0;
983 npei_ctl_port.s.ptlp_ro = 1;
984 npei_ctl_port.s.ctlp_ro = 1;
985 npei_ctl_port.s.wait_com = 0;
986 npei_ctl_port.s.waitl_com = 0;
987 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
988 }
989
990 /*
991 * Both pass 1 and pass 2 of CN52XX and CN56XX have an errata
992 * that causes TLP ordering to not be preserved after multiple
993 * PCIe port resets. This code detects this fault and corrects
994 * it by aligning the TLP counters properly. Another link
995 * reset is then performed. See PCIE-13340
996 */
997 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
998 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
999 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) ||
1000 OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1001 union cvmx_npei_dbg_data dbg_data;
1002 int old_in_fif_p_count;
1003 int in_fif_p_count;
1004 int out_p_count;
1005 int in_p_offset = (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) ? 4 : 1;
1006 int i;
1007
1008 /*
1009 * Choose a write address of 1MB. It should be
1010 * harmless as all bars haven't been setup.
1011 */
1012 uint64_t write_address = (cvmx_pcie_get_mem_base_address(pcie_port) + 0x100000) | (1ull<<63);
1013
1014 /*
1015 * Make sure at least in_p_offset have been executed before we try and
1016 * read in_fif_p_count
1017 */
1018 i = in_p_offset;
1019 while (i--) {
1020 cvmx_write64_uint32(write_address, 0);
1021 cvmx_wait(10000);
1022 }
1023
1024 /*
1025 * Read the IN_FIF_P_COUNT from the debug
1026 * select. IN_FIF_P_COUNT can be unstable sometimes so
1027 * read it twice with a write between the reads. This
1028 * way we can tell the value is good as it will
1029 * increment by one due to the write
1030 */
1031 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd7fc : 0xcffc);
1032 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1033 do {
1034 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1035 old_in_fif_p_count = dbg_data.s.data & 0xff;
1036 cvmx_write64_uint32(write_address, 0);
1037 cvmx_wait(10000);
1038 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1039 in_fif_p_count = dbg_data.s.data & 0xff;
1040 } while (in_fif_p_count != ((old_in_fif_p_count+1) & 0xff));
1041
1042 /* Update in_fif_p_count for it's offset with respect to out_p_count */
1043 in_fif_p_count = (in_fif_p_count + in_p_offset) & 0xff;
1044
1045 /* Read the OUT_P_COUNT from the debug select */
1046 cvmx_write_csr(CVMX_PEXP_NPEI_DBG_SELECT, (pcie_port) ? 0xd00f : 0xc80f);
1047 cvmx_read_csr(CVMX_PEXP_NPEI_DBG_SELECT);
1048 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1049 out_p_count = (dbg_data.s.data>>1) & 0xff;
1050
1051 /* Check that the two counters are aligned */
1052 if (out_p_count != in_fif_p_count) {
1053 cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port);
1054 while (in_fif_p_count != 0) {
1055 cvmx_write64_uint32(write_address, 0);
1056 cvmx_wait(10000);
1057 in_fif_p_count = (in_fif_p_count + 1) & 0xff;
1058 }
1059 /*
1060 * The EBH5200 board swapped the PCIe reset
1061 * lines on the board. This means we must
1062 * bring both links down and up, which will
1063 * cause the PCIe0 to need alignment
1064 * again. Lots of messages will be displayed,
1065 * but everything should work
1066 */
1067 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) &&
1068 (pcie_port == 1))
1069 cvmx_pcie_rc_initialize(0);
1070 /* Rety bringing this port up */
1071 goto retry;
1072 }
1073 }
1074
1075 /* Display the link status */
1076 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1077 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw);
1078
1079 return 0;
1080}
1081
1082/**
1083 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1084 * port from reset to a link up state. Software can then begin
1085 * configuring the rest of the link.
1086 *
1087 * @pcie_port: PCIe port to initialize
1088 *
1089 * Return Zero on success.
1090 */
1091static int __cvmx_pcie_rc_initialize_link_gen2(int pcie_port)
1092{
1093 uint64_t start_cycle;
1094 union cvmx_pemx_ctl_status pem_ctl_status;
1095 union cvmx_pciercx_cfg032 pciercx_cfg032;
1096 union cvmx_pciercx_cfg448 pciercx_cfg448;
1097
1098 /* Bring up the link */
1099 pem_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1100 pem_ctl_status.s.lnk_enb = 1;
1101 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pem_ctl_status.u64);
1102
1103 /* Wait for the link to come up */
1104 start_cycle = cvmx_get_cycle();
1105 do {
1106 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate())
1107 return -1;
1108 cvmx_wait(10000);
1109 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1110 } while ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1));
1111
1112 /*
1113 * Update the Replay Time Limit. Empirically, some PCIe
1114 * devices take a little longer to respond than expected under
1115 * load. As a workaround for this we configure the Replay Time
1116 * Limit to the value expected for a 512 byte MPS instead of
1117 * our actual 256 byte MPS. The numbers below are directly
1118 * from the PCIe spec table 3-4
1119 */
1120 pciercx_cfg448.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1121 switch (pciercx_cfg032.s.nlw) {
1122 case 1: /* 1 lane */
1123 pciercx_cfg448.s.rtl = 1677;
1124 break;
1125 case 2: /* 2 lanes */
1126 pciercx_cfg448.s.rtl = 867;
1127 break;
1128 case 4: /* 4 lanes */
1129 pciercx_cfg448.s.rtl = 462;
1130 break;
1131 case 8: /* 8 lanes */
1132 pciercx_cfg448.s.rtl = 258;
1133 break;
1134 }
1135 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port), pciercx_cfg448.u32);
1136
1137 return 0;
1138}
1139
1140
1141/**
1142 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1143 * the bus.
1144 *
1145 * @pcie_port: PCIe port to initialize
1146 *
1147 * Returns Zero on success.
1148 */
1149static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
1150{
1151 int i;
1152 union cvmx_ciu_soft_prst ciu_soft_prst;
1153 union cvmx_mio_rst_ctlx mio_rst_ctl;
1154 union cvmx_pemx_bar_ctl pemx_bar_ctl;
1155 union cvmx_pemx_ctl_status pemx_ctl_status;
1156 union cvmx_pemx_bist_status pemx_bist_status;
1157 union cvmx_pemx_bist_status2 pemx_bist_status2;
1158 union cvmx_pciercx_cfg032 pciercx_cfg032;
1159 union cvmx_pciercx_cfg515 pciercx_cfg515;
1160 union cvmx_sli_ctl_portx sli_ctl_portx;
1161 union cvmx_sli_mem_access_ctl sli_mem_access_ctl;
1162 union cvmx_sli_mem_access_subidx mem_access_subid;
1163 union cvmx_sriox_status_reg sriox_status_reg;
1164 union cvmx_pemx_bar1_indexx bar1_index;
1165
1166 if (octeon_has_feature(OCTEON_FEATURE_SRIO)) {
1167 /* Make sure this interface isn't SRIO */
1168 if (OCTEON_IS_MODEL(OCTEON_CN66XX)) {
1169 /*
1170 * The CN66XX requires reading the
1171 * MIO_QLMX_CFG register to figure out the
1172 * port type.
1173 */
1174 union cvmx_mio_qlmx_cfg qlmx_cfg;
1175 qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(pcie_port));
1176
1177 if (qlmx_cfg.s.qlm_spd == 15) {
1178 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port);
1179 return -1;
1180 }
1181
1182 switch (qlmx_cfg.s.qlm_spd) {
1183 case 0x1: /* SRIO 1x4 short */
1184 case 0x3: /* SRIO 1x4 long */
1185 case 0x4: /* SRIO 2x2 short */
1186 case 0x6: /* SRIO 2x2 long */
1187 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1188 return -1;
1189 case 0x9: /* SGMII */
1190 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port);
1191 return -1;
1192 case 0xb: /* XAUI */
1193 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port);
1194 return -1;
1195 case 0x0: /* PCIE gen2 */
1196 case 0x8: /* PCIE gen2 (alias) */
1197 case 0x2: /* PCIE gen1 */
1198 case 0xa: /* PCIE gen1 (alias) */
1199 break;
1200 default:
1201 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port);
1202 return -1;
1203 }
1204 } else {
1205 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(pcie_port));
1206 if (sriox_status_reg.s.srio) {
1207 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port);
1208 return -1;
1209 }
1210 }
1211 }
1212
1213#if 0
1214 /* This code is so that the PCIe analyzer is able to see 63XX traffic */
1215 pr_notice("PCIE : init for pcie analyzer.\n");
1216 cvmx_helper_qlm_jtag_init();
1217 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1218 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1219 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1220 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1221 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1222 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1224 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1225 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 85);
1227 cvmx_helper_qlm_jtag_shift(pcie_port, 1, 1);
1228 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86);
1229 cvmx_helper_qlm_jtag_update(pcie_port);
1230#endif
1231
1232 /* Make sure we aren't trying to setup a target mode interface in host mode */
1233 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(pcie_port));
1234 if (!mio_rst_ctl.s.host_mode) {
1235 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port);
1236 return -1;
1237 }
1238
1239 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */
1240 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_0)) {
1241 if (pcie_port) {
1242 union cvmx_ciu_qlm1 ciu_qlm;
1243 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM1);
1244 ciu_qlm.s.txbypass = 1;
1245 ciu_qlm.s.txdeemph = 5;
1246 ciu_qlm.s.txmargin = 0x17;
1247 cvmx_write_csr(CVMX_CIU_QLM1, ciu_qlm.u64);
1248 } else {
1249 union cvmx_ciu_qlm0 ciu_qlm;
1250 ciu_qlm.u64 = cvmx_read_csr(CVMX_CIU_QLM0);
1251 ciu_qlm.s.txbypass = 1;
1252 ciu_qlm.s.txdeemph = 5;
1253 ciu_qlm.s.txmargin = 0x17;
1254 cvmx_write_csr(CVMX_CIU_QLM0, ciu_qlm.u64);
1255 }
1256 }
1257 /* Bring the PCIe out of reset */
1258 if (pcie_port)
1259 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1260 else
1261 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1262 /*
1263 * After a chip reset the PCIe will also be in reset. If it
1264 * isn't, most likely someone is trying to init it again
1265 * without a proper PCIe reset
1266 */
1267 if (ciu_soft_prst.s.soft_prst == 0) {
1268 /* Reset the port */
1269 ciu_soft_prst.s.soft_prst = 1;
1270 if (pcie_port)
1271 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1272 else
1273 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1274 /* Wait until pcie resets the ports. */
1275 udelay(2000);
1276 }
1277 if (pcie_port) {
1278 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1279 ciu_soft_prst.s.soft_prst = 0;
1280 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1281 } else {
1282 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1283 ciu_soft_prst.s.soft_prst = 0;
1284 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1285 }
1286
1287 /* Wait for PCIe reset to complete */
1288 udelay(1000);
1289
1290 /*
1291 * Check and make sure PCIe came out of reset. If it doesn't
1292 * the board probably hasn't wired the clocks up and the
1293 * interface should be skipped.
1294 */
1295 if (CVMX_WAIT_FOR_FIELD64(CVMX_MIO_RST_CTLX(pcie_port), union cvmx_mio_rst_ctlx, rst_done, ==, 1, 10000)) {
1296 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port);
1297 return -1;
1298 }
1299
1300 /* Check BIST status */
1301 pemx_bist_status.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS(pcie_port));
1302 if (pemx_bist_status.u64)
1303 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64));
1304 pemx_bist_status2.u64 = cvmx_read_csr(CVMX_PEMX_BIST_STATUS2(pcie_port));
1305 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */
1306 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
1307 pemx_bist_status2.u64 &= ~0x3full;
1308 if (pemx_bist_status2.u64)
1309 pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64));
1310
1311 /* Initialize the config space CSRs */
1312 __cvmx_pcie_rc_initialize_config_space(pcie_port);
1313
1314 /* Enable gen2 speed selection */
1315 pciercx_cfg515.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG515(pcie_port));
1316 pciercx_cfg515.s.dsc = 1;
1317 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG515(pcie_port), pciercx_cfg515.u32);
1318
1319 /* Bring the link up */
1320 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1321 /*
1322 * Some gen1 devices don't handle the gen 2 training
1323 * correctly. Disable gen2 and try again with only
1324 * gen1
1325 */
1326 union cvmx_pciercx_cfg031 pciercx_cfg031;
1327 pciercx_cfg031.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG031(pcie_port));
1328 pciercx_cfg031.s.mls = 1;
1329 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG031(pcie_port), pciercx_cfg031.u32);
1330 if (__cvmx_pcie_rc_initialize_link_gen2(pcie_port)) {
1331 pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port);
1332 return -1;
1333 }
1334 }
1335
1336 /* Store merge control (SLI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1337 sli_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL);
1338 sli_mem_access_ctl.s.max_word = 0; /* Allow 16 words to combine */
1339 sli_mem_access_ctl.s.timer = 127; /* Wait up to 127 cycles for more data */
1340 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_CTL, sli_mem_access_ctl.u64);
1341
1342 /* Setup Mem access SubDIDs */
1343 mem_access_subid.u64 = 0;
1344 mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
1345 mem_access_subid.s.nmerge = 0; /* Allow merging as it works on CN6XXX. */
1346 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */
1347 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */
1348 mem_access_subid.s.wtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1349 mem_access_subid.s.rtype = 0; /* "No snoop" and "Relaxed ordering" are not set */
1350 /* PCIe Adddress Bits <63:34>. */
1351 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
1352 mem_access_subid.cn68xx.ba = 0;
1353 else
1354 mem_access_subid.cn63xx.ba = 0;
1355
1356 /*
1357 * Setup mem access 12-15 for port 0, 16-19 for port 1,
1358 * supplying 36 bits of address space.
1359 */
1360 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1361 cvmx_write_csr(CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(i), mem_access_subid.u64);
1362 /* Set each SUBID to extend the addressable range */
1363 __cvmx_increment_ba(&mem_access_subid);
1364 }
1365
1366 /*
1367 * Disable the peer to peer forwarding register. This must be
1368 * setup by the OS after it enumerates the bus and assigns
1369 * addresses to the PCIe busses.
1370 */
1371 for (i = 0; i < 4; i++) {
1372 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1);
1373 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1);
1374 }
1375
1376 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1377 cvmx_write_csr(CVMX_PEMX_P2N_BAR0_START(pcie_port), 0);
1378
1379 /*
1380 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take
1381 * precedence where they overlap. It also overlaps with the
1382 * device addresses, so make sure the peer to peer forwarding
1383 * is set right.
1384 */
1385 cvmx_write_csr(CVMX_PEMX_P2N_BAR2_START(pcie_port), 0);
1386
1387 /*
1388 * Setup BAR2 attributes
1389 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
1390 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
1391 * - WAIT_COM=0 will likely work for all applications.
1392 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM])
1393 */
1394 pemx_bar_ctl.u64 = cvmx_read_csr(CVMX_PEMX_BAR_CTL(pcie_port));
1395 pemx_bar_ctl.s.bar1_siz = 3; /* 256MB BAR1*/
1396 pemx_bar_ctl.s.bar2_enb = 1;
1397 pemx_bar_ctl.s.bar2_esx = 1;
1398 pemx_bar_ctl.s.bar2_cax = 0;
1399 cvmx_write_csr(CVMX_PEMX_BAR_CTL(pcie_port), pemx_bar_ctl.u64);
1400 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port));
1401 sli_ctl_portx.s.ptlp_ro = 1;
1402 sli_ctl_portx.s.ctlp_ro = 1;
1403 sli_ctl_portx.s.wait_com = 0;
1404 sli_ctl_portx.s.waitl_com = 0;
1405 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(pcie_port), sli_ctl_portx.u64);
1406
1407 /* BAR1 follows BAR2 */
1408 cvmx_write_csr(CVMX_PEMX_P2N_BAR1_START(pcie_port), CVMX_PCIE_BAR1_RC_BASE);
1409
1410 bar1_index.u64 = 0;
1411 bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
1412 bar1_index.s.ca = 1; /* Not Cached */
1413 bar1_index.s.end_swp = 1; /* Endian Swap mode */
1414 bar1_index.s.addr_v = 1; /* Valid entry */
1415
1416 for (i = 0; i < 16; i++) {
1417 cvmx_write_csr(CVMX_PEMX_BAR1_INDEXX(i, pcie_port), bar1_index.u64);
1418 /* 256MB / 16 >> 22 == 4 */
1419 bar1_index.s.addr_idx += (((1ull << 28) / 16ull) >> 22);
1420 }
1421
1422 /*
1423 * Allow config retries for 250ms. Count is based off the 5Ghz
1424 * SERDES clock.
1425 */
1426 pemx_ctl_status.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(pcie_port));
1427 pemx_ctl_status.s.cfg_rtry = 250 * 5000000 / 0x10000;
1428 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(pcie_port), pemx_ctl_status.u64);
1429
1430 /* Display the link status */
1431 pciercx_cfg032.u32 = cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1432 pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, pciercx_cfg032.s.ls);
1433
1434 return 0;
1435}
1436
1437/**
1438 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1439 *
1440 * @pcie_port: PCIe port to initialize
1441 *
1442 * Returns Zero on success
1443 */
1444static int cvmx_pcie_rc_initialize(int pcie_port)
1445{
1446 int result;
1447 if (octeon_has_feature(OCTEON_FEATURE_NPEI))
1448 result = __cvmx_pcie_rc_initialize_gen1(pcie_port);
1449 else
1450 result = __cvmx_pcie_rc_initialize_gen2(pcie_port);
1451 return result;
1452}
1453
1454/* Above was cvmx-pcie.c, below original pcie.c */
1455
1456/**
1457 * Map a PCI device to the appropriate interrupt line
1458 *
1459 * @dev: The Linux PCI device structure for the device to map
1460 * @slot: The slot number for this device on __BUS 0__. Linux
1461 * enumerates through all the bridges and figures out the
1462 * slot on Bus 0 where this device eventually hooks to.
1463 * @pin: The PCI interrupt pin read from the device, then swizzled
1464 * as it goes through each bridge.
1465 * Returns Interrupt number for the device
1466 */
1467int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
1468 u8 slot, u8 pin)
1469{
1470 /*
1471 * The EBH5600 board with the PCI to PCIe bridge mistakenly
1472 * wires the first slot for both device id 2 and interrupt
1473 * A. According to the PCI spec, device id 2 should be C. The
1474 * following kludge attempts to fix this.
1475 */
1476 if (strstr(octeon_board_type_string(), "EBH5600") &&
1477 dev->bus && dev->bus->parent) {
1478 /*
1479 * Iterate all the way up the device chain and find
1480 * the root bus.
1481 */
1482 while (dev->bus && dev->bus->parent)
1483 dev = to_pci_dev(dev->bus->bridge);
1484 /*
1485 * If the root bus is number 0 and the PEX 8114 is the
1486 * root, assume we are behind the miswired bus. We
1487 * need to correct the swizzle level by two. Yuck.
1488 */
1489 if ((dev->bus->number == 1) &&
1490 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1491 /*
1492 * The pin field is one based, not zero. We
1493 * need to swizzle it by minus two.
1494 */
1495 pin = ((pin - 3) & 3) + 1;
1496 }
1497 }
1498 /*
1499 * The -1 is because pin starts with one, not zero. It might
1500 * be that this equation needs to include the slot number, but
1501 * I don't have hardware to check that against.
1502 */
1503 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1504}
1505
1506static void set_cfg_read_retry(u32 retry_cnt)
1507{
1508 union cvmx_pemx_ctl_status pemx_ctl;
1509 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1510 pemx_ctl.s.cfg_rtry = retry_cnt;
1511 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1512}
1513
1514
1515static u32 disable_cfg_read_retry(void)
1516{
1517 u32 retry_cnt;
1518
1519 union cvmx_pemx_ctl_status pemx_ctl;
1520 pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
1521 retry_cnt = pemx_ctl.s.cfg_rtry;
1522 pemx_ctl.s.cfg_rtry = 0;
1523 cvmx_write_csr(CVMX_PEMX_CTL_STATUS(1), pemx_ctl.u64);
1524 return retry_cnt;
1525}
1526
1527static int is_cfg_retry(void)
1528{
1529 union cvmx_pemx_int_sum pemx_int_sum;
1530 pemx_int_sum.u64 = cvmx_read_csr(CVMX_PEMX_INT_SUM(1));
1531 if (pemx_int_sum.s.crs_dr)
1532 return 1;
1533 return 0;
1534}
1535
1536/*
1537 * Read a value from configuration space
1538 *
1539 */
1540static int octeon_pcie_read_config(unsigned int pcie_port, struct pci_bus *bus,
1541 unsigned int devfn, int reg, int size,
1542 u32 *val)
1543{
1544 union octeon_cvmemctl cvmmemctl;
1545 union octeon_cvmemctl cvmmemctl_save;
1546 int bus_number = bus->number;
1547 int cfg_retry = 0;
1548 int retry_cnt = 0;
1549 int max_retry_cnt = 10;
1550 u32 cfg_retry_cnt = 0;
1551
1552 cvmmemctl_save.u64 = 0;
1553 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1554 /*
1555 * For the top level bus make sure our hardware bus number
1556 * matches the software one
1557 */
1558 if (bus->parent == NULL) {
1559 if (enable_pcie_bus_num_war[pcie_port])
1560 bus_number = 0;
1561 else {
1562 union cvmx_pciercx_cfg006 pciercx_cfg006;
1563 pciercx_cfg006.u32 = cvmx_pcie_cfgx_read(pcie_port,
1564 CVMX_PCIERCX_CFG006(pcie_port));
1565 if (pciercx_cfg006.s.pbnum != bus_number) {
1566 pciercx_cfg006.s.pbnum = bus_number;
1567 pciercx_cfg006.s.sbnum = bus_number;
1568 pciercx_cfg006.s.subbnum = bus_number;
1569 cvmx_pcie_cfgx_write(pcie_port,
1570 CVMX_PCIERCX_CFG006(pcie_port),
1571 pciercx_cfg006.u32);
1572 }
1573 }
1574 }
1575
1576 /*
1577 * PCIe only has a single device connected to Octeon. It is
1578 * always device ID 0. Don't bother doing reads for other
1579 * device IDs on the first segment.
1580 */
1581 if ((bus->parent == NULL) && (devfn >> 3 != 0))
1582 return PCIBIOS_FUNC_NOT_SUPPORTED;
1583
1584 /*
1585 * The following is a workaround for the CN57XX, CN56XX,
1586 * CN55XX, and CN54XX errata with PCIe config reads from non
1587 * existent devices. These chips will hang the PCIe link if a
1588 * config read is performed that causes a UR response.
1589 */
1590 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1591 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1592 /*
1593 * For our EBH5600 board, port 0 has a bridge with two
1594 * PCI-X slots. We need a new special checks to make
1595 * sure we only probe valid stuff. The PCIe->PCI-X
1596 * bridge only respondes to device ID 0, function
1597 * 0-1
1598 */
1599 if ((bus->parent == NULL) && (devfn >= 2))
1600 return PCIBIOS_FUNC_NOT_SUPPORTED;
1601 /*
1602 * The PCI-X slots are device ID 2,3. Choose one of
1603 * the below "if" blocks based on what is plugged into
1604 * the board.
1605 */
1606#if 1
1607 /* Use this option if you aren't using either slot */
1608 if (bus_number == 2)
1609 return PCIBIOS_FUNC_NOT_SUPPORTED;
1610#elif 0
1611 /*
1612 * Use this option if you are using the first slot but
1613 * not the second.
1614 */
1615 if ((bus_number == 2) && (devfn >> 3 != 2))
1616 return PCIBIOS_FUNC_NOT_SUPPORTED;
1617#elif 0
1618 /*
1619 * Use this option if you are using the second slot
1620 * but not the first.
1621 */
1622 if ((bus_number == 2) && (devfn >> 3 != 3))
1623 return PCIBIOS_FUNC_NOT_SUPPORTED;
1624#elif 0
1625 /* Use this opion if you are using both slots */
1626 if ((bus_number == 2) &&
1627 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1628 return PCIBIOS_FUNC_NOT_SUPPORTED;
1629#endif
1630
1631 /* The following #if gives a more complicated example. This is
1632 the required checks for running a Nitrox CN16XX-NHBX in the
1633 slot of the EBH5600. This card has a PLX PCIe bridge with
1634 four Nitrox PLX parts behind it */
1635#if 0
1636 /* PLX bridge with 4 ports */
1637 if ((bus_number == 4) &&
1638 !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
1639 return PCIBIOS_FUNC_NOT_SUPPORTED;
1640 /* Nitrox behind PLX 1 */
1641 if ((bus_number == 5) && (devfn >> 3 != 0))
1642 return PCIBIOS_FUNC_NOT_SUPPORTED;
1643 /* Nitrox behind PLX 2 */
1644 if ((bus_number == 6) && (devfn >> 3 != 0))
1645 return PCIBIOS_FUNC_NOT_SUPPORTED;
1646 /* Nitrox behind PLX 3 */
1647 if ((bus_number == 7) && (devfn >> 3 != 0))
1648 return PCIBIOS_FUNC_NOT_SUPPORTED;
1649 /* Nitrox behind PLX 4 */
1650 if ((bus_number == 8) && (devfn >> 3 != 0))
1651 return PCIBIOS_FUNC_NOT_SUPPORTED;
1652#endif
1653
1654 /*
1655 * Shorten the DID timeout so bus errors for PCIe
1656 * config reads from non existent devices happen
1657 * faster. This allows us to continue booting even if
1658 * the above "if" checks are wrong. Once one of these
1659 * errors happens, the PCIe port is dead.
1660 */
1661 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1662 cvmmemctl.u64 = cvmmemctl_save.u64;
1663 cvmmemctl.s.didtto = 2;
1664 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1665 }
1666
1667 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1668 cfg_retry_cnt = disable_cfg_read_retry();
1669
1670 pr_debug("pcie_cfg_rd port=%d b=%d devfn=0x%03x reg=0x%03x"
1671 " size=%d ", pcie_port, bus_number, devfn, reg, size);
1672 do {
1673 switch (size) {
1674 case 4:
1675 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1676 devfn >> 3, devfn & 0x7, reg);
1677 break;
1678 case 2:
1679 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1680 devfn >> 3, devfn & 0x7, reg);
1681 break;
1682 case 1:
1683 *val = cvmx_pcie_config_read8(pcie_port, bus_number,
1684 devfn >> 3, devfn & 0x7, reg);
1685 break;
1686 default:
1687 if (OCTEON_IS_MODEL(OCTEON_CN63XX))
1688 set_cfg_read_retry(cfg_retry_cnt);
1689 return PCIBIOS_FUNC_NOT_SUPPORTED;
1690 }
1691 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) &&
1692 (enable_pcie_14459_war)) {
1693 cfg_retry = is_cfg_retry();
1694 retry_cnt++;
1695 if (retry_cnt > max_retry_cnt) {
1696 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n",
1697 retry_cnt);
1698 cfg_retry = 0;
1699 }
1700 }
1701 } while (cfg_retry);
1702
1703 if ((OCTEON_IS_MODEL(OCTEON_CN63XX)) && (enable_pcie_14459_war))
1704 set_cfg_read_retry(cfg_retry_cnt);
1705 pr_debug("val=%08x : tries=%02d\n", *val, retry_cnt);
1706 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1707 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1708 write_c0_cvmmemctl(cvmmemctl_save.u64);
1709 return PCIBIOS_SUCCESSFUL;
1710}
1711
1712static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1713 int reg, int size, u32 *val)
1714{
1715 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1716}
1717
1718static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1719 int reg, int size, u32 *val)
1720{
1721 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1722}
1723
1724static int octeon_dummy_read_config(struct pci_bus *bus, unsigned int devfn,
1725 int reg, int size, u32 *val)
1726{
1727 return PCIBIOS_FUNC_NOT_SUPPORTED;
1728}
1729
1730/*
1731 * Write a value to PCI configuration space
1732 */
1733static int octeon_pcie_write_config(unsigned int pcie_port, struct pci_bus *bus,
1734 unsigned int devfn, int reg,
1735 int size, u32 val)
1736{
1737 int bus_number = bus->number;
1738
1739 BUG_ON(pcie_port >= ARRAY_SIZE(enable_pcie_bus_num_war));
1740
1741 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port]))
1742 bus_number = 0;
1743
1744 pr_debug("pcie_cfg_wr port=%d b=%d devfn=0x%03x"
1745 " reg=0x%03x size=%d val=%08x\n", pcie_port, bus_number, devfn,
1746 reg, size, val);
1747
1748
1749 switch (size) {
1750 case 4:
1751 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1752 devfn & 0x7, reg, val);
1753 break;
1754 case 2:
1755 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1756 devfn & 0x7, reg, val);
1757 break;
1758 case 1:
1759 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1760 devfn & 0x7, reg, val);
1761 break;
1762 default:
1763 return PCIBIOS_FUNC_NOT_SUPPORTED;
1764 }
1765 return PCIBIOS_SUCCESSFUL;
1766}
1767
1768static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1769 int reg, int size, u32 val)
1770{
1771 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1772}
1773
1774static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1775 int reg, int size, u32 val)
1776{
1777 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1778}
1779
1780static int octeon_dummy_write_config(struct pci_bus *bus, unsigned int devfn,
1781 int reg, int size, u32 val)
1782{
1783 return PCIBIOS_FUNC_NOT_SUPPORTED;
1784}
1785
1786static struct pci_ops octeon_pcie0_ops = {
1787 .read = octeon_pcie0_read_config,
1788 .write = octeon_pcie0_write_config,
1789};
1790
1791static struct resource octeon_pcie0_mem_resource = {
1792 .name = "Octeon PCIe0 MEM",
1793 .flags = IORESOURCE_MEM,
1794};
1795
1796static struct resource octeon_pcie0_io_resource = {
1797 .name = "Octeon PCIe0 IO",
1798 .flags = IORESOURCE_IO,
1799};
1800
1801static struct pci_controller octeon_pcie0_controller = {
1802 .pci_ops = &octeon_pcie0_ops,
1803 .mem_resource = &octeon_pcie0_mem_resource,
1804 .io_resource = &octeon_pcie0_io_resource,
1805};
1806
1807static struct pci_ops octeon_pcie1_ops = {
1808 .read = octeon_pcie1_read_config,
1809 .write = octeon_pcie1_write_config,
1810};
1811
1812static struct resource octeon_pcie1_mem_resource = {
1813 .name = "Octeon PCIe1 MEM",
1814 .flags = IORESOURCE_MEM,
1815};
1816
1817static struct resource octeon_pcie1_io_resource = {
1818 .name = "Octeon PCIe1 IO",
1819 .flags = IORESOURCE_IO,
1820};
1821
1822static struct pci_controller octeon_pcie1_controller = {
1823 .pci_ops = &octeon_pcie1_ops,
1824 .mem_resource = &octeon_pcie1_mem_resource,
1825 .io_resource = &octeon_pcie1_io_resource,
1826};
1827
1828static struct pci_ops octeon_dummy_ops = {
1829 .read = octeon_dummy_read_config,
1830 .write = octeon_dummy_write_config,
1831};
1832
1833static struct resource octeon_dummy_mem_resource = {
1834 .name = "Virtual PCIe MEM",
1835 .flags = IORESOURCE_MEM,
1836};
1837
1838static struct resource octeon_dummy_io_resource = {
1839 .name = "Virtual PCIe IO",
1840 .flags = IORESOURCE_IO,
1841};
1842
1843static struct pci_controller octeon_dummy_controller = {
1844 .pci_ops = &octeon_dummy_ops,
1845 .mem_resource = &octeon_dummy_mem_resource,
1846 .io_resource = &octeon_dummy_io_resource,
1847};
1848
1849static int device_needs_bus_num_war(uint32_t deviceid)
1850{
1851#define IDT_VENDOR_ID 0x111d
1852
1853 if ((deviceid & 0xffff) == IDT_VENDOR_ID)
1854 return 1;
1855 return 0;
1856}
1857
1858/**
1859 * Initialize the Octeon PCIe controllers
1860 *
1861 * Returns
1862 */
1863static int __init octeon_pcie_setup(void)
1864{
1865 int result;
1866 int host_mode;
1867 int srio_war15205 = 0, port;
1868 union cvmx_sli_ctl_portx sli_ctl_portx;
1869 union cvmx_sriox_status_reg sriox_status_reg;
1870
1871 /* These chips don't have PCIe */
1872 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1873 return 0;
1874
1875 /* No PCIe simulation */
1876 if (octeon_is_simulation())
1877 return 0;
1878
1879 /* Disable PCI if instructed on the command line */
1880 if (pcie_disable)
1881 return 0;
1882
1883 /* Point pcibios_map_irq() to the PCIe version of it */
1884 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1885
1886 /*
1887 * PCIe I/O range. It is based on port 0 but includes up until
1888 * port 1's end.
1889 */
1890 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1891 ioport_resource.start = 0;
1892 ioport_resource.end =
1893 cvmx_pcie_get_io_base_address(1) -
1894 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1895
1896 /*
1897 * Create a dummy PCIe controller to swallow up bus 0. IDT bridges
1898 * don't work if the primary bus number is zero. Here we add a fake
1899 * PCIe controller that the kernel will give bus 0. This allows
1900 * us to not change the normal kernel bus enumeration
1901 */
1902 octeon_dummy_controller.io_map_base = -1;
1903 octeon_dummy_controller.mem_resource->start = (1ull<<48);
1904 octeon_dummy_controller.mem_resource->end = (1ull<<48);
1905 register_pci_controller(&octeon_dummy_controller);
1906
1907 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1908 union cvmx_npei_ctl_status npei_ctl_status;
1909 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1910 host_mode = npei_ctl_status.s.host_mode;
1911 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1912 } else {
1913 union cvmx_mio_rst_ctlx mio_rst_ctl;
1914 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(0));
1915 host_mode = mio_rst_ctl.s.host_mode;
1916 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE2;
1917 }
1918
1919 if (host_mode) {
1920 pr_notice("PCIe: Initializing port 0\n");
1921 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1922 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1923 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1924 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
1925 if (sriox_status_reg.s.srio) {
1926 srio_war15205 += 1; /* Port is SRIO */
1927 port = 0;
1928 }
1929 }
1930 result = cvmx_pcie_rc_initialize(0);
1931 if (result == 0) {
1932 uint32_t device0;
1933 /* Memory offsets are physical addresses */
1934 octeon_pcie0_controller.mem_offset =
1935 cvmx_pcie_get_mem_base_address(0);
1936 /* IO offsets are Mips virtual addresses */
1937 octeon_pcie0_controller.io_map_base =
1938 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1939 (0));
1940 octeon_pcie0_controller.io_offset = 0;
1941 /*
1942 * To keep things similar to PCI, we start
1943 * device addresses at the same place as PCI
1944 * uisng big bar support. This normally
1945 * translates to 4GB-256MB, which is the same
1946 * as most x86 PCs.
1947 */
1948 octeon_pcie0_controller.mem_resource->start =
1949 cvmx_pcie_get_mem_base_address(0) +
1950 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1951 octeon_pcie0_controller.mem_resource->end =
1952 cvmx_pcie_get_mem_base_address(0) +
1953 cvmx_pcie_get_mem_size(0) - 1;
1954 /*
1955 * Ports must be above 16KB for the ISA bus
1956 * filtering in the PCI-X to PCI bridge.
1957 */
1958 octeon_pcie0_controller.io_resource->start = 4 << 10;
1959 octeon_pcie0_controller.io_resource->end =
1960 cvmx_pcie_get_io_size(0) - 1;
1961 msleep(100); /* Some devices need extra time */
1962 register_pci_controller(&octeon_pcie0_controller);
1963 device0 = cvmx_pcie_config_read32(0, 0, 0, 0, 0);
1964 enable_pcie_bus_num_war[0] =
1965 device_needs_bus_num_war(device0);
1966 }
1967 } else {
1968 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1969 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1970 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1971 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1972 srio_war15205 += 1;
1973 port = 0;
1974 }
1975 }
1976
1977 if (octeon_has_feature(OCTEON_FEATURE_NPEI)) {
1978 host_mode = 1;
1979 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1980 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1981 union cvmx_npei_dbg_data dbg_data;
1982 dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1983 if (dbg_data.cn52xx.qlm0_link_width)
1984 host_mode = 0;
1985 }
1986 } else {
1987 union cvmx_mio_rst_ctlx mio_rst_ctl;
1988 mio_rst_ctl.u64 = cvmx_read_csr(CVMX_MIO_RST_CTLX(1));
1989 host_mode = mio_rst_ctl.s.host_mode;
1990 }
1991
1992 if (host_mode) {
1993 pr_notice("PCIe: Initializing port 1\n");
1994 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
1995 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
1996 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
1997 sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
1998 if (sriox_status_reg.s.srio) {
1999 srio_war15205 += 1; /* Port is SRIO */
2000 port = 1;
2001 }
2002 }
2003 result = cvmx_pcie_rc_initialize(1);
2004 if (result == 0) {
2005 uint32_t device0;
2006 /* Memory offsets are physical addresses */
2007 octeon_pcie1_controller.mem_offset =
2008 cvmx_pcie_get_mem_base_address(1);
2009 /*
2010 * To calculate the address for accessing the 2nd PCIe device,
2011 * either 'io_map_base' (pci_iomap()), or 'mips_io_port_base'
2012 * (ioport_map()) value is added to
2013 * pci_resource_start(dev,bar)). The 'mips_io_port_base' is set
2014 * only once based on first PCIe. Also changing 'io_map_base'
2015 * based on first slot's value so that both the routines will
2016 * work properly.
2017 */
2018 octeon_pcie1_controller.io_map_base =
2019 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0));
2020 /* IO offsets are Mips virtual addresses */
2021 octeon_pcie1_controller.io_offset =
2022 cvmx_pcie_get_io_base_address(1) -
2023 cvmx_pcie_get_io_base_address(0);
2024 /*
2025 * To keep things similar to PCI, we start device
2026 * addresses at the same place as PCI uisng big bar
2027 * support. This normally translates to 4GB-256MB,
2028 * which is the same as most x86 PCs.
2029 */
2030 octeon_pcie1_controller.mem_resource->start =
2031 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
2032 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
2033 octeon_pcie1_controller.mem_resource->end =
2034 cvmx_pcie_get_mem_base_address(1) +
2035 cvmx_pcie_get_mem_size(1) - 1;
2036 /*
2037 * Ports must be above 16KB for the ISA bus filtering
2038 * in the PCI-X to PCI bridge.
2039 */
2040 octeon_pcie1_controller.io_resource->start =
2041 cvmx_pcie_get_io_base_address(1) -
2042 cvmx_pcie_get_io_base_address(0);
2043 octeon_pcie1_controller.io_resource->end =
2044 octeon_pcie1_controller.io_resource->start +
2045 cvmx_pcie_get_io_size(1) - 1;
2046 msleep(100); /* Some devices need extra time */
2047 register_pci_controller(&octeon_pcie1_controller);
2048 device0 = cvmx_pcie_config_read32(1, 0, 0, 0, 0);
2049 enable_pcie_bus_num_war[1] =
2050 device_needs_bus_num_war(device0);
2051 }
2052 } else {
2053 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n");
2054 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */
2055 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2056 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2057 srio_war15205 += 1;
2058 port = 1;
2059 }
2060 }
2061
2062 /*
2063 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all
2064 * of SRIO MACs SLI_CTL_PORT*[INT*_MAP] to similar value and
2065 * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value
2066 * from the previous set values
2067 */
2068 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
2069 OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
2070 if (srio_war15205 == 1) {
2071 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(port));
2072 sli_ctl_portx.s.inta_map = 1;
2073 sli_ctl_portx.s.intb_map = 1;
2074 sli_ctl_portx.s.intc_map = 1;
2075 sli_ctl_portx.s.intd_map = 1;
2076 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(port), sli_ctl_portx.u64);
2077
2078 sli_ctl_portx.u64 = cvmx_read_csr(CVMX_PEXP_SLI_CTL_PORTX(!port));
2079 sli_ctl_portx.s.inta_map = 0;
2080 sli_ctl_portx.s.intb_map = 0;
2081 sli_ctl_portx.s.intc_map = 0;
2082 sli_ctl_portx.s.intd_map = 0;
2083 cvmx_write_csr(CVMX_PEXP_SLI_CTL_PORTX(!port), sli_ctl_portx.u64);
2084 }
2085 }
2086
2087 octeon_pci_dma_init();
2088
2089 return 0;
2090}
2091arch_initcall(octeon_pcie_setup);