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1#ifndef __ASM_SH_MOBILE_LCDC_H__
2#define __ASM_SH_MOBILE_LCDC_H__
3
4#include <linux/fb.h>
5#include <video/sh_mobile_meram.h>
6
7enum {
8 RGB8, /* 24bpp, 8:8:8 */
9 RGB9, /* 18bpp, 9:9 */
10 RGB12A, /* 24bpp, 12:12 */
11 RGB12B, /* 12bpp */
12 RGB16, /* 16bpp */
13 RGB18, /* 18bpp */
14 RGB24, /* 24bpp */
15 YUV422, /* 16bpp */
16 SYS8A, /* 24bpp, 8:8:8 */
17 SYS8B, /* 18bpp, 8:8:2 */
18 SYS8C, /* 18bpp, 2:8:8 */
19 SYS8D, /* 16bpp, 8:8 */
20 SYS9, /* 18bpp, 9:9 */
21 SYS12, /* 24bpp, 12:12 */
22 SYS16A, /* 16bpp */
23 SYS16B, /* 18bpp, 16:2 */
24 SYS16C, /* 18bpp, 2:16 */
25 SYS18, /* 18bpp */
26 SYS24, /* 24bpp */
27};
28
29enum { LCDC_CHAN_DISABLED = 0,
30 LCDC_CHAN_MAINLCD,
31 LCDC_CHAN_SUBLCD };
32
33enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
34
35#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
36#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
37#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
38#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
39#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
40
41struct sh_mobile_lcdc_sys_bus_cfg {
42 unsigned long ldmt2r;
43 unsigned long ldmt3r;
44 unsigned long deferred_io_msec;
45};
46
47struct sh_mobile_lcdc_sys_bus_ops {
48 void (*write_index)(void *handle, unsigned long data);
49 void (*write_data)(void *handle, unsigned long data);
50 unsigned long (*read_data)(void *handle);
51};
52
53struct module;
54struct sh_mobile_lcdc_board_cfg {
55 struct module *owner;
56 void *board_data;
57 int (*setup_sys)(void *board_data, void *sys_ops_handle,
58 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
59 void (*start_transfer)(void *board_data, void *sys_ops_handle,
60 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
61 void (*display_on)(void *board_data, struct fb_info *info);
62 void (*display_off)(void *board_data);
63 int (*set_brightness)(void *board_data, int brightness);
64 int (*get_brightness)(void *board_data);
65};
66
67struct sh_mobile_lcdc_lcd_size_cfg { /* width and height of panel in mm */
68 unsigned long width;
69 unsigned long height;
70};
71
72/* backlight info */
73struct sh_mobile_lcdc_bl_info {
74 const char *name;
75 int max_brightness;
76};
77
78struct sh_mobile_lcdc_chan_cfg {
79 int chan;
80 int bpp;
81 int interface_type; /* selects RGBn or SYSn I/F, see above */
82 int clock_divider;
83 unsigned long flags; /* LCDC_FLAGS_... */
84 const struct fb_videomode *lcd_cfg;
85 int num_cfg;
86 struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg;
87 struct sh_mobile_lcdc_board_cfg board_cfg;
88 struct sh_mobile_lcdc_bl_info bl_info;
89 struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
90 int nonstd;
91 struct sh_mobile_meram_cfg *meram_cfg;
92};
93
94struct sh_mobile_lcdc_info {
95 int clock_source;
96 struct sh_mobile_lcdc_chan_cfg ch[2];
97 struct sh_mobile_meram_info *meram_dev;
98};
99
100#endif /* __ASM_SH_MOBILE_LCDC_H__ */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_SH_MOBILE_LCDC_H__
3#define __ASM_SH_MOBILE_LCDC_H__
4
5#include <linux/fb.h>
6#include <video/sh_mobile_meram.h>
7
8/* Register definitions */
9#define _LDDCKR 0x410
10#define LDDCKR_ICKSEL_BUS (0 << 16)
11#define LDDCKR_ICKSEL_MIPI (1 << 16)
12#define LDDCKR_ICKSEL_HDMI (2 << 16)
13#define LDDCKR_ICKSEL_EXT (3 << 16)
14#define LDDCKR_ICKSEL_MASK (7 << 16)
15#define LDDCKR_MOSEL (1 << 6)
16#define _LDDCKSTPR 0x414
17#define _LDINTR 0x468
18#define LDINTR_FE (1 << 10)
19#define LDINTR_VSE (1 << 9)
20#define LDINTR_VEE (1 << 8)
21#define LDINTR_FS (1 << 2)
22#define LDINTR_VSS (1 << 1)
23#define LDINTR_VES (1 << 0)
24#define LDINTR_STATUS_MASK (0xff << 0)
25#define _LDSR 0x46c
26#define LDSR_MSS (1 << 10)
27#define LDSR_MRS (1 << 8)
28#define LDSR_AS (1 << 1)
29#define _LDCNT1R 0x470
30#define LDCNT1R_DE (1 << 0)
31#define _LDCNT2R 0x474
32#define LDCNT2R_BR (1 << 8)
33#define LDCNT2R_MD (1 << 3)
34#define LDCNT2R_SE (1 << 2)
35#define LDCNT2R_ME (1 << 1)
36#define LDCNT2R_DO (1 << 0)
37#define _LDRCNTR 0x478
38#define LDRCNTR_SRS (1 << 17)
39#define LDRCNTR_SRC (1 << 16)
40#define LDRCNTR_MRS (1 << 1)
41#define LDRCNTR_MRC (1 << 0)
42#define _LDDDSR 0x47c
43#define LDDDSR_LS (1 << 2)
44#define LDDDSR_WS (1 << 1)
45#define LDDDSR_BS (1 << 0)
46
47#define LDMT1R_VPOL (1 << 28)
48#define LDMT1R_HPOL (1 << 27)
49#define LDMT1R_DWPOL (1 << 26)
50#define LDMT1R_DIPOL (1 << 25)
51#define LDMT1R_DAPOL (1 << 24)
52#define LDMT1R_HSCNT (1 << 17)
53#define LDMT1R_DWCNT (1 << 16)
54#define LDMT1R_IFM (1 << 12)
55#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
56#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
57#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
58#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
59#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
60#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
61#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
62#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
63#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
64#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
65#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
66#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
67#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
68#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
69#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
70#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
71#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
72#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
73#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
74#define LDMT1R_MIFTYP_MASK (0xf << 0)
75
76#define LDDFR_CF1 (1 << 18)
77#define LDDFR_CF0 (1 << 17)
78#define LDDFR_CC (1 << 16)
79#define LDDFR_YF_420 (0 << 8)
80#define LDDFR_YF_422 (1 << 8)
81#define LDDFR_YF_444 (2 << 8)
82#define LDDFR_YF_MASK (3 << 8)
83#define LDDFR_PKF_ARGB32 (0x00 << 0)
84#define LDDFR_PKF_RGB16 (0x03 << 0)
85#define LDDFR_PKF_RGB24 (0x0b << 0)
86#define LDDFR_PKF_MASK (0x1f << 0)
87
88#define LDSM1R_OS (1 << 0)
89
90#define LDSM2R_OSTRG (1 << 0)
91
92#define LDPMR_LPS (3 << 0)
93
94#define _LDDWD0R 0x800
95#define LDDWDxR_WDACT (1 << 28)
96#define LDDWDxR_RSW (1 << 24)
97#define _LDDRDR 0x840
98#define LDDRDR_RSR (1 << 24)
99#define LDDRDR_DRD_MASK (0x3ffff << 0)
100#define _LDDWAR 0x900
101#define LDDWAR_WA (1 << 0)
102#define _LDDRAR 0x904
103#define LDDRAR_RA (1 << 0)
104
105enum {
106 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
107 RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
108 RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
109 RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
110 RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
111 RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
112 RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
113 YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
114 SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
115 SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
116 SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
117 SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
118 SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */
119 SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
120 SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */
121 SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */
122 SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */
123 SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
124 SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
125};
126
127enum { LCDC_CHAN_DISABLED = 0,
128 LCDC_CHAN_MAINLCD,
129 LCDC_CHAN_SUBLCD };
130
131enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
132
133#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
134#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
135#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
136#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
137#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
138
139struct sh_mobile_lcdc_sys_bus_cfg {
140 unsigned long ldmt2r;
141 unsigned long ldmt3r;
142 unsigned long deferred_io_msec;
143};
144
145struct sh_mobile_lcdc_sys_bus_ops {
146 void (*write_index)(void *handle, unsigned long data);
147 void (*write_data)(void *handle, unsigned long data);
148 unsigned long (*read_data)(void *handle);
149};
150
151struct sh_mobile_lcdc_panel_cfg {
152 unsigned long width; /* Panel width in mm */
153 unsigned long height; /* Panel height in mm */
154 int (*setup_sys)(void *sys_ops_handle,
155 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
156 void (*start_transfer)(void *sys_ops_handle,
157 struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
158 void (*display_on)(void);
159 void (*display_off)(void);
160};
161
162/* backlight info */
163struct sh_mobile_lcdc_bl_info {
164 const char *name;
165 int max_brightness;
166 int (*set_brightness)(int brightness);
167};
168
169struct sh_mobile_lcdc_overlay_cfg {
170 int fourcc;
171 unsigned int max_xres;
172 unsigned int max_yres;
173};
174
175struct sh_mobile_lcdc_chan_cfg {
176 int chan;
177 int fourcc;
178 int colorspace;
179 int interface_type; /* selects RGBn or SYSn I/F, see above */
180 int clock_divider;
181 unsigned long flags; /* LCDC_FLAGS_... */
182 const struct fb_videomode *lcd_modes;
183 int num_modes;
184 struct sh_mobile_lcdc_panel_cfg panel_cfg;
185 struct sh_mobile_lcdc_bl_info bl_info;
186 struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
187 const struct sh_mobile_meram_cfg *meram_cfg;
188
189 struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
190};
191
192struct sh_mobile_lcdc_info {
193 int clock_source;
194 struct sh_mobile_lcdc_chan_cfg ch[2];
195 struct sh_mobile_lcdc_overlay_cfg overlays[4];
196 struct sh_mobile_meram_info *meram_dev;
197};
198
199#endif /* __ASM_SH_MOBILE_LCDC_H__ */