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1/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34#if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430)
35#include "omap2430.h"
36#endif
37
38#ifndef CONFIG_BLACKFIN
39
40#define MUSB_HSDMA_BASE 0x200
41#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
42#define MUSB_HSDMA_CONTROL 0x4
43#define MUSB_HSDMA_ADDRESS 0x8
44#define MUSB_HSDMA_COUNT 0xc
45
46#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
47 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
48
49#define musb_read_hsdma_addr(mbase, bchannel) \
50 musb_readl(mbase, \
51 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
52
53#define musb_write_hsdma_addr(mbase, bchannel, addr) \
54 musb_writel(mbase, \
55 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
56 addr)
57
58#define musb_read_hsdma_count(mbase, bchannel) \
59 musb_readl(mbase, \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
61
62#define musb_write_hsdma_count(mbase, bchannel, len) \
63 musb_writel(mbase, \
64 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
65 len)
66#else
67
68#define MUSB_HSDMA_BASE 0x400
69#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
70#define MUSB_HSDMA_CONTROL 0x04
71#define MUSB_HSDMA_ADDR_LOW 0x08
72#define MUSB_HSDMA_ADDR_HIGH 0x0C
73#define MUSB_HSDMA_COUNT_LOW 0x10
74#define MUSB_HSDMA_COUNT_HIGH 0x14
75
76#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
77 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
78
79static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
80{
81 u32 addr = musb_readw(mbase,
82 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
83
84 addr = addr << 16;
85
86 addr |= musb_readw(mbase,
87 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
88
89 return addr;
90}
91
92static inline void musb_write_hsdma_addr(void __iomem *mbase,
93 u8 bchannel, dma_addr_t dma_addr)
94{
95 musb_writew(mbase,
96 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
97 dma_addr);
98 musb_writew(mbase,
99 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
100 (dma_addr >> 16));
101}
102
103static inline u32 musb_read_hsdma_count(void __iomem *mbase, u8 bchannel)
104{
105 u32 count = musb_readw(mbase,
106 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH));
107
108 count = count << 16;
109
110 count |= musb_readw(mbase,
111 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW));
112
113 return count;
114}
115
116static inline void musb_write_hsdma_count(void __iomem *mbase,
117 u8 bchannel, u32 len)
118{
119 musb_writew(mbase,
120 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),len);
121 musb_writew(mbase,
122 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
123 (len >> 16));
124}
125
126#endif /* CONFIG_BLACKFIN */
127
128/* control register (16-bit): */
129#define MUSB_HSDMA_ENABLE_SHIFT 0
130#define MUSB_HSDMA_TRANSMIT_SHIFT 1
131#define MUSB_HSDMA_MODE1_SHIFT 2
132#define MUSB_HSDMA_IRQENABLE_SHIFT 3
133#define MUSB_HSDMA_ENDPOINT_SHIFT 4
134#define MUSB_HSDMA_BUSERROR_SHIFT 8
135#define MUSB_HSDMA_BURSTMODE_SHIFT 9
136#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
137#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
138#define MUSB_HSDMA_BURSTMODE_INCR4 1
139#define MUSB_HSDMA_BURSTMODE_INCR8 2
140#define MUSB_HSDMA_BURSTMODE_INCR16 3
141
142#define MUSB_HSDMA_CHANNELS 8
143
144struct musb_dma_controller;
145
146struct musb_dma_channel {
147 struct dma_channel channel;
148 struct musb_dma_controller *controller;
149 u32 start_addr;
150 u32 len;
151 u16 max_packet_sz;
152 u8 idx;
153 u8 epnum;
154 u8 transmit;
155};
156
157struct musb_dma_controller {
158 struct dma_controller controller;
159 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
160 void *private_data;
161 void __iomem *base;
162 u8 channel_count;
163 u8 used_channels;
164 u8 irq;
165};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver - support for Mentor's DMA controller
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2007 by Texas Instruments
7 */
8
9#define MUSB_HSDMA_BASE 0x200
10#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
11#define MUSB_HSDMA_CONTROL 0x4
12#define MUSB_HSDMA_ADDRESS 0x8
13#define MUSB_HSDMA_COUNT 0xc
14
15#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
16 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
17
18#define musb_read_hsdma_addr(mbase, bchannel) \
19 musb_readl(mbase, \
20 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
21
22#define musb_write_hsdma_addr(mbase, bchannel, addr) \
23 musb_writel(mbase, \
24 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
25 addr)
26
27#define musb_read_hsdma_count(mbase, bchannel) \
28 musb_readl(mbase, \
29 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT))
30
31#define musb_write_hsdma_count(mbase, bchannel, len) \
32 musb_writel(mbase, \
33 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
34 len)
35/* control register (16-bit): */
36#define MUSB_HSDMA_ENABLE_SHIFT 0
37#define MUSB_HSDMA_TRANSMIT_SHIFT 1
38#define MUSB_HSDMA_MODE1_SHIFT 2
39#define MUSB_HSDMA_IRQENABLE_SHIFT 3
40#define MUSB_HSDMA_ENDPOINT_SHIFT 4
41#define MUSB_HSDMA_BUSERROR_SHIFT 8
42#define MUSB_HSDMA_BURSTMODE_SHIFT 9
43#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
44#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
45#define MUSB_HSDMA_BURSTMODE_INCR4 1
46#define MUSB_HSDMA_BURSTMODE_INCR8 2
47#define MUSB_HSDMA_BURSTMODE_INCR16 3
48
49#define MUSB_HSDMA_CHANNELS 8
50
51struct musb_dma_controller;
52
53struct musb_dma_channel {
54 struct dma_channel channel;
55 struct musb_dma_controller *controller;
56 u32 start_addr;
57 u32 len;
58 u16 max_packet_sz;
59 u8 idx;
60 u8 epnum;
61 u8 transmit;
62};
63
64struct musb_dma_controller {
65 struct dma_controller controller;
66 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
67 void *private_data;
68 void __iomem *base;
69 u8 channel_count;
70 u8 used_channels;
71 int irq;
72};