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1/*
2 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
3 *
4 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * Based on the DaVinci "glue layer" code.
7 * Copyright (C) 2005-2006 by Texas Instruments
8 *
9 * This file is part of the Inventra Controller Driver for Linux.
10 *
11 * The Inventra Controller Driver for Linux is free software; you
12 * can redistribute it and/or modify it under the terms of the GNU
13 * General Public License version 2 as published by the Free Software
14 * Foundation.
15 *
16 * The Inventra Controller Driver for Linux is distributed in
17 * the hope that it will be useful, but WITHOUT ANY WARRANTY;
18 * without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
20 * License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with The Inventra Controller Driver for Linux ; if not,
24 * write to the Free Software Foundation, Inc., 59 Temple Place,
25 * Suite 330, Boston, MA 02111-1307 USA
26 *
27 */
28
29#include <linux/init.h>
30#include <linux/clk.h>
31#include <linux/io.h>
32#include <linux/platform_device.h>
33#include <linux/dma-mapping.h>
34
35#include <mach/da8xx.h>
36#include <mach/usb.h>
37
38#include "musb_core.h"
39
40/*
41 * DA8XX specific definitions
42 */
43
44/* USB 2.0 OTG module registers */
45#define DA8XX_USB_REVISION_REG 0x00
46#define DA8XX_USB_CTRL_REG 0x04
47#define DA8XX_USB_STAT_REG 0x08
48#define DA8XX_USB_EMULATION_REG 0x0c
49#define DA8XX_USB_MODE_REG 0x10 /* Transparent, CDC, [Generic] RNDIS */
50#define DA8XX_USB_AUTOREQ_REG 0x14
51#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
52#define DA8XX_USB_TEARDOWN_REG 0x1c
53#define DA8XX_USB_INTR_SRC_REG 0x20
54#define DA8XX_USB_INTR_SRC_SET_REG 0x24
55#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
56#define DA8XX_USB_INTR_MASK_REG 0x2c
57#define DA8XX_USB_INTR_MASK_SET_REG 0x30
58#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
59#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
60#define DA8XX_USB_END_OF_INTR_REG 0x3c
61#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
62
63/* Control register bits */
64#define DA8XX_SOFT_RESET_MASK 1
65
66#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
67#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
68
69/* USB interrupt register bits */
70#define DA8XX_INTR_USB_SHIFT 16
71#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
72 /* interrupts and DRVVBUS interrupt */
73#define DA8XX_INTR_DRVVBUS 0x100
74#define DA8XX_INTR_RX_SHIFT 8
75#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
76#define DA8XX_INTR_TX_SHIFT 0
77#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
78
79#define DA8XX_MENTOR_CORE_OFFSET 0x400
80
81#define CFGCHIP2 IO_ADDRESS(DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP2_REG)
82
83struct da8xx_glue {
84 struct device *dev;
85 struct platform_device *musb;
86 struct clk *clk;
87};
88
89/*
90 * REVISIT (PM): we should be able to keep the PHY in low power mode most
91 * of the time (24 MHz oscillator and PLL off, etc.) by setting POWER.D0
92 * and, when in host mode, autosuspending idle root ports... PHY_PLLON
93 * (overriding SUSPENDM?) then likely needs to stay off.
94 */
95
96static inline void phy_on(void)
97{
98 u32 cfgchip2 = __raw_readl(CFGCHIP2);
99
100 /*
101 * Start the on-chip PHY and its PLL.
102 */
103 cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN);
104 cfgchip2 |= CFGCHIP2_PHY_PLLON;
105 __raw_writel(cfgchip2, CFGCHIP2);
106
107 pr_info("Waiting for USB PHY clock good...\n");
108 while (!(__raw_readl(CFGCHIP2) & CFGCHIP2_PHYCLKGD))
109 cpu_relax();
110}
111
112static inline void phy_off(void)
113{
114 u32 cfgchip2 = __raw_readl(CFGCHIP2);
115
116 /*
117 * Ensure that USB 1.1 reference clock is not being sourced from
118 * USB 2.0 PHY. Otherwise do not power down the PHY.
119 */
120 if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX) &&
121 (cfgchip2 & CFGCHIP2_USB1SUSPENDM)) {
122 pr_warning("USB 1.1 clocked from USB 2.0 PHY -- "
123 "can't power it down\n");
124 return;
125 }
126
127 /*
128 * Power down the on-chip PHY.
129 */
130 cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN;
131 __raw_writel(cfgchip2, CFGCHIP2);
132}
133
134/*
135 * Because we don't set CTRL.UINT, it's "important" to:
136 * - not read/write INTRUSB/INTRUSBE (except during
137 * initial setup, as a workaround);
138 * - use INTSET/INTCLR instead.
139 */
140
141/**
142 * da8xx_musb_enable - enable interrupts
143 */
144static void da8xx_musb_enable(struct musb *musb)
145{
146 void __iomem *reg_base = musb->ctrl_base;
147 u32 mask;
148
149 /* Workaround: setup IRQs through both register sets. */
150 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
151 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
152 DA8XX_INTR_USB_MASK;
153 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
154
155 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
156 if (is_otg_enabled(musb))
157 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
158 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
159}
160
161/**
162 * da8xx_musb_disable - disable HDRC and flush interrupts
163 */
164static void da8xx_musb_disable(struct musb *musb)
165{
166 void __iomem *reg_base = musb->ctrl_base;
167
168 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
169 DA8XX_INTR_USB_MASK |
170 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
171 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
172 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
173}
174
175#define portstate(stmt) stmt
176
177static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
178{
179 WARN_ON(is_on && is_peripheral_active(musb));
180}
181
182#define POLL_SECONDS 2
183
184static struct timer_list otg_workaround;
185
186static void otg_timer(unsigned long _musb)
187{
188 struct musb *musb = (void *)_musb;
189 void __iomem *mregs = musb->mregs;
190 u8 devctl;
191 unsigned long flags;
192
193 /*
194 * We poll because DaVinci's won't expose several OTG-critical
195 * status change events (from the transceiver) otherwise.
196 */
197 devctl = musb_readb(mregs, MUSB_DEVCTL);
198 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
199 otg_state_string(musb->xceiv->state));
200
201 spin_lock_irqsave(&musb->lock, flags);
202 switch (musb->xceiv->state) {
203 case OTG_STATE_A_WAIT_BCON:
204 devctl &= ~MUSB_DEVCTL_SESSION;
205 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
206
207 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
208 if (devctl & MUSB_DEVCTL_BDEVICE) {
209 musb->xceiv->state = OTG_STATE_B_IDLE;
210 MUSB_DEV_MODE(musb);
211 } else {
212 musb->xceiv->state = OTG_STATE_A_IDLE;
213 MUSB_HST_MODE(musb);
214 }
215 break;
216 case OTG_STATE_A_WAIT_VFALL:
217 /*
218 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
219 * RTL seems to mis-handle session "start" otherwise (or in
220 * our case "recover"), in routine "VBUS was valid by the time
221 * VBUSERR got reported during enumeration" cases.
222 */
223 if (devctl & MUSB_DEVCTL_VBUS) {
224 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
225 break;
226 }
227 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
228 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
229 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
230 break;
231 case OTG_STATE_B_IDLE:
232 if (!is_peripheral_enabled(musb))
233 break;
234
235 /*
236 * There's no ID-changed IRQ, so we have no good way to tell
237 * when to switch to the A-Default state machine (by setting
238 * the DEVCTL.Session bit).
239 *
240 * Workaround: whenever we're in B_IDLE, try setting the
241 * session flag every few seconds. If it works, ID was
242 * grounded and we're now in the A-Default state machine.
243 *
244 * NOTE: setting the session flag is _supposed_ to trigger
245 * SRP but clearly it doesn't.
246 */
247 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
248 devctl = musb_readb(mregs, MUSB_DEVCTL);
249 if (devctl & MUSB_DEVCTL_BDEVICE)
250 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
251 else
252 musb->xceiv->state = OTG_STATE_A_IDLE;
253 break;
254 default:
255 break;
256 }
257 spin_unlock_irqrestore(&musb->lock, flags);
258}
259
260static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
261{
262 static unsigned long last_timer;
263
264 if (!is_otg_enabled(musb))
265 return;
266
267 if (timeout == 0)
268 timeout = jiffies + msecs_to_jiffies(3);
269
270 /* Never idle if active, or when VBUS timeout is not set as host */
271 if (musb->is_active || (musb->a_wait_bcon == 0 &&
272 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
273 dev_dbg(musb->controller, "%s active, deleting timer\n",
274 otg_state_string(musb->xceiv->state));
275 del_timer(&otg_workaround);
276 last_timer = jiffies;
277 return;
278 }
279
280 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
281 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
282 return;
283 }
284 last_timer = timeout;
285
286 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
287 otg_state_string(musb->xceiv->state),
288 jiffies_to_msecs(timeout - jiffies));
289 mod_timer(&otg_workaround, timeout);
290}
291
292static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
293{
294 struct musb *musb = hci;
295 void __iomem *reg_base = musb->ctrl_base;
296 unsigned long flags;
297 irqreturn_t ret = IRQ_NONE;
298 u32 status;
299
300 spin_lock_irqsave(&musb->lock, flags);
301
302 /*
303 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
304 * the Mentor registers (except for setup), use the TI ones and EOI.
305 */
306
307 /* Acknowledge and handle non-CPPI interrupts */
308 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
309 if (!status)
310 goto eoi;
311
312 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
313 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
314
315 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
316 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
317 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
318
319 /*
320 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
321 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
322 * switch appropriately between halves of the OTG state machine.
323 * Managing DEVCTL.Session per Mentor docs requires that we know its
324 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
325 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
326 */
327 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
328 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
329 void __iomem *mregs = musb->mregs;
330 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
331 int err;
332
333 err = is_host_enabled(musb) && (musb->int_usb &
334 MUSB_INTR_VBUSERROR);
335 if (err) {
336 /*
337 * The Mentor core doesn't debounce VBUS as needed
338 * to cope with device connect current spikes. This
339 * means it's not uncommon for bus-powered devices
340 * to get VBUS errors during enumeration.
341 *
342 * This is a workaround, but newer RTL from Mentor
343 * seems to allow a better one: "re"-starting sessions
344 * without waiting for VBUS to stop registering in
345 * devctl.
346 */
347 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
348 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
349 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
350 WARNING("VBUS error workaround (delay coming)\n");
351 } else if (is_host_enabled(musb) && drvvbus) {
352 MUSB_HST_MODE(musb);
353 musb->xceiv->default_a = 1;
354 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
355 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
356 del_timer(&otg_workaround);
357 } else {
358 musb->is_active = 0;
359 MUSB_DEV_MODE(musb);
360 musb->xceiv->default_a = 0;
361 musb->xceiv->state = OTG_STATE_B_IDLE;
362 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
363 }
364
365 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
366 drvvbus ? "on" : "off",
367 otg_state_string(musb->xceiv->state),
368 err ? " ERROR" : "",
369 devctl);
370 ret = IRQ_HANDLED;
371 }
372
373 if (musb->int_tx || musb->int_rx || musb->int_usb)
374 ret |= musb_interrupt(musb);
375
376 eoi:
377 /* EOI needs to be written for the IRQ to be re-asserted. */
378 if (ret == IRQ_HANDLED || status)
379 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
380
381 /* Poll for ID change */
382 if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
383 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
384
385 spin_unlock_irqrestore(&musb->lock, flags);
386
387 return ret;
388}
389
390static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
391{
392 u32 cfgchip2 = __raw_readl(CFGCHIP2);
393
394 cfgchip2 &= ~CFGCHIP2_OTGMODE;
395 switch (musb_mode) {
396 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
397 cfgchip2 |= CFGCHIP2_FORCE_HOST;
398 break;
399 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
400 cfgchip2 |= CFGCHIP2_FORCE_DEVICE;
401 break;
402 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
403 cfgchip2 |= CFGCHIP2_NO_OVERRIDE;
404 break;
405 default:
406 dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
407 }
408
409 __raw_writel(cfgchip2, CFGCHIP2);
410 return 0;
411}
412
413static int da8xx_musb_init(struct musb *musb)
414{
415 void __iomem *reg_base = musb->ctrl_base;
416 u32 rev;
417
418 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
419
420 /* Returns zero if e.g. not clocked */
421 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
422 if (!rev)
423 goto fail;
424
425 usb_nop_xceiv_register();
426 musb->xceiv = otg_get_transceiver();
427 if (!musb->xceiv)
428 goto fail;
429
430 if (is_host_enabled(musb))
431 setup_timer(&otg_workaround, otg_timer, (unsigned long)musb);
432
433 /* Reset the controller */
434 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
435
436 /* Start the on-chip PHY and its PLL. */
437 phy_on();
438
439 msleep(5);
440
441 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
442 pr_debug("DA8xx OTG revision %08x, PHY %03x, control %02x\n",
443 rev, __raw_readl(CFGCHIP2),
444 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
445
446 musb->isr = da8xx_musb_interrupt;
447 return 0;
448fail:
449 return -ENODEV;
450}
451
452static int da8xx_musb_exit(struct musb *musb)
453{
454 if (is_host_enabled(musb))
455 del_timer_sync(&otg_workaround);
456
457 phy_off();
458
459 otg_put_transceiver(musb->xceiv);
460 usb_nop_xceiv_unregister();
461
462 return 0;
463}
464
465static const struct musb_platform_ops da8xx_ops = {
466 .init = da8xx_musb_init,
467 .exit = da8xx_musb_exit,
468
469 .enable = da8xx_musb_enable,
470 .disable = da8xx_musb_disable,
471
472 .set_mode = da8xx_musb_set_mode,
473 .try_idle = da8xx_musb_try_idle,
474
475 .set_vbus = da8xx_musb_set_vbus,
476};
477
478static u64 da8xx_dmamask = DMA_BIT_MASK(32);
479
480static int __init da8xx_probe(struct platform_device *pdev)
481{
482 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
483 struct platform_device *musb;
484 struct da8xx_glue *glue;
485
486 struct clk *clk;
487
488 int ret = -ENOMEM;
489
490 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
491 if (!glue) {
492 dev_err(&pdev->dev, "failed to allocate glue context\n");
493 goto err0;
494 }
495
496 musb = platform_device_alloc("musb-hdrc", -1);
497 if (!musb) {
498 dev_err(&pdev->dev, "failed to allocate musb device\n");
499 goto err1;
500 }
501
502 clk = clk_get(&pdev->dev, "usb20");
503 if (IS_ERR(clk)) {
504 dev_err(&pdev->dev, "failed to get clock\n");
505 ret = PTR_ERR(clk);
506 goto err2;
507 }
508
509 ret = clk_enable(clk);
510 if (ret) {
511 dev_err(&pdev->dev, "failed to enable clock\n");
512 goto err3;
513 }
514
515 musb->dev.parent = &pdev->dev;
516 musb->dev.dma_mask = &da8xx_dmamask;
517 musb->dev.coherent_dma_mask = da8xx_dmamask;
518
519 glue->dev = &pdev->dev;
520 glue->musb = musb;
521 glue->clk = clk;
522
523 pdata->platform_ops = &da8xx_ops;
524
525 platform_set_drvdata(pdev, glue);
526
527 ret = platform_device_add_resources(musb, pdev->resource,
528 pdev->num_resources);
529 if (ret) {
530 dev_err(&pdev->dev, "failed to add resources\n");
531 goto err4;
532 }
533
534 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
535 if (ret) {
536 dev_err(&pdev->dev, "failed to add platform_data\n");
537 goto err4;
538 }
539
540 ret = platform_device_add(musb);
541 if (ret) {
542 dev_err(&pdev->dev, "failed to register musb device\n");
543 goto err4;
544 }
545
546 return 0;
547
548err4:
549 clk_disable(clk);
550
551err3:
552 clk_put(clk);
553
554err2:
555 platform_device_put(musb);
556
557err1:
558 kfree(glue);
559
560err0:
561 return ret;
562}
563
564static int __exit da8xx_remove(struct platform_device *pdev)
565{
566 struct da8xx_glue *glue = platform_get_drvdata(pdev);
567
568 platform_device_del(glue->musb);
569 platform_device_put(glue->musb);
570 clk_disable(glue->clk);
571 clk_put(glue->clk);
572 kfree(glue);
573
574 return 0;
575}
576
577static struct platform_driver da8xx_driver = {
578 .remove = __exit_p(da8xx_remove),
579 .driver = {
580 .name = "musb-da8xx",
581 },
582};
583
584MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
585MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
586MODULE_LICENSE("GPL v2");
587
588static int __init da8xx_init(void)
589{
590 return platform_driver_probe(&da8xx_driver, da8xx_probe);
591}
592subsys_initcall(da8xx_init);
593
594static void __exit da8xx_exit(void)
595{
596 platform_driver_unregister(&da8xx_driver);
597}
598module_exit(da8xx_exit);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
4 *
5 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
6 *
7 * Based on the DaVinci "glue layer" code.
8 * Copyright (C) 2005-2006 by Texas Instruments
9 *
10 * DT support
11 * Copyright (c) 2016 Petr Kulhavy <petr@barix.com>
12 *
13 * This file is part of the Inventra Controller Driver for Linux.
14 */
15
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/of_platform.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/dma-mapping.h>
24#include <linux/usb/usb_phy_generic.h>
25
26#include "musb_core.h"
27
28/*
29 * DA8XX specific definitions
30 */
31
32/* USB 2.0 OTG module registers */
33#define DA8XX_USB_REVISION_REG 0x00
34#define DA8XX_USB_CTRL_REG 0x04
35#define DA8XX_USB_STAT_REG 0x08
36#define DA8XX_USB_EMULATION_REG 0x0c
37#define DA8XX_USB_SRP_FIX_TIME_REG 0x18
38#define DA8XX_USB_INTR_SRC_REG 0x20
39#define DA8XX_USB_INTR_SRC_SET_REG 0x24
40#define DA8XX_USB_INTR_SRC_CLEAR_REG 0x28
41#define DA8XX_USB_INTR_MASK_REG 0x2c
42#define DA8XX_USB_INTR_MASK_SET_REG 0x30
43#define DA8XX_USB_INTR_MASK_CLEAR_REG 0x34
44#define DA8XX_USB_INTR_SRC_MASKED_REG 0x38
45#define DA8XX_USB_END_OF_INTR_REG 0x3c
46#define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
47
48/* Control register bits */
49#define DA8XX_SOFT_RESET_MASK 1
50
51#define DA8XX_USB_TX_EP_MASK 0x1f /* EP0 + 4 Tx EPs */
52#define DA8XX_USB_RX_EP_MASK 0x1e /* 4 Rx EPs */
53
54/* USB interrupt register bits */
55#define DA8XX_INTR_USB_SHIFT 16
56#define DA8XX_INTR_USB_MASK (0x1ff << DA8XX_INTR_USB_SHIFT) /* 8 Mentor */
57 /* interrupts and DRVVBUS interrupt */
58#define DA8XX_INTR_DRVVBUS 0x100
59#define DA8XX_INTR_RX_SHIFT 8
60#define DA8XX_INTR_RX_MASK (DA8XX_USB_RX_EP_MASK << DA8XX_INTR_RX_SHIFT)
61#define DA8XX_INTR_TX_SHIFT 0
62#define DA8XX_INTR_TX_MASK (DA8XX_USB_TX_EP_MASK << DA8XX_INTR_TX_SHIFT)
63
64#define DA8XX_MENTOR_CORE_OFFSET 0x400
65
66struct da8xx_glue {
67 struct device *dev;
68 struct platform_device *musb;
69 struct platform_device *usb_phy;
70 struct clk *clk;
71 struct phy *phy;
72};
73
74/*
75 * Because we don't set CTRL.UINT, it's "important" to:
76 * - not read/write INTRUSB/INTRUSBE (except during
77 * initial setup, as a workaround);
78 * - use INTSET/INTCLR instead.
79 */
80
81/**
82 * da8xx_musb_enable - enable interrupts
83 */
84static void da8xx_musb_enable(struct musb *musb)
85{
86 void __iomem *reg_base = musb->ctrl_base;
87 u32 mask;
88
89 /* Workaround: setup IRQs through both register sets. */
90 mask = ((musb->epmask & DA8XX_USB_TX_EP_MASK) << DA8XX_INTR_TX_SHIFT) |
91 ((musb->epmask & DA8XX_USB_RX_EP_MASK) << DA8XX_INTR_RX_SHIFT) |
92 DA8XX_INTR_USB_MASK;
93 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
94
95 /* Force the DRVVBUS IRQ so we can start polling for ID change. */
96 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_REG,
97 DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT);
98}
99
100/**
101 * da8xx_musb_disable - disable HDRC and flush interrupts
102 */
103static void da8xx_musb_disable(struct musb *musb)
104{
105 void __iomem *reg_base = musb->ctrl_base;
106
107 musb_writel(reg_base, DA8XX_USB_INTR_MASK_CLEAR_REG,
108 DA8XX_INTR_USB_MASK |
109 DA8XX_INTR_TX_MASK | DA8XX_INTR_RX_MASK);
110 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
111}
112
113#define portstate(stmt) stmt
114
115static void da8xx_musb_set_vbus(struct musb *musb, int is_on)
116{
117 WARN_ON(is_on && is_peripheral_active(musb));
118}
119
120#define POLL_SECONDS 2
121
122static void otg_timer(struct timer_list *t)
123{
124 struct musb *musb = from_timer(musb, t, dev_timer);
125 void __iomem *mregs = musb->mregs;
126 u8 devctl;
127 unsigned long flags;
128
129 /*
130 * We poll because DaVinci's won't expose several OTG-critical
131 * status change events (from the transceiver) otherwise.
132 */
133 devctl = musb_readb(mregs, MUSB_DEVCTL);
134 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
135 usb_otg_state_string(musb->xceiv->otg->state));
136
137 spin_lock_irqsave(&musb->lock, flags);
138 switch (musb->xceiv->otg->state) {
139 case OTG_STATE_A_WAIT_BCON:
140 devctl &= ~MUSB_DEVCTL_SESSION;
141 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
142
143 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
144 if (devctl & MUSB_DEVCTL_BDEVICE) {
145 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
146 MUSB_DEV_MODE(musb);
147 } else {
148 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
149 MUSB_HST_MODE(musb);
150 }
151 break;
152 case OTG_STATE_A_WAIT_VFALL:
153 /*
154 * Wait till VBUS falls below SessionEnd (~0.2 V); the 1.3
155 * RTL seems to mis-handle session "start" otherwise (or in
156 * our case "recover"), in routine "VBUS was valid by the time
157 * VBUSERR got reported during enumeration" cases.
158 */
159 if (devctl & MUSB_DEVCTL_VBUS) {
160 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
161 break;
162 }
163 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
164 musb_writel(musb->ctrl_base, DA8XX_USB_INTR_SRC_SET_REG,
165 MUSB_INTR_VBUSERROR << DA8XX_INTR_USB_SHIFT);
166 break;
167 case OTG_STATE_B_IDLE:
168 /*
169 * There's no ID-changed IRQ, so we have no good way to tell
170 * when to switch to the A-Default state machine (by setting
171 * the DEVCTL.Session bit).
172 *
173 * Workaround: whenever we're in B_IDLE, try setting the
174 * session flag every few seconds. If it works, ID was
175 * grounded and we're now in the A-Default state machine.
176 *
177 * NOTE: setting the session flag is _supposed_ to trigger
178 * SRP but clearly it doesn't.
179 */
180 musb_writeb(mregs, MUSB_DEVCTL, devctl | MUSB_DEVCTL_SESSION);
181 devctl = musb_readb(mregs, MUSB_DEVCTL);
182 if (devctl & MUSB_DEVCTL_BDEVICE)
183 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
184 else
185 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
186 break;
187 default:
188 break;
189 }
190 spin_unlock_irqrestore(&musb->lock, flags);
191}
192
193static void da8xx_musb_try_idle(struct musb *musb, unsigned long timeout)
194{
195 static unsigned long last_timer;
196
197 if (timeout == 0)
198 timeout = jiffies + msecs_to_jiffies(3);
199
200 /* Never idle if active, or when VBUS timeout is not set as host */
201 if (musb->is_active || (musb->a_wait_bcon == 0 &&
202 musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)) {
203 dev_dbg(musb->controller, "%s active, deleting timer\n",
204 usb_otg_state_string(musb->xceiv->otg->state));
205 del_timer(&musb->dev_timer);
206 last_timer = jiffies;
207 return;
208 }
209
210 if (time_after(last_timer, timeout) && timer_pending(&musb->dev_timer)) {
211 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
212 return;
213 }
214 last_timer = timeout;
215
216 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
217 usb_otg_state_string(musb->xceiv->otg->state),
218 jiffies_to_msecs(timeout - jiffies));
219 mod_timer(&musb->dev_timer, timeout);
220}
221
222static irqreturn_t da8xx_musb_interrupt(int irq, void *hci)
223{
224 struct musb *musb = hci;
225 void __iomem *reg_base = musb->ctrl_base;
226 struct usb_otg *otg = musb->xceiv->otg;
227 unsigned long flags;
228 irqreturn_t ret = IRQ_NONE;
229 u32 status;
230
231 spin_lock_irqsave(&musb->lock, flags);
232
233 /*
234 * NOTE: DA8XX shadows the Mentor IRQs. Don't manage them through
235 * the Mentor registers (except for setup), use the TI ones and EOI.
236 */
237
238 /* Acknowledge and handle non-CPPI interrupts */
239 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
240 if (!status)
241 goto eoi;
242
243 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
244 dev_dbg(musb->controller, "USB IRQ %08x\n", status);
245
246 musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
247 musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
248 musb->int_usb = (status & DA8XX_INTR_USB_MASK) >> DA8XX_INTR_USB_SHIFT;
249
250 /*
251 * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
252 * DA8xx's missing ID change IRQ. We need an ID change IRQ to
253 * switch appropriately between halves of the OTG state machine.
254 * Managing DEVCTL.Session per Mentor docs requires that we know its
255 * value but DEVCTL.BDevice is invalid without DEVCTL.Session set.
256 * Also, DRVVBUS pulses for SRP (but not at 5 V)...
257 */
258 if (status & (DA8XX_INTR_DRVVBUS << DA8XX_INTR_USB_SHIFT)) {
259 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
260 void __iomem *mregs = musb->mregs;
261 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
262 int err;
263
264 err = musb->int_usb & MUSB_INTR_VBUSERROR;
265 if (err) {
266 /*
267 * The Mentor core doesn't debounce VBUS as needed
268 * to cope with device connect current spikes. This
269 * means it's not uncommon for bus-powered devices
270 * to get VBUS errors during enumeration.
271 *
272 * This is a workaround, but newer RTL from Mentor
273 * seems to allow a better one: "re"-starting sessions
274 * without waiting for VBUS to stop registering in
275 * devctl.
276 */
277 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
278 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
279 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
280 WARNING("VBUS error workaround (delay coming)\n");
281 } else if (drvvbus) {
282 MUSB_HST_MODE(musb);
283 otg->default_a = 1;
284 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
285 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
286 del_timer(&musb->dev_timer);
287 } else if (!(musb->int_usb & MUSB_INTR_BABBLE)) {
288 /*
289 * When babble condition happens, drvvbus interrupt
290 * is also generated. Ignore this drvvbus interrupt
291 * and let babble interrupt handler recovers the
292 * controller; otherwise, the host-mode flag is lost
293 * due to the MUSB_DEV_MODE() call below and babble
294 * recovery logic will not be called.
295 */
296 musb->is_active = 0;
297 MUSB_DEV_MODE(musb);
298 otg->default_a = 0;
299 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
300 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
301 }
302
303 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
304 drvvbus ? "on" : "off",
305 usb_otg_state_string(musb->xceiv->otg->state),
306 err ? " ERROR" : "",
307 devctl);
308 ret = IRQ_HANDLED;
309 }
310
311 if (musb->int_tx || musb->int_rx || musb->int_usb)
312 ret |= musb_interrupt(musb);
313
314 eoi:
315 /* EOI needs to be written for the IRQ to be re-asserted. */
316 if (ret == IRQ_HANDLED || status)
317 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
318
319 /* Poll for ID change */
320 if (musb->xceiv->otg->state == OTG_STATE_B_IDLE)
321 mod_timer(&musb->dev_timer, jiffies + POLL_SECONDS * HZ);
322
323 spin_unlock_irqrestore(&musb->lock, flags);
324
325 return ret;
326}
327
328static int da8xx_musb_set_mode(struct musb *musb, u8 musb_mode)
329{
330 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
331 enum phy_mode phy_mode;
332
333 /*
334 * The PHY has some issues when it is forced in device or host mode.
335 * Unless the user request another mode, configure the PHY in OTG mode.
336 */
337 if (!musb->is_initialized)
338 return phy_set_mode(glue->phy, PHY_MODE_USB_OTG);
339
340 switch (musb_mode) {
341 case MUSB_HOST: /* Force VBUS valid, ID = 0 */
342 phy_mode = PHY_MODE_USB_HOST;
343 break;
344 case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
345 phy_mode = PHY_MODE_USB_DEVICE;
346 break;
347 case MUSB_OTG: /* Don't override the VBUS/ID comparators */
348 phy_mode = PHY_MODE_USB_OTG;
349 break;
350 default:
351 return -EINVAL;
352 }
353
354 return phy_set_mode(glue->phy, phy_mode);
355}
356
357static int da8xx_musb_init(struct musb *musb)
358{
359 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
360 void __iomem *reg_base = musb->ctrl_base;
361 u32 rev;
362 int ret = -ENODEV;
363
364 musb->mregs += DA8XX_MENTOR_CORE_OFFSET;
365
366 ret = clk_prepare_enable(glue->clk);
367 if (ret) {
368 dev_err(glue->dev, "failed to enable clock\n");
369 return ret;
370 }
371
372 /* Returns zero if e.g. not clocked */
373 rev = musb_readl(reg_base, DA8XX_USB_REVISION_REG);
374 if (!rev)
375 goto fail;
376
377 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
378 if (IS_ERR_OR_NULL(musb->xceiv)) {
379 ret = -EPROBE_DEFER;
380 goto fail;
381 }
382
383 timer_setup(&musb->dev_timer, otg_timer, 0);
384
385 /* Reset the controller */
386 musb_writel(reg_base, DA8XX_USB_CTRL_REG, DA8XX_SOFT_RESET_MASK);
387
388 /* Start the on-chip PHY and its PLL. */
389 ret = phy_init(glue->phy);
390 if (ret) {
391 dev_err(glue->dev, "Failed to init phy.\n");
392 goto fail;
393 }
394
395 ret = phy_power_on(glue->phy);
396 if (ret) {
397 dev_err(glue->dev, "Failed to power on phy.\n");
398 goto err_phy_power_on;
399 }
400
401 msleep(5);
402
403 /* NOTE: IRQs are in mixed mode, not bypass to pure MUSB */
404 pr_debug("DA8xx OTG revision %08x, control %02x\n", rev,
405 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
406
407 musb->isr = da8xx_musb_interrupt;
408 return 0;
409
410err_phy_power_on:
411 phy_exit(glue->phy);
412fail:
413 clk_disable_unprepare(glue->clk);
414 return ret;
415}
416
417static int da8xx_musb_exit(struct musb *musb)
418{
419 struct da8xx_glue *glue = dev_get_drvdata(musb->controller->parent);
420
421 del_timer_sync(&musb->dev_timer);
422
423 phy_power_off(glue->phy);
424 phy_exit(glue->phy);
425 clk_disable_unprepare(glue->clk);
426
427 usb_put_phy(musb->xceiv);
428
429 return 0;
430}
431
432static inline u8 get_vbus_power(struct device *dev)
433{
434 struct regulator *vbus_supply;
435 int current_uA;
436
437 vbus_supply = regulator_get_optional(dev, "vbus");
438 if (IS_ERR(vbus_supply))
439 return 255;
440 current_uA = regulator_get_current_limit(vbus_supply);
441 regulator_put(vbus_supply);
442 if (current_uA <= 0 || current_uA > 510000)
443 return 255;
444 return current_uA / 1000 / 2;
445}
446
447#ifdef CONFIG_USB_TI_CPPI41_DMA
448static void da8xx_dma_controller_callback(struct dma_controller *c)
449{
450 struct musb *musb = c->musb;
451 void __iomem *reg_base = musb->ctrl_base;
452
453 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
454}
455
456static struct dma_controller *
457da8xx_dma_controller_create(struct musb *musb, void __iomem *base)
458{
459 struct dma_controller *controller;
460
461 controller = cppi41_dma_controller_create(musb, base);
462 if (IS_ERR_OR_NULL(controller))
463 return controller;
464
465 controller->dma_callback = da8xx_dma_controller_callback;
466
467 return controller;
468}
469#endif
470
471static const struct musb_platform_ops da8xx_ops = {
472 .quirks = MUSB_INDEXED_EP | MUSB_PRESERVE_SESSION |
473 MUSB_DMA_CPPI41 | MUSB_DA8XX,
474 .init = da8xx_musb_init,
475 .exit = da8xx_musb_exit,
476
477 .fifo_mode = 2,
478#ifdef CONFIG_USB_TI_CPPI41_DMA
479 .dma_init = da8xx_dma_controller_create,
480 .dma_exit = cppi41_dma_controller_destroy,
481#endif
482 .enable = da8xx_musb_enable,
483 .disable = da8xx_musb_disable,
484
485 .set_mode = da8xx_musb_set_mode,
486 .try_idle = da8xx_musb_try_idle,
487
488 .set_vbus = da8xx_musb_set_vbus,
489};
490
491static const struct platform_device_info da8xx_dev_info = {
492 .name = "musb-hdrc",
493 .id = PLATFORM_DEVID_AUTO,
494 .dma_mask = DMA_BIT_MASK(32),
495};
496
497static const struct musb_hdrc_config da8xx_config = {
498 .ram_bits = 10,
499 .num_eps = 5,
500 .multipoint = 1,
501};
502
503static struct of_dev_auxdata da8xx_auxdata_lookup[] = {
504 OF_DEV_AUXDATA("ti,da830-cppi41", 0x01e01000, "cppi41-dmaengine",
505 NULL),
506 {}
507};
508
509static int da8xx_probe(struct platform_device *pdev)
510{
511 struct resource musb_resources[2];
512 struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
513 struct da8xx_glue *glue;
514 struct platform_device_info pinfo;
515 struct clk *clk;
516 struct device_node *np = pdev->dev.of_node;
517 int ret;
518
519 glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
520 if (!glue)
521 return -ENOMEM;
522
523 clk = devm_clk_get(&pdev->dev, NULL);
524 if (IS_ERR(clk)) {
525 dev_err(&pdev->dev, "failed to get clock\n");
526 return PTR_ERR(clk);
527 }
528
529 glue->phy = devm_phy_get(&pdev->dev, "usb-phy");
530 if (IS_ERR(glue->phy)) {
531 if (PTR_ERR(glue->phy) != -EPROBE_DEFER)
532 dev_err(&pdev->dev, "failed to get phy\n");
533 return PTR_ERR(glue->phy);
534 }
535
536 glue->dev = &pdev->dev;
537 glue->clk = clk;
538
539 if (IS_ENABLED(CONFIG_OF) && np) {
540 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
541 if (!pdata)
542 return -ENOMEM;
543
544 pdata->config = &da8xx_config;
545 pdata->mode = musb_get_mode(&pdev->dev);
546 pdata->power = get_vbus_power(&pdev->dev);
547 }
548
549 pdata->platform_ops = &da8xx_ops;
550
551 glue->usb_phy = usb_phy_generic_register();
552 ret = PTR_ERR_OR_ZERO(glue->usb_phy);
553 if (ret) {
554 dev_err(&pdev->dev, "failed to register usb_phy\n");
555 return ret;
556 }
557 platform_set_drvdata(pdev, glue);
558
559 ret = of_platform_populate(pdev->dev.of_node, NULL,
560 da8xx_auxdata_lookup, &pdev->dev);
561 if (ret)
562 return ret;
563
564 memset(musb_resources, 0x00, sizeof(*musb_resources) *
565 ARRAY_SIZE(musb_resources));
566
567 musb_resources[0].name = pdev->resource[0].name;
568 musb_resources[0].start = pdev->resource[0].start;
569 musb_resources[0].end = pdev->resource[0].end;
570 musb_resources[0].flags = pdev->resource[0].flags;
571
572 musb_resources[1].name = pdev->resource[1].name;
573 musb_resources[1].start = pdev->resource[1].start;
574 musb_resources[1].end = pdev->resource[1].end;
575 musb_resources[1].flags = pdev->resource[1].flags;
576
577 pinfo = da8xx_dev_info;
578 pinfo.parent = &pdev->dev;
579 pinfo.res = musb_resources;
580 pinfo.num_res = ARRAY_SIZE(musb_resources);
581 pinfo.data = pdata;
582 pinfo.size_data = sizeof(*pdata);
583
584 glue->musb = platform_device_register_full(&pinfo);
585 ret = PTR_ERR_OR_ZERO(glue->musb);
586 if (ret) {
587 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
588 usb_phy_generic_unregister(glue->usb_phy);
589 }
590
591 return ret;
592}
593
594static int da8xx_remove(struct platform_device *pdev)
595{
596 struct da8xx_glue *glue = platform_get_drvdata(pdev);
597
598 platform_device_unregister(glue->musb);
599 usb_phy_generic_unregister(glue->usb_phy);
600
601 return 0;
602}
603
604#ifdef CONFIG_PM_SLEEP
605static int da8xx_suspend(struct device *dev)
606{
607 int ret;
608 struct da8xx_glue *glue = dev_get_drvdata(dev);
609
610 ret = phy_power_off(glue->phy);
611 if (ret)
612 return ret;
613 clk_disable_unprepare(glue->clk);
614
615 return 0;
616}
617
618static int da8xx_resume(struct device *dev)
619{
620 int ret;
621 struct da8xx_glue *glue = dev_get_drvdata(dev);
622
623 ret = clk_prepare_enable(glue->clk);
624 if (ret)
625 return ret;
626 return phy_power_on(glue->phy);
627}
628#endif
629
630static SIMPLE_DEV_PM_OPS(da8xx_pm_ops, da8xx_suspend, da8xx_resume);
631
632#ifdef CONFIG_OF
633static const struct of_device_id da8xx_id_table[] = {
634 {
635 .compatible = "ti,da830-musb",
636 },
637 {},
638};
639MODULE_DEVICE_TABLE(of, da8xx_id_table);
640#endif
641
642static struct platform_driver da8xx_driver = {
643 .probe = da8xx_probe,
644 .remove = da8xx_remove,
645 .driver = {
646 .name = "musb-da8xx",
647 .pm = &da8xx_pm_ops,
648 .of_match_table = of_match_ptr(da8xx_id_table),
649 },
650};
651
652MODULE_DESCRIPTION("DA8xx/OMAP-L1x MUSB Glue Layer");
653MODULE_AUTHOR("Sergei Shtylyov <sshtylyov@ru.mvista.com>");
654MODULE_LICENSE("GPL v2");
655module_platform_driver(da8xx_driver);