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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * mtu3_hw_regs.h - MediaTek USB3 DRD register and field definitions
4 *
5 * Copyright (C) 2016 MediaTek Inc.
6 *
7 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#ifndef _SSUSB_HW_REGS_H_
11#define _SSUSB_HW_REGS_H_
12
13/* segment offset of MAC register */
14#define SSUSB_DEV_BASE 0x0000
15#define SSUSB_EPCTL_CSR_BASE 0x0800
16#define SSUSB_USB3_MAC_CSR_BASE 0x1400
17#define SSUSB_USB3_SYS_CSR_BASE 0x1400
18#define SSUSB_USB2_CSR_BASE 0x2400
19
20/* IPPC register in Infra */
21#define SSUSB_SIFSLV_IPPC_BASE 0x0000
22
23/* --------------- SSUSB_DEV REGISTER DEFINITION --------------- */
24
25#define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26#define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27#define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28#define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
29
30#define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
31#define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
32#define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
33#define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
34
35#define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
36#define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
37#define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
38#define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
39#define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
40#define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
41
42#define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
43#define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
44#define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
45
46#define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
47
48#define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
49#define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
50#define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
51#define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
52#define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
53#define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
54
55#define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
56#define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
57#define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
58
59#define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
60#define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
61#define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
62#define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
63
64#define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
65#define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
66#define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
67#define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
68#define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
69#define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
70#define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
71#define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
72
73#define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
74#define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
75#define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
76#define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
77#define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
78#define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
79#define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
80#define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
81#define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
82#define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
83#define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
84#define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
85
86#define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
87#define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
88#define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
89#define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
90#define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
91
92/*---------------- SSUSB_DEV FIELD DEFINITION ---------------*/
93
94/* U3D_LV1ISR */
95#define EP_CTRL_INTR BIT(5)
96#define MAC2_INTR BIT(4)
97#define DMA_INTR BIT(3)
98#define MAC3_INTR BIT(2)
99#define QMU_INTR BIT(1)
100#define BMU_INTR BIT(0)
101
102/* U3D_LV1IECR */
103#define LV1IECR_MSK GENMASK(31, 0)
104
105/* U3D_EPISR */
106#define EPRISR(x) (BIT(16) << (x))
107#define EPTISR(x) (BIT(0) << (x))
108#define EP0ISR BIT(0)
109
110/* U3D_EP0CSR */
111#define EP0_SENDSTALL BIT(25)
112#define EP0_FIFOFULL BIT(23)
113#define EP0_SENTSTALL BIT(22)
114#define EP0_DPHTX BIT(20)
115#define EP0_DATAEND BIT(19)
116#define EP0_TXPKTRDY BIT(18)
117#define EP0_SETUPPKTRDY BIT(17)
118#define EP0_RXPKTRDY BIT(16)
119#define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
120#define EP0_MAXPKTSZ(x) ((x) & EP0_MAXPKTSZ_MSK)
121#define EP0_W1C_BITS (~(EP0_RXPKTRDY | EP0_SETUPPKTRDY | EP0_SENTSTALL))
122
123/* U3D_TX1CSR0 */
124#define TX_DMAREQEN BIT(29)
125#define TX_FIFOFULL BIT(25)
126#define TX_FIFOEMPTY BIT(24)
127#define TX_SENTSTALL BIT(22)
128#define TX_SENDSTALL BIT(21)
129#define TX_TXPKTRDY BIT(16)
130#define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
131#define TX_TXMAXPKTSZ(x) ((x) & TX_TXMAXPKTSZ_MSK)
132#define TX_W1C_BITS (~(TX_SENTSTALL))
133
134/* U3D_TX1CSR1 */
135#define TX_MULT(x) (((x) & 0x3) << 22)
136#define TX_MAX_PKT(x) (((x) & 0x3f) << 16)
137#define TX_SLOT(x) (((x) & 0x3f) << 8)
138#define TX_TYPE(x) (((x) & 0x3) << 4)
139#define TX_SS_BURST(x) (((x) & 0xf) << 0)
140
141/* for TX_TYPE & RX_TYPE */
142#define TYPE_BULK (0x0)
143#define TYPE_INT (0x1)
144#define TYPE_ISO (0x2)
145#define TYPE_MASK (0x3)
146
147/* U3D_TX1CSR2 */
148#define TX_BINTERVAL(x) (((x) & 0xff) << 24)
149#define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
150#define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
151
152/* U3D_RX1CSR0 */
153#define RX_DMAREQEN BIT(29)
154#define RX_SENTSTALL BIT(22)
155#define RX_SENDSTALL BIT(21)
156#define RX_RXPKTRDY BIT(16)
157#define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
158#define RX_RXMAXPKTSZ(x) ((x) & RX_RXMAXPKTSZ_MSK)
159#define RX_W1C_BITS (~(RX_SENTSTALL | RX_RXPKTRDY))
160
161/* U3D_RX1CSR1 */
162#define RX_MULT(x) (((x) & 0x3) << 22)
163#define RX_MAX_PKT(x) (((x) & 0x3f) << 16)
164#define RX_SLOT(x) (((x) & 0x3f) << 8)
165#define RX_TYPE(x) (((x) & 0x3) << 4)
166#define RX_SS_BURST(x) (((x) & 0xf) << 0)
167
168/* U3D_RX1CSR2 */
169#define RX_BINTERVAL(x) (((x) & 0xff) << 24)
170#define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
171#define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
172
173/* U3D_QCR0 */
174#define QMU_RX_CS_EN(x) (BIT(16) << (x))
175#define QMU_TX_CS_EN(x) (BIT(0) << (x))
176#define QMU_CS16B_EN BIT(0)
177
178/* U3D_QCR1 */
179#define QMU_TX_ZLP(x) (BIT(0) << (x))
180
181/* U3D_QCR3 */
182#define QMU_RX_COZ(x) (BIT(16) << (x))
183#define QMU_RX_ZLP(x) (BIT(0) << (x))
184
185/* U3D_TXQHIAR1 */
186/* U3D_RXQHIAR1 */
187#define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
188#define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
189#define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
190#define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
191
192/* U3D_TXQCSR1 */
193/* U3D_RXQCSR1 */
194#define QMU_Q_ACTIVE BIT(15)
195#define QMU_Q_STOP BIT(2)
196#define QMU_Q_RESUME BIT(1)
197#define QMU_Q_START BIT(0)
198
199/* U3D_QISAR0, U3D_QIER0, U3D_QIESR0, U3D_QIECR0 */
200#define QMU_RX_DONE_INT(x) (BIT(16) << (x))
201#define QMU_TX_DONE_INT(x) (BIT(0) << (x))
202
203/* U3D_QISAR1, U3D_QIER1, U3D_QIESR1, U3D_QIECR1 */
204#define RXQ_ZLPERR_INT BIT(20)
205#define RXQ_LENERR_INT BIT(18)
206#define RXQ_CSERR_INT BIT(17)
207#define RXQ_EMPTY_INT BIT(16)
208#define TXQ_LENERR_INT BIT(2)
209#define TXQ_CSERR_INT BIT(1)
210#define TXQ_EMPTY_INT BIT(0)
211
212/* U3D_TQERRIR0, U3D_TQERRIER0, U3D_TQERRIESR0, U3D_TQERRIECR0 */
213#define QMU_TX_LEN_ERR(x) (BIT(16) << (x))
214#define QMU_TX_CS_ERR(x) (BIT(0) << (x))
215
216/* U3D_RQERRIR0, U3D_RQERRIER0, U3D_RQERRIESR0, U3D_RQERRIECR0 */
217#define QMU_RX_LEN_ERR(x) (BIT(16) << (x))
218#define QMU_RX_CS_ERR(x) (BIT(0) << (x))
219
220/* U3D_RQERRIR1, U3D_RQERRIER1, U3D_RQERRIESR1, U3D_RQERRIECR1 */
221#define QMU_RX_ZLP_ERR(n) (BIT(16) << (n))
222
223/* U3D_CAP_EPINFO */
224#define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
225#define CAP_TX_EP_NUM(x) ((x) & 0x1f)
226
227/* U3D_MISC_CTRL */
228#define DMA_ADDR_36BIT BIT(31)
229#define VBUS_ON BIT(1)
230#define VBUS_FRC_EN BIT(0)
231
232
233/*---------------- SSUSB_EPCTL_CSR REGISTER DEFINITION ----------------*/
234
235#define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
236#define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
237
238#define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
239#define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
240
241/*---------------- SSUSB_EPCTL_CSR FIELD DEFINITION ----------------*/
242
243/* U3D_DEVICE_CONF */
244#define DEV_ADDR_MSK GENMASK(30, 24)
245#define DEV_ADDR(x) ((0x7f & (x)) << 24)
246#define HW_USB2_3_SEL BIT(18)
247#define SW_USB2_3_SEL_EN BIT(17)
248#define SW_USB2_3_SEL BIT(16)
249#define SSUSB_DEV_SPEED(x) ((x) & 0x7)
250
251/* U3D_EP_RST */
252#define EP1_IN_RST BIT(17)
253#define EP1_OUT_RST BIT(1)
254#define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
255#define EP0_RST BIT(0)
256
257/* U3D_DEV_LINK_INTR_ENABLE */
258/* U3D_DEV_LINK_INTR */
259#define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
260
261
262/*---------------- SSUSB_USB3_MAC_CSR REGISTER DEFINITION ----------------*/
263
264#define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
265#define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
266
267#define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
268#define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
269
270/*---------------- SSUSB_USB3_MAC_CSR FIELD DEFINITION ----------------*/
271
272/* U3D_LTSSM_CTRL */
273#define FORCE_POLLING_FAIL BIT(4)
274#define FORCE_RXDETECT_FAIL BIT(3)
275#define SOFT_U3_EXIT_EN BIT(2)
276#define COMPLIANCE_EN BIT(1)
277#define U1_GO_U2_EN BIT(0)
278
279/* U3D_USB3_CONFIG */
280#define USB3_EN BIT(0)
281
282/* U3D_LTSSM_INTR_ENABLE */
283/* U3D_LTSSM_INTR */
284#define U3_RESUME_INTR BIT(18)
285#define U3_LFPS_TMOUT_INTR BIT(17)
286#define VBUS_FALL_INTR BIT(16)
287#define VBUS_RISE_INTR BIT(15)
288#define RXDET_SUCCESS_INTR BIT(14)
289#define EXIT_U3_INTR BIT(13)
290#define EXIT_U2_INTR BIT(12)
291#define EXIT_U1_INTR BIT(11)
292#define ENTER_U3_INTR BIT(10)
293#define ENTER_U2_INTR BIT(9)
294#define ENTER_U1_INTR BIT(8)
295#define ENTER_U0_INTR BIT(7)
296#define RECOVERY_INTR BIT(6)
297#define WARM_RST_INTR BIT(5)
298#define HOT_RST_INTR BIT(4)
299#define LOOPBACK_INTR BIT(3)
300#define COMPLIANCE_INTR BIT(2)
301#define SS_DISABLE_INTR BIT(1)
302#define SS_INACTIVE_INTR BIT(0)
303
304/*---------------- SSUSB_USB3_SYS_CSR REGISTER DEFINITION ----------------*/
305
306#define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
307#define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
308#define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
309
310/*---------------- SSUSB_USB3_SYS_CSR FIELD DEFINITION ----------------*/
311
312/* U3D_LINK_UX_INACT_TIMER */
313#define DEV_U2_INACT_TIMEOUT_MSK GENMASK(23, 16)
314#define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
315#define U2_INACT_TIMEOUT_MSK GENMASK(15, 8)
316#define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
317#define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
318
319/* U3D_LINK_POWER_CONTROL */
320#define SW_U2_ACCEPT_ENABLE BIT(9)
321#define SW_U1_ACCEPT_ENABLE BIT(8)
322#define UX_EXIT BIT(5)
323#define LGO_U3 BIT(4)
324#define LGO_U2 BIT(3)
325#define LGO_U1 BIT(2)
326#define SW_U2_REQUEST_ENABLE BIT(1)
327#define SW_U1_REQUEST_ENABLE BIT(0)
328
329/* U3D_LINK_ERR_COUNT */
330#define CLR_LINK_ERR_CNT BIT(16)
331#define LINK_ERROR_COUNT GENMASK(15, 0)
332
333/*---------------- SSUSB_USB2_CSR REGISTER DEFINITION ----------------*/
334
335#define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
336#define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
337#define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
338#define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
339#define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
340#define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
341#define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
342#define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
343#define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
344
345/*---------------- SSUSB_USB2_CSR FIELD DEFINITION ----------------*/
346
347/* U3D_POWER_MANAGEMENT */
348#define LPM_BESL_STALL BIT(14)
349#define LPM_BESLD_STALL BIT(13)
350#define LPM_RWP BIT(11)
351#define LPM_HRWE BIT(10)
352#define LPM_MODE(x) (((x) & 0x3) << 8)
353#define ISO_UPDATE BIT(7)
354#define SOFT_CONN BIT(6)
355#define HS_ENABLE BIT(5)
356#define RESUME BIT(2)
357#define SUSPENDM_ENABLE BIT(0)
358
359/* U3D_DEVICE_CONTROL */
360#define DC_HOSTREQ BIT(1)
361#define DC_SESSION BIT(0)
362
363/* U3D_USB2_TEST_MODE */
364#define U2U3_AUTO_SWITCH BIT(10)
365#define LPM_FORCE_STALL BIT(8)
366#define FIFO_ACCESS BIT(6)
367#define FORCE_FS BIT(5)
368#define FORCE_HS BIT(4)
369#define TEST_PACKET_MODE BIT(3)
370#define TEST_K_MODE BIT(2)
371#define TEST_J_MODE BIT(1)
372#define TEST_SE0_NAK_MODE BIT(0)
373
374/* U3D_COMMON_USB_INTR_ENABLE */
375/* U3D_COMMON_USB_INTR */
376#define LPM_RESUME_INTR BIT(9)
377#define LPM_INTR BIT(8)
378#define DISCONN_INTR BIT(5)
379#define CONN_INTR BIT(4)
380#define SOF_INTR BIT(3)
381#define RESET_INTR BIT(2)
382#define RESUME_INTR BIT(1)
383#define SUSPEND_INTR BIT(0)
384
385/* U3D_LINK_RESET_INFO */
386#define WTCHRP_MSK GENMASK(19, 16)
387
388/* U3D_USB20_LPM_PARAMETER */
389#define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
390#define LPM_BESLCK(x) (((x) & 0xf) << 8)
391#define LPM_BESLDCK(x) (((x) & 0xf) << 4)
392#define LPM_BESL GENMASK(3, 0)
393
394/* U3D_USB20_MISC_CONTROL */
395#define LPM_U3_ACK_EN BIT(0)
396
397/*---------------- SSUSB_SIFSLV_IPPC REGISTER DEFINITION ----------------*/
398
399#define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
400#define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
401#define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
402#define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
403#define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
404#define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
405#define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
406#define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
407#define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
408#define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
409#define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
410#define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
411#define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
412#define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
413#define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
414#define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
415#define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
416#define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
417
418/*---------------- SSUSB_SIFSLV_IPPC FIELD DEFINITION ----------------*/
419
420/* U3D_SSUSB_IP_PW_CTRL0 */
421#define SSUSB_IP_SW_RST BIT(0)
422
423/* U3D_SSUSB_IP_PW_CTRL1 */
424#define SSUSB_IP_HOST_PDN BIT(0)
425
426/* U3D_SSUSB_IP_PW_CTRL2 */
427#define SSUSB_IP_DEV_PDN BIT(0)
428
429/* U3D_SSUSB_IP_PW_CTRL3 */
430#define SSUSB_IP_PCIE_PDN BIT(0)
431
432/* U3D_SSUSB_IP_PW_STS1 */
433#define SSUSB_IP_SLEEP_STS BIT(30)
434#define SSUSB_U3_MAC_RST_B_STS BIT(16)
435#define SSUSB_XHCI_RST_B_STS BIT(11)
436#define SSUSB_SYS125_RST_B_STS BIT(10)
437#define SSUSB_REF_RST_B_STS BIT(8)
438#define SSUSB_SYSPLL_STABLE BIT(0)
439
440/* U3D_SSUSB_IP_PW_STS2 */
441#define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
442
443/* U3D_SSUSB_OTG_STS */
444#define SSUSB_VBUS_VALID BIT(9)
445
446/* U3D_SSUSB_OTG_STS_CLR */
447#define SSUSB_VBUS_INTR_CLR BIT(6)
448
449/* U3D_SSUSB_IP_XHCI_CAP */
450#define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
451#define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
452
453/* U3D_SSUSB_IP_DEV_CAP */
454#define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
455
456/* U3D_SSUSB_OTG_INT_EN */
457#define SSUSB_VBUS_CHG_INT_A_EN BIT(7)
458#define SSUSB_VBUS_CHG_INT_B_EN BIT(6)
459
460/* U3D_SSUSB_U3_CTRL_0P */
461#define SSUSB_U3_PORT_SSP_SPEED BIT(9)
462#define SSUSB_U3_PORT_HOST_SEL BIT(2)
463#define SSUSB_U3_PORT_PDN BIT(1)
464#define SSUSB_U3_PORT_DIS BIT(0)
465
466/* U3D_SSUSB_U2_CTRL_0P */
467#define SSUSB_U2_PORT_RG_IDDIG BIT(12)
468#define SSUSB_U2_PORT_FORCE_IDDIG BIT(11)
469#define SSUSB_U2_PORT_VBUSVALID BIT(9)
470#define SSUSB_U2_PORT_OTG_SEL BIT(7)
471#define SSUSB_U2_PORT_HOST BIT(2)
472#define SSUSB_U2_PORT_PDN BIT(1)
473#define SSUSB_U2_PORT_DIS BIT(0)
474#define SSUSB_U2_PORT_HOST_SEL (SSUSB_U2_PORT_VBUSVALID | SSUSB_U2_PORT_HOST)
475
476/* U3D_SSUSB_DEV_RST_CTRL */
477#define SSUSB_DEV_SW_RST BIT(0)
478
479#endif /* _SSUSB_HW_REGS_H_ */