Loading...
Note: File does not exist in v4.17.
1/*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#undef DEBUG
25#undef VERBOSE
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/ioport.h>
30#include <linux/types.h>
31#include <linux/errno.h>
32#include <linux/delay.h>
33#include <linux/slab.h>
34#include <linux/init.h>
35#include <linux/timer.h>
36#include <linux/list.h>
37#include <linux/interrupt.h>
38#include <linux/proc_fs.h>
39#include <linux/mm.h>
40#include <linux/moduleparam.h>
41#include <linux/platform_device.h>
42#include <linux/usb/ch9.h>
43#include <linux/usb/gadget.h>
44#include <linux/usb/otg.h>
45#include <linux/dma-mapping.h>
46#include <linux/clk.h>
47#include <linux/prefetch.h>
48
49#include <asm/byteorder.h>
50#include <asm/io.h>
51#include <asm/irq.h>
52#include <asm/system.h>
53#include <asm/unaligned.h>
54#include <asm/mach-types.h>
55
56#include <plat/dma.h>
57#include <plat/usb.h>
58
59#include "omap_udc.h"
60
61#undef USB_TRACE
62
63/* bulk DMA seems to be behaving for both IN and OUT */
64#define USE_DMA
65
66/* ISO too */
67#define USE_ISO
68
69#define DRIVER_DESC "OMAP UDC driver"
70#define DRIVER_VERSION "4 October 2004"
71
72#define DMA_ADDR_INVALID (~(dma_addr_t)0)
73
74#define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
75#define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
76
77/*
78 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
79 * D+ pullup to allow enumeration. That's too early for the gadget
80 * framework to use from usb_endpoint_enable(), which happens after
81 * enumeration as part of activating an interface. (But if we add an
82 * optional new "UDC not yet running" state to the gadget driver model,
83 * even just during driver binding, the endpoint autoconfig logic is the
84 * natural spot to manufacture new endpoints.)
85 *
86 * So instead of using endpoint enable calls to control the hardware setup,
87 * this driver defines a "fifo mode" parameter. It's used during driver
88 * initialization to choose among a set of pre-defined endpoint configs.
89 * See omap_udc_setup() for available modes, or to add others. That code
90 * lives in an init section, so use this driver as a module if you need
91 * to change the fifo mode after the kernel boots.
92 *
93 * Gadget drivers normally ignore endpoints they don't care about, and
94 * won't include them in configuration descriptors. That means only
95 * misbehaving hosts would even notice they exist.
96 */
97#ifdef USE_ISO
98static unsigned fifo_mode = 3;
99#else
100static unsigned fifo_mode = 0;
101#endif
102
103/* "modprobe omap_udc fifo_mode=42", or else as a kernel
104 * boot parameter "omap_udc:fifo_mode=42"
105 */
106module_param (fifo_mode, uint, 0);
107MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
108
109#ifdef USE_DMA
110static unsigned use_dma = 1;
111
112/* "modprobe omap_udc use_dma=y", or else as a kernel
113 * boot parameter "omap_udc:use_dma=y"
114 */
115module_param (use_dma, bool, 0);
116MODULE_PARM_DESC (use_dma, "enable/disable DMA");
117#else /* !USE_DMA */
118
119/* save a bit of code */
120#define use_dma 0
121#endif /* !USE_DMA */
122
123
124static const char driver_name [] = "omap_udc";
125static const char driver_desc [] = DRIVER_DESC;
126
127/*-------------------------------------------------------------------------*/
128
129/* there's a notion of "current endpoint" for modifying endpoint
130 * state, and PIO access to its FIFO.
131 */
132
133static void use_ep(struct omap_ep *ep, u16 select)
134{
135 u16 num = ep->bEndpointAddress & 0x0f;
136
137 if (ep->bEndpointAddress & USB_DIR_IN)
138 num |= UDC_EP_DIR;
139 omap_writew(num | select, UDC_EP_NUM);
140 /* when select, MUST deselect later !! */
141}
142
143static inline void deselect_ep(void)
144{
145 u16 w;
146
147 w = omap_readw(UDC_EP_NUM);
148 w &= ~UDC_EP_SEL;
149 omap_writew(w, UDC_EP_NUM);
150 /* 6 wait states before TX will happen */
151}
152
153static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
154
155/*-------------------------------------------------------------------------*/
156
157static int omap_ep_enable(struct usb_ep *_ep,
158 const struct usb_endpoint_descriptor *desc)
159{
160 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
161 struct omap_udc *udc;
162 unsigned long flags;
163 u16 maxp;
164
165 /* catch various bogus parameters */
166 if (!_ep || !desc || ep->desc
167 || desc->bDescriptorType != USB_DT_ENDPOINT
168 || ep->bEndpointAddress != desc->bEndpointAddress
169 || ep->maxpacket < le16_to_cpu
170 (desc->wMaxPacketSize)) {
171 DBG("%s, bad ep or descriptor\n", __func__);
172 return -EINVAL;
173 }
174 maxp = le16_to_cpu (desc->wMaxPacketSize);
175 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
176 && maxp != ep->maxpacket)
177 || le16_to_cpu(desc->wMaxPacketSize) > ep->maxpacket
178 || !desc->wMaxPacketSize) {
179 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
180 return -ERANGE;
181 }
182
183#ifdef USE_ISO
184 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
185 && desc->bInterval != 1)) {
186 /* hardware wants period = 1; USB allows 2^(Interval-1) */
187 DBG("%s, unsupported ISO period %dms\n", _ep->name,
188 1 << (desc->bInterval - 1));
189 return -EDOM;
190 }
191#else
192 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
193 DBG("%s, ISO nyet\n", _ep->name);
194 return -EDOM;
195 }
196#endif
197
198 /* xfer types must match, except that interrupt ~= bulk */
199 if (ep->bmAttributes != desc->bmAttributes
200 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
201 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
202 DBG("%s, %s type mismatch\n", __func__, _ep->name);
203 return -EINVAL;
204 }
205
206 udc = ep->udc;
207 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
208 DBG("%s, bogus device state\n", __func__);
209 return -ESHUTDOWN;
210 }
211
212 spin_lock_irqsave(&udc->lock, flags);
213
214 ep->desc = desc;
215 ep->irqs = 0;
216 ep->stopped = 0;
217 ep->ep.maxpacket = maxp;
218
219 /* set endpoint to initial state */
220 ep->dma_channel = 0;
221 ep->has_dma = 0;
222 ep->lch = -1;
223 use_ep(ep, UDC_EP_SEL);
224 omap_writew(udc->clr_halt, UDC_CTRL);
225 ep->ackwait = 0;
226 deselect_ep();
227
228 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
229 list_add(&ep->iso, &udc->iso);
230
231 /* maybe assign a DMA channel to this endpoint */
232 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
233 /* FIXME ISO can dma, but prefers first channel */
234 dma_channel_claim(ep, 0);
235
236 /* PIO OUT may RX packets */
237 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
238 && !ep->has_dma
239 && !(ep->bEndpointAddress & USB_DIR_IN)) {
240 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
241 ep->ackwait = 1 + ep->double_buf;
242 }
243
244 spin_unlock_irqrestore(&udc->lock, flags);
245 VDBG("%s enabled\n", _ep->name);
246 return 0;
247}
248
249static void nuke(struct omap_ep *, int status);
250
251static int omap_ep_disable(struct usb_ep *_ep)
252{
253 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
254 unsigned long flags;
255
256 if (!_ep || !ep->desc) {
257 DBG("%s, %s not enabled\n", __func__,
258 _ep ? ep->ep.name : NULL);
259 return -EINVAL;
260 }
261
262 spin_lock_irqsave(&ep->udc->lock, flags);
263 ep->desc = NULL;
264 nuke (ep, -ESHUTDOWN);
265 ep->ep.maxpacket = ep->maxpacket;
266 ep->has_dma = 0;
267 omap_writew(UDC_SET_HALT, UDC_CTRL);
268 list_del_init(&ep->iso);
269 del_timer(&ep->timer);
270
271 spin_unlock_irqrestore(&ep->udc->lock, flags);
272
273 VDBG("%s disabled\n", _ep->name);
274 return 0;
275}
276
277/*-------------------------------------------------------------------------*/
278
279static struct usb_request *
280omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
281{
282 struct omap_req *req;
283
284 req = kzalloc(sizeof(*req), gfp_flags);
285 if (req) {
286 req->req.dma = DMA_ADDR_INVALID;
287 INIT_LIST_HEAD (&req->queue);
288 }
289 return &req->req;
290}
291
292static void
293omap_free_request(struct usb_ep *ep, struct usb_request *_req)
294{
295 struct omap_req *req = container_of(_req, struct omap_req, req);
296
297 if (_req)
298 kfree (req);
299}
300
301/*-------------------------------------------------------------------------*/
302
303static void
304done(struct omap_ep *ep, struct omap_req *req, int status)
305{
306 unsigned stopped = ep->stopped;
307
308 list_del_init(&req->queue);
309
310 if (req->req.status == -EINPROGRESS)
311 req->req.status = status;
312 else
313 status = req->req.status;
314
315 if (use_dma && ep->has_dma) {
316 if (req->mapped) {
317 dma_unmap_single(ep->udc->gadget.dev.parent,
318 req->req.dma, req->req.length,
319 (ep->bEndpointAddress & USB_DIR_IN)
320 ? DMA_TO_DEVICE
321 : DMA_FROM_DEVICE);
322 req->req.dma = DMA_ADDR_INVALID;
323 req->mapped = 0;
324 } else
325 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
326 req->req.dma, req->req.length,
327 (ep->bEndpointAddress & USB_DIR_IN)
328 ? DMA_TO_DEVICE
329 : DMA_FROM_DEVICE);
330 }
331
332#ifndef USB_TRACE
333 if (status && status != -ESHUTDOWN)
334#endif
335 VDBG("complete %s req %p stat %d len %u/%u\n",
336 ep->ep.name, &req->req, status,
337 req->req.actual, req->req.length);
338
339 /* don't modify queue heads during completion callback */
340 ep->stopped = 1;
341 spin_unlock(&ep->udc->lock);
342 req->req.complete(&ep->ep, &req->req);
343 spin_lock(&ep->udc->lock);
344 ep->stopped = stopped;
345}
346
347/*-------------------------------------------------------------------------*/
348
349#define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
350#define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
351
352#define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
353#define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
354
355static inline int
356write_packet(u8 *buf, struct omap_req *req, unsigned max)
357{
358 unsigned len;
359 u16 *wp;
360
361 len = min(req->req.length - req->req.actual, max);
362 req->req.actual += len;
363
364 max = len;
365 if (likely((((int)buf) & 1) == 0)) {
366 wp = (u16 *)buf;
367 while (max >= 2) {
368 omap_writew(*wp++, UDC_DATA);
369 max -= 2;
370 }
371 buf = (u8 *)wp;
372 }
373 while (max--)
374 omap_writeb(*buf++, UDC_DATA);
375 return len;
376}
377
378// FIXME change r/w fifo calling convention
379
380
381// return: 0 = still running, 1 = completed, negative = errno
382static int write_fifo(struct omap_ep *ep, struct omap_req *req)
383{
384 u8 *buf;
385 unsigned count;
386 int is_last;
387 u16 ep_stat;
388
389 buf = req->req.buf + req->req.actual;
390 prefetch(buf);
391
392 /* PIO-IN isn't double buffered except for iso */
393 ep_stat = omap_readw(UDC_STAT_FLG);
394 if (ep_stat & UDC_FIFO_UNWRITABLE)
395 return 0;
396
397 count = ep->ep.maxpacket;
398 count = write_packet(buf, req, count);
399 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
400 ep->ackwait = 1;
401
402 /* last packet is often short (sometimes a zlp) */
403 if (count != ep->ep.maxpacket)
404 is_last = 1;
405 else if (req->req.length == req->req.actual
406 && !req->req.zero)
407 is_last = 1;
408 else
409 is_last = 0;
410
411 /* NOTE: requests complete when all IN data is in a
412 * FIFO (or sometimes later, if a zlp was needed).
413 * Use usb_ep_fifo_status() where needed.
414 */
415 if (is_last)
416 done(ep, req, 0);
417 return is_last;
418}
419
420static inline int
421read_packet(u8 *buf, struct omap_req *req, unsigned avail)
422{
423 unsigned len;
424 u16 *wp;
425
426 len = min(req->req.length - req->req.actual, avail);
427 req->req.actual += len;
428 avail = len;
429
430 if (likely((((int)buf) & 1) == 0)) {
431 wp = (u16 *)buf;
432 while (avail >= 2) {
433 *wp++ = omap_readw(UDC_DATA);
434 avail -= 2;
435 }
436 buf = (u8 *)wp;
437 }
438 while (avail--)
439 *buf++ = omap_readb(UDC_DATA);
440 return len;
441}
442
443// return: 0 = still running, 1 = queue empty, negative = errno
444static int read_fifo(struct omap_ep *ep, struct omap_req *req)
445{
446 u8 *buf;
447 unsigned count, avail;
448 int is_last;
449
450 buf = req->req.buf + req->req.actual;
451 prefetchw(buf);
452
453 for (;;) {
454 u16 ep_stat = omap_readw(UDC_STAT_FLG);
455
456 is_last = 0;
457 if (ep_stat & FIFO_EMPTY) {
458 if (!ep->double_buf)
459 break;
460 ep->fnf = 1;
461 }
462 if (ep_stat & UDC_EP_HALTED)
463 break;
464
465 if (ep_stat & UDC_FIFO_FULL)
466 avail = ep->ep.maxpacket;
467 else {
468 avail = omap_readw(UDC_RXFSTAT);
469 ep->fnf = ep->double_buf;
470 }
471 count = read_packet(buf, req, avail);
472
473 /* partial packet reads may not be errors */
474 if (count < ep->ep.maxpacket) {
475 is_last = 1;
476 /* overflowed this request? flush extra data */
477 if (count != avail) {
478 req->req.status = -EOVERFLOW;
479 avail -= count;
480 while (avail--)
481 omap_readw(UDC_DATA);
482 }
483 } else if (req->req.length == req->req.actual)
484 is_last = 1;
485 else
486 is_last = 0;
487
488 if (!ep->bEndpointAddress)
489 break;
490 if (is_last)
491 done(ep, req, 0);
492 break;
493 }
494 return is_last;
495}
496
497/*-------------------------------------------------------------------------*/
498
499static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
500{
501 dma_addr_t end;
502
503 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
504 * the last transfer's bytecount by more than a FIFO's worth.
505 */
506 if (cpu_is_omap15xx())
507 return 0;
508
509 end = omap_get_dma_src_pos(ep->lch);
510 if (end == ep->dma_counter)
511 return 0;
512
513 end |= start & (0xffff << 16);
514 if (end < start)
515 end += 0x10000;
516 return end - start;
517}
518
519static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
520{
521 dma_addr_t end;
522
523 end = omap_get_dma_dst_pos(ep->lch);
524 if (end == ep->dma_counter)
525 return 0;
526
527 end |= start & (0xffff << 16);
528 if (cpu_is_omap15xx())
529 end++;
530 if (end < start)
531 end += 0x10000;
532 return end - start;
533}
534
535
536/* Each USB transfer request using DMA maps to one or more DMA transfers.
537 * When DMA completion isn't request completion, the UDC continues with
538 * the next DMA transfer for that USB transfer.
539 */
540
541static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
542{
543 u16 txdma_ctrl, w;
544 unsigned length = req->req.length - req->req.actual;
545 const int sync_mode = cpu_is_omap15xx()
546 ? OMAP_DMA_SYNC_FRAME
547 : OMAP_DMA_SYNC_ELEMENT;
548 int dma_trigger = 0;
549
550 if (cpu_is_omap24xx())
551 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
552
553 /* measure length in either bytes or packets */
554 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
555 || (cpu_is_omap24xx() && length < ep->maxpacket)
556 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
557 txdma_ctrl = UDC_TXN_EOT | length;
558 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
559 length, 1, sync_mode, dma_trigger, 0);
560 } else {
561 length = min(length / ep->maxpacket,
562 (unsigned) UDC_TXN_TSC + 1);
563 txdma_ctrl = length;
564 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
565 ep->ep.maxpacket >> 1, length, sync_mode,
566 dma_trigger, 0);
567 length *= ep->maxpacket;
568 }
569 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
570 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
571 0, 0);
572
573 omap_start_dma(ep->lch);
574 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
575 w = omap_readw(UDC_DMA_IRQ_EN);
576 w |= UDC_TX_DONE_IE(ep->dma_channel);
577 omap_writew(w, UDC_DMA_IRQ_EN);
578 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
579 req->dma_bytes = length;
580}
581
582static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
583{
584 u16 w;
585
586 if (status == 0) {
587 req->req.actual += req->dma_bytes;
588
589 /* return if this request needs to send data or zlp */
590 if (req->req.actual < req->req.length)
591 return;
592 if (req->req.zero
593 && req->dma_bytes != 0
594 && (req->req.actual % ep->maxpacket) == 0)
595 return;
596 } else
597 req->req.actual += dma_src_len(ep, req->req.dma
598 + req->req.actual);
599
600 /* tx completion */
601 omap_stop_dma(ep->lch);
602 w = omap_readw(UDC_DMA_IRQ_EN);
603 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
604 omap_writew(w, UDC_DMA_IRQ_EN);
605 done(ep, req, status);
606}
607
608static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
609{
610 unsigned packets = req->req.length - req->req.actual;
611 int dma_trigger = 0;
612 u16 w;
613
614 if (cpu_is_omap24xx())
615 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
616
617 /* NOTE: we filtered out "short reads" before, so we know
618 * the buffer has only whole numbers of packets.
619 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
620 */
621 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
622 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
623 packets, 1, OMAP_DMA_SYNC_ELEMENT,
624 dma_trigger, 0);
625 req->dma_bytes = packets;
626 } else {
627 /* set up this DMA transfer, enable the fifo, start */
628 packets /= ep->ep.maxpacket;
629 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
630 req->dma_bytes = packets * ep->ep.maxpacket;
631 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
632 ep->ep.maxpacket >> 1, packets,
633 OMAP_DMA_SYNC_ELEMENT,
634 dma_trigger, 0);
635 }
636 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
637 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
638 0, 0);
639 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
640
641 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
642 w = omap_readw(UDC_DMA_IRQ_EN);
643 w |= UDC_RX_EOT_IE(ep->dma_channel);
644 omap_writew(w, UDC_DMA_IRQ_EN);
645 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
646 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
647
648 omap_start_dma(ep->lch);
649}
650
651static void
652finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
653{
654 u16 count, w;
655
656 if (status == 0)
657 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
658 count = dma_dest_len(ep, req->req.dma + req->req.actual);
659 count += req->req.actual;
660 if (one)
661 count--;
662 if (count <= req->req.length)
663 req->req.actual = count;
664
665 if (count != req->dma_bytes || status)
666 omap_stop_dma(ep->lch);
667
668 /* if this wasn't short, request may need another transfer */
669 else if (req->req.actual < req->req.length)
670 return;
671
672 /* rx completion */
673 w = omap_readw(UDC_DMA_IRQ_EN);
674 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
675 omap_writew(w, UDC_DMA_IRQ_EN);
676 done(ep, req, status);
677}
678
679static void dma_irq(struct omap_udc *udc, u16 irq_src)
680{
681 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
682 struct omap_ep *ep;
683 struct omap_req *req;
684
685 /* IN dma: tx to host */
686 if (irq_src & UDC_TXN_DONE) {
687 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
688 ep->irqs++;
689 /* can see TXN_DONE after dma abort */
690 if (!list_empty(&ep->queue)) {
691 req = container_of(ep->queue.next,
692 struct omap_req, queue);
693 finish_in_dma(ep, req, 0);
694 }
695 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
696
697 if (!list_empty (&ep->queue)) {
698 req = container_of(ep->queue.next,
699 struct omap_req, queue);
700 next_in_dma(ep, req);
701 }
702 }
703
704 /* OUT dma: rx from host */
705 if (irq_src & UDC_RXN_EOT) {
706 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
707 ep->irqs++;
708 /* can see RXN_EOT after dma abort */
709 if (!list_empty(&ep->queue)) {
710 req = container_of(ep->queue.next,
711 struct omap_req, queue);
712 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
713 }
714 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
715
716 if (!list_empty (&ep->queue)) {
717 req = container_of(ep->queue.next,
718 struct omap_req, queue);
719 next_out_dma(ep, req);
720 }
721 }
722
723 if (irq_src & UDC_RXN_CNT) {
724 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
725 ep->irqs++;
726 /* omap15xx does this unasked... */
727 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
728 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
729 }
730}
731
732static void dma_error(int lch, u16 ch_status, void *data)
733{
734 struct omap_ep *ep = data;
735
736 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
737 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
738 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
739
740 /* complete current transfer ... */
741}
742
743static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
744{
745 u16 reg;
746 int status, restart, is_in;
747 int dma_channel;
748
749 is_in = ep->bEndpointAddress & USB_DIR_IN;
750 if (is_in)
751 reg = omap_readw(UDC_TXDMA_CFG);
752 else
753 reg = omap_readw(UDC_RXDMA_CFG);
754 reg |= UDC_DMA_REQ; /* "pulse" activated */
755
756 ep->dma_channel = 0;
757 ep->lch = -1;
758 if (channel == 0 || channel > 3) {
759 if ((reg & 0x0f00) == 0)
760 channel = 3;
761 else if ((reg & 0x00f0) == 0)
762 channel = 2;
763 else if ((reg & 0x000f) == 0) /* preferred for ISO */
764 channel = 1;
765 else {
766 status = -EMLINK;
767 goto just_restart;
768 }
769 }
770 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
771 ep->dma_channel = channel;
772
773 if (is_in) {
774 if (cpu_is_omap24xx())
775 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
776 else
777 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
778 status = omap_request_dma(dma_channel,
779 ep->ep.name, dma_error, ep, &ep->lch);
780 if (status == 0) {
781 omap_writew(reg, UDC_TXDMA_CFG);
782 /* EMIFF or SDRC */
783 omap_set_dma_src_burst_mode(ep->lch,
784 OMAP_DMA_DATA_BURST_4);
785 omap_set_dma_src_data_pack(ep->lch, 1);
786 /* TIPB */
787 omap_set_dma_dest_params(ep->lch,
788 OMAP_DMA_PORT_TIPB,
789 OMAP_DMA_AMODE_CONSTANT,
790 UDC_DATA_DMA,
791 0, 0);
792 }
793 } else {
794 if (cpu_is_omap24xx())
795 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
796 else
797 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
798
799 status = omap_request_dma(dma_channel,
800 ep->ep.name, dma_error, ep, &ep->lch);
801 if (status == 0) {
802 omap_writew(reg, UDC_RXDMA_CFG);
803 /* TIPB */
804 omap_set_dma_src_params(ep->lch,
805 OMAP_DMA_PORT_TIPB,
806 OMAP_DMA_AMODE_CONSTANT,
807 UDC_DATA_DMA,
808 0, 0);
809 /* EMIFF or SDRC */
810 omap_set_dma_dest_burst_mode(ep->lch,
811 OMAP_DMA_DATA_BURST_4);
812 omap_set_dma_dest_data_pack(ep->lch, 1);
813 }
814 }
815 if (status)
816 ep->dma_channel = 0;
817 else {
818 ep->has_dma = 1;
819 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
820
821 /* channel type P: hw synch (fifo) */
822 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
823 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
824 }
825
826just_restart:
827 /* restart any queue, even if the claim failed */
828 restart = !ep->stopped && !list_empty(&ep->queue);
829
830 if (status)
831 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
832 restart ? " (restart)" : "");
833 else
834 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
835 is_in ? 't' : 'r',
836 ep->dma_channel - 1, ep->lch,
837 restart ? " (restart)" : "");
838
839 if (restart) {
840 struct omap_req *req;
841 req = container_of(ep->queue.next, struct omap_req, queue);
842 if (ep->has_dma)
843 (is_in ? next_in_dma : next_out_dma)(ep, req);
844 else {
845 use_ep(ep, UDC_EP_SEL);
846 (is_in ? write_fifo : read_fifo)(ep, req);
847 deselect_ep();
848 if (!is_in) {
849 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
850 ep->ackwait = 1 + ep->double_buf;
851 }
852 /* IN: 6 wait states before it'll tx */
853 }
854 }
855}
856
857static void dma_channel_release(struct omap_ep *ep)
858{
859 int shift = 4 * (ep->dma_channel - 1);
860 u16 mask = 0x0f << shift;
861 struct omap_req *req;
862 int active;
863
864 /* abort any active usb transfer request */
865 if (!list_empty(&ep->queue))
866 req = container_of(ep->queue.next, struct omap_req, queue);
867 else
868 req = NULL;
869
870 active = omap_get_dma_active_status(ep->lch);
871
872 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
873 active ? "active" : "idle",
874 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
875 ep->dma_channel - 1, req);
876
877 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
878 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
879 */
880
881 /* wait till current packet DMA finishes, and fifo empties */
882 if (ep->bEndpointAddress & USB_DIR_IN) {
883 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
884 UDC_TXDMA_CFG);
885
886 if (req) {
887 finish_in_dma(ep, req, -ECONNRESET);
888
889 /* clear FIFO; hosts probably won't empty it */
890 use_ep(ep, UDC_EP_SEL);
891 omap_writew(UDC_CLR_EP, UDC_CTRL);
892 deselect_ep();
893 }
894 while (omap_readw(UDC_TXDMA_CFG) & mask)
895 udelay(10);
896 } else {
897 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
898 UDC_RXDMA_CFG);
899
900 /* dma empties the fifo */
901 while (omap_readw(UDC_RXDMA_CFG) & mask)
902 udelay(10);
903 if (req)
904 finish_out_dma(ep, req, -ECONNRESET, 0);
905 }
906 omap_free_dma(ep->lch);
907 ep->dma_channel = 0;
908 ep->lch = -1;
909 /* has_dma still set, till endpoint is fully quiesced */
910}
911
912
913/*-------------------------------------------------------------------------*/
914
915static int
916omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
917{
918 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
919 struct omap_req *req = container_of(_req, struct omap_req, req);
920 struct omap_udc *udc;
921 unsigned long flags;
922 int is_iso = 0;
923
924 /* catch various bogus parameters */
925 if (!_req || !req->req.complete || !req->req.buf
926 || !list_empty(&req->queue)) {
927 DBG("%s, bad params\n", __func__);
928 return -EINVAL;
929 }
930 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
931 DBG("%s, bad ep\n", __func__);
932 return -EINVAL;
933 }
934 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
935 if (req->req.length > ep->ep.maxpacket)
936 return -EMSGSIZE;
937 is_iso = 1;
938 }
939
940 /* this isn't bogus, but OMAP DMA isn't the only hardware to
941 * have a hard time with partial packet reads... reject it.
942 * Except OMAP2 can handle the small packets.
943 */
944 if (use_dma
945 && ep->has_dma
946 && ep->bEndpointAddress != 0
947 && (ep->bEndpointAddress & USB_DIR_IN) == 0
948 && !cpu_class_is_omap2()
949 && (req->req.length % ep->ep.maxpacket) != 0) {
950 DBG("%s, no partial packet OUT reads\n", __func__);
951 return -EMSGSIZE;
952 }
953
954 udc = ep->udc;
955 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
956 return -ESHUTDOWN;
957
958 if (use_dma && ep->has_dma) {
959 if (req->req.dma == DMA_ADDR_INVALID) {
960 req->req.dma = dma_map_single(
961 ep->udc->gadget.dev.parent,
962 req->req.buf,
963 req->req.length,
964 (ep->bEndpointAddress & USB_DIR_IN)
965 ? DMA_TO_DEVICE
966 : DMA_FROM_DEVICE);
967 req->mapped = 1;
968 } else {
969 dma_sync_single_for_device(
970 ep->udc->gadget.dev.parent,
971 req->req.dma, req->req.length,
972 (ep->bEndpointAddress & USB_DIR_IN)
973 ? DMA_TO_DEVICE
974 : DMA_FROM_DEVICE);
975 req->mapped = 0;
976 }
977 }
978
979 VDBG("%s queue req %p, len %d buf %p\n",
980 ep->ep.name, _req, _req->length, _req->buf);
981
982 spin_lock_irqsave(&udc->lock, flags);
983
984 req->req.status = -EINPROGRESS;
985 req->req.actual = 0;
986
987 /* maybe kickstart non-iso i/o queues */
988 if (is_iso) {
989 u16 w;
990
991 w = omap_readw(UDC_IRQ_EN);
992 w |= UDC_SOF_IE;
993 omap_writew(w, UDC_IRQ_EN);
994 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
995 int is_in;
996
997 if (ep->bEndpointAddress == 0) {
998 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
999 spin_unlock_irqrestore(&udc->lock, flags);
1000 return -EL2HLT;
1001 }
1002
1003 /* empty DATA stage? */
1004 is_in = udc->ep0_in;
1005 if (!req->req.length) {
1006
1007 /* chip became CONFIGURED or ADDRESSED
1008 * earlier; drivers may already have queued
1009 * requests to non-control endpoints
1010 */
1011 if (udc->ep0_set_config) {
1012 u16 irq_en = omap_readw(UDC_IRQ_EN);
1013
1014 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1015 if (!udc->ep0_reset_config)
1016 irq_en |= UDC_EPN_RX_IE
1017 | UDC_EPN_TX_IE;
1018 omap_writew(irq_en, UDC_IRQ_EN);
1019 }
1020
1021 /* STATUS for zero length DATA stages is
1022 * always an IN ... even for IN transfers,
1023 * a weird case which seem to stall OMAP.
1024 */
1025 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1026 omap_writew(UDC_CLR_EP, UDC_CTRL);
1027 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1028 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1029
1030 /* cleanup */
1031 udc->ep0_pending = 0;
1032 done(ep, req, 0);
1033 req = NULL;
1034
1035 /* non-empty DATA stage */
1036 } else if (is_in) {
1037 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1038 } else {
1039 if (udc->ep0_setup)
1040 goto irq_wait;
1041 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1042 }
1043 } else {
1044 is_in = ep->bEndpointAddress & USB_DIR_IN;
1045 if (!ep->has_dma)
1046 use_ep(ep, UDC_EP_SEL);
1047 /* if ISO: SOF IRQs must be enabled/disabled! */
1048 }
1049
1050 if (ep->has_dma)
1051 (is_in ? next_in_dma : next_out_dma)(ep, req);
1052 else if (req) {
1053 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1054 req = NULL;
1055 deselect_ep();
1056 if (!is_in) {
1057 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1058 ep->ackwait = 1 + ep->double_buf;
1059 }
1060 /* IN: 6 wait states before it'll tx */
1061 }
1062 }
1063
1064irq_wait:
1065 /* irq handler advances the queue */
1066 if (req != NULL)
1067 list_add_tail(&req->queue, &ep->queue);
1068 spin_unlock_irqrestore(&udc->lock, flags);
1069
1070 return 0;
1071}
1072
1073static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1074{
1075 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1076 struct omap_req *req;
1077 unsigned long flags;
1078
1079 if (!_ep || !_req)
1080 return -EINVAL;
1081
1082 spin_lock_irqsave(&ep->udc->lock, flags);
1083
1084 /* make sure it's actually queued on this endpoint */
1085 list_for_each_entry (req, &ep->queue, queue) {
1086 if (&req->req == _req)
1087 break;
1088 }
1089 if (&req->req != _req) {
1090 spin_unlock_irqrestore(&ep->udc->lock, flags);
1091 return -EINVAL;
1092 }
1093
1094 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1095 int channel = ep->dma_channel;
1096
1097 /* releasing the channel cancels the request,
1098 * reclaiming the channel restarts the queue
1099 */
1100 dma_channel_release(ep);
1101 dma_channel_claim(ep, channel);
1102 } else
1103 done(ep, req, -ECONNRESET);
1104 spin_unlock_irqrestore(&ep->udc->lock, flags);
1105 return 0;
1106}
1107
1108/*-------------------------------------------------------------------------*/
1109
1110static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1111{
1112 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1113 unsigned long flags;
1114 int status = -EOPNOTSUPP;
1115
1116 spin_lock_irqsave(&ep->udc->lock, flags);
1117
1118 /* just use protocol stalls for ep0; real halts are annoying */
1119 if (ep->bEndpointAddress == 0) {
1120 if (!ep->udc->ep0_pending)
1121 status = -EINVAL;
1122 else if (value) {
1123 if (ep->udc->ep0_set_config) {
1124 WARNING("error changing config?\n");
1125 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1126 }
1127 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1128 ep->udc->ep0_pending = 0;
1129 status = 0;
1130 } else /* NOP */
1131 status = 0;
1132
1133 /* otherwise, all active non-ISO endpoints can halt */
1134 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1135
1136 /* IN endpoints must already be idle */
1137 if ((ep->bEndpointAddress & USB_DIR_IN)
1138 && !list_empty(&ep->queue)) {
1139 status = -EAGAIN;
1140 goto done;
1141 }
1142
1143 if (value) {
1144 int channel;
1145
1146 if (use_dma && ep->dma_channel
1147 && !list_empty(&ep->queue)) {
1148 channel = ep->dma_channel;
1149 dma_channel_release(ep);
1150 } else
1151 channel = 0;
1152
1153 use_ep(ep, UDC_EP_SEL);
1154 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1155 omap_writew(UDC_SET_HALT, UDC_CTRL);
1156 status = 0;
1157 } else
1158 status = -EAGAIN;
1159 deselect_ep();
1160
1161 if (channel)
1162 dma_channel_claim(ep, channel);
1163 } else {
1164 use_ep(ep, 0);
1165 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1166 ep->ackwait = 0;
1167 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1168 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1169 ep->ackwait = 1 + ep->double_buf;
1170 }
1171 }
1172 }
1173done:
1174 VDBG("%s %s halt stat %d\n", ep->ep.name,
1175 value ? "set" : "clear", status);
1176
1177 spin_unlock_irqrestore(&ep->udc->lock, flags);
1178 return status;
1179}
1180
1181static struct usb_ep_ops omap_ep_ops = {
1182 .enable = omap_ep_enable,
1183 .disable = omap_ep_disable,
1184
1185 .alloc_request = omap_alloc_request,
1186 .free_request = omap_free_request,
1187
1188 .queue = omap_ep_queue,
1189 .dequeue = omap_ep_dequeue,
1190
1191 .set_halt = omap_ep_set_halt,
1192 // fifo_status ... report bytes in fifo
1193 // fifo_flush ... flush fifo
1194};
1195
1196/*-------------------------------------------------------------------------*/
1197
1198static int omap_get_frame(struct usb_gadget *gadget)
1199{
1200 u16 sof = omap_readw(UDC_SOF);
1201 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1202}
1203
1204static int omap_wakeup(struct usb_gadget *gadget)
1205{
1206 struct omap_udc *udc;
1207 unsigned long flags;
1208 int retval = -EHOSTUNREACH;
1209
1210 udc = container_of(gadget, struct omap_udc, gadget);
1211
1212 spin_lock_irqsave(&udc->lock, flags);
1213 if (udc->devstat & UDC_SUS) {
1214 /* NOTE: OTG spec erratum says that OTG devices may
1215 * issue wakeups without host enable.
1216 */
1217 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1218 DBG("remote wakeup...\n");
1219 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1220 retval = 0;
1221 }
1222
1223 /* NOTE: non-OTG systems may use SRP TOO... */
1224 } else if (!(udc->devstat & UDC_ATT)) {
1225 if (udc->transceiver)
1226 retval = otg_start_srp(udc->transceiver);
1227 }
1228 spin_unlock_irqrestore(&udc->lock, flags);
1229
1230 return retval;
1231}
1232
1233static int
1234omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1235{
1236 struct omap_udc *udc;
1237 unsigned long flags;
1238 u16 syscon1;
1239
1240 udc = container_of(gadget, struct omap_udc, gadget);
1241 spin_lock_irqsave(&udc->lock, flags);
1242 syscon1 = omap_readw(UDC_SYSCON1);
1243 if (is_selfpowered)
1244 syscon1 |= UDC_SELF_PWR;
1245 else
1246 syscon1 &= ~UDC_SELF_PWR;
1247 omap_writew(syscon1, UDC_SYSCON1);
1248 spin_unlock_irqrestore(&udc->lock, flags);
1249
1250 return 0;
1251}
1252
1253static int can_pullup(struct omap_udc *udc)
1254{
1255 return udc->driver && udc->softconnect && udc->vbus_active;
1256}
1257
1258static void pullup_enable(struct omap_udc *udc)
1259{
1260 u16 w;
1261
1262 w = omap_readw(UDC_SYSCON1);
1263 w |= UDC_PULLUP_EN;
1264 omap_writew(w, UDC_SYSCON1);
1265 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1266 u32 l;
1267
1268 l = omap_readl(OTG_CTRL);
1269 l |= OTG_BSESSVLD;
1270 omap_writel(l, OTG_CTRL);
1271 }
1272 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1273}
1274
1275static void pullup_disable(struct omap_udc *udc)
1276{
1277 u16 w;
1278
1279 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1280 u32 l;
1281
1282 l = omap_readl(OTG_CTRL);
1283 l &= ~OTG_BSESSVLD;
1284 omap_writel(l, OTG_CTRL);
1285 }
1286 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1287 w = omap_readw(UDC_SYSCON1);
1288 w &= ~UDC_PULLUP_EN;
1289 omap_writew(w, UDC_SYSCON1);
1290}
1291
1292static struct omap_udc *udc;
1293
1294static void omap_udc_enable_clock(int enable)
1295{
1296 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1297 return;
1298
1299 if (enable) {
1300 clk_enable(udc->dc_clk);
1301 clk_enable(udc->hhc_clk);
1302 udelay(100);
1303 } else {
1304 clk_disable(udc->hhc_clk);
1305 clk_disable(udc->dc_clk);
1306 }
1307}
1308
1309/*
1310 * Called by whatever detects VBUS sessions: external transceiver
1311 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1312 */
1313static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1314{
1315 struct omap_udc *udc;
1316 unsigned long flags;
1317 u32 l;
1318
1319 udc = container_of(gadget, struct omap_udc, gadget);
1320 spin_lock_irqsave(&udc->lock, flags);
1321 VDBG("VBUS %s\n", is_active ? "on" : "off");
1322 udc->vbus_active = (is_active != 0);
1323 if (cpu_is_omap15xx()) {
1324 /* "software" detect, ignored if !VBUS_MODE_1510 */
1325 l = omap_readl(FUNC_MUX_CTRL_0);
1326 if (is_active)
1327 l |= VBUS_CTRL_1510;
1328 else
1329 l &= ~VBUS_CTRL_1510;
1330 omap_writel(l, FUNC_MUX_CTRL_0);
1331 }
1332 if (udc->dc_clk != NULL && is_active) {
1333 if (!udc->clk_requested) {
1334 omap_udc_enable_clock(1);
1335 udc->clk_requested = 1;
1336 }
1337 }
1338 if (can_pullup(udc))
1339 pullup_enable(udc);
1340 else
1341 pullup_disable(udc);
1342 if (udc->dc_clk != NULL && !is_active) {
1343 if (udc->clk_requested) {
1344 omap_udc_enable_clock(0);
1345 udc->clk_requested = 0;
1346 }
1347 }
1348 spin_unlock_irqrestore(&udc->lock, flags);
1349 return 0;
1350}
1351
1352static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1353{
1354 struct omap_udc *udc;
1355
1356 udc = container_of(gadget, struct omap_udc, gadget);
1357 if (udc->transceiver)
1358 return otg_set_power(udc->transceiver, mA);
1359 return -EOPNOTSUPP;
1360}
1361
1362static int omap_pullup(struct usb_gadget *gadget, int is_on)
1363{
1364 struct omap_udc *udc;
1365 unsigned long flags;
1366
1367 udc = container_of(gadget, struct omap_udc, gadget);
1368 spin_lock_irqsave(&udc->lock, flags);
1369 udc->softconnect = (is_on != 0);
1370 if (can_pullup(udc))
1371 pullup_enable(udc);
1372 else
1373 pullup_disable(udc);
1374 spin_unlock_irqrestore(&udc->lock, flags);
1375 return 0;
1376}
1377
1378static int omap_udc_start(struct usb_gadget_driver *driver,
1379 int (*bind)(struct usb_gadget *));
1380static int omap_udc_stop(struct usb_gadget_driver *driver);
1381
1382static struct usb_gadget_ops omap_gadget_ops = {
1383 .get_frame = omap_get_frame,
1384 .wakeup = omap_wakeup,
1385 .set_selfpowered = omap_set_selfpowered,
1386 .vbus_session = omap_vbus_session,
1387 .vbus_draw = omap_vbus_draw,
1388 .pullup = omap_pullup,
1389 .start = omap_udc_start,
1390 .stop = omap_udc_stop,
1391};
1392
1393/*-------------------------------------------------------------------------*/
1394
1395/* dequeue ALL requests; caller holds udc->lock */
1396static void nuke(struct omap_ep *ep, int status)
1397{
1398 struct omap_req *req;
1399
1400 ep->stopped = 1;
1401
1402 if (use_dma && ep->dma_channel)
1403 dma_channel_release(ep);
1404
1405 use_ep(ep, 0);
1406 omap_writew(UDC_CLR_EP, UDC_CTRL);
1407 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1408 omap_writew(UDC_SET_HALT, UDC_CTRL);
1409
1410 while (!list_empty(&ep->queue)) {
1411 req = list_entry(ep->queue.next, struct omap_req, queue);
1412 done(ep, req, status);
1413 }
1414}
1415
1416/* caller holds udc->lock */
1417static void udc_quiesce(struct omap_udc *udc)
1418{
1419 struct omap_ep *ep;
1420
1421 udc->gadget.speed = USB_SPEED_UNKNOWN;
1422 nuke(&udc->ep[0], -ESHUTDOWN);
1423 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1424 nuke(ep, -ESHUTDOWN);
1425}
1426
1427/*-------------------------------------------------------------------------*/
1428
1429static void update_otg(struct omap_udc *udc)
1430{
1431 u16 devstat;
1432
1433 if (!gadget_is_otg(&udc->gadget))
1434 return;
1435
1436 if (omap_readl(OTG_CTRL) & OTG_ID)
1437 devstat = omap_readw(UDC_DEVSTAT);
1438 else
1439 devstat = 0;
1440
1441 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1442 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1443 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1444
1445 /* Enable HNP early, avoiding races on suspend irq path.
1446 * ASSUMES OTG state machine B_BUS_REQ input is true.
1447 */
1448 if (udc->gadget.b_hnp_enable) {
1449 u32 l;
1450
1451 l = omap_readl(OTG_CTRL);
1452 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1453 l &= ~OTG_PULLUP;
1454 omap_writel(l, OTG_CTRL);
1455 }
1456}
1457
1458static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1459{
1460 struct omap_ep *ep0 = &udc->ep[0];
1461 struct omap_req *req = NULL;
1462
1463 ep0->irqs++;
1464
1465 /* Clear any pending requests and then scrub any rx/tx state
1466 * before starting to handle the SETUP request.
1467 */
1468 if (irq_src & UDC_SETUP) {
1469 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1470
1471 nuke(ep0, 0);
1472 if (ack) {
1473 omap_writew(ack, UDC_IRQ_SRC);
1474 irq_src = UDC_SETUP;
1475 }
1476 }
1477
1478 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1479 * This driver uses only uses protocol stalls (ep0 never halts),
1480 * and if we got this far the gadget driver already had a
1481 * chance to stall. Tries to be forgiving of host oddities.
1482 *
1483 * NOTE: the last chance gadget drivers have to stall control
1484 * requests is during their request completion callback.
1485 */
1486 if (!list_empty(&ep0->queue))
1487 req = container_of(ep0->queue.next, struct omap_req, queue);
1488
1489 /* IN == TX to host */
1490 if (irq_src & UDC_EP0_TX) {
1491 int stat;
1492
1493 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1494 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1495 stat = omap_readw(UDC_STAT_FLG);
1496 if (stat & UDC_ACK) {
1497 if (udc->ep0_in) {
1498 /* write next IN packet from response,
1499 * or set up the status stage.
1500 */
1501 if (req)
1502 stat = write_fifo(ep0, req);
1503 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1504 if (!req && udc->ep0_pending) {
1505 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1506 omap_writew(UDC_CLR_EP, UDC_CTRL);
1507 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1508 omap_writew(0, UDC_EP_NUM);
1509 udc->ep0_pending = 0;
1510 } /* else: 6 wait states before it'll tx */
1511 } else {
1512 /* ack status stage of OUT transfer */
1513 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1514 if (req)
1515 done(ep0, req, 0);
1516 }
1517 req = NULL;
1518 } else if (stat & UDC_STALL) {
1519 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1520 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1521 } else {
1522 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1523 }
1524 }
1525
1526 /* OUT == RX from host */
1527 if (irq_src & UDC_EP0_RX) {
1528 int stat;
1529
1530 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1531 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1532 stat = omap_readw(UDC_STAT_FLG);
1533 if (stat & UDC_ACK) {
1534 if (!udc->ep0_in) {
1535 stat = 0;
1536 /* read next OUT packet of request, maybe
1537 * reactiviting the fifo; stall on errors.
1538 */
1539 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1540 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1541 udc->ep0_pending = 0;
1542 stat = 0;
1543 } else if (stat == 0)
1544 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1545 omap_writew(0, UDC_EP_NUM);
1546
1547 /* activate status stage */
1548 if (stat == 1) {
1549 done(ep0, req, 0);
1550 /* that may have STALLed ep0... */
1551 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1552 UDC_EP_NUM);
1553 omap_writew(UDC_CLR_EP, UDC_CTRL);
1554 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1555 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1556 udc->ep0_pending = 0;
1557 }
1558 } else {
1559 /* ack status stage of IN transfer */
1560 omap_writew(0, UDC_EP_NUM);
1561 if (req)
1562 done(ep0, req, 0);
1563 }
1564 } else if (stat & UDC_STALL) {
1565 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1566 omap_writew(0, UDC_EP_NUM);
1567 } else {
1568 omap_writew(0, UDC_EP_NUM);
1569 }
1570 }
1571
1572 /* SETUP starts all control transfers */
1573 if (irq_src & UDC_SETUP) {
1574 union u {
1575 u16 word[4];
1576 struct usb_ctrlrequest r;
1577 } u;
1578 int status = -EINVAL;
1579 struct omap_ep *ep;
1580
1581 /* read the (latest) SETUP message */
1582 do {
1583 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1584 /* two bytes at a time */
1585 u.word[0] = omap_readw(UDC_DATA);
1586 u.word[1] = omap_readw(UDC_DATA);
1587 u.word[2] = omap_readw(UDC_DATA);
1588 u.word[3] = omap_readw(UDC_DATA);
1589 omap_writew(0, UDC_EP_NUM);
1590 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1591
1592#define w_value le16_to_cpu(u.r.wValue)
1593#define w_index le16_to_cpu(u.r.wIndex)
1594#define w_length le16_to_cpu(u.r.wLength)
1595
1596 /* Delegate almost all control requests to the gadget driver,
1597 * except for a handful of ch9 status/feature requests that
1598 * hardware doesn't autodecode _and_ the gadget API hides.
1599 */
1600 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1601 udc->ep0_set_config = 0;
1602 udc->ep0_pending = 1;
1603 ep0->stopped = 0;
1604 ep0->ackwait = 0;
1605 switch (u.r.bRequest) {
1606 case USB_REQ_SET_CONFIGURATION:
1607 /* udc needs to know when ep != 0 is valid */
1608 if (u.r.bRequestType != USB_RECIP_DEVICE)
1609 goto delegate;
1610 if (w_length != 0)
1611 goto do_stall;
1612 udc->ep0_set_config = 1;
1613 udc->ep0_reset_config = (w_value == 0);
1614 VDBG("set config %d\n", w_value);
1615
1616 /* update udc NOW since gadget driver may start
1617 * queueing requests immediately; clear config
1618 * later if it fails the request.
1619 */
1620 if (udc->ep0_reset_config)
1621 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1622 else
1623 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1624 update_otg(udc);
1625 goto delegate;
1626 case USB_REQ_CLEAR_FEATURE:
1627 /* clear endpoint halt */
1628 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1629 goto delegate;
1630 if (w_value != USB_ENDPOINT_HALT
1631 || w_length != 0)
1632 goto do_stall;
1633 ep = &udc->ep[w_index & 0xf];
1634 if (ep != ep0) {
1635 if (w_index & USB_DIR_IN)
1636 ep += 16;
1637 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1638 || !ep->desc)
1639 goto do_stall;
1640 use_ep(ep, 0);
1641 omap_writew(udc->clr_halt, UDC_CTRL);
1642 ep->ackwait = 0;
1643 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1644 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1645 ep->ackwait = 1 + ep->double_buf;
1646 }
1647 /* NOTE: assumes the host behaves sanely,
1648 * only clearing real halts. Else we may
1649 * need to kill pending transfers and then
1650 * restart the queue... very messy for DMA!
1651 */
1652 }
1653 VDBG("%s halt cleared by host\n", ep->name);
1654 goto ep0out_status_stage;
1655 case USB_REQ_SET_FEATURE:
1656 /* set endpoint halt */
1657 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1658 goto delegate;
1659 if (w_value != USB_ENDPOINT_HALT
1660 || w_length != 0)
1661 goto do_stall;
1662 ep = &udc->ep[w_index & 0xf];
1663 if (w_index & USB_DIR_IN)
1664 ep += 16;
1665 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1666 || ep == ep0 || !ep->desc)
1667 goto do_stall;
1668 if (use_dma && ep->has_dma) {
1669 /* this has rude side-effects (aborts) and
1670 * can't really work if DMA-IN is active
1671 */
1672 DBG("%s host set_halt, NYET \n", ep->name);
1673 goto do_stall;
1674 }
1675 use_ep(ep, 0);
1676 /* can't halt if fifo isn't empty... */
1677 omap_writew(UDC_CLR_EP, UDC_CTRL);
1678 omap_writew(UDC_SET_HALT, UDC_CTRL);
1679 VDBG("%s halted by host\n", ep->name);
1680ep0out_status_stage:
1681 status = 0;
1682 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1683 omap_writew(UDC_CLR_EP, UDC_CTRL);
1684 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1685 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1686 udc->ep0_pending = 0;
1687 break;
1688 case USB_REQ_GET_STATUS:
1689 /* USB_ENDPOINT_HALT status? */
1690 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1691 goto intf_status;
1692
1693 /* ep0 never stalls */
1694 if (!(w_index & 0xf))
1695 goto zero_status;
1696
1697 /* only active endpoints count */
1698 ep = &udc->ep[w_index & 0xf];
1699 if (w_index & USB_DIR_IN)
1700 ep += 16;
1701 if (!ep->desc)
1702 goto do_stall;
1703
1704 /* iso never stalls */
1705 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1706 goto zero_status;
1707
1708 /* FIXME don't assume non-halted endpoints!! */
1709 ERR("%s status, can't report\n", ep->ep.name);
1710 goto do_stall;
1711
1712intf_status:
1713 /* return interface status. if we were pedantic,
1714 * we'd detect non-existent interfaces, and stall.
1715 */
1716 if (u.r.bRequestType
1717 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1718 goto delegate;
1719
1720zero_status:
1721 /* return two zero bytes */
1722 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1723 omap_writew(0, UDC_DATA);
1724 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1725 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1726 status = 0;
1727 VDBG("GET_STATUS, interface %d\n", w_index);
1728 /* next, status stage */
1729 break;
1730 default:
1731delegate:
1732 /* activate the ep0out fifo right away */
1733 if (!udc->ep0_in && w_length) {
1734 omap_writew(0, UDC_EP_NUM);
1735 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1736 }
1737
1738 /* gadget drivers see class/vendor specific requests,
1739 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1740 * and more
1741 */
1742 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1743 u.r.bRequestType, u.r.bRequest,
1744 w_value, w_index, w_length);
1745
1746#undef w_value
1747#undef w_index
1748#undef w_length
1749
1750 /* The gadget driver may return an error here,
1751 * causing an immediate protocol stall.
1752 *
1753 * Else it must issue a response, either queueing a
1754 * response buffer for the DATA stage, or halting ep0
1755 * (causing a protocol stall, not a real halt). A
1756 * zero length buffer means no DATA stage.
1757 *
1758 * It's fine to issue that response after the setup()
1759 * call returns, and this IRQ was handled.
1760 */
1761 udc->ep0_setup = 1;
1762 spin_unlock(&udc->lock);
1763 status = udc->driver->setup (&udc->gadget, &u.r);
1764 spin_lock(&udc->lock);
1765 udc->ep0_setup = 0;
1766 }
1767
1768 if (status < 0) {
1769do_stall:
1770 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1771 u.r.bRequestType, u.r.bRequest, status);
1772 if (udc->ep0_set_config) {
1773 if (udc->ep0_reset_config)
1774 WARNING("error resetting config?\n");
1775 else
1776 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1777 }
1778 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1779 udc->ep0_pending = 0;
1780 }
1781 }
1782}
1783
1784/*-------------------------------------------------------------------------*/
1785
1786#define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1787
1788static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1789{
1790 u16 devstat, change;
1791
1792 devstat = omap_readw(UDC_DEVSTAT);
1793 change = devstat ^ udc->devstat;
1794 udc->devstat = devstat;
1795
1796 if (change & (UDC_USB_RESET|UDC_ATT)) {
1797 udc_quiesce(udc);
1798
1799 if (change & UDC_ATT) {
1800 /* driver for any external transceiver will
1801 * have called omap_vbus_session() already
1802 */
1803 if (devstat & UDC_ATT) {
1804 udc->gadget.speed = USB_SPEED_FULL;
1805 VDBG("connect\n");
1806 if (!udc->transceiver)
1807 pullup_enable(udc);
1808 // if (driver->connect) call it
1809 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1810 udc->gadget.speed = USB_SPEED_UNKNOWN;
1811 if (!udc->transceiver)
1812 pullup_disable(udc);
1813 DBG("disconnect, gadget %s\n",
1814 udc->driver->driver.name);
1815 if (udc->driver->disconnect) {
1816 spin_unlock(&udc->lock);
1817 udc->driver->disconnect(&udc->gadget);
1818 spin_lock(&udc->lock);
1819 }
1820 }
1821 change &= ~UDC_ATT;
1822 }
1823
1824 if (change & UDC_USB_RESET) {
1825 if (devstat & UDC_USB_RESET) {
1826 VDBG("RESET=1\n");
1827 } else {
1828 udc->gadget.speed = USB_SPEED_FULL;
1829 INFO("USB reset done, gadget %s\n",
1830 udc->driver->driver.name);
1831 /* ep0 traffic is legal from now on */
1832 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1833 UDC_IRQ_EN);
1834 }
1835 change &= ~UDC_USB_RESET;
1836 }
1837 }
1838 if (change & UDC_SUS) {
1839 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1840 // FIXME tell isp1301 to suspend/resume (?)
1841 if (devstat & UDC_SUS) {
1842 VDBG("suspend\n");
1843 update_otg(udc);
1844 /* HNP could be under way already */
1845 if (udc->gadget.speed == USB_SPEED_FULL
1846 && udc->driver->suspend) {
1847 spin_unlock(&udc->lock);
1848 udc->driver->suspend(&udc->gadget);
1849 spin_lock(&udc->lock);
1850 }
1851 if (udc->transceiver)
1852 otg_set_suspend(udc->transceiver, 1);
1853 } else {
1854 VDBG("resume\n");
1855 if (udc->transceiver)
1856 otg_set_suspend(udc->transceiver, 0);
1857 if (udc->gadget.speed == USB_SPEED_FULL
1858 && udc->driver->resume) {
1859 spin_unlock(&udc->lock);
1860 udc->driver->resume(&udc->gadget);
1861 spin_lock(&udc->lock);
1862 }
1863 }
1864 }
1865 change &= ~UDC_SUS;
1866 }
1867 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1868 update_otg(udc);
1869 change &= ~OTG_FLAGS;
1870 }
1871
1872 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1873 if (change)
1874 VDBG("devstat %03x, ignore change %03x\n",
1875 devstat, change);
1876
1877 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1878}
1879
1880static irqreturn_t omap_udc_irq(int irq, void *_udc)
1881{
1882 struct omap_udc *udc = _udc;
1883 u16 irq_src;
1884 irqreturn_t status = IRQ_NONE;
1885 unsigned long flags;
1886
1887 spin_lock_irqsave(&udc->lock, flags);
1888 irq_src = omap_readw(UDC_IRQ_SRC);
1889
1890 /* Device state change (usb ch9 stuff) */
1891 if (irq_src & UDC_DS_CHG) {
1892 devstate_irq(_udc, irq_src);
1893 status = IRQ_HANDLED;
1894 irq_src &= ~UDC_DS_CHG;
1895 }
1896
1897 /* EP0 control transfers */
1898 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1899 ep0_irq(_udc, irq_src);
1900 status = IRQ_HANDLED;
1901 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1902 }
1903
1904 /* DMA transfer completion */
1905 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1906 dma_irq(_udc, irq_src);
1907 status = IRQ_HANDLED;
1908 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1909 }
1910
1911 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1912 if (irq_src)
1913 DBG("udc_irq, unhandled %03x\n", irq_src);
1914 spin_unlock_irqrestore(&udc->lock, flags);
1915
1916 return status;
1917}
1918
1919/* workaround for seemingly-lost IRQs for RX ACKs... */
1920#define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1921#define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1922
1923static void pio_out_timer(unsigned long _ep)
1924{
1925 struct omap_ep *ep = (void *) _ep;
1926 unsigned long flags;
1927 u16 stat_flg;
1928
1929 spin_lock_irqsave(&ep->udc->lock, flags);
1930 if (!list_empty(&ep->queue) && ep->ackwait) {
1931 use_ep(ep, UDC_EP_SEL);
1932 stat_flg = omap_readw(UDC_STAT_FLG);
1933
1934 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1935 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1936 struct omap_req *req;
1937
1938 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1939 req = container_of(ep->queue.next,
1940 struct omap_req, queue);
1941 (void) read_fifo(ep, req);
1942 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1943 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1944 ep->ackwait = 1 + ep->double_buf;
1945 } else
1946 deselect_ep();
1947 }
1948 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1949 spin_unlock_irqrestore(&ep->udc->lock, flags);
1950}
1951
1952static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1953{
1954 u16 epn_stat, irq_src;
1955 irqreturn_t status = IRQ_NONE;
1956 struct omap_ep *ep;
1957 int epnum;
1958 struct omap_udc *udc = _dev;
1959 struct omap_req *req;
1960 unsigned long flags;
1961
1962 spin_lock_irqsave(&udc->lock, flags);
1963 epn_stat = omap_readw(UDC_EPN_STAT);
1964 irq_src = omap_readw(UDC_IRQ_SRC);
1965
1966 /* handle OUT first, to avoid some wasteful NAKs */
1967 if (irq_src & UDC_EPN_RX) {
1968 epnum = (epn_stat >> 8) & 0x0f;
1969 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1970 status = IRQ_HANDLED;
1971 ep = &udc->ep[epnum];
1972 ep->irqs++;
1973
1974 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1975 ep->fnf = 0;
1976 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1977 ep->ackwait--;
1978 if (!list_empty(&ep->queue)) {
1979 int stat;
1980 req = container_of(ep->queue.next,
1981 struct omap_req, queue);
1982 stat = read_fifo(ep, req);
1983 if (!ep->double_buf)
1984 ep->fnf = 1;
1985 }
1986 }
1987 /* min 6 clock delay before clearing EP_SEL ... */
1988 epn_stat = omap_readw(UDC_EPN_STAT);
1989 epn_stat = omap_readw(UDC_EPN_STAT);
1990 omap_writew(epnum, UDC_EP_NUM);
1991
1992 /* enabling fifo _after_ clearing ACK, contrary to docs,
1993 * reduces lossage; timer still needed though (sigh).
1994 */
1995 if (ep->fnf) {
1996 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1997 ep->ackwait = 1 + ep->double_buf;
1998 }
1999 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
2000 }
2001
2002 /* then IN transfers */
2003 else if (irq_src & UDC_EPN_TX) {
2004 epnum = epn_stat & 0x0f;
2005 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
2006 status = IRQ_HANDLED;
2007 ep = &udc->ep[16 + epnum];
2008 ep->irqs++;
2009
2010 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2011 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2012 ep->ackwait = 0;
2013 if (!list_empty(&ep->queue)) {
2014 req = container_of(ep->queue.next,
2015 struct omap_req, queue);
2016 (void) write_fifo(ep, req);
2017 }
2018 }
2019 /* min 6 clock delay before clearing EP_SEL ... */
2020 epn_stat = omap_readw(UDC_EPN_STAT);
2021 epn_stat = omap_readw(UDC_EPN_STAT);
2022 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2023 /* then 6 clocks before it'd tx */
2024 }
2025
2026 spin_unlock_irqrestore(&udc->lock, flags);
2027 return status;
2028}
2029
2030#ifdef USE_ISO
2031static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2032{
2033 struct omap_udc *udc = _dev;
2034 struct omap_ep *ep;
2035 int pending = 0;
2036 unsigned long flags;
2037
2038 spin_lock_irqsave(&udc->lock, flags);
2039
2040 /* handle all non-DMA ISO transfers */
2041 list_for_each_entry (ep, &udc->iso, iso) {
2042 u16 stat;
2043 struct omap_req *req;
2044
2045 if (ep->has_dma || list_empty(&ep->queue))
2046 continue;
2047 req = list_entry(ep->queue.next, struct omap_req, queue);
2048
2049 use_ep(ep, UDC_EP_SEL);
2050 stat = omap_readw(UDC_STAT_FLG);
2051
2052 /* NOTE: like the other controller drivers, this isn't
2053 * currently reporting lost or damaged frames.
2054 */
2055 if (ep->bEndpointAddress & USB_DIR_IN) {
2056 if (stat & UDC_MISS_IN)
2057 /* done(ep, req, -EPROTO) */;
2058 else
2059 write_fifo(ep, req);
2060 } else {
2061 int status = 0;
2062
2063 if (stat & UDC_NO_RXPACKET)
2064 status = -EREMOTEIO;
2065 else if (stat & UDC_ISO_ERR)
2066 status = -EILSEQ;
2067 else if (stat & UDC_DATA_FLUSH)
2068 status = -ENOSR;
2069
2070 if (status)
2071 /* done(ep, req, status) */;
2072 else
2073 read_fifo(ep, req);
2074 }
2075 deselect_ep();
2076 /* 6 wait states before next EP */
2077
2078 ep->irqs++;
2079 if (!list_empty(&ep->queue))
2080 pending = 1;
2081 }
2082 if (!pending) {
2083 u16 w;
2084
2085 w = omap_readw(UDC_IRQ_EN);
2086 w &= ~UDC_SOF_IE;
2087 omap_writew(w, UDC_IRQ_EN);
2088 }
2089 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2090
2091 spin_unlock_irqrestore(&udc->lock, flags);
2092 return IRQ_HANDLED;
2093}
2094#endif
2095
2096/*-------------------------------------------------------------------------*/
2097
2098static inline int machine_without_vbus_sense(void)
2099{
2100 return (machine_is_omap_innovator()
2101 || machine_is_omap_osk()
2102 || machine_is_omap_apollon()
2103#ifndef CONFIG_MACH_OMAP_H4_OTG
2104 || machine_is_omap_h4()
2105#endif
2106 || machine_is_sx1()
2107 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
2108 );
2109}
2110
2111static int omap_udc_start(struct usb_gadget_driver *driver,
2112 int (*bind)(struct usb_gadget *))
2113{
2114 int status = -ENODEV;
2115 struct omap_ep *ep;
2116 unsigned long flags;
2117
2118 /* basic sanity tests */
2119 if (!udc)
2120 return -ENODEV;
2121 if (!driver
2122 // FIXME if otg, check: driver->is_otg
2123 || driver->speed < USB_SPEED_FULL
2124 || !bind || !driver->setup)
2125 return -EINVAL;
2126
2127 spin_lock_irqsave(&udc->lock, flags);
2128 if (udc->driver) {
2129 spin_unlock_irqrestore(&udc->lock, flags);
2130 return -EBUSY;
2131 }
2132
2133 /* reset state */
2134 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2135 ep->irqs = 0;
2136 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2137 continue;
2138 use_ep(ep, 0);
2139 omap_writew(UDC_SET_HALT, UDC_CTRL);
2140 }
2141 udc->ep0_pending = 0;
2142 udc->ep[0].irqs = 0;
2143 udc->softconnect = 1;
2144
2145 /* hook up the driver */
2146 driver->driver.bus = NULL;
2147 udc->driver = driver;
2148 udc->gadget.dev.driver = &driver->driver;
2149 spin_unlock_irqrestore(&udc->lock, flags);
2150
2151 if (udc->dc_clk != NULL)
2152 omap_udc_enable_clock(1);
2153
2154 status = bind(&udc->gadget);
2155 if (status) {
2156 DBG("bind to %s --> %d\n", driver->driver.name, status);
2157 udc->gadget.dev.driver = NULL;
2158 udc->driver = NULL;
2159 goto done;
2160 }
2161 DBG("bound to driver %s\n", driver->driver.name);
2162
2163 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2164
2165 /* connect to bus through transceiver */
2166 if (udc->transceiver) {
2167 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2168 if (status < 0) {
2169 ERR("can't bind to transceiver\n");
2170 if (driver->unbind) {
2171 driver->unbind (&udc->gadget);
2172 udc->gadget.dev.driver = NULL;
2173 udc->driver = NULL;
2174 }
2175 goto done;
2176 }
2177 } else {
2178 if (can_pullup(udc))
2179 pullup_enable (udc);
2180 else
2181 pullup_disable (udc);
2182 }
2183
2184 /* boards that don't have VBUS sensing can't autogate 48MHz;
2185 * can't enter deep sleep while a gadget driver is active.
2186 */
2187 if (machine_without_vbus_sense())
2188 omap_vbus_session(&udc->gadget, 1);
2189
2190done:
2191 if (udc->dc_clk != NULL)
2192 omap_udc_enable_clock(0);
2193 return status;
2194}
2195
2196static int omap_udc_stop(struct usb_gadget_driver *driver)
2197{
2198 unsigned long flags;
2199 int status = -ENODEV;
2200
2201 if (!udc)
2202 return -ENODEV;
2203 if (!driver || driver != udc->driver || !driver->unbind)
2204 return -EINVAL;
2205
2206 if (udc->dc_clk != NULL)
2207 omap_udc_enable_clock(1);
2208
2209 if (machine_without_vbus_sense())
2210 omap_vbus_session(&udc->gadget, 0);
2211
2212 if (udc->transceiver)
2213 (void) otg_set_peripheral(udc->transceiver, NULL);
2214 else
2215 pullup_disable(udc);
2216
2217 spin_lock_irqsave(&udc->lock, flags);
2218 udc_quiesce(udc);
2219 spin_unlock_irqrestore(&udc->lock, flags);
2220
2221 driver->unbind(&udc->gadget);
2222 udc->gadget.dev.driver = NULL;
2223 udc->driver = NULL;
2224
2225 if (udc->dc_clk != NULL)
2226 omap_udc_enable_clock(0);
2227 DBG("unregistered driver '%s'\n", driver->driver.name);
2228 return status;
2229}
2230
2231/*-------------------------------------------------------------------------*/
2232
2233#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2234
2235#include <linux/seq_file.h>
2236
2237static const char proc_filename[] = "driver/udc";
2238
2239#define FOURBITS "%s%s%s%s"
2240#define EIGHTBITS FOURBITS FOURBITS
2241
2242static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2243{
2244 u16 stat_flg;
2245 struct omap_req *req;
2246 char buf[20];
2247
2248 use_ep(ep, 0);
2249
2250 if (use_dma && ep->has_dma)
2251 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2252 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2253 ep->dma_channel - 1, ep->lch);
2254 else
2255 buf[0] = 0;
2256
2257 stat_flg = omap_readw(UDC_STAT_FLG);
2258 seq_printf(s,
2259 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2260 ep->name, buf,
2261 ep->double_buf ? "dbuf " : "",
2262 ({char *s; switch(ep->ackwait){
2263 case 0: s = ""; break;
2264 case 1: s = "(ackw) "; break;
2265 case 2: s = "(ackw2) "; break;
2266 default: s = "(?) "; break;
2267 } s;}),
2268 ep->irqs, stat_flg,
2269 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2270 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2271 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2272 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2273 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2274 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2275 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2276 (stat_flg & UDC_STALL) ? "STALL " : "",
2277 (stat_flg & UDC_NAK) ? "NAK " : "",
2278 (stat_flg & UDC_ACK) ? "ACK " : "",
2279 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2280 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2281 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2282
2283 if (list_empty (&ep->queue))
2284 seq_printf(s, "\t(queue empty)\n");
2285 else
2286 list_for_each_entry (req, &ep->queue, queue) {
2287 unsigned length = req->req.actual;
2288
2289 if (use_dma && buf[0]) {
2290 length += ((ep->bEndpointAddress & USB_DIR_IN)
2291 ? dma_src_len : dma_dest_len)
2292 (ep, req->req.dma + length);
2293 buf[0] = 0;
2294 }
2295 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2296 &req->req, length,
2297 req->req.length, req->req.buf);
2298 }
2299}
2300
2301static char *trx_mode(unsigned m, int enabled)
2302{
2303 switch (m) {
2304 case 0: return enabled ? "*6wire" : "unused";
2305 case 1: return "4wire";
2306 case 2: return "3wire";
2307 case 3: return "6wire";
2308 default: return "unknown";
2309 }
2310}
2311
2312static int proc_otg_show(struct seq_file *s)
2313{
2314 u32 tmp;
2315 u32 trans = 0;
2316 char *ctrl_name = "(UNKNOWN)";
2317
2318 /* XXX This needs major revision for OMAP2+ */
2319 tmp = omap_readl(OTG_REV);
2320 if (cpu_class_is_omap1()) {
2321 ctrl_name = "tranceiver_ctrl";
2322 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2323 }
2324 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2325 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2326 tmp = omap_readw(OTG_SYSCON_1);
2327 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2328 FOURBITS "\n", tmp,
2329 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2330 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2331 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2332 ? "internal"
2333 : trx_mode(USB0_TRX_MODE(tmp), 1),
2334 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2335 (tmp & HST_IDLE_EN) ? " !host" : "",
2336 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2337 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2338 tmp = omap_readl(OTG_SYSCON_2);
2339 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2340 " b_ase_brst=%d hmc=%d\n", tmp,
2341 (tmp & OTG_EN) ? " otg_en" : "",
2342 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2343 // much more SRP stuff
2344 (tmp & SRP_DATA) ? " srp_data" : "",
2345 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2346 (tmp & OTG_PADEN) ? " otg_paden" : "",
2347 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2348 (tmp & UHOST_EN) ? " uhost_en" : "",
2349 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2350 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2351 B_ASE_BRST(tmp),
2352 OTG_HMC(tmp));
2353 tmp = omap_readl(OTG_CTRL);
2354 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2355 (tmp & OTG_ASESSVLD) ? " asess" : "",
2356 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2357 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2358 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2359 (tmp & OTG_ID) ? " id" : "",
2360 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2361 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2362 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2363 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2364 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2365 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2366 (tmp & OTG_PULLDOWN) ? " down" : "",
2367 (tmp & OTG_PULLUP) ? " up" : "",
2368 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2369 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2370 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2371 (tmp & OTG_PU_ID) ? " pu_id" : ""
2372 );
2373 tmp = omap_readw(OTG_IRQ_EN);
2374 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2375 tmp = omap_readw(OTG_IRQ_SRC);
2376 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2377 tmp = omap_readw(OTG_OUTCTRL);
2378 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2379 tmp = omap_readw(OTG_TEST);
2380 seq_printf(s, "otg_test %04x" "\n", tmp);
2381 return 0;
2382}
2383
2384static int proc_udc_show(struct seq_file *s, void *_)
2385{
2386 u32 tmp;
2387 struct omap_ep *ep;
2388 unsigned long flags;
2389
2390 spin_lock_irqsave(&udc->lock, flags);
2391
2392 seq_printf(s, "%s, version: " DRIVER_VERSION
2393#ifdef USE_ISO
2394 " (iso)"
2395#endif
2396 "%s\n",
2397 driver_desc,
2398 use_dma ? " (dma)" : "");
2399
2400 tmp = omap_readw(UDC_REV) & 0xff;
2401 seq_printf(s,
2402 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2403 "hmc %d, transceiver %s\n",
2404 tmp >> 4, tmp & 0xf,
2405 fifo_mode,
2406 udc->driver ? udc->driver->driver.name : "(none)",
2407 HMC,
2408 udc->transceiver
2409 ? udc->transceiver->label
2410 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2411 ? "external" : "(none)"));
2412 if (cpu_class_is_omap1()) {
2413 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2414 omap_readw(ULPD_CLOCK_CTRL),
2415 omap_readw(ULPD_SOFT_REQ),
2416 omap_readw(ULPD_STATUS_REQ));
2417 }
2418
2419 /* OTG controller registers */
2420 if (!cpu_is_omap15xx())
2421 proc_otg_show(s);
2422
2423 tmp = omap_readw(UDC_SYSCON1);
2424 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2425 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2426 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2427 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2428 (tmp & UDC_NAK_EN) ? " nak" : "",
2429 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2430 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2431 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2432 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2433 // syscon2 is write-only
2434
2435 /* UDC controller registers */
2436 if (!(tmp & UDC_PULLUP_EN)) {
2437 seq_printf(s, "(suspended)\n");
2438 spin_unlock_irqrestore(&udc->lock, flags);
2439 return 0;
2440 }
2441
2442 tmp = omap_readw(UDC_DEVSTAT);
2443 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2444 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2445 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2446 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2447 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2448 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2449 (tmp & UDC_SUS) ? " SUS" : "",
2450 (tmp & UDC_CFG) ? " CFG" : "",
2451 (tmp & UDC_ADD) ? " ADD" : "",
2452 (tmp & UDC_DEF) ? " DEF" : "",
2453 (tmp & UDC_ATT) ? " ATT" : "");
2454 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2455 tmp = omap_readw(UDC_IRQ_EN);
2456 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2457 (tmp & UDC_SOF_IE) ? " sof" : "",
2458 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2459 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2460 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2461 (tmp & UDC_EP0_IE) ? " ep0" : "");
2462 tmp = omap_readw(UDC_IRQ_SRC);
2463 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2464 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2465 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2466 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2467 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2468 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2469 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2470 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2471 (tmp & UDC_SETUP) ? " setup" : "",
2472 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2473 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2474 if (use_dma) {
2475 unsigned i;
2476
2477 tmp = omap_readw(UDC_DMA_IRQ_EN);
2478 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2479 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2480 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2481 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2482
2483 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2484 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2485 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2486
2487 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2488 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2489 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2490
2491 tmp = omap_readw(UDC_RXDMA_CFG);
2492 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2493 if (tmp) {
2494 for (i = 0; i < 3; i++) {
2495 if ((tmp & (0x0f << (i * 4))) == 0)
2496 continue;
2497 seq_printf(s, "rxdma[%d] %04x\n", i,
2498 omap_readw(UDC_RXDMA(i + 1)));
2499 }
2500 }
2501 tmp = omap_readw(UDC_TXDMA_CFG);
2502 seq_printf(s, "txdma_cfg %04x\n", tmp);
2503 if (tmp) {
2504 for (i = 0; i < 3; i++) {
2505 if (!(tmp & (0x0f << (i * 4))))
2506 continue;
2507 seq_printf(s, "txdma[%d] %04x\n", i,
2508 omap_readw(UDC_TXDMA(i + 1)));
2509 }
2510 }
2511 }
2512
2513 tmp = omap_readw(UDC_DEVSTAT);
2514 if (tmp & UDC_ATT) {
2515 proc_ep_show(s, &udc->ep[0]);
2516 if (tmp & UDC_ADD) {
2517 list_for_each_entry (ep, &udc->gadget.ep_list,
2518 ep.ep_list) {
2519 if (ep->desc)
2520 proc_ep_show(s, ep);
2521 }
2522 }
2523 }
2524 spin_unlock_irqrestore(&udc->lock, flags);
2525 return 0;
2526}
2527
2528static int proc_udc_open(struct inode *inode, struct file *file)
2529{
2530 return single_open(file, proc_udc_show, NULL);
2531}
2532
2533static const struct file_operations proc_ops = {
2534 .owner = THIS_MODULE,
2535 .open = proc_udc_open,
2536 .read = seq_read,
2537 .llseek = seq_lseek,
2538 .release = single_release,
2539};
2540
2541static void create_proc_file(void)
2542{
2543 proc_create(proc_filename, 0, NULL, &proc_ops);
2544}
2545
2546static void remove_proc_file(void)
2547{
2548 remove_proc_entry(proc_filename, NULL);
2549}
2550
2551#else
2552
2553static inline void create_proc_file(void) {}
2554static inline void remove_proc_file(void) {}
2555
2556#endif
2557
2558/*-------------------------------------------------------------------------*/
2559
2560/* Before this controller can enumerate, we need to pick an endpoint
2561 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2562 * buffer space among the endpoints we'll be operating.
2563 *
2564 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2565 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2566 * capability yet though.
2567 */
2568static unsigned __init
2569omap_ep_setup(char *name, u8 addr, u8 type,
2570 unsigned buf, unsigned maxp, int dbuf)
2571{
2572 struct omap_ep *ep;
2573 u16 epn_rxtx = 0;
2574
2575 /* OUT endpoints first, then IN */
2576 ep = &udc->ep[addr & 0xf];
2577 if (addr & USB_DIR_IN)
2578 ep += 16;
2579
2580 /* in case of ep init table bugs */
2581 BUG_ON(ep->name[0]);
2582
2583 /* chip setup ... bit values are same for IN, OUT */
2584 if (type == USB_ENDPOINT_XFER_ISOC) {
2585 switch (maxp) {
2586 case 8: epn_rxtx = 0 << 12; break;
2587 case 16: epn_rxtx = 1 << 12; break;
2588 case 32: epn_rxtx = 2 << 12; break;
2589 case 64: epn_rxtx = 3 << 12; break;
2590 case 128: epn_rxtx = 4 << 12; break;
2591 case 256: epn_rxtx = 5 << 12; break;
2592 case 512: epn_rxtx = 6 << 12; break;
2593 default: BUG();
2594 }
2595 epn_rxtx |= UDC_EPN_RX_ISO;
2596 dbuf = 1;
2597 } else {
2598 /* double-buffering "not supported" on 15xx,
2599 * and ignored for PIO-IN on newer chips
2600 * (for more reliable behavior)
2601 */
2602 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2603 dbuf = 0;
2604
2605 switch (maxp) {
2606 case 8: epn_rxtx = 0 << 12; break;
2607 case 16: epn_rxtx = 1 << 12; break;
2608 case 32: epn_rxtx = 2 << 12; break;
2609 case 64: epn_rxtx = 3 << 12; break;
2610 default: BUG();
2611 }
2612 if (dbuf && addr)
2613 epn_rxtx |= UDC_EPN_RX_DB;
2614 init_timer(&ep->timer);
2615 ep->timer.function = pio_out_timer;
2616 ep->timer.data = (unsigned long) ep;
2617 }
2618 if (addr)
2619 epn_rxtx |= UDC_EPN_RX_VALID;
2620 BUG_ON(buf & 0x07);
2621 epn_rxtx |= buf >> 3;
2622
2623 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2624 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2625
2626 if (addr & USB_DIR_IN)
2627 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2628 else
2629 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2630
2631 /* next endpoint's buffer starts after this one's */
2632 buf += maxp;
2633 if (dbuf)
2634 buf += maxp;
2635 BUG_ON(buf > 2048);
2636
2637 /* set up driver data structures */
2638 BUG_ON(strlen(name) >= sizeof ep->name);
2639 strlcpy(ep->name, name, sizeof ep->name);
2640 INIT_LIST_HEAD(&ep->queue);
2641 INIT_LIST_HEAD(&ep->iso);
2642 ep->bEndpointAddress = addr;
2643 ep->bmAttributes = type;
2644 ep->double_buf = dbuf;
2645 ep->udc = udc;
2646
2647 ep->ep.name = ep->name;
2648 ep->ep.ops = &omap_ep_ops;
2649 ep->ep.maxpacket = ep->maxpacket = maxp;
2650 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2651
2652 return buf;
2653}
2654
2655static void omap_udc_release(struct device *dev)
2656{
2657 complete(udc->done);
2658 kfree (udc);
2659 udc = NULL;
2660}
2661
2662static int __init
2663omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2664{
2665 unsigned tmp, buf;
2666
2667 /* abolish any previous hardware state */
2668 omap_writew(0, UDC_SYSCON1);
2669 omap_writew(0, UDC_IRQ_EN);
2670 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2671 omap_writew(0, UDC_DMA_IRQ_EN);
2672 omap_writew(0, UDC_RXDMA_CFG);
2673 omap_writew(0, UDC_TXDMA_CFG);
2674
2675 /* UDC_PULLUP_EN gates the chip clock */
2676 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2677
2678 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2679 if (!udc)
2680 return -ENOMEM;
2681
2682 spin_lock_init (&udc->lock);
2683
2684 udc->gadget.ops = &omap_gadget_ops;
2685 udc->gadget.ep0 = &udc->ep[0].ep;
2686 INIT_LIST_HEAD(&udc->gadget.ep_list);
2687 INIT_LIST_HEAD(&udc->iso);
2688 udc->gadget.speed = USB_SPEED_UNKNOWN;
2689 udc->gadget.name = driver_name;
2690
2691 device_initialize(&udc->gadget.dev);
2692 dev_set_name(&udc->gadget.dev, "gadget");
2693 udc->gadget.dev.release = omap_udc_release;
2694 udc->gadget.dev.parent = &odev->dev;
2695 if (use_dma)
2696 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2697
2698 udc->transceiver = xceiv;
2699
2700 /* ep0 is special; put it right after the SETUP buffer */
2701 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2702 8 /* after SETUP */, 64 /* maxpacket */, 0);
2703 list_del_init(&udc->ep[0].ep.ep_list);
2704
2705 /* initially disable all non-ep0 endpoints */
2706 for (tmp = 1; tmp < 15; tmp++) {
2707 omap_writew(0, UDC_EP_RX(tmp));
2708 omap_writew(0, UDC_EP_TX(tmp));
2709 }
2710
2711#define OMAP_BULK_EP(name,addr) \
2712 buf = omap_ep_setup(name "-bulk", addr, \
2713 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2714#define OMAP_INT_EP(name,addr, maxp) \
2715 buf = omap_ep_setup(name "-int", addr, \
2716 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2717#define OMAP_ISO_EP(name,addr, maxp) \
2718 buf = omap_ep_setup(name "-iso", addr, \
2719 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2720
2721 switch (fifo_mode) {
2722 case 0:
2723 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2724 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2725 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2726 break;
2727 case 1:
2728 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2729 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2730 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2731
2732 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2733 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2734 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2735
2736 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2737 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2738 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2739
2740 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2741 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2742 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2743
2744 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2745 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2746 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2747 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2748
2749 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2750 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2751 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2752 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2753
2754 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2755 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2756
2757 break;
2758
2759#ifdef USE_ISO
2760 case 2: /* mixed iso/bulk */
2761 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2762 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2763 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2764 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2765
2766 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2767
2768 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2769 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2770 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2771 break;
2772 case 3: /* mixed bulk/iso */
2773 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2774 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2775 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2776
2777 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2778 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2779 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2780
2781 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2782 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2783 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2784 break;
2785#endif
2786
2787 /* add more modes as needed */
2788
2789 default:
2790 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2791 return -ENODEV;
2792 }
2793 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2794 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2795 return 0;
2796}
2797
2798static int __init omap_udc_probe(struct platform_device *pdev)
2799{
2800 int status = -ENODEV;
2801 int hmc;
2802 struct otg_transceiver *xceiv = NULL;
2803 const char *type = NULL;
2804 struct omap_usb_config *config = pdev->dev.platform_data;
2805 struct clk *dc_clk;
2806 struct clk *hhc_clk;
2807
2808 /* NOTE: "knows" the order of the resources! */
2809 if (!request_mem_region(pdev->resource[0].start,
2810 pdev->resource[0].end - pdev->resource[0].start + 1,
2811 driver_name)) {
2812 DBG("request_mem_region failed\n");
2813 return -EBUSY;
2814 }
2815
2816 if (cpu_is_omap16xx()) {
2817 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2818 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2819 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2820 /* can't use omap_udc_enable_clock yet */
2821 clk_enable(dc_clk);
2822 clk_enable(hhc_clk);
2823 udelay(100);
2824 }
2825
2826 if (cpu_is_omap24xx()) {
2827 dc_clk = clk_get(&pdev->dev, "usb_fck");
2828 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2829 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2830 /* can't use omap_udc_enable_clock yet */
2831 clk_enable(dc_clk);
2832 clk_enable(hhc_clk);
2833 udelay(100);
2834 }
2835
2836 if (cpu_is_omap7xx()) {
2837 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2838 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2839 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2840 /* can't use omap_udc_enable_clock yet */
2841 clk_enable(dc_clk);
2842 clk_enable(hhc_clk);
2843 udelay(100);
2844 }
2845
2846 INFO("OMAP UDC rev %d.%d%s\n",
2847 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2848 config->otg ? ", Mini-AB" : "");
2849
2850 /* use the mode given to us by board init code */
2851 if (cpu_is_omap15xx()) {
2852 hmc = HMC_1510;
2853 type = "(unknown)";
2854
2855 if (machine_without_vbus_sense()) {
2856 /* just set up software VBUS detect, and then
2857 * later rig it so we always report VBUS.
2858 * FIXME without really sensing VBUS, we can't
2859 * know when to turn PULLUP_EN on/off; and that
2860 * means we always "need" the 48MHz clock.
2861 */
2862 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2863 tmp &= ~VBUS_CTRL_1510;
2864 omap_writel(tmp, FUNC_MUX_CTRL_0);
2865 tmp |= VBUS_MODE_1510;
2866 tmp &= ~VBUS_CTRL_1510;
2867 omap_writel(tmp, FUNC_MUX_CTRL_0);
2868 }
2869 } else {
2870 /* The transceiver may package some GPIO logic or handle
2871 * loopback and/or transceiverless setup; if we find one,
2872 * use it. Except for OTG, we don't _need_ to talk to one;
2873 * but not having one probably means no VBUS detection.
2874 */
2875 xceiv = otg_get_transceiver();
2876 if (xceiv)
2877 type = xceiv->label;
2878 else if (config->otg) {
2879 DBG("OTG requires external transceiver!\n");
2880 goto cleanup0;
2881 }
2882
2883 hmc = HMC_1610;
2884
2885 if (cpu_is_omap24xx()) {
2886 /* this could be transceiverless in one of the
2887 * "we don't need to know" modes.
2888 */
2889 type = "external";
2890 goto known;
2891 }
2892
2893 switch (hmc) {
2894 case 0: /* POWERUP DEFAULT == 0 */
2895 case 4:
2896 case 12:
2897 case 20:
2898 if (!cpu_is_omap1710()) {
2899 type = "integrated";
2900 break;
2901 }
2902 /* FALL THROUGH */
2903 case 3:
2904 case 11:
2905 case 16:
2906 case 19:
2907 case 25:
2908 if (!xceiv) {
2909 DBG("external transceiver not registered!\n");
2910 type = "unknown";
2911 }
2912 break;
2913 case 21: /* internal loopback */
2914 type = "loopback";
2915 break;
2916 case 14: /* transceiverless */
2917 if (cpu_is_omap1710())
2918 goto bad_on_1710;
2919 /* FALL THROUGH */
2920 case 13:
2921 case 15:
2922 type = "no";
2923 break;
2924
2925 default:
2926bad_on_1710:
2927 ERR("unrecognized UDC HMC mode %d\n", hmc);
2928 goto cleanup0;
2929 }
2930 }
2931known:
2932 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2933
2934 /* a "gadget" abstracts/virtualizes the controller */
2935 status = omap_udc_setup(pdev, xceiv);
2936 if (status) {
2937 goto cleanup0;
2938 }
2939 xceiv = NULL;
2940 // "udc" is now valid
2941 pullup_disable(udc);
2942#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2943 udc->gadget.is_otg = (config->otg != 0);
2944#endif
2945
2946 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2947 if (omap_readw(UDC_REV) >= 0x61)
2948 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2949 else
2950 udc->clr_halt = UDC_RESET_EP;
2951
2952 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2953 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2954 IRQF_SAMPLE_RANDOM, driver_name, udc);
2955 if (status != 0) {
2956 ERR("can't get irq %d, err %d\n",
2957 (int) pdev->resource[1].start, status);
2958 goto cleanup1;
2959 }
2960
2961 /* USB "non-iso" IRQ (PIO for all but ep0) */
2962 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2963 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2964 if (status != 0) {
2965 ERR("can't get irq %d, err %d\n",
2966 (int) pdev->resource[2].start, status);
2967 goto cleanup2;
2968 }
2969#ifdef USE_ISO
2970 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2971 IRQF_DISABLED, "omap_udc iso", udc);
2972 if (status != 0) {
2973 ERR("can't get irq %d, err %d\n",
2974 (int) pdev->resource[3].start, status);
2975 goto cleanup3;
2976 }
2977#endif
2978 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2979 udc->dc_clk = dc_clk;
2980 udc->hhc_clk = hhc_clk;
2981 clk_disable(hhc_clk);
2982 clk_disable(dc_clk);
2983 }
2984
2985 if (cpu_is_omap24xx()) {
2986 udc->dc_clk = dc_clk;
2987 udc->hhc_clk = hhc_clk;
2988 /* FIXME OMAP2 don't release hhc & dc clock */
2989#if 0
2990 clk_disable(hhc_clk);
2991 clk_disable(dc_clk);
2992#endif
2993 }
2994
2995 create_proc_file();
2996 status = device_add(&udc->gadget.dev);
2997 if (status)
2998 goto cleanup4;
2999
3000 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
3001 if (!status)
3002 return status;
3003 /* If fail, fall through */
3004cleanup4:
3005 remove_proc_file();
3006
3007#ifdef USE_ISO
3008cleanup3:
3009 free_irq(pdev->resource[2].start, udc);
3010#endif
3011
3012cleanup2:
3013 free_irq(pdev->resource[1].start, udc);
3014
3015cleanup1:
3016 kfree (udc);
3017 udc = NULL;
3018
3019cleanup0:
3020 if (xceiv)
3021 otg_put_transceiver(xceiv);
3022
3023 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
3024 clk_disable(hhc_clk);
3025 clk_disable(dc_clk);
3026 clk_put(hhc_clk);
3027 clk_put(dc_clk);
3028 }
3029
3030 release_mem_region(pdev->resource[0].start,
3031 pdev->resource[0].end - pdev->resource[0].start + 1);
3032
3033 return status;
3034}
3035
3036static int __exit omap_udc_remove(struct platform_device *pdev)
3037{
3038 DECLARE_COMPLETION_ONSTACK(done);
3039
3040 if (!udc)
3041 return -ENODEV;
3042
3043 usb_del_gadget_udc(&udc->gadget);
3044 if (udc->driver)
3045 return -EBUSY;
3046
3047 udc->done = &done;
3048
3049 pullup_disable(udc);
3050 if (udc->transceiver) {
3051 otg_put_transceiver(udc->transceiver);
3052 udc->transceiver = NULL;
3053 }
3054 omap_writew(0, UDC_SYSCON1);
3055
3056 remove_proc_file();
3057
3058#ifdef USE_ISO
3059 free_irq(pdev->resource[3].start, udc);
3060#endif
3061 free_irq(pdev->resource[2].start, udc);
3062 free_irq(pdev->resource[1].start, udc);
3063
3064 if (udc->dc_clk) {
3065 if (udc->clk_requested)
3066 omap_udc_enable_clock(0);
3067 clk_put(udc->hhc_clk);
3068 clk_put(udc->dc_clk);
3069 }
3070
3071 release_mem_region(pdev->resource[0].start,
3072 pdev->resource[0].end - pdev->resource[0].start + 1);
3073
3074 device_unregister(&udc->gadget.dev);
3075 wait_for_completion(&done);
3076
3077 return 0;
3078}
3079
3080/* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3081 * system is forced into deep sleep
3082 *
3083 * REVISIT we should probably reject suspend requests when there's a host
3084 * session active, rather than disconnecting, at least on boards that can
3085 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3086 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3087 * may involve talking to an external transceiver (e.g. isp1301).
3088 */
3089
3090static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3091{
3092 u32 devstat;
3093
3094 devstat = omap_readw(UDC_DEVSTAT);
3095
3096 /* we're requesting 48 MHz clock if the pullup is enabled
3097 * (== we're attached to the host) and we're not suspended,
3098 * which would prevent entry to deep sleep...
3099 */
3100 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3101 WARNING("session active; suspend requires disconnect\n");
3102 omap_pullup(&udc->gadget, 0);
3103 }
3104
3105 return 0;
3106}
3107
3108static int omap_udc_resume(struct platform_device *dev)
3109{
3110 DBG("resume + wakeup/SRP\n");
3111 omap_pullup(&udc->gadget, 1);
3112
3113 /* maybe the host would enumerate us if we nudged it */
3114 msleep(100);
3115 return omap_wakeup(&udc->gadget);
3116}
3117
3118/*-------------------------------------------------------------------------*/
3119
3120static struct platform_driver udc_driver = {
3121 .remove = __exit_p(omap_udc_remove),
3122 .suspend = omap_udc_suspend,
3123 .resume = omap_udc_resume,
3124 .driver = {
3125 .owner = THIS_MODULE,
3126 .name = (char *) driver_name,
3127 },
3128};
3129
3130static int __init udc_init(void)
3131{
3132 /* Disable DMA for omap7xx -- it doesn't work right. */
3133 if (cpu_is_omap7xx())
3134 use_dma = 0;
3135
3136 INFO("%s, version: " DRIVER_VERSION
3137#ifdef USE_ISO
3138 " (iso)"
3139#endif
3140 "%s\n", driver_desc,
3141 use_dma ? " (dma)" : "");
3142 return platform_driver_probe(&udc_driver, omap_udc_probe);
3143}
3144module_init(udc_init);
3145
3146static void __exit udc_exit(void)
3147{
3148 platform_driver_unregister(&udc_driver);
3149}
3150module_exit(udc_exit);
3151
3152MODULE_DESCRIPTION(DRIVER_DESC);
3153MODULE_LICENSE("GPL");
3154MODULE_ALIAS("platform:omap_udc");