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1/*
2 * Fusb300 UDC (USB gadget)
3 *
4 * Copyright (C) 2010 Faraday Technology Corp.
5 *
6 * Author : Yuan-hsin Chen <yhchen@faraday-tech.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 *
21 */
22
23
24#ifndef __FUSB300_UDC_H__
25#define __FUSB300_UDC_H_
26
27#include <linux/kernel.h>
28
29#define FUSB300_OFFSET_GCR 0x00
30#define FUSB300_OFFSET_GTM 0x04
31#define FUSB300_OFFSET_DAR 0x08
32#define FUSB300_OFFSET_CSR 0x0C
33#define FUSB300_OFFSET_CXPORT 0x10
34#define FUSB300_OFFSET_EPSET0(n) (0x20 + (n - 1) * 0x30)
35#define FUSB300_OFFSET_EPSET1(n) (0x24 + (n - 1) * 0x30)
36#define FUSB300_OFFSET_EPSET2(n) (0x28 + (n - 1) * 0x30)
37#define FUSB300_OFFSET_EPFFR(n) (0x2c + (n - 1) * 0x30)
38#define FUSB300_OFFSET_EPSTRID(n) (0x40 + (n - 1) * 0x30)
39#define FUSB300_OFFSET_HSPTM 0x300
40#define FUSB300_OFFSET_HSCR 0x304
41#define FUSB300_OFFSET_SSCR0 0x308
42#define FUSB300_OFFSET_SSCR1 0x30C
43#define FUSB300_OFFSET_TT 0x310
44#define FUSB300_OFFSET_DEVNOTF 0x314
45#define FUSB300_OFFSET_DNC1 0x318
46#define FUSB300_OFFSET_CS 0x31C
47#define FUSB300_OFFSET_SOF 0x324
48#define FUSB300_OFFSET_EFCS 0x328
49#define FUSB300_OFFSET_IGR0 0x400
50#define FUSB300_OFFSET_IGR1 0x404
51#define FUSB300_OFFSET_IGR2 0x408
52#define FUSB300_OFFSET_IGR3 0x40C
53#define FUSB300_OFFSET_IGR4 0x410
54#define FUSB300_OFFSET_IGR5 0x414
55#define FUSB300_OFFSET_IGER0 0x420
56#define FUSB300_OFFSET_IGER1 0x424
57#define FUSB300_OFFSET_IGER2 0x428
58#define FUSB300_OFFSET_IGER3 0x42C
59#define FUSB300_OFFSET_IGER4 0x430
60#define FUSB300_OFFSET_IGER5 0x434
61#define FUSB300_OFFSET_DMAHMER 0x500
62#define FUSB300_OFFSET_EPPRDRDY 0x504
63#define FUSB300_OFFSET_DMAEPMR 0x508
64#define FUSB300_OFFSET_DMAENR 0x50C
65#define FUSB300_OFFSET_DMAAPR 0x510
66#define FUSB300_OFFSET_AHBCR 0x514
67#define FUSB300_OFFSET_EPPRD_W0(n) (0x520 + (n - 1) * 0x10)
68#define FUSB300_OFFSET_EPPRD_W1(n) (0x524 + (n - 1) * 0x10)
69#define FUSB300_OFFSET_EPPRD_W2(n) (0x528 + (n - 1) * 0x10)
70#define FUSB300_OFFSET_EPRD_PTR(n) (0x52C + (n - 1) * 0x10)
71#define FUSB300_OFFSET_BUFDBG_START 0x800
72#define FUSB300_OFFSET_BUFDBG_END 0xBFC
73#define FUSB300_OFFSET_EPPORT(n) (0x1010 + (n - 1) * 0x10)
74
75/*
76 * * Global Control Register (offset = 000H)
77 * */
78#define FUSB300_GCR_SF_RST (1 << 8)
79#define FUSB300_GCR_VBUS_STATUS (1 << 7)
80#define FUSB300_GCR_FORCE_HS_SUSP (1 << 6)
81#define FUSB300_GCR_SYNC_FIFO1_CLR (1 << 5)
82#define FUSB300_GCR_SYNC_FIFO0_CLR (1 << 4)
83#define FUSB300_GCR_FIFOCLR (1 << 3)
84#define FUSB300_GCR_GLINTEN (1 << 2)
85#define FUSB300_GCR_DEVEN_FS 0x3
86#define FUSB300_GCR_DEVEN_HS 0x2
87#define FUSB300_GCR_DEVEN_SS 0x1
88#define FUSB300_GCR_DEVDIS 0x0
89#define FUSB300_GCR_DEVEN_MSK 0x3
90
91
92/*
93 * *Global Test Mode (offset = 004H)
94 * */
95#define FUSB300_GTM_TST_DIS_SOFGEN (1 << 16)
96#define FUSB300_GTM_TST_CUR_EP_ENTRY(n) ((n & 0xF) << 12)
97#define FUSB300_GTM_TST_EP_ENTRY(n) ((n & 0xF) << 8)
98#define FUSB300_GTM_TST_EP_NUM(n) ((n & 0xF) << 4)
99#define FUSB300_GTM_TST_FIFO_DEG (1 << 1)
100#define FUSB300_GTM_TSTMODE (1 << 0)
101
102/*
103 * * Device Address Register (offset = 008H)
104 * */
105#define FUSB300_DAR_SETCONFG (1 << 7)
106#define FUSB300_DAR_DRVADDR(x) (x & 0x7F)
107#define FUSB300_DAR_DRVADDR_MSK 0x7F
108
109/*
110 * *Control Transfer Configuration and Status Register
111 * (CX_Config_Status, offset = 00CH)
112 * */
113#define FUSB300_CSR_LEN(x) ((x & 0xFFFF) << 8)
114#define FUSB300_CSR_LEN_MSK (0xFFFF << 8)
115#define FUSB300_CSR_EMP (1 << 4)
116#define FUSB300_CSR_FUL (1 << 3)
117#define FUSB300_CSR_CLR (1 << 2)
118#define FUSB300_CSR_STL (1 << 1)
119#define FUSB300_CSR_DONE (1 << 0)
120
121/*
122 * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
123 * */
124#define FUSB300_EPSET0_CLRSEQNUM (1 << 2)
125#define FUSB300_EPSET0_EPn_TX0BYTE (1 << 1)
126#define FUSB300_EPSET0_STL (1 << 0)
127
128/*
129 * * EPn Setting 1 (EPn_SET1, offset = 024H+(n-1)*30H, n=1~15)
130 * */
131#define FUSB300_EPSET1_START_ENTRY(x) ((x & 0xFF) << 24)
132#define FUSB300_EPSET1_START_ENTRY_MSK (0xFF << 24)
133#define FUSB300_EPSET1_FIFOENTRY(x) ((x & 0x1F) << 12)
134#define FUSB300_EPSET1_FIFOENTRY_MSK (0x1f << 12)
135#define FUSB300_EPSET1_INTERVAL(x) ((x & 0x7) << 6)
136#define FUSB300_EPSET1_BWNUM(x) ((x & 0x3) << 4)
137#define FUSB300_EPSET1_TYPEISO (1 << 2)
138#define FUSB300_EPSET1_TYPEBLK (2 << 2)
139#define FUSB300_EPSET1_TYPEINT (3 << 2)
140#define FUSB300_EPSET1_TYPE(x) ((x & 0x3) << 2)
141#define FUSB300_EPSET1_TYPE_MSK (0x3 << 2)
142#define FUSB300_EPSET1_DIROUT (0 << 1)
143#define FUSB300_EPSET1_DIRIN (1 << 1)
144#define FUSB300_EPSET1_DIR(x) ((x & 0x1) << 1)
145#define FUSB300_EPSET1_DIRIN (1 << 1)
146#define FUSB300_EPSET1_DIR_MSK ((0x1) << 1)
147#define FUSB300_EPSET1_ACTDIS 0
148#define FUSB300_EPSET1_ACTEN 1
149
150/*
151 * *EPn Setting 2 (EPn_SET2, offset = 028H+(n-1)*30H, n=1~15)
152 * */
153#define FUSB300_EPSET2_ADDROFS(x) ((x & 0x7FFF) << 16)
154#define FUSB300_EPSET2_ADDROFS_MSK (0x7fff << 16)
155#define FUSB300_EPSET2_MPS(x) (x & 0x7FF)
156#define FUSB300_EPSET2_MPS_MSK 0x7FF
157
158/*
159 * * EPn FIFO Register (offset = 2cH+(n-1)*30H)
160 * */
161#define FUSB300_FFR_RST (1 << 31)
162#define FUSB300_FF_FUL (1 << 30)
163#define FUSB300_FF_EMPTY (1 << 29)
164#define FUSB300_FFR_BYCNT 0x1FFFF
165
166/*
167 * *EPn Stream ID (EPn_STR_ID, offset = 040H+(n-1)*30H, n=1~15)
168 * */
169#define FUSB300_STRID_STREN (1 << 16)
170#define FUSB300_STRID_STRID(x) (x & 0xFFFF)
171
172/*
173 * *HS PHY Test Mode (offset = 300H)
174 * */
175#define FUSB300_HSPTM_TSTPKDONE (1 << 4)
176#define FUSB300_HSPTM_TSTPKT (1 << 3)
177#define FUSB300_HSPTM_TSTSET0NAK (1 << 2)
178#define FUSB300_HSPTM_TSTKSTA (1 << 1)
179#define FUSB300_HSPTM_TSTJSTA (1 << 0)
180
181/*
182 * *HS Control Register (offset = 304H)
183 * */
184#define FUSB300_HSCR_HS_LPM_PERMIT (1 << 8)
185#define FUSB300_HSCR_HS_LPM_RMWKUP (1 << 7)
186#define FUSB300_HSCR_CAP_LPM_RMWKUP (1 << 6)
187#define FUSB300_HSCR_HS_GOSUSP (1 << 5)
188#define FUSB300_HSCR_HS_GORMWKU (1 << 4)
189#define FUSB300_HSCR_CAP_RMWKUP (1 << 3)
190#define FUSB300_HSCR_IDLECNT_0MS 0
191#define FUSB300_HSCR_IDLECNT_1MS 1
192#define FUSB300_HSCR_IDLECNT_2MS 2
193#define FUSB300_HSCR_IDLECNT_3MS 3
194#define FUSB300_HSCR_IDLECNT_4MS 4
195#define FUSB300_HSCR_IDLECNT_5MS 5
196#define FUSB300_HSCR_IDLECNT_6MS 6
197#define FUSB300_HSCR_IDLECNT_7MS 7
198
199/*
200 * * SS Controller Register 0 (offset = 308H)
201 * */
202#define FUSB300_SSCR0_MAX_INTERVAL(x) ((x & 0x7) << 4)
203#define FUSB300_SSCR0_U2_FUN_EN (1 << 1)
204#define FUSB300_SSCR0_U1_FUN_EN (1 << 0)
205
206/*
207 * * SS Controller Register 1 (offset = 30CH)
208 * */
209#define FUSB300_SSCR1_GO_U3_DONE (1 << 8)
210#define FUSB300_SSCR1_TXDEEMPH_LEVEL (1 << 7)
211#define FUSB300_SSCR1_DIS_SCRMB (1 << 6)
212#define FUSB300_SSCR1_FORCE_RECOVERY (1 << 5)
213#define FUSB300_SSCR1_U3_WAKEUP_EN (1 << 4)
214#define FUSB300_SSCR1_U2_EXIT_EN (1 << 3)
215#define FUSB300_SSCR1_U1_EXIT_EN (1 << 2)
216#define FUSB300_SSCR1_U2_ENTRY_EN (1 << 1)
217#define FUSB300_SSCR1_U1_ENTRY_EN (1 << 0)
218
219/*
220 * *SS Controller Register 2 (offset = 310H)
221 * */
222#define FUSB300_SSCR2_SS_TX_SWING (1 << 25)
223#define FUSB300_SSCR2_FORCE_LINKPM_ACCEPT (1 << 24)
224#define FUSB300_SSCR2_U2_INACT_TIMEOUT(x) ((x & 0xFF) << 16)
225#define FUSB300_SSCR2_U1TIMEOUT(x) ((x & 0xFF) << 8)
226#define FUSB300_SSCR2_U2TIMEOUT(x) (x & 0xFF)
227
228/*
229 * *SS Device Notification Control (DEV_NOTF, offset = 314H)
230 * */
231#define FUSB300_DEVNOTF_CONTEXT0(x) ((x & 0xFFFFFF) << 8)
232#define FUSB300_DEVNOTF_TYPE_DIS 0
233#define FUSB300_DEVNOTF_TYPE_FUNCWAKE 1
234#define FUSB300_DEVNOTF_TYPE_LTM 2
235#define FUSB300_DEVNOTF_TYPE_BUSINT_ADJMSG 3
236
237/*
238 * *BFM Arbiter Priority Register (BFM_ARB offset = 31CH)
239 * */
240#define FUSB300_BFMARB_ARB_M1 (1 << 3)
241#define FUSB300_BFMARB_ARB_M0 (1 << 2)
242#define FUSB300_BFMARB_ARB_S1 (1 << 1)
243#define FUSB300_BFMARB_ARB_S0 1
244
245/*
246 * *Vendor Specific IO Control Register (offset = 320H)
247 * */
248#define FUSB300_VSIC_VCTLOAD_N (1 << 8)
249#define FUSB300_VSIC_VCTL(x) (x & 0x3F)
250
251/*
252 * *SOF Mask Timer (offset = 324H)
253 * */
254#define FUSB300_SOF_MASK_TIMER_HS 0x044c
255#define FUSB300_SOF_MASK_TIMER_FS 0x2710
256
257/*
258 * *Error Flag and Control Status (offset = 328H)
259 * */
260#define FUSB300_EFCS_PM_STATE_U3 3
261#define FUSB300_EFCS_PM_STATE_U2 2
262#define FUSB300_EFCS_PM_STATE_U1 1
263#define FUSB300_EFCS_PM_STATE_U0 0
264
265/*
266 * *Interrupt Group 0 Register (offset = 400H)
267 * */
268#define FUSB300_IGR0_EP15_PRD_INT (1 << 31)
269#define FUSB300_IGR0_EP14_PRD_INT (1 << 30)
270#define FUSB300_IGR0_EP13_PRD_INT (1 << 29)
271#define FUSB300_IGR0_EP12_PRD_INT (1 << 28)
272#define FUSB300_IGR0_EP11_PRD_INT (1 << 27)
273#define FUSB300_IGR0_EP10_PRD_INT (1 << 26)
274#define FUSB300_IGR0_EP9_PRD_INT (1 << 25)
275#define FUSB300_IGR0_EP8_PRD_INT (1 << 24)
276#define FUSB300_IGR0_EP7_PRD_INT (1 << 23)
277#define FUSB300_IGR0_EP6_PRD_INT (1 << 22)
278#define FUSB300_IGR0_EP5_PRD_INT (1 << 21)
279#define FUSB300_IGR0_EP4_PRD_INT (1 << 20)
280#define FUSB300_IGR0_EP3_PRD_INT (1 << 19)
281#define FUSB300_IGR0_EP2_PRD_INT (1 << 18)
282#define FUSB300_IGR0_EP1_PRD_INT (1 << 17)
283#define FUSB300_IGR0_EPn_PRD_INT(n) (1 << (n + 16))
284
285#define FUSB300_IGR0_EP15_FIFO_INT (1 << 15)
286#define FUSB300_IGR0_EP14_FIFO_INT (1 << 14)
287#define FUSB300_IGR0_EP13_FIFO_INT (1 << 13)
288#define FUSB300_IGR0_EP12_FIFO_INT (1 << 12)
289#define FUSB300_IGR0_EP11_FIFO_INT (1 << 11)
290#define FUSB300_IGR0_EP10_FIFO_INT (1 << 10)
291#define FUSB300_IGR0_EP9_FIFO_INT (1 << 9)
292#define FUSB300_IGR0_EP8_FIFO_INT (1 << 8)
293#define FUSB300_IGR0_EP7_FIFO_INT (1 << 7)
294#define FUSB300_IGR0_EP6_FIFO_INT (1 << 6)
295#define FUSB300_IGR0_EP5_FIFO_INT (1 << 5)
296#define FUSB300_IGR0_EP4_FIFO_INT (1 << 4)
297#define FUSB300_IGR0_EP3_FIFO_INT (1 << 3)
298#define FUSB300_IGR0_EP2_FIFO_INT (1 << 2)
299#define FUSB300_IGR0_EP1_FIFO_INT (1 << 1)
300#define FUSB300_IGR0_EPn_FIFO_INT(n) (1 << n)
301
302/*
303 * *Interrupt Group 1 Register (offset = 404H)
304 * */
305#define FUSB300_IGR1_INTGRP5 (1 << 31)
306#define FUSB300_IGR1_VBUS_CHG_INT (1 << 30)
307#define FUSB300_IGR1_SYNF1_EMPTY_INT (1 << 29)
308#define FUSB300_IGR1_SYNF0_EMPTY_INT (1 << 28)
309#define FUSB300_IGR1_U3_EXIT_FAIL_INT (1 << 27)
310#define FUSB300_IGR1_U2_EXIT_FAIL_INT (1 << 26)
311#define FUSB300_IGR1_U1_EXIT_FAIL_INT (1 << 25)
312#define FUSB300_IGR1_U2_ENTRY_FAIL_INT (1 << 24)
313#define FUSB300_IGR1_U1_ENTRY_FAIL_INT (1 << 23)
314#define FUSB300_IGR1_U3_EXIT_INT (1 << 22)
315#define FUSB300_IGR1_U2_EXIT_INT (1 << 21)
316#define FUSB300_IGR1_U1_EXIT_INT (1 << 20)
317#define FUSB300_IGR1_U3_ENTRY_INT (1 << 19)
318#define FUSB300_IGR1_U2_ENTRY_INT (1 << 18)
319#define FUSB300_IGR1_U1_ENTRY_INT (1 << 17)
320#define FUSB300_IGR1_HOT_RST_INT (1 << 16)
321#define FUSB300_IGR1_WARM_RST_INT (1 << 15)
322#define FUSB300_IGR1_RESM_INT (1 << 14)
323#define FUSB300_IGR1_SUSP_INT (1 << 13)
324#define FUSB300_IGR1_HS_LPM_INT (1 << 12)
325#define FUSB300_IGR1_USBRST_INT (1 << 11)
326#define FUSB300_IGR1_DEV_MODE_CHG_INT (1 << 9)
327#define FUSB300_IGR1_CX_COMABT_INT (1 << 8)
328#define FUSB300_IGR1_CX_COMFAIL_INT (1 << 7)
329#define FUSB300_IGR1_CX_CMDEND_INT (1 << 6)
330#define FUSB300_IGR1_CX_OUT_INT (1 << 5)
331#define FUSB300_IGR1_CX_IN_INT (1 << 4)
332#define FUSB300_IGR1_CX_SETUP_INT (1 << 3)
333#define FUSB300_IGR1_INTGRP4 (1 << 2)
334#define FUSB300_IGR1_INTGRP3 (1 << 1)
335#define FUSB300_IGR1_INTGRP2 (1 << 0)
336
337/*
338 * *Interrupt Group 2 Register (offset = 408H)
339 * */
340#define FUSB300_IGR2_EP6_STR_ACCEPT_INT (1 << 29)
341#define FUSB300_IGR2_EP6_STR_RESUME_INT (1 << 28)
342#define FUSB300_IGR2_EP6_STR_REQ_INT (1 << 27)
343#define FUSB300_IGR2_EP6_STR_NOTRDY_INT (1 << 26)
344#define FUSB300_IGR2_EP6_STR_PRIME_INT (1 << 25)
345#define FUSB300_IGR2_EP5_STR_ACCEPT_INT (1 << 24)
346#define FUSB300_IGR2_EP5_STR_RESUME_INT (1 << 23)
347#define FUSB300_IGR2_EP5_STR_REQ_INT (1 << 22)
348#define FUSB300_IGR2_EP5_STR_NOTRDY_INT (1 << 21)
349#define FUSB300_IGR2_EP5_STR_PRIME_INT (1 << 20)
350#define FUSB300_IGR2_EP4_STR_ACCEPT_INT (1 << 19)
351#define FUSB300_IGR2_EP4_STR_RESUME_INT (1 << 18)
352#define FUSB300_IGR2_EP4_STR_REQ_INT (1 << 17)
353#define FUSB300_IGR2_EP4_STR_NOTRDY_INT (1 << 16)
354#define FUSB300_IGR2_EP4_STR_PRIME_INT (1 << 15)
355#define FUSB300_IGR2_EP3_STR_ACCEPT_INT (1 << 14)
356#define FUSB300_IGR2_EP3_STR_RESUME_INT (1 << 13)
357#define FUSB300_IGR2_EP3_STR_REQ_INT (1 << 12)
358#define FUSB300_IGR2_EP3_STR_NOTRDY_INT (1 << 11)
359#define FUSB300_IGR2_EP3_STR_PRIME_INT (1 << 10)
360#define FUSB300_IGR2_EP2_STR_ACCEPT_INT (1 << 9)
361#define FUSB300_IGR2_EP2_STR_RESUME_INT (1 << 8)
362#define FUSB300_IGR2_EP2_STR_REQ_INT (1 << 7)
363#define FUSB300_IGR2_EP2_STR_NOTRDY_INT (1 << 6)
364#define FUSB300_IGR2_EP2_STR_PRIME_INT (1 << 5)
365#define FUSB300_IGR2_EP1_STR_ACCEPT_INT (1 << 4)
366#define FUSB300_IGR2_EP1_STR_RESUME_INT (1 << 3)
367#define FUSB300_IGR2_EP1_STR_REQ_INT (1 << 2)
368#define FUSB300_IGR2_EP1_STR_NOTRDY_INT (1 << 1)
369#define FUSB300_IGR2_EP1_STR_PRIME_INT (1 << 0)
370
371#define FUSB300_IGR2_EP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
372#define FUSB300_IGR2_EP_STR_RESUME_INT(n) (1 << (5 * n - 2))
373#define FUSB300_IGR2_EP_STR_REQ_INT(n) (1 << (5 * n - 3))
374#define FUSB300_IGR2_EP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
375#define FUSB300_IGR2_EP_STR_PRIME_INT(n) (1 << (5 * n - 5))
376
377/*
378 * *Interrupt Group 3 Register (offset = 40CH)
379 * */
380#define FUSB300_IGR3_EP12_STR_ACCEPT_INT (1 << 29)
381#define FUSB300_IGR3_EP12_STR_RESUME_INT (1 << 28)
382#define FUSB300_IGR3_EP12_STR_REQ_INT (1 << 27)
383#define FUSB300_IGR3_EP12_STR_NOTRDY_INT (1 << 26)
384#define FUSB300_IGR3_EP12_STR_PRIME_INT (1 << 25)
385#define FUSB300_IGR3_EP11_STR_ACCEPT_INT (1 << 24)
386#define FUSB300_IGR3_EP11_STR_RESUME_INT (1 << 23)
387#define FUSB300_IGR3_EP11_STR_REQ_INT (1 << 22)
388#define FUSB300_IGR3_EP11_STR_NOTRDY_INT (1 << 21)
389#define FUSB300_IGR3_EP11_STR_PRIME_INT (1 << 20)
390#define FUSB300_IGR3_EP10_STR_ACCEPT_INT (1 << 19)
391#define FUSB300_IGR3_EP10_STR_RESUME_INT (1 << 18)
392#define FUSB300_IGR3_EP10_STR_REQ_INT (1 << 17)
393#define FUSB300_IGR3_EP10_STR_NOTRDY_INT (1 << 16)
394#define FUSB300_IGR3_EP10_STR_PRIME_INT (1 << 15)
395#define FUSB300_IGR3_EP9_STR_ACCEPT_INT (1 << 14)
396#define FUSB300_IGR3_EP9_STR_RESUME_INT (1 << 13)
397#define FUSB300_IGR3_EP9_STR_REQ_INT (1 << 12)
398#define FUSB300_IGR3_EP9_STR_NOTRDY_INT (1 << 11)
399#define FUSB300_IGR3_EP9_STR_PRIME_INT (1 << 10)
400#define FUSB300_IGR3_EP8_STR_ACCEPT_INT (1 << 9)
401#define FUSB300_IGR3_EP8_STR_RESUME_INT (1 << 8)
402#define FUSB300_IGR3_EP8_STR_REQ_INT (1 << 7)
403#define FUSB300_IGR3_EP8_STR_NOTRDY_INT (1 << 6)
404#define FUSB300_IGR3_EP8_STR_PRIME_INT (1 << 5)
405#define FUSB300_IGR3_EP7_STR_ACCEPT_INT (1 << 4)
406#define FUSB300_IGR3_EP7_STR_RESUME_INT (1 << 3)
407#define FUSB300_IGR3_EP7_STR_REQ_INT (1 << 2)
408#define FUSB300_IGR3_EP7_STR_NOTRDY_INT (1 << 1)
409#define FUSB300_IGR3_EP7_STR_PRIME_INT (1 << 0)
410
411#define FUSB300_IGR3_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
412#define FUSB300_IGR3_EP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
413#define FUSB300_IGR3_EP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
414#define FUSB300_IGR3_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
415#define FUSB300_IGR3_EP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
416
417/*
418 * *Interrupt Group 4 Register (offset = 410H)
419 * */
420#define FUSB300_IGR4_EP15_RX0_INT (1 << 31)
421#define FUSB300_IGR4_EP14_RX0_INT (1 << 30)
422#define FUSB300_IGR4_EP13_RX0_INT (1 << 29)
423#define FUSB300_IGR4_EP12_RX0_INT (1 << 28)
424#define FUSB300_IGR4_EP11_RX0_INT (1 << 27)
425#define FUSB300_IGR4_EP10_RX0_INT (1 << 26)
426#define FUSB300_IGR4_EP9_RX0_INT (1 << 25)
427#define FUSB300_IGR4_EP8_RX0_INT (1 << 24)
428#define FUSB300_IGR4_EP7_RX0_INT (1 << 23)
429#define FUSB300_IGR4_EP6_RX0_INT (1 << 22)
430#define FUSB300_IGR4_EP5_RX0_INT (1 << 21)
431#define FUSB300_IGR4_EP4_RX0_INT (1 << 20)
432#define FUSB300_IGR4_EP3_RX0_INT (1 << 19)
433#define FUSB300_IGR4_EP2_RX0_INT (1 << 18)
434#define FUSB300_IGR4_EP1_RX0_INT (1 << 17)
435#define FUSB300_IGR4_EP_RX0_INT(x) (1 << (x + 16))
436#define FUSB300_IGR4_EP15_STR_ACCEPT_INT (1 << 14)
437#define FUSB300_IGR4_EP15_STR_RESUME_INT (1 << 13)
438#define FUSB300_IGR4_EP15_STR_REQ_INT (1 << 12)
439#define FUSB300_IGR4_EP15_STR_NOTRDY_INT (1 << 11)
440#define FUSB300_IGR4_EP15_STR_PRIME_INT (1 << 10)
441#define FUSB300_IGR4_EP14_STR_ACCEPT_INT (1 << 9)
442#define FUSB300_IGR4_EP14_STR_RESUME_INT (1 << 8)
443#define FUSB300_IGR4_EP14_STR_REQ_INT (1 << 7)
444#define FUSB300_IGR4_EP14_STR_NOTRDY_INT (1 << 6)
445#define FUSB300_IGR4_EP14_STR_PRIME_INT (1 << 5)
446#define FUSB300_IGR4_EP13_STR_ACCEPT_INT (1 << 4)
447#define FUSB300_IGR4_EP13_STR_RESUME_INT (1 << 3)
448#define FUSB300_IGR4_EP13_STR_REQ_INT (1 << 2)
449#define FUSB300_IGR4_EP13_STR_NOTRDY_INT (1 << 1)
450#define FUSB300_IGR4_EP13_STR_PRIME_INT (1 << 0)
451
452#define FUSB300_IGR4_EP_STR_ACCEPT_INT(n) (1 << (5 * (n - 12) - 1))
453#define FUSB300_IGR4_EP_STR_RESUME_INT(n) (1 << (5 * (n - 12) - 2))
454#define FUSB300_IGR4_EP_STR_REQ_INT(n) (1 << (5 * (n - 12) - 3))
455#define FUSB300_IGR4_EP_STR_NOTRDY_INT(n) (1 << (5 * (n - 12) - 4))
456#define FUSB300_IGR4_EP_STR_PRIME_INT(n) (1 << (5 * (n - 12) - 5))
457
458/*
459 * *Interrupt Group 5 Register (offset = 414H)
460 * */
461#define FUSB300_IGR5_EP_STL_INT(n) (1 << n)
462
463/*
464 * *Interrupt Enable Group 0 Register (offset = 420H)
465 * */
466#define FUSB300_IGER0_EEP15_PRD_INT (1 << 31)
467#define FUSB300_IGER0_EEP14_PRD_INT (1 << 30)
468#define FUSB300_IGER0_EEP13_PRD_INT (1 << 29)
469#define FUSB300_IGER0_EEP12_PRD_INT (1 << 28)
470#define FUSB300_IGER0_EEP11_PRD_INT (1 << 27)
471#define FUSB300_IGER0_EEP10_PRD_INT (1 << 26)
472#define FUSB300_IGER0_EEP9_PRD_INT (1 << 25)
473#define FUSB300_IGER0_EP8_PRD_INT (1 << 24)
474#define FUSB300_IGER0_EEP7_PRD_INT (1 << 23)
475#define FUSB300_IGER0_EEP6_PRD_INT (1 << 22)
476#define FUSB300_IGER0_EEP5_PRD_INT (1 << 21)
477#define FUSB300_IGER0_EEP4_PRD_INT (1 << 20)
478#define FUSB300_IGER0_EEP3_PRD_INT (1 << 19)
479#define FUSB300_IGER0_EEP2_PRD_INT (1 << 18)
480#define FUSB300_IGER0_EEP1_PRD_INT (1 << 17)
481#define FUSB300_IGER0_EEPn_PRD_INT(n) (1 << (n + 16))
482
483#define FUSB300_IGER0_EEP15_FIFO_INT (1 << 15)
484#define FUSB300_IGER0_EEP14_FIFO_INT (1 << 14)
485#define FUSB300_IGER0_EEP13_FIFO_INT (1 << 13)
486#define FUSB300_IGER0_EEP12_FIFO_INT (1 << 12)
487#define FUSB300_IGER0_EEP11_FIFO_INT (1 << 11)
488#define FUSB300_IGER0_EEP10_FIFO_INT (1 << 10)
489#define FUSB300_IGER0_EEP9_FIFO_INT (1 << 9)
490#define FUSB300_IGER0_EEP8_FIFO_INT (1 << 8)
491#define FUSB300_IGER0_EEP7_FIFO_INT (1 << 7)
492#define FUSB300_IGER0_EEP6_FIFO_INT (1 << 6)
493#define FUSB300_IGER0_EEP5_FIFO_INT (1 << 5)
494#define FUSB300_IGER0_EEP4_FIFO_INT (1 << 4)
495#define FUSB300_IGER0_EEP3_FIFO_INT (1 << 3)
496#define FUSB300_IGER0_EEP2_FIFO_INT (1 << 2)
497#define FUSB300_IGER0_EEP1_FIFO_INT (1 << 1)
498#define FUSB300_IGER0_EEPn_FIFO_INT(n) (1 << n)
499
500/*
501 * *Interrupt Enable Group 1 Register (offset = 424H)
502 * */
503#define FUSB300_IGER1_EINT_GRP5 (1 << 31)
504#define FUSB300_IGER1_VBUS_CHG_INT (1 << 30)
505#define FUSB300_IGER1_SYNF1_EMPTY_INT (1 << 29)
506#define FUSB300_IGER1_SYNF0_EMPTY_INT (1 << 28)
507#define FUSB300_IGER1_U3_EXIT_FAIL_INT (1 << 27)
508#define FUSB300_IGER1_U2_EXIT_FAIL_INT (1 << 26)
509#define FUSB300_IGER1_U1_EXIT_FAIL_INT (1 << 25)
510#define FUSB300_IGER1_U2_ENTRY_FAIL_INT (1 << 24)
511#define FUSB300_IGER1_U1_ENTRY_FAIL_INT (1 << 23)
512#define FUSB300_IGER1_U3_EXIT_INT (1 << 22)
513#define FUSB300_IGER1_U2_EXIT_INT (1 << 21)
514#define FUSB300_IGER1_U1_EXIT_INT (1 << 20)
515#define FUSB300_IGER1_U3_ENTRY_INT (1 << 19)
516#define FUSB300_IGER1_U2_ENTRY_INT (1 << 18)
517#define FUSB300_IGER1_U1_ENTRY_INT (1 << 17)
518#define FUSB300_IGER1_HOT_RST_INT (1 << 16)
519#define FUSB300_IGER1_WARM_RST_INT (1 << 15)
520#define FUSB300_IGER1_RESM_INT (1 << 14)
521#define FUSB300_IGER1_SUSP_INT (1 << 13)
522#define FUSB300_IGER1_LPM_INT (1 << 12)
523#define FUSB300_IGER1_HS_RST_INT (1 << 11)
524#define FUSB300_IGER1_EDEV_MODE_CHG_INT (1 << 9)
525#define FUSB300_IGER1_CX_COMABT_INT (1 << 8)
526#define FUSB300_IGER1_CX_COMFAIL_INT (1 << 7)
527#define FUSB300_IGER1_CX_CMDEND_INT (1 << 6)
528#define FUSB300_IGER1_CX_OUT_INT (1 << 5)
529#define FUSB300_IGER1_CX_IN_INT (1 << 4)
530#define FUSB300_IGER1_CX_SETUP_INT (1 << 3)
531#define FUSB300_IGER1_INTGRP4 (1 << 2)
532#define FUSB300_IGER1_INTGRP3 (1 << 1)
533#define FUSB300_IGER1_INTGRP2 (1 << 0)
534
535/*
536 * *Interrupt Enable Group 2 Register (offset = 428H)
537 * */
538#define FUSB300_IGER2_EEP_STR_ACCEPT_INT(n) (1 << (5 * n - 1))
539#define FUSB300_IGER2_EEP_STR_RESUME_INT(n) (1 << (5 * n - 2))
540#define FUSB300_IGER2_EEP_STR_REQ_INT(n) (1 << (5 * n - 3))
541#define FUSB300_IGER2_EEP_STR_NOTRDY_INT(n) (1 << (5 * n - 4))
542#define FUSB300_IGER2_EEP_STR_PRIME_INT(n) (1 << (5 * n - 5))
543
544/*
545 * *Interrupt Enable Group 3 Register (offset = 42CH)
546 * */
547
548#define FUSB300_IGER3_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
549#define FUSB300_IGER3_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
550#define FUSB300_IGER3_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
551#define FUSB300_IGER3_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
552#define FUSB300_IGER3_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
553
554/*
555 * *Interrupt Enable Group 4 Register (offset = 430H)
556 * */
557
558#define FUSB300_IGER4_EEP_RX0_INT(n) (1 << (n + 16))
559#define FUSB300_IGER4_EEP_STR_ACCEPT_INT(n) (1 << (5 * (n - 6) - 1))
560#define FUSB300_IGER4_EEP_STR_RESUME_INT(n) (1 << (5 * (n - 6) - 2))
561#define FUSB300_IGER4_EEP_STR_REQ_INT(n) (1 << (5 * (n - 6) - 3))
562#define FUSB300_IGER4_EEP_STR_NOTRDY_INT(n) (1 << (5 * (n - 6) - 4))
563#define FUSB300_IGER4_EEP_STR_PRIME_INT(n) (1 << (5 * (n - 6) - 5))
564
565/* EP PRD Ready (EP_PRD_RDY, offset = 504H) */
566
567#define FUSB300_EPPRDR_EP15_PRD_RDY (1 << 15)
568#define FUSB300_EPPRDR_EP14_PRD_RDY (1 << 14)
569#define FUSB300_EPPRDR_EP13_PRD_RDY (1 << 13)
570#define FUSB300_EPPRDR_EP12_PRD_RDY (1 << 12)
571#define FUSB300_EPPRDR_EP11_PRD_RDY (1 << 11)
572#define FUSB300_EPPRDR_EP10_PRD_RDY (1 << 10)
573#define FUSB300_EPPRDR_EP9_PRD_RDY (1 << 9)
574#define FUSB300_EPPRDR_EP8_PRD_RDY (1 << 8)
575#define FUSB300_EPPRDR_EP7_PRD_RDY (1 << 7)
576#define FUSB300_EPPRDR_EP6_PRD_RDY (1 << 6)
577#define FUSB300_EPPRDR_EP5_PRD_RDY (1 << 5)
578#define FUSB300_EPPRDR_EP4_PRD_RDY (1 << 4)
579#define FUSB300_EPPRDR_EP3_PRD_RDY (1 << 3)
580#define FUSB300_EPPRDR_EP2_PRD_RDY (1 << 2)
581#define FUSB300_EPPRDR_EP1_PRD_RDY (1 << 1)
582#define FUSB300_EPPRDR_EP_PRD_RDY(n) (1 << n)
583
584/* AHB Bus Control Register (offset = 514H) */
585#define FUSB300_AHBBCR_S1_SPLIT_ON (1 << 17)
586#define FUSB300_AHBBCR_S0_SPLIT_ON (1 << 16)
587#define FUSB300_AHBBCR_S1_1entry (0 << 12)
588#define FUSB300_AHBBCR_S1_4entry (3 << 12)
589#define FUSB300_AHBBCR_S1_8entry (5 << 12)
590#define FUSB300_AHBBCR_S1_16entry (7 << 12)
591#define FUSB300_AHBBCR_S0_1entry (0 << 8)
592#define FUSB300_AHBBCR_S0_4entry (3 << 8)
593#define FUSB300_AHBBCR_S0_8entry (5 << 8)
594#define FUSB300_AHBBCR_S0_16entry (7 << 8)
595#define FUSB300_AHBBCR_M1_BURST_SINGLE (0 << 4)
596#define FUSB300_AHBBCR_M1_BURST_INCR (1 << 4)
597#define FUSB300_AHBBCR_M1_BURST_INCR4 (3 << 4)
598#define FUSB300_AHBBCR_M1_BURST_INCR8 (5 << 4)
599#define FUSB300_AHBBCR_M1_BURST_INCR16 (7 << 4)
600#define FUSB300_AHBBCR_M0_BURST_SINGLE 0
601#define FUSB300_AHBBCR_M0_BURST_INCR 1
602#define FUSB300_AHBBCR_M0_BURST_INCR4 3
603#define FUSB300_AHBBCR_M0_BURST_INCR8 5
604#define FUSB300_AHBBCR_M0_BURST_INCR16 7
605#define FUSB300_IGER5_EEP_STL_INT(n) (1 << n)
606
607/* WORD 0 Data Structure of PRD Table */
608#define FUSB300_EPPRD0_M (1 << 30)
609#define FUSB300_EPPRD0_O (1 << 29)
610/* The finished prd */
611#define FUSB300_EPPRD0_F (1 << 28)
612#define FUSB300_EPPRD0_I (1 << 27)
613#define FUSB300_EPPRD0_A (1 << 26)
614/* To decide HW point to first prd at next time */
615#define FUSB300_EPPRD0_L (1 << 25)
616#define FUSB300_EPPRD0_H (1 << 24)
617#define FUSB300_EPPRD0_BTC(n) (n & 0xFFFFFF)
618
619/*----------------------------------------------------------------------*/
620#define FUSB300_MAX_NUM_EP 16
621
622#define FUSB300_FIFO_ENTRY_NUM 8
623#define FUSB300_MAX_FIFO_ENTRY 8
624
625#define SS_CTL_MAX_PACKET_SIZE 0x200
626#define SS_BULK_MAX_PACKET_SIZE 0x400
627#define SS_INT_MAX_PACKET_SIZE 0x400
628#define SS_ISO_MAX_PACKET_SIZE 0x400
629
630#define HS_BULK_MAX_PACKET_SIZE 0x200
631#define HS_CTL_MAX_PACKET_SIZE 0x40
632#define HS_INT_MAX_PACKET_SIZE 0x400
633#define HS_ISO_MAX_PACKET_SIZE 0x400
634
635struct fusb300_ep_info {
636 u8 epnum;
637 u8 type;
638 u8 interval;
639 u8 dir_in;
640 u16 maxpacket;
641 u16 addrofs;
642 u16 bw_num;
643};
644
645struct fusb300_request {
646
647 struct usb_request req;
648 struct list_head queue;
649};
650
651
652struct fusb300_ep {
653 struct usb_ep ep;
654 struct fusb300 *fusb300;
655
656 struct list_head queue;
657 unsigned stall:1;
658 unsigned wedged:1;
659 unsigned use_dma:1;
660
661 unsigned char epnum;
662 unsigned char type;
663 const struct usb_endpoint_descriptor *desc;
664};
665
666struct fusb300 {
667 spinlock_t lock;
668 void __iomem *reg;
669
670 unsigned long irq_trigger;
671
672 struct usb_gadget gadget;
673 struct usb_gadget_driver *driver;
674
675 struct fusb300_ep *ep[FUSB300_MAX_NUM_EP];
676
677 struct usb_request *ep0_req; /* for internal request */
678 __le16 ep0_data;
679 u32 ep0_length; /* for internal request */
680 u8 ep0_dir; /* 0/0x80 out/in */
681
682 u8 fifo_entry_num; /* next start fifo entry */
683 u32 addrofs; /* next fifo address offset */
684 u8 reenum; /* if re-enumeration */
685};
686
687#endif