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1/******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26#include "wifi.h"
27#include "core.h"
28#include "pci.h"
29#include "base.h"
30#include "ps.h"
31#include "efuse.h"
32#include <linux/interrupt.h>
33#include <linux/export.h>
34#include <linux/module.h>
35
36MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
37MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
38MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
39MODULE_LICENSE("GPL");
40MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
41
42static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
43 INTEL_VENDOR_ID,
44 ATI_VENDOR_ID,
45 AMD_VENDOR_ID,
46 SIS_VENDOR_ID
47};
48
49static const u8 ac_to_hwq[] = {
50 VO_QUEUE,
51 VI_QUEUE,
52 BE_QUEUE,
53 BK_QUEUE
54};
55
56static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
57 struct sk_buff *skb)
58{
59 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
60 __le16 fc = rtl_get_fc(skb);
61 u8 queue_index = skb_get_queue_mapping(skb);
62 struct ieee80211_hdr *hdr;
63
64 if (unlikely(ieee80211_is_beacon(fc)))
65 return BEACON_QUEUE;
66 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
67 return MGNT_QUEUE;
68 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
69 if (ieee80211_is_nullfunc(fc))
70 return HIGH_QUEUE;
71 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
72 hdr = rtl_get_hdr(skb);
73
74 if (is_multicast_ether_addr(hdr->addr1) ||
75 is_broadcast_ether_addr(hdr->addr1))
76 return HIGH_QUEUE;
77 }
78
79 return ac_to_hwq[queue_index];
80}
81
82/* Update PCI dependent default settings*/
83static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
84{
85 struct rtl_priv *rtlpriv = rtl_priv(hw);
86 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
87 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
88 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
89 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
90 u8 init_aspm;
91
92 ppsc->reg_rfps_level = 0;
93 ppsc->support_aspm = false;
94
95 /*Update PCI ASPM setting */
96 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
97 switch (rtlpci->const_pci_aspm) {
98 case 0:
99 /*No ASPM */
100 break;
101
102 case 1:
103 /*ASPM dynamically enabled/disable. */
104 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
105 break;
106
107 case 2:
108 /*ASPM with Clock Req dynamically enabled/disable. */
109 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
110 RT_RF_OFF_LEVL_CLK_REQ);
111 break;
112
113 case 3:
114 /* Always enable ASPM and Clock Req
115 * from initialization to halt.
116 */
117 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
118 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
119 RT_RF_OFF_LEVL_CLK_REQ);
120 break;
121
122 case 4:
123 /* Always enable ASPM without Clock Req
124 * from initialization to halt.
125 */
126 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
127 RT_RF_OFF_LEVL_CLK_REQ);
128 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
129 break;
130 }
131
132 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
133
134 /*Update Radio OFF setting */
135 switch (rtlpci->const_hwsw_rfoff_d3) {
136 case 1:
137 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
138 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
139 break;
140
141 case 2:
142 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
144 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
145 break;
146
147 case 3:
148 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
149 break;
150 }
151
152 /*Set HW definition to determine if it supports ASPM. */
153 switch (rtlpci->const_support_pciaspm) {
154 case 0:{
155 /*Not support ASPM. */
156 bool support_aspm = false;
157
158 ppsc->support_aspm = support_aspm;
159 break;
160 }
161 case 1:{
162 /*Support ASPM. */
163 bool support_aspm = true;
164 bool support_backdoor = true;
165
166 ppsc->support_aspm = support_aspm;
167
168 /*if (priv->oem_id == RT_CID_TOSHIBA &&
169 * !priv->ndis_adapter.amd_l1_patch)
170 * support_backdoor = false;
171 */
172
173 ppsc->support_backdoor = support_backdoor;
174
175 break;
176 }
177 case 2:
178 /*ASPM value set by chipset. */
179 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
180 bool support_aspm = true;
181
182 ppsc->support_aspm = support_aspm;
183 }
184 break;
185 default:
186 pr_err("switch case %#x not processed\n",
187 rtlpci->const_support_pciaspm);
188 break;
189 }
190
191 /* toshiba aspm issue, toshiba will set aspm selfly
192 * so we should not set aspm in driver
193 */
194 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
195 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
196 init_aspm == 0x43)
197 ppsc->support_aspm = false;
198}
199
200static bool _rtl_pci_platform_switch_device_pci_aspm(
201 struct ieee80211_hw *hw,
202 u8 value)
203{
204 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206
207 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
208 value |= 0x40;
209
210 pci_write_config_byte(rtlpci->pdev, 0x80, value);
211
212 return false;
213}
214
215/*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
216static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
217{
218 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
219 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
220
221 pci_write_config_byte(rtlpci->pdev, 0x81, value);
222
223 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
224 udelay(100);
225}
226
227/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
228static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
229{
230 struct rtl_priv *rtlpriv = rtl_priv(hw);
231 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
232 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
233 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
234 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
235 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
236 /*Retrieve original configuration settings. */
237 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
238 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.pcibridge_linkctrlreg;
239 u16 aspmlevel = 0;
240 u8 tmp_u1b = 0;
241
242 if (!ppsc->support_aspm)
243 return;
244
245 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
246 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
247 "PCI(Bridge) UNKNOWN\n");
248
249 return;
250 }
251
252 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
253 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
254 _rtl_pci_switch_clk_req(hw, 0x0);
255 }
256
257 /*for promising device will in L0 state after an I/O. */
258 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
259
260 /*Set corresponding value. */
261 aspmlevel |= BIT(0) | BIT(1);
262 linkctrl_reg &= ~aspmlevel;
263 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
264
265 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
266 udelay(50);
267
268 /*4 Disable Pci Bridge ASPM */
269 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
270 pcibridge_linkctrlreg);
271
272 udelay(50);
273}
274
275/*
276 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
277 *power saving We should follow the sequence to enable
278 *RTL8192SE first then enable Pci Bridge ASPM
279 *or the system will show bluescreen.
280 */
281static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
282{
283 struct rtl_priv *rtlpriv = rtl_priv(hw);
284 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
285 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
286 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
287 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
288 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
289 u16 aspmlevel;
290 u8 u_pcibridge_aspmsetting;
291 u8 u_device_aspmsetting;
292
293 if (!ppsc->support_aspm)
294 return;
295
296 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
297 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
298 "PCI(Bridge) UNKNOWN\n");
299 return;
300 }
301
302 /*4 Enable Pci Bridge ASPM */
303
304 u_pcibridge_aspmsetting =
305 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
306 rtlpci->const_hostpci_aspm_setting;
307
308 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
309 u_pcibridge_aspmsetting &= ~BIT(0);
310
311 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
312 u_pcibridge_aspmsetting);
313
314 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
315 "PlatformEnableASPM(): Write reg[%x] = %x\n",
316 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
317 u_pcibridge_aspmsetting);
318
319 udelay(50);
320
321 /*Get ASPM level (with/without Clock Req) */
322 aspmlevel = rtlpci->const_devicepci_aspm_setting;
323 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
324
325 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
326 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
327
328 u_device_aspmsetting |= aspmlevel;
329
330 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
331
332 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
333 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
334 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
335 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
336 }
337 udelay(100);
338}
339
340static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
341{
342 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
343
344 bool status = false;
345 u8 offset_e0;
346 unsigned int offset_e4;
347
348 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
349
350 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
351
352 if (offset_e0 == 0xA0) {
353 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
354 if (offset_e4 & BIT(23))
355 status = true;
356 }
357
358 return status;
359}
360
361static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
362 struct rtl_priv **buddy_priv)
363{
364 struct rtl_priv *rtlpriv = rtl_priv(hw);
365 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
366 bool find_buddy_priv = false;
367 struct rtl_priv *tpriv;
368 struct rtl_pci_priv *tpcipriv = NULL;
369
370 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
371 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
372 list) {
373 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
374 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
375 "pcipriv->ndis_adapter.funcnumber %x\n",
376 pcipriv->ndis_adapter.funcnumber);
377 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
378 "tpcipriv->ndis_adapter.funcnumber %x\n",
379 tpcipriv->ndis_adapter.funcnumber);
380
381 if ((pcipriv->ndis_adapter.busnumber ==
382 tpcipriv->ndis_adapter.busnumber) &&
383 (pcipriv->ndis_adapter.devnumber ==
384 tpcipriv->ndis_adapter.devnumber) &&
385 (pcipriv->ndis_adapter.funcnumber !=
386 tpcipriv->ndis_adapter.funcnumber)) {
387 find_buddy_priv = true;
388 break;
389 }
390 }
391 }
392
393 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
394 "find_buddy_priv %d\n", find_buddy_priv);
395
396 if (find_buddy_priv)
397 *buddy_priv = tpriv;
398
399 return find_buddy_priv;
400}
401
402static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
403{
404 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
405 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
406 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
407 u8 linkctrl_reg;
408 u8 num4bbytes;
409
410 num4bbytes = (capabilityoffset + 0x10) / 4;
411
412 /*Read Link Control Register */
413 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
414
415 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
416}
417
418static void rtl_pci_parse_configuration(struct pci_dev *pdev,
419 struct ieee80211_hw *hw)
420{
421 struct rtl_priv *rtlpriv = rtl_priv(hw);
422 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
423
424 u8 tmp;
425 u16 linkctrl_reg;
426
427 /*Link Control Register */
428 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
429 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
430
431 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
432 pcipriv->ndis_adapter.linkctrl_reg);
433
434 pci_read_config_byte(pdev, 0x98, &tmp);
435 tmp |= BIT(4);
436 pci_write_config_byte(pdev, 0x98, tmp);
437
438 tmp = 0x17;
439 pci_write_config_byte(pdev, 0x70f, tmp);
440}
441
442static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
443{
444 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
445
446 _rtl_pci_update_default_setting(hw);
447
448 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
449 /*Always enable ASPM & Clock Req. */
450 rtl_pci_enable_aspm(hw);
451 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
452 }
453}
454
455static void _rtl_pci_io_handler_init(struct device *dev,
456 struct ieee80211_hw *hw)
457{
458 struct rtl_priv *rtlpriv = rtl_priv(hw);
459
460 rtlpriv->io.dev = dev;
461
462 rtlpriv->io.write8_async = pci_write8_async;
463 rtlpriv->io.write16_async = pci_write16_async;
464 rtlpriv->io.write32_async = pci_write32_async;
465
466 rtlpriv->io.read8_sync = pci_read8_sync;
467 rtlpriv->io.read16_sync = pci_read16_sync;
468 rtlpriv->io.read32_sync = pci_read32_sync;
469}
470
471static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
472 struct sk_buff *skb,
473 struct rtl_tcb_desc *tcb_desc, u8 tid)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
477 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
478 struct sk_buff *next_skb;
479 u8 additionlen = FCS_LEN;
480
481 /* here open is 4, wep/tkip is 8, aes is 12*/
482 if (info->control.hw_key)
483 additionlen += info->control.hw_key->icv_len;
484
485 /* The most skb num is 6 */
486 tcb_desc->empkt_num = 0;
487 spin_lock_bh(&rtlpriv->locks.waitq_lock);
488 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
489 struct ieee80211_tx_info *next_info;
490
491 next_info = IEEE80211_SKB_CB(next_skb);
492 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
493 tcb_desc->empkt_len[tcb_desc->empkt_num] =
494 next_skb->len + additionlen;
495 tcb_desc->empkt_num++;
496 } else {
497 break;
498 }
499
500 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
501 next_skb))
502 break;
503
504 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
505 break;
506 }
507 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
508
509 return true;
510}
511
512/* just for early mode now */
513static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
514{
515 struct rtl_priv *rtlpriv = rtl_priv(hw);
516 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
517 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
518 struct sk_buff *skb = NULL;
519 struct ieee80211_tx_info *info = NULL;
520 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
521 int tid;
522
523 if (!rtlpriv->rtlhal.earlymode_enable)
524 return;
525
526 if (rtlpriv->dm.supp_phymode_switch &&
527 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
528 (rtlpriv->buddy_priv &&
529 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
530 return;
531 /* we just use em for BE/BK/VI/VO */
532 for (tid = 7; tid >= 0; tid--) {
533 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
534 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
535
536 while (!mac->act_scanning &&
537 rtlpriv->psc.rfpwr_state == ERFON) {
538 struct rtl_tcb_desc tcb_desc;
539
540 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
541 spin_lock_bh(&rtlpriv->locks.waitq_lock);
542 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
543 (ring->entries - skb_queue_len(&ring->queue) >
544 rtlhal->max_earlymode_num)) {
545 skb = skb_dequeue(&mac->skb_waitq[tid]);
546 } else {
547 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
548 break;
549 }
550 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
551
552 /* Some macaddr can't do early mode. like
553 * multicast/broadcast/no_qos data
554 */
555 info = IEEE80211_SKB_CB(skb);
556 if (info->flags & IEEE80211_TX_CTL_AMPDU)
557 _rtl_update_earlymode_info(hw, skb,
558 &tcb_desc, tid);
559
560 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
561 }
562 }
563}
564
565static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
566{
567 struct rtl_priv *rtlpriv = rtl_priv(hw);
568 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
569
570 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
571
572 while (skb_queue_len(&ring->queue)) {
573 struct sk_buff *skb;
574 struct ieee80211_tx_info *info;
575 __le16 fc;
576 u8 tid;
577 u8 *entry;
578
579 if (rtlpriv->use_new_trx_flow)
580 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
581 else
582 entry = (u8 *)(&ring->desc[ring->idx]);
583
584 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
585 return;
586 ring->idx = (ring->idx + 1) % ring->entries;
587
588 skb = __skb_dequeue(&ring->queue);
589 pci_unmap_single(rtlpci->pdev,
590 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry, true,
591 HW_DESC_TXBUFF_ADDR),
592 skb->len, PCI_DMA_TODEVICE);
593
594 /* remove early mode header */
595 if (rtlpriv->rtlhal.earlymode_enable)
596 skb_pull(skb, EM_HDR_LEN);
597
598 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
599 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
600 ring->idx,
601 skb_queue_len(&ring->queue),
602 *(u16 *)(skb->data + 22));
603
604 if (prio == TXCMD_QUEUE) {
605 dev_kfree_skb(skb);
606 goto tx_status_ok;
607 }
608
609 /* for sw LPS, just after NULL skb send out, we can
610 * sure AP knows we are sleeping, we should not let
611 * rf sleep
612 */
613 fc = rtl_get_fc(skb);
614 if (ieee80211_is_nullfunc(fc)) {
615 if (ieee80211_has_pm(fc)) {
616 rtlpriv->mac80211.offchan_delay = true;
617 rtlpriv->psc.state_inap = true;
618 } else {
619 rtlpriv->psc.state_inap = false;
620 }
621 }
622 if (ieee80211_is_action(fc)) {
623 struct ieee80211_mgmt *action_frame =
624 (struct ieee80211_mgmt *)skb->data;
625 if (action_frame->u.action.u.ht_smps.action ==
626 WLAN_HT_ACTION_SMPS) {
627 dev_kfree_skb(skb);
628 goto tx_status_ok;
629 }
630 }
631
632 /* update tid tx pkt num */
633 tid = rtl_get_tid(skb);
634 if (tid <= 7)
635 rtlpriv->link_info.tidtx_inperiod[tid]++;
636
637 info = IEEE80211_SKB_CB(skb);
638 ieee80211_tx_info_clear_status(info);
639
640 info->flags |= IEEE80211_TX_STAT_ACK;
641 /*info->status.rates[0].count = 1; */
642
643 ieee80211_tx_status_irqsafe(hw, skb);
644
645 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
646 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
647 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
648 prio, ring->idx,
649 skb_queue_len(&ring->queue));
650
651 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
652 }
653tx_status_ok:
654 skb = NULL;
655 }
656
657 if (((rtlpriv->link_info.num_rx_inperiod +
658 rtlpriv->link_info.num_tx_inperiod) > 8) ||
659 (rtlpriv->link_info.num_rx_inperiod > 2))
660 rtl_lps_leave(hw);
661}
662
663static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
664 struct sk_buff *new_skb, u8 *entry,
665 int rxring_idx, int desc_idx)
666{
667 struct rtl_priv *rtlpriv = rtl_priv(hw);
668 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
669 u32 bufferaddress;
670 u8 tmp_one = 1;
671 struct sk_buff *skb;
672
673 if (likely(new_skb)) {
674 skb = new_skb;
675 goto remap;
676 }
677 skb = dev_alloc_skb(rtlpci->rxbuffersize);
678 if (!skb)
679 return 0;
680
681remap:
682 /* just set skb->cb to mapping addr for pci_unmap_single use */
683 *((dma_addr_t *)skb->cb) =
684 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
685 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
686 bufferaddress = *((dma_addr_t *)skb->cb);
687 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
688 return 0;
689 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
690 if (rtlpriv->use_new_trx_flow) {
691 /* skb->cb may be 64 bit address */
692 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
693 HW_DESC_RX_PREPARE,
694 (u8 *)(dma_addr_t *)skb->cb);
695 } else {
696 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
697 HW_DESC_RXBUFF_ADDR,
698 (u8 *)&bufferaddress);
699 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
700 HW_DESC_RXPKT_LEN,
701 (u8 *)&rtlpci->rxbuffersize);
702 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
703 HW_DESC_RXOWN,
704 (u8 *)&tmp_one);
705 }
706 return 1;
707}
708
709/* inorder to receive 8K AMSDU we have set skb to
710 * 9100bytes in init rx ring, but if this packet is
711 * not a AMSDU, this large packet will be sent to
712 * TCP/IP directly, this cause big packet ping fail
713 * like: "ping -s 65507", so here we will realloc skb
714 * based on the true size of packet, Mac80211
715 * Probably will do it better, but does not yet.
716 *
717 * Some platform will fail when alloc skb sometimes.
718 * in this condition, we will send the old skb to
719 * mac80211 directly, this will not cause any other
720 * issues, but only this packet will be lost by TCP/IP
721 */
722static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
723 struct sk_buff *skb,
724 struct ieee80211_rx_status rx_status)
725{
726 if (unlikely(!rtl_action_proc(hw, skb, false))) {
727 dev_kfree_skb_any(skb);
728 } else {
729 struct sk_buff *uskb = NULL;
730
731 uskb = dev_alloc_skb(skb->len + 128);
732 if (likely(uskb)) {
733 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
734 sizeof(rx_status));
735 skb_put_data(uskb, skb->data, skb->len);
736 dev_kfree_skb_any(skb);
737 ieee80211_rx_irqsafe(hw, uskb);
738 } else {
739 ieee80211_rx_irqsafe(hw, skb);
740 }
741 }
742}
743
744/*hsisr interrupt handler*/
745static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
746{
747 struct rtl_priv *rtlpriv = rtl_priv(hw);
748 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
749
750 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
751 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
752 rtlpci->sys_irq_mask);
753}
754
755static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
759 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
760 struct ieee80211_rx_status rx_status = { 0 };
761 unsigned int count = rtlpci->rxringcount;
762 u8 own;
763 u8 tmp_one;
764 bool unicast = false;
765 u8 hw_queue = 0;
766 unsigned int rx_remained_cnt = 0;
767 struct rtl_stats stats = {
768 .signal = 0,
769 .rate = 0,
770 };
771
772 /*RX NORMAL PKT */
773 while (count--) {
774 struct ieee80211_hdr *hdr;
775 __le16 fc;
776 u16 len;
777 /*rx buffer descriptor */
778 struct rtl_rx_buffer_desc *buffer_desc = NULL;
779 /*if use new trx flow, it means wifi info */
780 struct rtl_rx_desc *pdesc = NULL;
781 /*rx pkt */
782 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
783 rtlpci->rx_ring[rxring_idx].idx];
784 struct sk_buff *new_skb;
785
786 if (rtlpriv->use_new_trx_flow) {
787 if (rx_remained_cnt == 0)
788 rx_remained_cnt =
789 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
790 hw_queue);
791 if (rx_remained_cnt == 0)
792 return;
793 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
794 rtlpci->rx_ring[rxring_idx].idx];
795 pdesc = (struct rtl_rx_desc *)skb->data;
796 } else { /* rx descriptor */
797 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
798 rtlpci->rx_ring[rxring_idx].idx];
799
800 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
801 false,
802 HW_DESC_OWN);
803 if (own) /* wait data to be filled by hardware */
804 return;
805 }
806
807 /* Reaching this point means: data is filled already
808 * AAAAAAttention !!!
809 * We can NOT access 'skb' before 'pci_unmap_single'
810 */
811 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
812 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
813
814 /* get a new skb - if fail, old one will be reused */
815 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
816 if (unlikely(!new_skb))
817 goto no_new;
818 memset(&rx_status, 0, sizeof(rx_status));
819 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
820 &rx_status, (u8 *)pdesc, skb);
821
822 if (rtlpriv->use_new_trx_flow)
823 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
824 (u8 *)buffer_desc,
825 hw_queue);
826
827 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
828 HW_DESC_RXPKT_LEN);
829
830 if (skb->end - skb->tail > len) {
831 skb_put(skb, len);
832 if (rtlpriv->use_new_trx_flow)
833 skb_reserve(skb, stats.rx_drvinfo_size +
834 stats.rx_bufshift + 24);
835 else
836 skb_reserve(skb, stats.rx_drvinfo_size +
837 stats.rx_bufshift);
838 } else {
839 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
840 "skb->end - skb->tail = %d, len is %d\n",
841 skb->end - skb->tail, len);
842 dev_kfree_skb_any(skb);
843 goto new_trx_end;
844 }
845 /* handle command packet here */
846 if (rtlpriv->cfg->ops->rx_command_packet &&
847 rtlpriv->cfg->ops->rx_command_packet(hw, &stats, skb)) {
848 dev_kfree_skb_any(skb);
849 goto new_trx_end;
850 }
851
852 /*
853 * NOTICE This can not be use for mac80211,
854 * this is done in mac80211 code,
855 * if done here sec DHCP will fail
856 * skb_trim(skb, skb->len - 4);
857 */
858
859 hdr = rtl_get_hdr(skb);
860 fc = rtl_get_fc(skb);
861
862 if (!stats.crc && !stats.hwerror) {
863 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
864 sizeof(rx_status));
865
866 if (is_broadcast_ether_addr(hdr->addr1)) {
867 ;/*TODO*/
868 } else if (is_multicast_ether_addr(hdr->addr1)) {
869 ;/*TODO*/
870 } else {
871 unicast = true;
872 rtlpriv->stats.rxbytesunicast += skb->len;
873 }
874 rtl_is_special_data(hw, skb, false, true);
875
876 if (ieee80211_is_data(fc)) {
877 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
878 if (unicast)
879 rtlpriv->link_info.num_rx_inperiod++;
880 }
881
882 rtl_collect_scan_list(hw, skb);
883
884 /* static bcn for roaming */
885 rtl_beacon_statistic(hw, skb);
886 rtl_p2p_info(hw, (void *)skb->data, skb->len);
887 /* for sw lps */
888 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
889 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
890 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
891 (rtlpriv->rtlhal.current_bandtype ==
892 BAND_ON_2_4G) &&
893 (ieee80211_is_beacon(fc) ||
894 ieee80211_is_probe_resp(fc))) {
895 dev_kfree_skb_any(skb);
896 } else {
897 rtl_check_beacon_key(hw, (void *)skb->data,
898 skb->len);
899 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
900 }
901 } else {
902 dev_kfree_skb_any(skb);
903 }
904new_trx_end:
905 if (rtlpriv->use_new_trx_flow) {
906 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
907 rtlpci->rx_ring[hw_queue].next_rx_rp %=
908 RTL_PCI_MAX_RX_COUNT;
909
910 rx_remained_cnt--;
911 rtl_write_word(rtlpriv, 0x3B4,
912 rtlpci->rx_ring[hw_queue].next_rx_rp);
913 }
914 if (((rtlpriv->link_info.num_rx_inperiod +
915 rtlpriv->link_info.num_tx_inperiod) > 8) ||
916 (rtlpriv->link_info.num_rx_inperiod > 2))
917 rtl_lps_leave(hw);
918 skb = new_skb;
919no_new:
920 if (rtlpriv->use_new_trx_flow) {
921 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
922 rxring_idx,
923 rtlpci->rx_ring[rxring_idx].idx);
924 } else {
925 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
926 rxring_idx,
927 rtlpci->rx_ring[rxring_idx].idx);
928 if (rtlpci->rx_ring[rxring_idx].idx ==
929 rtlpci->rxringcount - 1)
930 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
931 false,
932 HW_DESC_RXERO,
933 (u8 *)&tmp_one);
934 }
935 rtlpci->rx_ring[rxring_idx].idx =
936 (rtlpci->rx_ring[rxring_idx].idx + 1) %
937 rtlpci->rxringcount;
938 }
939}
940
941static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
942{
943 struct ieee80211_hw *hw = dev_id;
944 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
945 struct rtl_priv *rtlpriv = rtl_priv(hw);
946 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
947 unsigned long flags;
948 u32 inta = 0;
949 u32 intb = 0;
950 u32 intc = 0;
951 u32 intd = 0;
952 irqreturn_t ret = IRQ_HANDLED;
953
954 if (rtlpci->irq_enabled == 0)
955 return ret;
956
957 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
958 rtlpriv->cfg->ops->disable_interrupt(hw);
959
960 /*read ISR: 4/8bytes */
961 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb, &intc, &intd);
962
963 /*Shared IRQ or HW disappeared */
964 if (!inta || inta == 0xffff)
965 goto done;
966
967 /*<1> beacon related */
968 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
969 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
970 "beacon ok interrupt!\n");
971 }
972
973 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
974 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
975 "beacon err interrupt!\n");
976 }
977
978 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
979 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
980
981 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
982 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
983 "prepare beacon for interrupt!\n");
984 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
985 }
986
987 /*<2> Tx related */
988 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
989 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
990
991 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
992 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
993 "Manage ok interrupt!\n");
994 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
995 }
996
997 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
998 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
999 "HIGH_QUEUE ok interrupt!\n");
1000 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
1001 }
1002
1003 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
1004 rtlpriv->link_info.num_tx_inperiod++;
1005
1006 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1007 "BK Tx OK interrupt!\n");
1008 _rtl_pci_tx_isr(hw, BK_QUEUE);
1009 }
1010
1011 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
1012 rtlpriv->link_info.num_tx_inperiod++;
1013
1014 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1015 "BE TX OK interrupt!\n");
1016 _rtl_pci_tx_isr(hw, BE_QUEUE);
1017 }
1018
1019 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
1020 rtlpriv->link_info.num_tx_inperiod++;
1021
1022 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1023 "VI TX OK interrupt!\n");
1024 _rtl_pci_tx_isr(hw, VI_QUEUE);
1025 }
1026
1027 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1028 rtlpriv->link_info.num_tx_inperiod++;
1029
1030 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1031 "Vo TX OK interrupt!\n");
1032 _rtl_pci_tx_isr(hw, VO_QUEUE);
1033 }
1034
1035 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
1036 if (intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
1037 rtlpriv->link_info.num_tx_inperiod++;
1038
1039 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1040 "H2C TX OK interrupt!\n");
1041 _rtl_pci_tx_isr(hw, H2C_QUEUE);
1042 }
1043 }
1044
1045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1046 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1047 rtlpriv->link_info.num_tx_inperiod++;
1048
1049 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1050 "CMD TX OK interrupt!\n");
1051 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1052 }
1053 }
1054
1055 /*<3> Rx related */
1056 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1057 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1058 _rtl_pci_rx_interrupt(hw);
1059 }
1060
1061 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1062 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1063 "rx descriptor unavailable!\n");
1064 _rtl_pci_rx_interrupt(hw);
1065 }
1066
1067 if (unlikely(intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1068 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1069 _rtl_pci_rx_interrupt(hw);
1070 }
1071
1072 /*<4> fw related*/
1073 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1074 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1075 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1076 "firmware interrupt!\n");
1077 queue_delayed_work(rtlpriv->works.rtl_wq,
1078 &rtlpriv->works.fwevt_wq, 0);
1079 }
1080 }
1081
1082 /*<5> hsisr related*/
1083 /* Only 8188EE & 8723BE Supported.
1084 * If Other ICs Come in, System will corrupt,
1085 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1086 * are not initialized
1087 */
1088 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1089 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1090 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1091 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1092 "hsisr interrupt!\n");
1093 _rtl_pci_hs_interrupt(hw);
1094 }
1095 }
1096
1097 if (rtlpriv->rtlhal.earlymode_enable)
1098 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1099
1100done:
1101 rtlpriv->cfg->ops->enable_interrupt(hw);
1102 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1103 return ret;
1104}
1105
1106static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1107{
1108 _rtl_pci_tx_chk_waitq(hw);
1109}
1110
1111static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1112{
1113 struct rtl_priv *rtlpriv = rtl_priv(hw);
1114 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1115 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1116 struct rtl8192_tx_ring *ring = NULL;
1117 struct ieee80211_hdr *hdr = NULL;
1118 struct ieee80211_tx_info *info = NULL;
1119 struct sk_buff *pskb = NULL;
1120 struct rtl_tx_desc *pdesc = NULL;
1121 struct rtl_tcb_desc tcb_desc;
1122 /*This is for new trx flow*/
1123 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1124 u8 temp_one = 1;
1125 u8 *entry;
1126
1127 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1128 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1129 pskb = __skb_dequeue(&ring->queue);
1130 if (rtlpriv->use_new_trx_flow)
1131 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1132 else
1133 entry = (u8 *)(&ring->desc[ring->idx]);
1134 if (pskb) {
1135 pci_unmap_single(rtlpci->pdev,
1136 rtlpriv->cfg->ops->get_desc(
1137 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1138 pskb->len, PCI_DMA_TODEVICE);
1139 kfree_skb(pskb);
1140 }
1141
1142 /*NB: the beacon data buffer must be 32-bit aligned. */
1143 pskb = ieee80211_beacon_get(hw, mac->vif);
1144 if (!pskb)
1145 return;
1146 hdr = rtl_get_hdr(pskb);
1147 info = IEEE80211_SKB_CB(pskb);
1148 pdesc = &ring->desc[0];
1149 if (rtlpriv->use_new_trx_flow)
1150 pbuffer_desc = &ring->buffer_desc[0];
1151
1152 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1153 (u8 *)pbuffer_desc, info, NULL, pskb,
1154 BEACON_QUEUE, &tcb_desc);
1155
1156 __skb_queue_tail(&ring->queue, pskb);
1157
1158 if (rtlpriv->use_new_trx_flow) {
1159 temp_one = 4;
1160 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1161 HW_DESC_OWN, (u8 *)&temp_one);
1162 } else {
1163 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1164 &temp_one);
1165 }
1166}
1167
1168static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1169{
1170 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1173 u8 i;
1174 u16 desc_num;
1175
1176 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1177 desc_num = TX_DESC_NUM_92E;
1178 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1179 desc_num = TX_DESC_NUM_8822B;
1180 else
1181 desc_num = RT_TXDESC_NUM;
1182
1183 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1184 rtlpci->txringcount[i] = desc_num;
1185
1186 /*
1187 *we just alloc 2 desc for beacon queue,
1188 *because we just need first desc in hw beacon.
1189 */
1190 rtlpci->txringcount[BEACON_QUEUE] = 2;
1191
1192 /*BE queue need more descriptor for performance
1193 *consideration or, No more tx desc will happen,
1194 *and may cause mac80211 mem leakage.
1195 */
1196 if (!rtl_priv(hw)->use_new_trx_flow)
1197 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1198
1199 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1200 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1201}
1202
1203static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1204 struct pci_dev *pdev)
1205{
1206 struct rtl_priv *rtlpriv = rtl_priv(hw);
1207 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1210
1211 rtlpci->up_first_time = true;
1212 rtlpci->being_init_adapter = false;
1213
1214 rtlhal->hw = hw;
1215 rtlpci->pdev = pdev;
1216
1217 /*Tx/Rx related var */
1218 _rtl_pci_init_trx_var(hw);
1219
1220 /*IBSS*/
1221 mac->beacon_interval = 100;
1222
1223 /*AMPDU*/
1224 mac->min_space_cfg = 0;
1225 mac->max_mss_density = 0;
1226 /*set sane AMPDU defaults */
1227 mac->current_ampdu_density = 7;
1228 mac->current_ampdu_factor = 3;
1229
1230 /*Retry Limit*/
1231 mac->retry_short = 7;
1232 mac->retry_long = 7;
1233
1234 /*QOS*/
1235 rtlpci->acm_method = EACMWAY2_SW;
1236
1237 /*task */
1238 tasklet_init(&rtlpriv->works.irq_tasklet,
1239 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1240 (unsigned long)hw);
1241 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1242 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1243 (unsigned long)hw);
1244 INIT_WORK(&rtlpriv->works.lps_change_work,
1245 rtl_lps_change_work_callback);
1246}
1247
1248static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1249 unsigned int prio, unsigned int entries)
1250{
1251 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1252 struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 struct rtl_tx_buffer_desc *buffer_desc;
1254 struct rtl_tx_desc *desc;
1255 dma_addr_t buffer_desc_dma, desc_dma;
1256 u32 nextdescaddress;
1257 int i;
1258
1259 /* alloc tx buffer desc for new trx flow*/
1260 if (rtlpriv->use_new_trx_flow) {
1261 buffer_desc =
1262 pci_zalloc_consistent(rtlpci->pdev,
1263 sizeof(*buffer_desc) * entries,
1264 &buffer_desc_dma);
1265
1266 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1267 pr_err("Cannot allocate TX ring (prio = %d)\n",
1268 prio);
1269 return -ENOMEM;
1270 }
1271
1272 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1273 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1274
1275 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1276 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1277 }
1278
1279 /* alloc dma for this ring */
1280 desc = pci_zalloc_consistent(rtlpci->pdev,
1281 sizeof(*desc) * entries, &desc_dma);
1282
1283 if (!desc || (unsigned long)desc & 0xFF) {
1284 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1285 return -ENOMEM;
1286 }
1287
1288 rtlpci->tx_ring[prio].desc = desc;
1289 rtlpci->tx_ring[prio].dma = desc_dma;
1290
1291 rtlpci->tx_ring[prio].idx = 0;
1292 rtlpci->tx_ring[prio].entries = entries;
1293 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1294
1295 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1296 prio, desc);
1297
1298 /* init every desc in this ring */
1299 if (!rtlpriv->use_new_trx_flow) {
1300 for (i = 0; i < entries; i++) {
1301 nextdescaddress = (u32)desc_dma +
1302 ((i + 1) % entries) *
1303 sizeof(*desc);
1304
1305 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1306 true,
1307 HW_DESC_TX_NEXTDESC_ADDR,
1308 (u8 *)&nextdescaddress);
1309 }
1310 }
1311 return 0;
1312}
1313
1314static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1315{
1316 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317 struct rtl_priv *rtlpriv = rtl_priv(hw);
1318 int i;
1319
1320 if (rtlpriv->use_new_trx_flow) {
1321 struct rtl_rx_buffer_desc *entry = NULL;
1322 /* alloc dma for this ring */
1323 rtlpci->rx_ring[rxring_idx].buffer_desc =
1324 pci_zalloc_consistent(rtlpci->pdev,
1325 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1326 rtlpci->rxringcount,
1327 &rtlpci->rx_ring[rxring_idx].dma);
1328 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1329 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1330 pr_err("Cannot allocate RX ring\n");
1331 return -ENOMEM;
1332 }
1333
1334 /* init every desc in this ring */
1335 rtlpci->rx_ring[rxring_idx].idx = 0;
1336 for (i = 0; i < rtlpci->rxringcount; i++) {
1337 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1338 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1339 rxring_idx, i))
1340 return -ENOMEM;
1341 }
1342 } else {
1343 struct rtl_rx_desc *entry = NULL;
1344 u8 tmp_one = 1;
1345 /* alloc dma for this ring */
1346 rtlpci->rx_ring[rxring_idx].desc =
1347 pci_zalloc_consistent(rtlpci->pdev,
1348 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1349 rtlpci->rxringcount,
1350 &rtlpci->rx_ring[rxring_idx].dma);
1351 if (!rtlpci->rx_ring[rxring_idx].desc ||
1352 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1353 pr_err("Cannot allocate RX ring\n");
1354 return -ENOMEM;
1355 }
1356
1357 /* init every desc in this ring */
1358 rtlpci->rx_ring[rxring_idx].idx = 0;
1359
1360 for (i = 0; i < rtlpci->rxringcount; i++) {
1361 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1362 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1363 rxring_idx, i))
1364 return -ENOMEM;
1365 }
1366
1367 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1368 HW_DESC_RXERO, &tmp_one);
1369 }
1370 return 0;
1371}
1372
1373static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1374 unsigned int prio)
1375{
1376 struct rtl_priv *rtlpriv = rtl_priv(hw);
1377 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1378 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1379
1380 /* free every desc in this ring */
1381 while (skb_queue_len(&ring->queue)) {
1382 u8 *entry;
1383 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1384
1385 if (rtlpriv->use_new_trx_flow)
1386 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1387 else
1388 entry = (u8 *)(&ring->desc[ring->idx]);
1389
1390 pci_unmap_single(rtlpci->pdev,
1391 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1392 true,
1393 HW_DESC_TXBUFF_ADDR),
1394 skb->len, PCI_DMA_TODEVICE);
1395 kfree_skb(skb);
1396 ring->idx = (ring->idx + 1) % ring->entries;
1397 }
1398
1399 /* free dma of this ring */
1400 pci_free_consistent(rtlpci->pdev,
1401 sizeof(*ring->desc) * ring->entries,
1402 ring->desc, ring->dma);
1403 ring->desc = NULL;
1404 if (rtlpriv->use_new_trx_flow) {
1405 pci_free_consistent(rtlpci->pdev,
1406 sizeof(*ring->buffer_desc) * ring->entries,
1407 ring->buffer_desc, ring->buffer_desc_dma);
1408 ring->buffer_desc = NULL;
1409 }
1410}
1411
1412static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1413{
1414 struct rtl_priv *rtlpriv = rtl_priv(hw);
1415 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1416 int i;
1417
1418 /* free every desc in this ring */
1419 for (i = 0; i < rtlpci->rxringcount; i++) {
1420 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1421
1422 if (!skb)
1423 continue;
1424 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1425 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1426 kfree_skb(skb);
1427 }
1428
1429 /* free dma of this ring */
1430 if (rtlpriv->use_new_trx_flow) {
1431 pci_free_consistent(rtlpci->pdev,
1432 sizeof(*rtlpci->rx_ring[rxring_idx].buffer_desc) *
1433 rtlpci->rxringcount,
1434 rtlpci->rx_ring[rxring_idx].buffer_desc,
1435 rtlpci->rx_ring[rxring_idx].dma);
1436 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1437 } else {
1438 pci_free_consistent(rtlpci->pdev,
1439 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1440 rtlpci->rxringcount,
1441 rtlpci->rx_ring[rxring_idx].desc,
1442 rtlpci->rx_ring[rxring_idx].dma);
1443 rtlpci->rx_ring[rxring_idx].desc = NULL;
1444 }
1445}
1446
1447static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1448{
1449 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1450 int ret;
1451 int i, rxring_idx;
1452
1453 /* rxring_idx 0:RX_MPDU_QUEUE
1454 * rxring_idx 1:RX_CMD_QUEUE
1455 */
1456 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1457 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1458 if (ret)
1459 return ret;
1460 }
1461
1462 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1463 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1464 if (ret)
1465 goto err_free_rings;
1466 }
1467
1468 return 0;
1469
1470err_free_rings:
1471 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1472 _rtl_pci_free_rx_ring(hw, rxring_idx);
1473
1474 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1475 if (rtlpci->tx_ring[i].desc ||
1476 rtlpci->tx_ring[i].buffer_desc)
1477 _rtl_pci_free_tx_ring(hw, i);
1478
1479 return 1;
1480}
1481
1482static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1483{
1484 u32 i, rxring_idx;
1485
1486 /*free rx rings */
1487 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1488 _rtl_pci_free_rx_ring(hw, rxring_idx);
1489
1490 /*free tx rings */
1491 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1492 _rtl_pci_free_tx_ring(hw, i);
1493
1494 return 0;
1495}
1496
1497int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1498{
1499 struct rtl_priv *rtlpriv = rtl_priv(hw);
1500 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1501 int i, rxring_idx;
1502 unsigned long flags;
1503 u8 tmp_one = 1;
1504 u32 bufferaddress;
1505 /* rxring_idx 0:RX_MPDU_QUEUE */
1506 /* rxring_idx 1:RX_CMD_QUEUE */
1507 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1508 /* force the rx_ring[RX_MPDU_QUEUE/
1509 * RX_CMD_QUEUE].idx to the first one
1510 * new trx flow, do nothing
1511 */
1512 if (!rtlpriv->use_new_trx_flow &&
1513 rtlpci->rx_ring[rxring_idx].desc) {
1514 struct rtl_rx_desc *entry = NULL;
1515
1516 rtlpci->rx_ring[rxring_idx].idx = 0;
1517 for (i = 0; i < rtlpci->rxringcount; i++) {
1518 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1519 bufferaddress =
1520 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1521 false, HW_DESC_RXBUFF_ADDR);
1522 memset((u8 *)entry, 0,
1523 sizeof(*rtlpci->rx_ring
1524 [rxring_idx].desc));/*clear one entry*/
1525 if (rtlpriv->use_new_trx_flow) {
1526 /* This is deadcode */
1527 rtlpriv->cfg->ops->set_desc(hw,
1528 (u8 *)entry, false,
1529 HW_DESC_RX_PREPARE,
1530 (u8 *)&bufferaddress);
1531 } else {
1532 rtlpriv->cfg->ops->set_desc(hw,
1533 (u8 *)entry, false,
1534 HW_DESC_RXBUFF_ADDR,
1535 (u8 *)&bufferaddress);
1536 rtlpriv->cfg->ops->set_desc(hw,
1537 (u8 *)entry, false,
1538 HW_DESC_RXPKT_LEN,
1539 (u8 *)&rtlpci->rxbuffersize);
1540 rtlpriv->cfg->ops->set_desc(hw,
1541 (u8 *)entry, false,
1542 HW_DESC_RXOWN,
1543 (u8 *)&tmp_one);
1544 }
1545 }
1546 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1547 HW_DESC_RXERO, (u8 *)&tmp_one);
1548 }
1549 rtlpci->rx_ring[rxring_idx].idx = 0;
1550 }
1551
1552 /*
1553 *after reset, release previous pending packet,
1554 *and force the tx idx to the first one
1555 */
1556 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1557 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1558 if (rtlpci->tx_ring[i].desc ||
1559 rtlpci->tx_ring[i].buffer_desc) {
1560 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1561
1562 while (skb_queue_len(&ring->queue)) {
1563 u8 *entry;
1564 struct sk_buff *skb =
1565 __skb_dequeue(&ring->queue);
1566 if (rtlpriv->use_new_trx_flow)
1567 entry = (u8 *)(&ring->buffer_desc
1568 [ring->idx]);
1569 else
1570 entry = (u8 *)(&ring->desc[ring->idx]);
1571
1572 pci_unmap_single(rtlpci->pdev,
1573 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1574 true, HW_DESC_TXBUFF_ADDR),
1575 skb->len, PCI_DMA_TODEVICE);
1576 dev_kfree_skb_irq(skb);
1577 ring->idx = (ring->idx + 1) % ring->entries;
1578 }
1579
1580 if (rtlpriv->use_new_trx_flow) {
1581 rtlpci->tx_ring[i].cur_tx_rp = 0;
1582 rtlpci->tx_ring[i].cur_tx_wp = 0;
1583 }
1584
1585 ring->idx = 0;
1586 ring->entries = rtlpci->txringcount[i];
1587 }
1588 }
1589 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1590
1591 return 0;
1592}
1593
1594static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1595 struct ieee80211_sta *sta,
1596 struct sk_buff *skb)
1597{
1598 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 struct rtl_sta_info *sta_entry = NULL;
1600 u8 tid = rtl_get_tid(skb);
1601 __le16 fc = rtl_get_fc(skb);
1602
1603 if (!sta)
1604 return false;
1605 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1606
1607 if (!rtlpriv->rtlhal.earlymode_enable)
1608 return false;
1609 if (ieee80211_is_nullfunc(fc))
1610 return false;
1611 if (ieee80211_is_qos_nullfunc(fc))
1612 return false;
1613 if (ieee80211_is_pspoll(fc))
1614 return false;
1615 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1616 return false;
1617 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1618 return false;
1619 if (tid > 7)
1620 return false;
1621
1622 /* maybe every tid should be checked */
1623 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1624 return false;
1625
1626 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1627 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1628 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1629
1630 return true;
1631}
1632
1633static int rtl_pci_tx(struct ieee80211_hw *hw,
1634 struct ieee80211_sta *sta,
1635 struct sk_buff *skb,
1636 struct rtl_tcb_desc *ptcb_desc)
1637{
1638 struct rtl_priv *rtlpriv = rtl_priv(hw);
1639 struct rtl_sta_info *sta_entry = NULL;
1640 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1641 struct rtl8192_tx_ring *ring;
1642 struct rtl_tx_desc *pdesc;
1643 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1644 u16 idx;
1645 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1646 unsigned long flags;
1647 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1648 __le16 fc = rtl_get_fc(skb);
1649 u8 *pda_addr = hdr->addr1;
1650 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1651 /*ssn */
1652 u8 tid = 0;
1653 u16 seq_number = 0;
1654 u8 own;
1655 u8 temp_one = 1;
1656
1657 if (ieee80211_is_mgmt(fc))
1658 rtl_tx_mgmt_proc(hw, skb);
1659
1660 if (rtlpriv->psc.sw_ps_enabled) {
1661 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1662 !ieee80211_has_pm(fc))
1663 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1664 }
1665
1666 rtl_action_proc(hw, skb, true);
1667
1668 if (is_multicast_ether_addr(pda_addr))
1669 rtlpriv->stats.txbytesmulticast += skb->len;
1670 else if (is_broadcast_ether_addr(pda_addr))
1671 rtlpriv->stats.txbytesbroadcast += skb->len;
1672 else
1673 rtlpriv->stats.txbytesunicast += skb->len;
1674
1675 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1676 ring = &rtlpci->tx_ring[hw_queue];
1677 if (hw_queue != BEACON_QUEUE) {
1678 if (rtlpriv->use_new_trx_flow)
1679 idx = ring->cur_tx_wp;
1680 else
1681 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1682 ring->entries;
1683 } else {
1684 idx = 0;
1685 }
1686
1687 pdesc = &ring->desc[idx];
1688 if (rtlpriv->use_new_trx_flow) {
1689 ptx_bd_desc = &ring->buffer_desc[idx];
1690 } else {
1691 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1692 true, HW_DESC_OWN);
1693
1694 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1695 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1696 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1697 hw_queue, ring->idx, idx,
1698 skb_queue_len(&ring->queue));
1699
1700 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1701 flags);
1702 return skb->len;
1703 }
1704 }
1705
1706 if (rtlpriv->cfg->ops->get_available_desc &&
1707 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1708 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1709 "get_available_desc fail\n");
1710 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1711 return skb->len;
1712 }
1713
1714 if (ieee80211_is_data_qos(fc)) {
1715 tid = rtl_get_tid(skb);
1716 if (sta) {
1717 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1718 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1719 IEEE80211_SCTL_SEQ) >> 4;
1720 seq_number += 1;
1721
1722 if (!ieee80211_has_morefrags(hdr->frame_control))
1723 sta_entry->tids[tid].seq_number = seq_number;
1724 }
1725 }
1726
1727 if (ieee80211_is_data(fc))
1728 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1729
1730 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1731 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1732
1733 __skb_queue_tail(&ring->queue, skb);
1734
1735 if (rtlpriv->use_new_trx_flow) {
1736 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1737 HW_DESC_OWN, &hw_queue);
1738 } else {
1739 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1740 HW_DESC_OWN, &temp_one);
1741 }
1742
1743 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1744 hw_queue != BEACON_QUEUE) {
1745 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1746 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1747 hw_queue, ring->idx, idx,
1748 skb_queue_len(&ring->queue));
1749
1750 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1751 }
1752
1753 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1754
1755 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1756
1757 return 0;
1758}
1759
1760static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1761{
1762 struct rtl_priv *rtlpriv = rtl_priv(hw);
1763 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1764 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1765 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1766 u16 i = 0;
1767 int queue_id;
1768 struct rtl8192_tx_ring *ring;
1769
1770 if (mac->skip_scan)
1771 return;
1772
1773 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1774 u32 queue_len;
1775
1776 if (((queues >> queue_id) & 0x1) == 0) {
1777 queue_id--;
1778 continue;
1779 }
1780 ring = &pcipriv->dev.tx_ring[queue_id];
1781 queue_len = skb_queue_len(&ring->queue);
1782 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1783 queue_id == TXCMD_QUEUE) {
1784 queue_id--;
1785 continue;
1786 } else {
1787 msleep(20);
1788 i++;
1789 }
1790
1791 /* we just wait 1s for all queues */
1792 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1793 is_hal_stop(rtlhal) || i >= 200)
1794 return;
1795 }
1796}
1797
1798static void rtl_pci_deinit(struct ieee80211_hw *hw)
1799{
1800 struct rtl_priv *rtlpriv = rtl_priv(hw);
1801 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1802
1803 _rtl_pci_deinit_trx_ring(hw);
1804
1805 synchronize_irq(rtlpci->pdev->irq);
1806 tasklet_kill(&rtlpriv->works.irq_tasklet);
1807 cancel_work_sync(&rtlpriv->works.lps_change_work);
1808
1809 flush_workqueue(rtlpriv->works.rtl_wq);
1810 destroy_workqueue(rtlpriv->works.rtl_wq);
1811}
1812
1813static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1814{
1815 int err;
1816
1817 _rtl_pci_init_struct(hw, pdev);
1818
1819 err = _rtl_pci_init_trx_ring(hw);
1820 if (err) {
1821 pr_err("tx ring initialization failed\n");
1822 return err;
1823 }
1824
1825 return 0;
1826}
1827
1828static int rtl_pci_start(struct ieee80211_hw *hw)
1829{
1830 struct rtl_priv *rtlpriv = rtl_priv(hw);
1831 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1832 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1833 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1834 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1835
1836 int err;
1837
1838 rtl_pci_reset_trx_ring(hw);
1839
1840 rtlpci->driver_is_goingto_unload = false;
1841 if (rtlpriv->cfg->ops->get_btc_status &&
1842 rtlpriv->cfg->ops->get_btc_status()) {
1843 rtlpriv->btcoexist.btc_info.ap_num = 36;
1844 rtlpriv->btcoexist.btc_ops->btc_init_variables(rtlpriv);
1845 rtlpriv->btcoexist.btc_ops->btc_init_hal_vars(rtlpriv);
1846 } else if (rtlpriv->btcoexist.btc_ops) {
1847 rtlpriv->btcoexist.btc_ops->btc_init_variables_wifi_only(
1848 rtlpriv);
1849 }
1850
1851 err = rtlpriv->cfg->ops->hw_init(hw);
1852 if (err) {
1853 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1854 "Failed to config hardware!\n");
1855 return err;
1856 }
1857 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1858 &rtlmac->retry_long);
1859
1860 rtlpriv->cfg->ops->enable_interrupt(hw);
1861 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1862
1863 rtl_init_rx_config(hw);
1864
1865 /*should be after adapter start and interrupt enable. */
1866 set_hal_start(rtlhal);
1867
1868 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1869
1870 rtlpci->up_first_time = false;
1871
1872 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1873 return 0;
1874}
1875
1876static void rtl_pci_stop(struct ieee80211_hw *hw)
1877{
1878 struct rtl_priv *rtlpriv = rtl_priv(hw);
1879 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1880 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1881 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1882 unsigned long flags;
1883 u8 rf_timeout = 0;
1884
1885 if (rtlpriv->cfg->ops->get_btc_status())
1886 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1887
1888 if (rtlpriv->btcoexist.btc_ops)
1889 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1890
1891 /*
1892 *should be before disable interrupt&adapter
1893 *and will do it immediately.
1894 */
1895 set_hal_stop(rtlhal);
1896
1897 rtlpci->driver_is_goingto_unload = true;
1898 rtlpriv->cfg->ops->disable_interrupt(hw);
1899 cancel_work_sync(&rtlpriv->works.lps_change_work);
1900
1901 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1902 while (ppsc->rfchange_inprogress) {
1903 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1904 if (rf_timeout > 100) {
1905 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1906 break;
1907 }
1908 mdelay(1);
1909 rf_timeout++;
1910 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1911 }
1912 ppsc->rfchange_inprogress = true;
1913 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1914
1915 rtlpriv->cfg->ops->hw_disable(hw);
1916 /* some things are not needed if firmware not available */
1917 if (!rtlpriv->max_fw_size)
1918 return;
1919 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1920
1921 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1922 ppsc->rfchange_inprogress = false;
1923 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1924
1925 rtl_pci_enable_aspm(hw);
1926}
1927
1928static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1929 struct ieee80211_hw *hw)
1930{
1931 struct rtl_priv *rtlpriv = rtl_priv(hw);
1932 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1933 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1934 struct pci_dev *bridge_pdev = pdev->bus->self;
1935 u16 venderid;
1936 u16 deviceid;
1937 u8 revisionid;
1938 u16 irqline;
1939 u8 tmp;
1940
1941 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1942 venderid = pdev->vendor;
1943 deviceid = pdev->device;
1944 pci_read_config_byte(pdev, 0x8, &revisionid);
1945 pci_read_config_word(pdev, 0x3C, &irqline);
1946
1947 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1948 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1949 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1950 * the correct driver is r8192e_pci, thus this routine should
1951 * return false.
1952 */
1953 if (deviceid == RTL_PCI_8192SE_DID &&
1954 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1955 return false;
1956
1957 if (deviceid == RTL_PCI_8192_DID ||
1958 deviceid == RTL_PCI_0044_DID ||
1959 deviceid == RTL_PCI_0047_DID ||
1960 deviceid == RTL_PCI_8192SE_DID ||
1961 deviceid == RTL_PCI_8174_DID ||
1962 deviceid == RTL_PCI_8173_DID ||
1963 deviceid == RTL_PCI_8172_DID ||
1964 deviceid == RTL_PCI_8171_DID) {
1965 switch (revisionid) {
1966 case RTL_PCI_REVISION_ID_8192PCIE:
1967 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1968 "8192 PCI-E is found - vid/did=%x/%x\n",
1969 venderid, deviceid);
1970 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1971 return false;
1972 case RTL_PCI_REVISION_ID_8192SE:
1973 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1974 "8192SE is found - vid/did=%x/%x\n",
1975 venderid, deviceid);
1976 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1977 break;
1978 default:
1979 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1980 "Err: Unknown device - vid/did=%x/%x\n",
1981 venderid, deviceid);
1982 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1983 break;
1984 }
1985 } else if (deviceid == RTL_PCI_8723AE_DID) {
1986 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1988 "8723AE PCI-E is found - vid/did=%x/%x\n",
1989 venderid, deviceid);
1990 } else if (deviceid == RTL_PCI_8192CET_DID ||
1991 deviceid == RTL_PCI_8192CE_DID ||
1992 deviceid == RTL_PCI_8191CE_DID ||
1993 deviceid == RTL_PCI_8188CE_DID) {
1994 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1995 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1996 "8192C PCI-E is found - vid/did=%x/%x\n",
1997 venderid, deviceid);
1998 } else if (deviceid == RTL_PCI_8192DE_DID ||
1999 deviceid == RTL_PCI_8192DE_DID2) {
2000 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
2001 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2002 "8192D PCI-E is found - vid/did=%x/%x\n",
2003 venderid, deviceid);
2004 } else if (deviceid == RTL_PCI_8188EE_DID) {
2005 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
2006 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2007 "Find adapter, Hardware type is 8188EE\n");
2008 } else if (deviceid == RTL_PCI_8723BE_DID) {
2009 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
2010 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2011 "Find adapter, Hardware type is 8723BE\n");
2012 } else if (deviceid == RTL_PCI_8192EE_DID) {
2013 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
2014 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2015 "Find adapter, Hardware type is 8192EE\n");
2016 } else if (deviceid == RTL_PCI_8821AE_DID) {
2017 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
2018 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2019 "Find adapter, Hardware type is 8821AE\n");
2020 } else if (deviceid == RTL_PCI_8812AE_DID) {
2021 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2023 "Find adapter, Hardware type is 8812AE\n");
2024 } else if (deviceid == RTL_PCI_8822BE_DID) {
2025 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
2026 rtlhal->bandset = BAND_ON_BOTH;
2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2028 "Find adapter, Hardware type is 8822BE\n");
2029 } else {
2030 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2031 "Err: Unknown device - vid/did=%x/%x\n",
2032 venderid, deviceid);
2033
2034 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
2035 }
2036
2037 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2038 if (revisionid == 0 || revisionid == 1) {
2039 if (revisionid == 0) {
2040 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2041 "Find 92DE MAC0\n");
2042 rtlhal->interfaceindex = 0;
2043 } else if (revisionid == 1) {
2044 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2045 "Find 92DE MAC1\n");
2046 rtlhal->interfaceindex = 1;
2047 }
2048 } else {
2049 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2050 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2051 venderid, deviceid, revisionid);
2052 rtlhal->interfaceindex = 0;
2053 }
2054 }
2055
2056 switch (rtlhal->hw_type) {
2057 case HARDWARE_TYPE_RTL8192EE:
2058 case HARDWARE_TYPE_RTL8822BE:
2059 /* use new trx flow */
2060 rtlpriv->use_new_trx_flow = true;
2061 break;
2062
2063 default:
2064 rtlpriv->use_new_trx_flow = false;
2065 break;
2066 }
2067
2068 /*find bus info */
2069 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2070 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2071 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2072
2073 /*find bridge info */
2074 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2075 /* some ARM have no bridge_pdev and will crash here
2076 * so we should check if bridge_pdev is NULL
2077 */
2078 if (bridge_pdev) {
2079 /*find bridge info if available */
2080 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2081 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2082 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2083 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2084 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2085 "Pci Bridge Vendor is found index: %d\n",
2086 tmp);
2087 break;
2088 }
2089 }
2090 }
2091
2092 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2093 PCI_BRIDGE_VENDOR_UNKNOWN) {
2094 pcipriv->ndis_adapter.pcibridge_busnum =
2095 bridge_pdev->bus->number;
2096 pcipriv->ndis_adapter.pcibridge_devnum =
2097 PCI_SLOT(bridge_pdev->devfn);
2098 pcipriv->ndis_adapter.pcibridge_funcnum =
2099 PCI_FUNC(bridge_pdev->devfn);
2100 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2101 pci_pcie_cap(bridge_pdev);
2102 pcipriv->ndis_adapter.num4bytes =
2103 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2104
2105 rtl_pci_get_linkcontrol_field(hw);
2106
2107 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2108 PCI_BRIDGE_VENDOR_AMD) {
2109 pcipriv->ndis_adapter.amd_l1_patch =
2110 rtl_pci_get_amd_l1_patch(hw);
2111 }
2112 }
2113
2114 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2115 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2116 pcipriv->ndis_adapter.busnumber,
2117 pcipriv->ndis_adapter.devnumber,
2118 pcipriv->ndis_adapter.funcnumber,
2119 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2120
2121 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2122 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2123 pcipriv->ndis_adapter.pcibridge_busnum,
2124 pcipriv->ndis_adapter.pcibridge_devnum,
2125 pcipriv->ndis_adapter.pcibridge_funcnum,
2126 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2127 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2128 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2129 pcipriv->ndis_adapter.amd_l1_patch);
2130
2131 rtl_pci_parse_configuration(pdev, hw);
2132 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2133
2134 return true;
2135}
2136
2137static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2138{
2139 struct rtl_priv *rtlpriv = rtl_priv(hw);
2140 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2141 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2142 int ret;
2143
2144 ret = pci_enable_msi(rtlpci->pdev);
2145 if (ret < 0)
2146 return ret;
2147
2148 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2149 IRQF_SHARED, KBUILD_MODNAME, hw);
2150 if (ret < 0) {
2151 pci_disable_msi(rtlpci->pdev);
2152 return ret;
2153 }
2154
2155 rtlpci->using_msi = true;
2156
2157 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2158 "MSI Interrupt Mode!\n");
2159 return 0;
2160}
2161
2162static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2163{
2164 struct rtl_priv *rtlpriv = rtl_priv(hw);
2165 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2166 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2167 int ret;
2168
2169 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2170 IRQF_SHARED, KBUILD_MODNAME, hw);
2171 if (ret < 0)
2172 return ret;
2173
2174 rtlpci->using_msi = false;
2175 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2176 "Pin-based Interrupt Mode!\n");
2177 return 0;
2178}
2179
2180static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2181{
2182 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2183 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2184 int ret;
2185
2186 if (rtlpci->msi_support) {
2187 ret = rtl_pci_intr_mode_msi(hw);
2188 if (ret < 0)
2189 ret = rtl_pci_intr_mode_legacy(hw);
2190 } else {
2191 ret = rtl_pci_intr_mode_legacy(hw);
2192 }
2193 return ret;
2194}
2195
2196static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2197{
2198 u8 value;
2199
2200 pci_read_config_byte(pdev, 0x719, &value);
2201
2202 /* 0x719 Bit5 is DMA64 bit fetch. */
2203 if (dma64)
2204 value |= BIT(5);
2205 else
2206 value &= ~BIT(5);
2207
2208 pci_write_config_byte(pdev, 0x719, value);
2209}
2210
2211int rtl_pci_probe(struct pci_dev *pdev,
2212 const struct pci_device_id *id)
2213{
2214 struct ieee80211_hw *hw = NULL;
2215
2216 struct rtl_priv *rtlpriv = NULL;
2217 struct rtl_pci_priv *pcipriv = NULL;
2218 struct rtl_pci *rtlpci;
2219 unsigned long pmem_start, pmem_len, pmem_flags;
2220 int err;
2221
2222 err = rtl_core_module_init();
2223 if (err)
2224 return err;
2225 err = pci_enable_device(pdev);
2226 if (err) {
2227 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2228 pci_name(pdev));
2229 return err;
2230 }
2231
2232 if (((struct rtl_hal_cfg *)(id->driver_data))->mod_params->dma64 &&
2233 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2234 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2235 WARN_ONCE(true,
2236 "Unable to obtain 64bit DMA for consistent allocations\n");
2237 err = -ENOMEM;
2238 goto fail1;
2239 }
2240
2241 platform_enable_dma64(pdev, true);
2242 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2243 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2244 WARN_ONCE(true,
2245 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2246 err = -ENOMEM;
2247 goto fail1;
2248 }
2249
2250 platform_enable_dma64(pdev, false);
2251 }
2252
2253 pci_set_master(pdev);
2254
2255 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2256 sizeof(struct rtl_priv), &rtl_ops);
2257 if (!hw) {
2258 WARN_ONCE(true,
2259 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2260 err = -ENOMEM;
2261 goto fail1;
2262 }
2263
2264 SET_IEEE80211_DEV(hw, &pdev->dev);
2265 pci_set_drvdata(pdev, hw);
2266
2267 rtlpriv = hw->priv;
2268 rtlpriv->hw = hw;
2269 pcipriv = (void *)rtlpriv->priv;
2270 pcipriv->dev.pdev = pdev;
2271 init_completion(&rtlpriv->firmware_loading_complete);
2272 /*proximity init here*/
2273 rtlpriv->proximity.proxim_on = false;
2274
2275 pcipriv = (void *)rtlpriv->priv;
2276 pcipriv->dev.pdev = pdev;
2277
2278 /* init cfg & intf_ops */
2279 rtlpriv->rtlhal.interface = INTF_PCI;
2280 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2281 rtlpriv->intf_ops = &rtl_pci_ops;
2282 rtlpriv->glb_var = &rtl_global_var;
2283
2284 /* MEM map */
2285 err = pci_request_regions(pdev, KBUILD_MODNAME);
2286 if (err) {
2287 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2288 goto fail1;
2289 }
2290
2291 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2292 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2293 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2294
2295 /*shared mem start */
2296 rtlpriv->io.pci_mem_start =
2297 (unsigned long)pci_iomap(pdev,
2298 rtlpriv->cfg->bar_id, pmem_len);
2299 if (rtlpriv->io.pci_mem_start == 0) {
2300 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2301 err = -ENOMEM;
2302 goto fail2;
2303 }
2304
2305 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2306 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2307 pmem_start, pmem_len, pmem_flags,
2308 rtlpriv->io.pci_mem_start);
2309
2310 /* Disable Clk Request */
2311 pci_write_config_byte(pdev, 0x81, 0);
2312 /* leave D3 mode */
2313 pci_write_config_byte(pdev, 0x44, 0);
2314 pci_write_config_byte(pdev, 0x04, 0x06);
2315 pci_write_config_byte(pdev, 0x04, 0x07);
2316
2317 /* find adapter */
2318 if (!_rtl_pci_find_adapter(pdev, hw)) {
2319 err = -ENODEV;
2320 goto fail2;
2321 }
2322
2323 /* Init IO handler */
2324 _rtl_pci_io_handler_init(&pdev->dev, hw);
2325
2326 /*like read eeprom and so on */
2327 rtlpriv->cfg->ops->read_eeprom_info(hw);
2328
2329 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2330 pr_err("Can't init_sw_vars\n");
2331 err = -ENODEV;
2332 goto fail3;
2333 }
2334 rtlpriv->cfg->ops->init_sw_leds(hw);
2335
2336 /*aspm */
2337 rtl_pci_init_aspm(hw);
2338
2339 /* Init mac80211 sw */
2340 err = rtl_init_core(hw);
2341 if (err) {
2342 pr_err("Can't allocate sw for mac80211\n");
2343 goto fail3;
2344 }
2345
2346 /* Init PCI sw */
2347 err = rtl_pci_init(hw, pdev);
2348 if (err) {
2349 pr_err("Failed to init PCI\n");
2350 goto fail3;
2351 }
2352
2353 err = ieee80211_register_hw(hw);
2354 if (err) {
2355 pr_err("Can't register mac80211 hw.\n");
2356 err = -ENODEV;
2357 goto fail3;
2358 }
2359 rtlpriv->mac80211.mac80211_registered = 1;
2360
2361 /* add for debug */
2362 rtl_debug_add_one(hw);
2363
2364 /*init rfkill */
2365 rtl_init_rfkill(hw); /* Init PCI sw */
2366
2367 rtlpci = rtl_pcidev(pcipriv);
2368 err = rtl_pci_intr_mode_decide(hw);
2369 if (err) {
2370 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2371 "%s: failed to register IRQ handler\n",
2372 wiphy_name(hw->wiphy));
2373 goto fail3;
2374 }
2375 rtlpci->irq_alloc = 1;
2376
2377 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2378 return 0;
2379
2380fail3:
2381 pci_set_drvdata(pdev, NULL);
2382 rtl_deinit_core(hw);
2383
2384fail2:
2385 if (rtlpriv->io.pci_mem_start != 0)
2386 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2387
2388 pci_release_regions(pdev);
2389 complete(&rtlpriv->firmware_loading_complete);
2390
2391fail1:
2392 if (hw)
2393 ieee80211_free_hw(hw);
2394 pci_disable_device(pdev);
2395
2396 return err;
2397}
2398
2399void rtl_pci_disconnect(struct pci_dev *pdev)
2400{
2401 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2402 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2403 struct rtl_priv *rtlpriv = rtl_priv(hw);
2404 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2405 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2406
2407 /* just in case driver is removed before firmware callback */
2408 wait_for_completion(&rtlpriv->firmware_loading_complete);
2409 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2410
2411 /* remove form debug */
2412 rtl_debug_remove_one(hw);
2413
2414 /*ieee80211_unregister_hw will call ops_stop */
2415 if (rtlmac->mac80211_registered == 1) {
2416 ieee80211_unregister_hw(hw);
2417 rtlmac->mac80211_registered = 0;
2418 } else {
2419 rtl_deinit_deferred_work(hw);
2420 rtlpriv->intf_ops->adapter_stop(hw);
2421 }
2422 rtlpriv->cfg->ops->disable_interrupt(hw);
2423
2424 /*deinit rfkill */
2425 rtl_deinit_rfkill(hw);
2426
2427 rtl_pci_deinit(hw);
2428 rtl_deinit_core(hw);
2429 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2430
2431 if (rtlpci->irq_alloc) {
2432 free_irq(rtlpci->pdev->irq, hw);
2433 rtlpci->irq_alloc = 0;
2434 }
2435
2436 if (rtlpci->using_msi)
2437 pci_disable_msi(rtlpci->pdev);
2438
2439 list_del(&rtlpriv->list);
2440 if (rtlpriv->io.pci_mem_start != 0) {
2441 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2442 pci_release_regions(pdev);
2443 }
2444
2445 pci_disable_device(pdev);
2446
2447 rtl_pci_disable_aspm(hw);
2448
2449 pci_set_drvdata(pdev, NULL);
2450
2451 ieee80211_free_hw(hw);
2452 rtl_core_module_exit();
2453}
2454
2455#ifdef CONFIG_PM_SLEEP
2456/***************************************
2457 * kernel pci power state define:
2458 * PCI_D0 ((pci_power_t __force) 0)
2459 * PCI_D1 ((pci_power_t __force) 1)
2460 * PCI_D2 ((pci_power_t __force) 2)
2461 * PCI_D3hot ((pci_power_t __force) 3)
2462 * PCI_D3cold ((pci_power_t __force) 4)
2463 * PCI_UNKNOWN ((pci_power_t __force) 5)
2464
2465 * This function is called when system
2466 * goes into suspend state mac80211 will
2467 * call rtl_mac_stop() from the mac80211
2468 * suspend function first, So there is
2469 * no need to call hw_disable here.
2470 ****************************************/
2471int rtl_pci_suspend(struct device *dev)
2472{
2473 struct pci_dev *pdev = to_pci_dev(dev);
2474 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2475 struct rtl_priv *rtlpriv = rtl_priv(hw);
2476
2477 rtlpriv->cfg->ops->hw_suspend(hw);
2478 rtl_deinit_rfkill(hw);
2479
2480 return 0;
2481}
2482
2483int rtl_pci_resume(struct device *dev)
2484{
2485 struct pci_dev *pdev = to_pci_dev(dev);
2486 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2487 struct rtl_priv *rtlpriv = rtl_priv(hw);
2488
2489 rtlpriv->cfg->ops->hw_resume(hw);
2490 rtl_init_rfkill(hw);
2491 return 0;
2492}
2493#endif /* CONFIG_PM_SLEEP */
2494
2495const struct rtl_intf_ops rtl_pci_ops = {
2496 .read_efuse_byte = read_efuse_byte,
2497 .adapter_start = rtl_pci_start,
2498 .adapter_stop = rtl_pci_stop,
2499 .check_buddy_priv = rtl_pci_check_buddy_priv,
2500 .adapter_tx = rtl_pci_tx,
2501 .flush = rtl_pci_flush,
2502 .reset_trx_ring = rtl_pci_reset_trx_ring,
2503 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2504
2505 .disable_aspm = rtl_pci_disable_aspm,
2506 .enable_aspm = rtl_pci_enable_aspm,
2507};