1/* -*- mode: c; c-basic-offset: 8 -*- */
 2
 3/* NCR Quad 720 MCA SCSI Driver
 4 *
 5 * Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
 6 */
 7
 8#ifndef _NCR_Q720_H
 9#define _NCR_Q720_H
10
11/* The MCA identifier */
12#define NCR_Q720_MCA_ID		0x0720
13
14#define NCR_Q720_CLOCK_MHZ	30
15
16#define NCR_Q720_POS2_BOARD_ENABLE	0x01
17#define NCR_Q720_POS2_INTERRUPT_ENABLE	0x02
18#define NCR_Q720_POS2_PARITY_DISABLE	0x04
19#define NCR_Q720_POS2_IO_MASK		0xf8
20#define NCR_Q720_POS2_IO_SHIFT		8
21
22#define NCR_Q720_CHIP_REGISTER_OFFSET	0x200
23#define NCR_Q720_SCSR_OFFSET		0x070
24#define NCR_Q720_SIOP_SHIFT		0x080
25
26#endif
27
28

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/* -*- mode: c; c-basic-offset: 8 -*- */
 3
 4/* NCR Quad 720 MCA SCSI Driver
 5 *
 6 * Copyright (C) 2003 by James.Bottomley@HansenPartnership.com
 7 */
 8
 9#ifndef _NCR_Q720_H
10#define _NCR_Q720_H
11
12/* The MCA identifier */
13#define NCR_Q720_MCA_ID		0x0720
14
15#define NCR_Q720_CLOCK_MHZ	30
16
17#define NCR_Q720_POS2_BOARD_ENABLE	0x01
18#define NCR_Q720_POS2_INTERRUPT_ENABLE	0x02
19#define NCR_Q720_POS2_PARITY_DISABLE	0x04
20#define NCR_Q720_POS2_IO_MASK		0xf8
21#define NCR_Q720_POS2_IO_SHIFT		8
22
23#define NCR_Q720_CHIP_REGISTER_OFFSET	0x200
24#define NCR_Q720_SCSR_OFFSET		0x070
25#define NCR_Q720_SIOP_SHIFT		0x080
26
27#endif
28
29